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US3478322A - Data processor employing electronically changeable control storage - Google Patents

Data processor employing electronically changeable control storage Download PDF

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US3478322A
US3478322A US3478322DA US3478322A US 3478322 A US3478322 A US 3478322A US 3478322D A US3478322D A US 3478322DA US 3478322 A US3478322 A US 3478322A
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means
control
storage
eccs
register
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Bob O Evans
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International Business Machines Corp
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International Business Machines Corp
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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for programme control, e.g. control unit
    • G06F9/06Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/22Microcontrol or microprogramme arrangements
    • G06F9/24Loading of the microprogramme
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18Handling requests for interconnection or transfer for access to memory bus based on priority control
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for programme control, e.g. control unit
    • G06F9/06Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/30Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/30145Instruction analysis, e.g. decoding, instruction word fields
    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00Program-control systems
    • G05B2219/30Nc systems
    • G05B2219/33Director till display
    • G05B2219/33125System configuration, reconfiguration, customization, automatic
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
    • Y02P90/18Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS] characterised by the network communication
    • Y02P90/185Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS] characterised by the network communication using local area networks [LAN]

Abstract

1,154,299. Microprogramme-controlled computers. INTERNATIONAL BUSINESS MACHINES CORP. 14 May, 1968 [23 May, 1967], No. 22789/68. Heading G4A. A microprogramme-controlled electronic digital computer includes a plurality of control stores at least one of which is an electronicallychangeable control store, and means for loading micro-instructions into an electronically-changeable control store while the computer is operating under the control of micro-instructions stored in the other control store or stores. One read-only and two read-write control stores are provided and the latter can be loaded from a main store, an external control programme store, or a register receiving micro-instructions modified in an arithmetic and logic unit.

Description

Nov. 11. 1969 Filed llay 23, 1967 FIG.|B

B. o. EVANS 3,478,322 DATA PROCESSOR EMPLOYING ELECTRONICALLY CHANGEABLE CONTROL STORAGE .5 Sheets-Sheet 2 Nov. 11. 1969 a. o. EVANS DATA PROCESSOR EMPLOYING ELECTRONICALLY CHANGEABLE CONTROL STORAGE Filed May 23, 1967 3 Sheets-Sheet 3 53mm 5 wwu mw 5.58 was $2.95 558 s N 2 8X :82 Il .5528 .tllL l. 525 was SEE; I: 326 5.25 o: 33 N a; E2: was :5; cm

8N fi rafi m 55;: :2 n 25; 2 c f 5 SE5; 358 r :2 E m 2 N2 oz 2 United States Patent 3,478,322 DATA PROCESSOR EMPLOYING ELECTRONI- CALLY CHANGEABLE CONTROL STORAGE Bob 0. Evans, Bethesda, Md., assignor to International Business Machines Corporation, Armonk, N.Y., a corporation of New York Filed May 23, 1967, Ser. No. 640,652 Int. Cl. Gllh 13/00 US. Cl. 340-1725 23 Claims ABSTRACT OF THE DISCLOSURE A digital computer, having a control element comprising read/write control storage means loadable with precoded microinstructions from storage external to said computer to allow direct execution of macro instructions without compiling machine language; said control element also being loadable from main storage or from data register means within the computer to allow said computer to construct its own gating patterns, and rendering said computer restructurable.

This invention relates to electronic digital computers, and more particularly to the control element of electronic digital computers. The invention involves a digtal computer with the significant improvement of providing the programmer with complete dynamic control of the contents of the control element that is directing the functions of the computer.

Over the past several years great strides have been made in the development of electronic digital computers. Large scale digital computer systems have been developed which possess immense power enabling them to solve virtually any present day computing problem. However, the power of the system has been hampered by the difficulty of developing eflicient programming systems.

The heart of any digital computing machine is the control element. Prior art control elements have been of the fixed type. That is, the control element operates the computing machine in precisely the same manner each time a computer program for the solving of a problem is run on the machine. These prior art control elements have evolved in stages. Originally, the control element was made by of various active and passive hardware components which were spread physically throughout a computing machine in an amorphous manner. More recently, with the advent of the concept of read-only control storage elements (ROCS), the control of many digital computing machines has become regularized and located in a central area within the machine. In prior art computers, an instruction set is made up of a fixed sequence of socalled primitive instructions which are fixed in the computing machine. The execution of each primitive instruction requires a number of so-called micro instructions which are fixed in ROCS to be executed within the machine. A so-called macro instruction, the type a programmer generally writes in a high level language such as Fortran, requires a number of the above-mentioned primitive instructions to be strung together and inserted in the systems main storage. Each primitive instruction is executed in turn, by the control storage by executing the micro instructions required for each particular primitive instruction. In such a system the prior art computer suffers from the disadvantage that for all of the myriad various macro functions that the computer may be called upon to perform, only a limited fixed set of instructions are available, so that even optimal sequences of instructions may represent an awkward and ineflicient method of implementing the macro functions compared to that 3,478,322 Patented Nov. 11, 1969 which could be achieved given free access to the micro instructions themselves.

It is therefore an object of the present invention to provide an improved computer system.

A particular object of this invention is to effect a control element for obtaining a better matching application of the operational problem to be solved to the digital computer.

A more specific object of this invention is to provide a control element for a digital computer which allows the machine to tailor itself to each new instruction to be executed.

A still more specific object of this invention is to achieve a control element for a digital computer which allows the programmer to modify machine control prior to or durifig program execution to enable the computer to restructure itself and provide a high level of efficiency in program execution.

A particular object of the present invention is to effect a control element for a digital computer with drastically improved control characteristics.

Another more particular object of the invention is to effect a control element for a digital computer which eliminates the need for the computer to have a prespecified instruction repertoire and renders the instruction repertoire universal.

Another and still more particular object of the invention is to effect a control element for a digital computer which allows the computer to construct its own gating patterns and to dynamically alter and optimize algorithms, information flow and data path bandwidths.

One feature of the invention comprises loadable, or read/write, control storage means in conjunction with an external control program storage device, used as a control element for a digitial computing machine.

The loadable or read/write control storage means may be disgnated as electronically changeable control storage (ECCS) inasmuch as the contents of the storage, used to control the machine circuitry, can be electronically modified prior to or during program execution. The control element may contain a conventional read-only control storage (ROCS) which allows the machine also to operate in the conventional fixed control manner when such operation is desired.

The basic digital computer can be any computer data paths, arithmetic, registers, and logical elements of a known type, but possessing the new control element described herein. An example of a known type of digital computer suitable for use with the control element described herein is seen in US. Patent No. 3,400,371 filed Apr. 6, 1964, and assigned to the assignee of the present invention.

The control element of the present invention contains micro instructions which operate the various circuits of the computer in sequences to allow execution of a computer program. Micro instructions in general might be viewed as gazing patterns, and the manner in which they operate computer circuitry is explained in the above-referenced copending application. As mentioned above, micro instructions in conventional control means are fixed in ROCS. The control element of the present invention, however, comprises ECCS means and, if desired, ROCS means also. The micro instructions located in the ROCS of the present invention are fixed, but the micro instructions in the ECCS means are loadable. That is to say, the micro instructions in the ECCS means may be changed prior to or during program execution to facilitate eflicient execution. Micro instructions are loadable into ECCS from any of several sources, including main storage, internal computer data flow, or external control program storage devices. This gives a digital computer flexibility to restructure or tailor itself to the task at hand.

In one type of operation, the programmer may, for example, write a micro program in a symbolic or functional language. The functional language comprises symbolic statements, for each of which statements micro instructions are prerecorded on an external control program storage device. The micro program would be loaded into the main storage of the computing machine in a manner similar to that of present day computers. However, instead of compiling the program as is done in present day computers, the micro instructions corresponding to the instructions of the symbolic language are located on the external control program storage device, read from said device into the ECCS means and executed to control machine function. The system may contain more than one ECCS so that the loading of oen can be overlapped in parallel with the execution of another to enhance time efliciency. In the presently described mode of operation the prior art requirement of program translation into a fixed intermediate machine language is eliminated and a digital computer is achieved which gives the user the ability to apply his micro instructions directly without the many fixed instruction programming steps required in present day computer systems.

As another feature of the invention, the ECCS means are loadable from main storage and also from the computers data paths, as well as from the abovesaid external control program storage. Thus the system can be operated so as to construct its own gating patterns allowing the user to dynamically alter and optimize algorithms and information flow.

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawings.

In the drawings:

FIGURE 1A is a representation of a digital computer showing the basic control element of the present invention.

FIGURE 1B is a representation of the data flow of FIG- URE 1A.

FIGURE 1C is an expression of the selection control seen in FIGURE 1A.

GENERAL DESCRIPTION As mentioned above, the control element of the present invention comprises ECCS means. Any number of ECCS means can be employed. However, the invention will be described, for illustrative purposes, as having two ECCS means.

As seen in FIGURE 1A, the control element of the present invention comprises ECCS 1, ECCS 2, and ROCS 3, in conjunction with Control Storage Select 4, ECCS I/O, Channel 5, and External Control Program Storage 7. ECCS l and 2 are storage devices of the type well known in the art, the read/write speed of which is matched to the timing requirements of the digital computer. ECCS 1 and 2 might be, for example, well known core storage matrices or other appropriate read/write storage devices. ROCS 3 may be, for example, Well known transformer or capacitor card read only storage devices. The control element is equipped with appropriate sequencing means such as Address Generator 8, which might be constructed such as that described in the above copending application, for locating, reading out and executing micro instructions.

ROCS, ECCS 1 and ECCS 2 each has an associated control storage register such as Data Register 9, 10, and 11, respectively. The output of any of Data Registers 9, 10, and 11, can be connected to Control Circuits 20 via Select circuitry 22. Select circuitry 22 may be, for example, AND gates enabled by a Data Out Select line 220. Likewise the output of any of Data Registers 9, 10 and 11 can be connected to ECCS I/O Channel via Select circuitry 21 which is similar to Select circuitry 22 and similarly enabled by Data Out Select line 220.

Information read out of ROCS and ECCS enters Data Registers 9, 10, or 11 from which it can be used to generate a new address in Address Generator 8, or be used to supply control information to Control Storage Select 4 or ECCS I/O Channel 5. Gating patterns are derived from the micro instructions and are applied to Control Circuits 20 from Data Register 9, 10, or 11 via Select circuit 22 to establish information flow paths, sequence operations in other parts of the machine and determine future events in the scheme of control, as explained in the above-referenced copending application.

Main System Storage 36, also seen in FIGURE 1A can be any appropriate storage means such as a core plane storage. Macro instructions can be contained in individual cells or groups of cells of the Main System Storage.

With reference to FIGURE 13, other portions of the computer shown generally at Data Flow 46 in FIGURE 1A include general purpose registers 108 through and arithmetic logic unit (ALU) 140. Data entry to the ALU is via A bus 144 or B bus 146 by way of registers 132 and 134, respectively. The B bus is also provided with true/complement means 136. The output of the ALU is by way of bus 142 which has entries to each general purpose register, under control of the micro instructions executed from ECCS 1 and 2, and ROCS 3. Each general purpose register has an enty to the ALU via A bus 144, while registers 108 and 128 each have entries to the ALU via B bus 146. Output data can be supplied to external utilization devices 42 via Computer I/O Channel 6. Register 108 also has a data entry to Address Generator 8, Control Storage Select 4 and ECCS 1 and 2 via lines 148. In operation, the said registers. ALU, and described data paths operate under micro instruction control in a manner similar to the operation described in the above-referenced copending application.

ECCS I/O Channel 5 fonctions as an information transmission means between External Control Program Storage 7 and either of ECCS 1 or 2. A channel suitable for use might be, for example, one such as disclosed in US. Patent No. 3,411,144 filed Apr. 26, 1966 and assigned to the assignee of the present invention. Control Storage Select 4 receives mode information over line 148 or line 12 and sets up proper gating for appropriately requested ROCS and ECCS cycles to enable ECCS I/O Channel 5 to enter information into the proper ECCS. ECCS l/O Channel 5 serves to enable the transfer to ECCS 1 or 2 of information to be used as micro instructions under control of selection lines 224, 226 of FIGURE 1C, over line 16 to the proper address as designated on line 17. ECCS I/O Channel 5 may connect to various external control program storage devices 7, and may also establish a path to main storage 36 via Channel-to-Channel adapter 40 and Computer I/O Channel 6. The Channel-to-Channel Adapter 40 may be a suitable device such as that disclosed in copending application Ser. No. 432,970 filed Feb. 16, 1965 and assigned to the assignee of the present invention. Other means, Well known to those skilled in the art may also be used to establish a data path between Main Storage 36 and ECCS 1 or 2.

During program execution it may be desired to transfer information contained in the computer data flow 46 to ECCS 1 or 2 by lines 148 as controlled by selection lines 224, 226 of FIG. 1C.

Hence ECCS 1 or 2 are loadable from any of three sources (1) from Main System Storage 36 via Computer I/O Channel 6, Channel-to-Channel Adapter 40, and ECCS I/O Channel 5, or via any suitable means, well known to those skilled in the art, for establishing a data path; (2) from DR Register 108 via lines 148; (3) from External Control Program Storage 7 via ECCS I/O Channel 5.

FIGURE 1C shows the structure of Control Storage Select seen generally at 4 in FIGURE 1A. The Control Storage $lect contains the registers and controls neccssary to record the current mode of operation, establish the correct flow of data into and out of ECCS 1 and EOCS 2 by manipulation of registers and switch gate controls, and assign appropriate ECCS cycles in response to cycle requests from ECCS I/O Channel 5 and from machine clocking controls.

With continued reference to FIGURE 1C, the Control Storage Select comprises Control Mode Register 200, Control Store Status Register 202, Cycle Allocation Control 204 and Control Decode 206.

Control Mode Register 200 is capable of receiving data via gating means 210. Data can be entered from DR Register 108 over bus 148, or from the contents of a particular micro instruction field, reserved for mode information, over bus 214. The particular bus, 148 or 214, chosen is indicated by an enabling signal over Control Store Mode Select Control line 208. This line transmits a gating signal from a designated micro instruction field which causes the contents of either bus 148 or 214 to be entered into register 200.

Cycle Allocation Control 204, of a type well known in the computer art, has input lines 216 and 30 for Machine Cycle Request and for ECCS I/O Channel Cycle Request, respectively. The Machine Cycle Request line transmits a signal from the machine clocking controls requesting a new micro instruction. ECCS I/O Channel Request line 30 transmits a request from ECCS I/O Channel 5 to Cycle Allocation Control 204 for an input cycle. Machine Cycle Granted line 218 and ECCS I/O Channel Cycle Granted line 32 indicates to the internal machine controls and to ECCS I/O Channel, respectively, when requested cycles are initiated.

Cycle allocation information from Cycle Allocation Control 204 is also entered into Control Decode 206 over lines 230, 232, 240. Control Decode 206 is of a type well known in the art such as, for example, a matrix decode. Said Control Decode decodes the cycle allocation information and presents control gating signals over lines 220, 222, 224, and 226. Line 222 is designated Control Store Cycle Control and serves to initiate read or Write cycles as appropriate from the currently active control stores. Line 20 is designated Data Out Select and serves to control the switching of information from the appropriate ECCS through Select means 21 or 22 to line 12 or to computer control circuitry 20, respectively. Address In Select line 224 controls the switching of Address Generator 8 and ECCS I/O Channel addresses to the appropriate ECCS via lines 30 and 17, respectively. Data In Select line 226 switches ECCS I/O data bus 17 to the appropriate ECCS.

In addition to the above described primary controls in Control Storage Select, there may be added well known controls necessary for establishing synchronism, monitoring the status of various system elements, as well as responding to exceptional conditions.

In operation, the contents of Control Mode Register 200 define the current mode of operation. Some possible modes are suggested on page 11 et. seq. The Control Store Status Register 202 records the current status of each store and indicates such conditions as whether a cycle is in progress, whether the desired ECCS is available, or busy. Cycle allocation Control 204 responds to cycle requests, analyzes current mode setting and status, and issues appropriate cycle information to Control Decode 206 from which information on lines 220, 222, 224, and 226 is derived.

OPERATION As stated above, the purpose of the present invention is to provide a control element for a digital computer which enables the computer to restructure itself prior to or during program execution. Micro instructions for execution of macro instructions are executed from either ROCS, ECCS 1, or ECCS 2. The following are some of the possible operational modes of the control element.

In the ROCS mode of operation, ROCS 3 is used for control. Macro instructions may be read out of Main System Storage 36 and executed by means of micro instructions fixed in ROCS 3 in a manner explained in referenced copending application 357,372. Additionally, either ECCS 1 or ECCS 2 is available for block transfer of prerecorded micro instructions from Main Store 36 or External Control Program Storage 7 via I/O Channels 5 and 6, said micro instructions to be used for subsequent program execution of macro instructions. Further, either ECCS 1 or ECCS 2 may be loaded with micro instructions from DR Register 108 via lines 148. Micro instructions are loaded from any of the above three sources in parallel cycles with ROCS operation. Thus while instructions are being executed by ROCS, either of ECCS 1 or 2 may be setting up for subsequent instruction execution.

In another operational mode, either of ROCS or ECCS 1 may be used for control. Micro instructions may be read from either or both to effect execution of a program. During this time, ECCS 2 can be loaded from either External Control Program Storage, DR Register 108 or Main Store 36 in order to set up micro instructions for future execution.

As an example, during the time that program execution is being performed from ROCS or ECCS 1, an instruction to call a new control program into ECCS 2 may be read out of main store. ECCS I/O Channel 5 would then receive instructions to perform a read operation from the appropriate area of External Control Program Storage 7, thus loading ECCS 2 with the appropriate micro instruction under control of lines 222, 224, and 226. The micro instructions are subsequently read out of said ECCS 2 and applied as control information for the macro instruction statements to be executed at a later time. In this manner, for example, ECCS l and ECCS 2 can alternate in receiving the micro instructions for every other control program in a look-ahead fashion.

As another example of this mode of operation, it may be desirable to load information directly from Main Storage 36 into ECCS 2 While ECCS 1 or ROCS is executing so that said information can serve as micro instructions for subsequent program execution. In so doing, the word or words from main storage are transferred to Computer I/O Channel 6, through Channelto-Channel Adapter 40 to ECCS I/O Channel 5 and thence into ECCS 2 for subsequent program execution.

In yet another example of a possible mode of operation, it may be desirable to generate mirco instructions from information contained in Main System Storage 36-, or ROCS, or ECCS 1, and load the micro instructions into ECCS 2 for future execution. In this type of situation information would be read from Main System Storage, into the data-flow 46 via bus 102; or from ROCS, ECCS 1 or ECCS 2 via Data Registers 9, 10, or 11 respectively and bus 12; to bus 146 and then to the ALU which would manipulate the information to generate the desired micro instructions. Upon generation, each micro instruction would be loaded into DR Register 108 from which it would be transferred via line 148 to ECCS 2 for subsequent execution.

In yet another mode of operation ROCS and ECCS 2 can be used to execute micro instructions for control. During this time ECCS 1 is available to be loaded with micro instructions from External Control Program Storage 7, Main System Storage 36, or DR Register 108 in a manner similar to that explained for ECCS 2 above.

In an extended mode operation, ROCS, ECCS 1 and ECCS 2 can be used in any desired order to execute micro instructions for control. In parallel cycles during which one or the other ECCS is executing micro instructions for control, the alternate ECCS can be available to be loaded with micro instructions in a manner similar to that described for ECCS 2 or ECCS 1 above.

7 SUMMARY In summary, it can be seen that a control element for a digital computer has been provided which utilizes electronically changeable, or read/write, control storages. The control element thus provided enables the computer to restructure itself prior to or during program execution to allow the most efficient possible execution of the program instruction of the moment. Micro instructions necessary for the execution of individual macro instructions of a computer program are prerecorded on an External Control Program Storage device and can be loaded into the control element to be used for executing the macro instructions of the moment. Further, the use of loadable control storages allows the computer to generate its own micro instructions or gating patterns and to load these patterns into the control element for subsequent use in program execution. Additionally, means have been provided to load information, to be used as micro instructions, from main system storage into the control element, for subsequent use in program execution.

While the invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.

I claim:

1. In an electronic digital computer for executing electronic data processing tasks written in the form of a list of individual instruction statements, said computer including main storage means, input means, output means, general storage register means, arithmetic means, control means, control sequencing means and control circuitry, wherein the improvement is in said control means comprising:

control storage register means;

multiple read/write control storage means each having an input for receiving micro code necessary for the execution of said instruction statements, and an output connected to said control storage register means for applying said micro code to said control circuitry;

control program storage means external to said computer and having prerecorded thereon micro code necessary to execute said individual instruction statements;

switching and selection means having an input connected to said main storage means for receiving information for retrieving from said control program storage means said prerecorded instruction code corresponding to said instruction statements,

said switching and selection means having an output buss connected to each of said multiple read/write control storage means for transferring said prerecorded micro code from said control program storage means to any of said multiple read/write control storage means.

2. An electronic digital computer according to the combination of claim 1, wherein said general storage register means has a data transmission buss connected to the input of each of said multiple read/write control storage means for enabling the transfer of information from said general storage register means to any of said multiple read/ write control storage means.

3. An electronic digital computer according to the combination of claim 1, wherein said switching and selection means has an input connected to said main storage means for enabling said switching and selection means to transfer information from said main storage means over said output buss to any of said multiple read/write control storage means.

4. An electronic digital computer according to the combination of claim 1, wherein said control storage register means is connected to said general storage register means via said arithmetic means, for enabling the transfer of information from said control storage register means to said general storage register means.

5. An electronic digital computer according to the combination of claim 1, wherein said control storage register means is connected to said arithmetic means, for enabling the transfer of information from said control storage register means to said arithmetic means.

6. An electronic digital computer according to the combination of claim 1 wherein said control storage register means is connected to said arithmetic means for enabling the transfer of information from said control storage register means to said arithmetic means for manipulation therein;

said arithmetic means is connected to said general storage register means, for enabling transfer of said manipulated information from said arithmetic means to said general storage register means; and

said general storage register means is connected to said multiple read/write control storage means, for enabling the transfer of said manipulated information from said general storage register means to any of said multiple read/write control storage means.

7. In an electronic digital computer for executing electronic data processing tasks written in the form of a list of individual instruction statements, said computer including main storage means, input means, output means, general storage register means, arithmetic means, control means, control sequencing means and control circuitry, wherein the improvement is in said control means comprising:

control storage register means;

single read/ write control storage means having an input for receiving micro code necessary for the execution of said instruction statements, and having an output connected to said control storage register means for applying said micro code to said control circuitry;

control program storage means external to said computer and having prerecorder thereon micro code necessary to execute said individual instruction statements;

switching and selection means having an input connected to said main storage means for receiving information for retrieving from said control program storage means said prerecorded instruction code corresponding to said instruction statements,

said switching and selection means having an output buss connected to said single read/write control storage means for transferring said prerecorded micro code from said control program storage means to said single read/write control storage means.

8. An electronic digital computer according to the combination of claim 7 wherein said general storage register means has a data transmission buss connected to the input of said single read/write control storage means for enabling the transfer of information from said general storage register means to said single read/write control storage means.

9. An electronic digital computer according to the combination of claim 7 wherein said switching and selection means has an input connected to said main storage means for enabling said switching and selection means to transfer information from said main storage means over said output buss to said single read/ write control storage means.

10. An electronic digital computer according to the combination of claim 7, wherein said control storage register means is connected to said general storage register means via said arithmetic means, switching and selection means for enabling the transfer of information from said control storage register means to general storage register means.

11. An eletrconic digital computer according to the combination of claim 7, wherein said control storage register means is connected to said arithmetic means for enabling the transfer of information from said control storage means to said arithmetic means.

12. An electronic digital computer according to the combination of claim 7 wherein said control storage register means is connected to said arithmetic means for enabling the transfer of information from said control storage register means to said arithmetic means for manipulation therein;

said arithmetic means is ocnnected to said general storage register means, for enabling the transfer of said manipulated information from said arithmetic means to said general storage register means; and

said general storage register means is connected to said single read/write control storage means, for enabling the transfer of said manipulated information from said general storage register means to said single read/ write control storage means.

13. In an electronic digital computer for executing electronic data processing tasks written in the form of a list of individual instruction statements, said computer including main storage means, input means, output means, general storage register means, arithmetic means, control means, control sequencing means and control circuitry, wherein the improvement is in said control means comprising:

control storage register means;

read/write control storage means having an input for receiving micro code necessary for the execution of said instruction statements, and an output connected to control storage register means for applying said micro code to said control circuitry;

switching and selection means having an input connected to said main storage means for receiving information to be used as micro code corresponding to said instruction statements,

said switching and selection means having an output buss connected to said read/write control storage means for transferring said micro code from said main storage means to said read/ write control storage means.

14. An electronic digital computer according to the combination of claim 13 wherein said general storage register means has a data transmission buss connected to the input of said read/ write control storage means for enabling the transfer of information from said general storage means to said read/ write control storage means.

15. An electronic digital computer according to the combination of claim 13, wherein said control storage register means is connected to said general storage register means by said arithmetic means, for enabling the transfer of information from said control storage register means to said general storage register means.

16. An electronic digital computer according to the combination of claim 13 wherein said control storage register means is connected to said arithmetic means, for enabling the transfer of information from said control storage register means to said arithmetic means.

17. An electronic digital computer according to the combination of claim 13 wherein said control storage register means is connected to said arithmetic means for enabling the transfer of information from said control storage register means to said arithmetic means for manipulation therein;

said arithmetic means is connected to said general storage register means, or enabling transfer of said manipulated information from said arithmetic means to said general storage register means; and

said general storage register means is connected to said read/write control storage means, for enabling the transfer of said manipulated information from said general storage register means to said read/ write control storage means. 18. In an electronic digital computer for executing electronic data processing tasks written in the form of a list of individual instruction statements, said computer including main storage means, input means, output means, general storage register means, arithmetic means, control means, control sequencing means, and control circuitry, wherein the improvement is in said control means comprising:

control storage register means; read-only control storage means containing micro code necessary for the execution of said instruction statements and having an output connected to said control storage register means for applying said micro code to said control circuitry; read/write control storage means having an input for receiving micro code necessary for the execution of said instruction statements and having an output connected to said control storage register means for applying said micro code to said control circuitry;

control program storage means external to said computer and having prerecorded thereon micro code necessary to execute said individual instruction statements;

switching and selection means having an input connected to said main storage means for receiving information for retrieving from said control program storage means said prerecorded instruction code corresponding to said instruction statements,

said switching and selection means having an output buss connected to said read/write control storage means for transferring said prerecorded micro code from said control program storage means to said read/ write control storage means.

19. An electronic digital computer according to the combination of claim 18, wherein said general storage register means has a data transmission buss connected to the input of said read/write control means for enabling the transfer of information from said general storage register means to said read/write control storage means.

20. An electronic digital computer according to the combination of claim 18, wherein said switching and selection means have an input connected to said main storage means for enabling said switching and selection means to transfer information from said main storage means over said output buss to said read/write control storage means.

21. An electronic digital computer according to the combination of claim 18, wherein said control storage register means is connected to said general storage register means via said arithmetic means for enabling the transfer of information from said control storage register means to said general storage register means.

22. An electronic digital computer according to the combination of claim 18, wherein said control storage register means is connected to said arithmetic means, for enabling the transfer of information from said control storage register means to said arithmetic means.

23. An electronic digital computer according to the combination of claim 18 wherein said control storage register means is connected to said arithmetic means for enabling the transfer of information from said control storage register means to said arithmetic means for manipulation therein;

said arithmetic means is connected to said general storage register means, for enabling the transfer of said manipulated information from said arithmetic means to said general storage register means; and said general storage register means is connected to said read/write control storage for enabling the transfer of said manipulated information from said 11 general storage register means to said read/ write con- 3,315,235 trol storage means. 3,325,788 3,343,141 References Cited 3,345,611 UNITED STATES PATENTS 5 giggg 3,258,748 6/1966 Schneberger et a1. 340 127.s 3,281,792 10/1966 Raymond 340 172.5

Carnevale et a]. 340172.5

Hack! 340-1725 Hackl 34()172.S

Tachus 340172.5 Ottaway et a1 340-4725 Amdahl et a1 340-172.5

JOHN P. VANDENBURG, Primary Examiner 333 UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION patent 3,478,322 Dated November 11, 1969 lnventofls) B. 0. Evans It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

Column 3, line 17 "oen" should read --one.

Column 4, line 38 "fonctions" should read functions.

Column 6, line 52 "or ROCS, or ECCS 1," should read -or ROCS, or ECCS l, or ECCS 2-.

Column 9, line 12 "ocnnected" should read -connected-; line 70 "means, or" should read -means for.

Signed and sealed this 20th day of April 1971.

(SEAL) Attest:

EDWARD I-I.FLETCHER, JR. WILLIAM E. SCHUYLER, JR. Attesting Officer Commissioner of Patents

US3478322A 1967-05-23 1967-05-23 Data processor employing electronically changeable control storage Expired - Lifetime US3478322A (en)

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Cited By (78)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3579192A (en) * 1967-11-02 1971-05-18 Burroughs Corp Data processing machine
US3686637A (en) * 1970-09-14 1972-08-22 Ncr Co Retail terminal
US3689893A (en) * 1969-05-09 1972-09-05 Olivetti & Co Spa Accounting machine processor
US3736563A (en) * 1970-03-31 1973-05-29 Siemens Ag Program control unit for a digital data processing installation
US3768075A (en) * 1969-10-25 1973-10-23 Philips Corp Extensible microprogram store
US3781807A (en) * 1969-01-20 1973-12-25 Olivetti & Co Spa Stored program electronic computer using macroinstructions
US3787817A (en) * 1972-06-21 1974-01-22 Us Navy Memory and logic module
US3792441A (en) * 1972-03-08 1974-02-12 Burroughs Corp Micro-program having an overlay micro-instruction
DE2339636A1 (en) * 1972-09-21 1974-04-04 Ibm Program control device
DE2357003A1 (en) * 1972-11-20 1974-05-22 Burroughs Corp programmable processor
US3938103A (en) * 1974-03-20 1976-02-10 Welin Andrew M Inherently micro programmable high level language processor
US3959774A (en) * 1974-07-25 1976-05-25 California Institute Of Technology Processor which sequences externally of a central processor
DE2547488A1 (en) * 1975-10-23 1977-04-28 Ibm Deutschland Micro-programmed data processing system
US4037202A (en) * 1975-04-21 1977-07-19 Raytheon Company Microprogram controlled digital processor having addressable flip/flop section
DE2717976A1 (en) * 1976-04-22 1977-11-03 Olivetti & Co Spa Computer with an arrangement for the alteration of the working environment of the computer
FR2386076A1 (en) * 1977-03-28 1978-10-27 Data General Corp computer firmware memory
US4342080A (en) * 1978-11-08 1982-07-27 Data General Corporation Computer with microcode generator system
EP0073419A2 (en) * 1981-08-24 1983-03-09 Itt Industries Inc. Dynamically programmable processing element
US4399505A (en) * 1981-02-06 1983-08-16 Data General Corporaton External microcode operation in a multi-level microprocessor
DE3303488A1 (en) * 1982-02-19 1983-09-01 Sony Corp Digital signal processing system
US4463419A (en) * 1980-09-29 1984-07-31 Nippon Electric Co., Ltd. Microprogram control system
US4510582A (en) * 1981-06-01 1985-04-09 International Business Machines Corp. Binary number substitution mechanism
US4531199A (en) * 1981-06-01 1985-07-23 International Business Machines Corporation Binary number substitution mechanism in a control store element
US4558411A (en) * 1969-05-19 1985-12-10 Burroughs Corp. Polymorphic programmable units employing plural levels of sub-instruction sets
US4740895A (en) * 1981-08-24 1988-04-26 Genrad, Inc. Method of and apparatus for external control of computer program flow
US4862351A (en) * 1983-09-01 1989-08-29 Unisys Corporation Method of executing called activities via depictor-linked low level language microcode, hardware logic, and high level language commands; and apparatus for same
US4870595A (en) * 1985-07-25 1989-09-26 Fanuc Ltd Numerical control equipment
US4920482A (en) * 1985-11-19 1990-04-24 Sony Corporation Multiple mode microprogram controller
WO1997041501A1 (en) * 1996-04-29 1997-11-06 Atmel Corporation Signal processing system and method with rom storing instructions encoded for reducing power consumption during reads
US5724534A (en) * 1993-06-30 1998-03-03 U.S. Philips Corporation Transferring instructions into DSP memory including testing instructions to determine if they are to be processed by an instruction interpreter or a first kernel
US5790874A (en) * 1994-09-30 1998-08-04 Kabushiki Kaisha Toshiba Information processing apparatus for reducing power consumption by minimizing hamming distance between consecutive instruction
US6081888A (en) * 1997-08-21 2000-06-27 Advanced Micro Devices Inc. Adaptive microprocessor with dynamically reconfigurable microcode responsive to external signals to initiate microcode reloading
US6157997A (en) * 1997-03-13 2000-12-05 Kabushiki Kaisha Toshiba Processor and information processing apparatus with a reconfigurable circuit
US20020053017A1 (en) * 2000-09-01 2002-05-02 Adiletta Matthew J. Register instructions for a multithreaded processor
US20020056037A1 (en) * 2000-08-31 2002-05-09 Gilbert Wolrich Method and apparatus for providing large register address space while maximizing cycletime performance for a multi-threaded register file set
US20030041216A1 (en) * 2001-08-27 2003-02-27 Rosenbluth Mark B. Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment
US20030110166A1 (en) * 2001-12-12 2003-06-12 Gilbert Wolrich Queue management
US20030115426A1 (en) * 2001-12-17 2003-06-19 Rosenbluth Mark B. Congestion management for high speed queuing
US20030115347A1 (en) * 2001-12-18 2003-06-19 Gilbert Wolrich Control mechanisms for enqueue and dequeue operations in a pipelined network processor
US20030131022A1 (en) * 2002-01-04 2003-07-10 Gilbert Wolrich Queue arrays in network devices
US20030131198A1 (en) * 2002-01-07 2003-07-10 Gilbert Wolrich Queue array caching in network devices
US20030145173A1 (en) * 2002-01-25 2003-07-31 Wilkinson Hugh M. Context pipelines
US20030147409A1 (en) * 2002-02-01 2003-08-07 Gilbert Wolrich Processing data packets
US6606704B1 (en) * 1999-08-31 2003-08-12 Intel Corporation Parallel multithreaded processor with plural microengines executing multiple threads each microengine having loadable microcode
US20030191866A1 (en) * 2002-04-03 2003-10-09 Gilbert Wolrich Registers for data transfers
US20040139290A1 (en) * 2003-01-10 2004-07-15 Gilbert Wolrich Memory interleaving
US20040205747A1 (en) * 2000-12-21 2004-10-14 Debra Bernstein Breakpoint for parallel hardware threads in multithreaded processor
EP1510915A1 (en) * 2003-08-26 2005-03-02 Siemens Aktiengesellschaft Apparatus and method to adapt a hardware platform to any application program
US6868476B2 (en) 2001-08-27 2005-03-15 Intel Corporation Software controlled content addressable memory in a general purpose execution datapath
US6876561B2 (en) 1999-12-28 2005-04-05 Intel Corporation Scratchpad memory
US6895457B2 (en) 1999-12-28 2005-05-17 Intel Corporation Bus interface with a first-in-first-out memory
US6934951B2 (en) 2002-01-17 2005-08-23 Intel Corporation Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section
US6976095B1 (en) 1999-12-30 2005-12-13 Intel Corporation Port blocking technique for maintaining receive packet ordering for a multiple ethernet port switch
US6983350B1 (en) 1999-08-31 2006-01-03 Intel Corporation SDRAM controller for parallel processor architecture
US7103759B1 (en) * 1999-10-28 2006-09-05 Imsys Technologies Ab Microcontroller architecture supporting microcode-implemented peripheral devices
US7111296B2 (en) 1999-12-28 2006-09-19 Intel Corporation Thread signaling in multi-threaded processor
US7126952B2 (en) 2001-09-28 2006-10-24 Intel Corporation Multiprotocol decapsulation/encapsulation control structure and packet protocol conversion method
US7191321B2 (en) 1999-08-31 2007-03-13 Intel Corporation Microengine for parallel processor architecture
US7191309B1 (en) 1999-09-01 2007-03-13 Intel Corporation Double shift instruction for micro engine used in multithreaded parallel processor architecture
US7213099B2 (en) 2003-12-30 2007-05-01 Intel Corporation Method and apparatus utilizing non-uniformly distributed DRAM configurations and to detect in-range memory address matches
US7225281B2 (en) 2001-08-27 2007-05-29 Intel Corporation Multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms
US7305500B2 (en) 1999-08-31 2007-12-04 Intel Corporation Sram controller for parallel processor architecture including a read queue and an order queue for handling requests
US7328289B2 (en) 1999-12-30 2008-02-05 Intel Corporation Communication between processors
US7337275B2 (en) 2002-08-13 2008-02-26 Intel Corporation Free list and ring data structure management
US7352769B2 (en) 2002-09-12 2008-04-01 Intel Corporation Multiple calendar schedule reservation structure and method
US7421572B1 (en) 1999-09-01 2008-09-02 Intel Corporation Branch instruction for processor with branching dependent on a specified bit in a register
US7433307B2 (en) 2002-11-05 2008-10-07 Intel Corporation Flow control in a network environment
US7434221B2 (en) 1999-12-30 2008-10-07 Intel Corporation Multi-threaded sequenced receive for fast network port stream of packets
US7443836B2 (en) 2003-06-16 2008-10-28 Intel Corporation Processing a data packet
US7471688B2 (en) 2002-06-18 2008-12-30 Intel Corporation Scheduling system for transmission of cells to ATM virtual circuits and DSL ports
US7480706B1 (en) 1999-12-30 2009-01-20 Intel Corporation Multi-threaded round-robin receive for fast network port
US7487505B2 (en) 2001-08-27 2009-02-03 Intel Corporation Multithreaded microprocessor with register allocation based on number of active threads
US7546444B1 (en) 1999-09-01 2009-06-09 Intel Corporation Register set used in multithreaded parallel processor architecture
US7610451B2 (en) 2002-01-25 2009-10-27 Intel Corporation Data transfer mechanism using unidirectional pull bus and push bus
US7620702B1 (en) 1999-12-28 2009-11-17 Intel Corporation Providing real-time control data for a network processor
US7751402B2 (en) 1999-12-29 2010-07-06 Intel Corporation Method and apparatus for gigabit packet assignment for multithreaded packet processing
USRE41849E1 (en) 1999-12-22 2010-10-19 Intel Corporation Parallel multi-threaded processing
US8738886B2 (en) 1999-12-27 2014-05-27 Intel Corporation Memory mapping in a processor having multiple programmable units

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4024504A (en) * 1973-12-21 1977-05-17 Burroughs Corporation Firmware loader for load time binding
FR2461301B1 (en) * 1978-04-25 1982-09-17 Cii Honeywell Bull
US4236210A (en) * 1978-10-02 1980-11-25 Honeywell Information Systems Inc. Architecture for a control store included in a data processing system
GB2161001B (en) * 1984-06-25 1988-09-01 Rational Distributed microcode address apparatus for computer

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3258748A (en) * 1962-01-08 1966-06-28 Fntan, fntin
US3281792A (en) * 1960-02-01 1966-10-25 Electronique & Automatisme Sa Electrical digital computers
US3315235A (en) * 1964-08-04 1967-04-18 Ibm Data processing system
US3325788A (en) * 1964-12-21 1967-06-13 Ibm Extrinsically variable microprogram controls
US3343141A (en) * 1964-12-23 1967-09-19 Ibm Bypassing of processor sequence controls for diagnostic tests
US3345611A (en) * 1959-09-30 1967-10-03 Honeywell Inc Control signal generator for a computer apparatus
US3391394A (en) * 1965-10-22 1968-07-02 Ibm Microprogram control for a data processing system
US3400371A (en) * 1964-04-06 1968-09-03 Ibm Data processing system

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3058659A (en) * 1958-12-31 1962-10-16 Ibm Add address to memory instruction
GB1020924A (en) * 1961-08-25
US3215987A (en) * 1962-06-04 1965-11-02 Sylvania Electric Prod Electronic data processing

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3345611A (en) * 1959-09-30 1967-10-03 Honeywell Inc Control signal generator for a computer apparatus
US3281792A (en) * 1960-02-01 1966-10-25 Electronique & Automatisme Sa Electrical digital computers
US3258748A (en) * 1962-01-08 1966-06-28 Fntan, fntin
US3400371A (en) * 1964-04-06 1968-09-03 Ibm Data processing system
US3315235A (en) * 1964-08-04 1967-04-18 Ibm Data processing system
US3325788A (en) * 1964-12-21 1967-06-13 Ibm Extrinsically variable microprogram controls
US3343141A (en) * 1964-12-23 1967-09-19 Ibm Bypassing of processor sequence controls for diagnostic tests
US3391394A (en) * 1965-10-22 1968-07-02 Ibm Microprogram control for a data processing system

Cited By (105)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3579192A (en) * 1967-11-02 1971-05-18 Burroughs Corp Data processing machine
US3781807A (en) * 1969-01-20 1973-12-25 Olivetti & Co Spa Stored program electronic computer using macroinstructions
US3689893A (en) * 1969-05-09 1972-09-05 Olivetti & Co Spa Accounting machine processor
US4558411A (en) * 1969-05-19 1985-12-10 Burroughs Corp. Polymorphic programmable units employing plural levels of sub-instruction sets
US3768075A (en) * 1969-10-25 1973-10-23 Philips Corp Extensible microprogram store
US3736563A (en) * 1970-03-31 1973-05-29 Siemens Ag Program control unit for a digital data processing installation
US3686637A (en) * 1970-09-14 1972-08-22 Ncr Co Retail terminal
US3792441A (en) * 1972-03-08 1974-02-12 Burroughs Corp Micro-program having an overlay micro-instruction
US3787817A (en) * 1972-06-21 1974-01-22 Us Navy Memory and logic module
DE2339636A1 (en) * 1972-09-21 1974-04-04 Ibm Program control device
DE2357003A1 (en) * 1972-11-20 1974-05-22 Burroughs Corp programmable processor
US3938103A (en) * 1974-03-20 1976-02-10 Welin Andrew M Inherently micro programmable high level language processor
US3959774A (en) * 1974-07-25 1976-05-25 California Institute Of Technology Processor which sequences externally of a central processor
US4037202A (en) * 1975-04-21 1977-07-19 Raytheon Company Microprogram controlled digital processor having addressable flip/flop section
DE2547488A1 (en) * 1975-10-23 1977-04-28 Ibm Deutschland Micro-programmed data processing system
DE2717976A1 (en) * 1976-04-22 1977-11-03 Olivetti & Co Spa Computer with an arrangement for the alteration of the working environment of the computer
US4179735A (en) * 1976-04-22 1979-12-18 Ing. C. Olivetti & C., S.P.A. Computer with an arrangement for changing its working environment
FR2386076A1 (en) * 1977-03-28 1978-10-27 Data General Corp computer firmware memory
US4342080A (en) * 1978-11-08 1982-07-27 Data General Corporation Computer with microcode generator system
US4463419A (en) * 1980-09-29 1984-07-31 Nippon Electric Co., Ltd. Microprogram control system
US4399505A (en) * 1981-02-06 1983-08-16 Data General Corporaton External microcode operation in a multi-level microprocessor
US4510582A (en) * 1981-06-01 1985-04-09 International Business Machines Corp. Binary number substitution mechanism
US4531199A (en) * 1981-06-01 1985-07-23 International Business Machines Corporation Binary number substitution mechanism in a control store element
US4740895A (en) * 1981-08-24 1988-04-26 Genrad, Inc. Method of and apparatus for external control of computer program flow
EP0073419A3 (en) * 1981-08-24 1984-07-25 Deutsche Itt Industries Gmbh Dynamically programmable processing element
EP0073419A2 (en) * 1981-08-24 1983-03-09 Itt Industries Inc. Dynamically programmable processing element
DE3303488A1 (en) * 1982-02-19 1983-09-01 Sony Corp Digital signal processing system
US4862351A (en) * 1983-09-01 1989-08-29 Unisys Corporation Method of executing called activities via depictor-linked low level language microcode, hardware logic, and high level language commands; and apparatus for same
US4870595A (en) * 1985-07-25 1989-09-26 Fanuc Ltd Numerical control equipment
US4920482A (en) * 1985-11-19 1990-04-24 Sony Corporation Multiple mode microprogram controller
US5724534A (en) * 1993-06-30 1998-03-03 U.S. Philips Corporation Transferring instructions into DSP memory including testing instructions to determine if they are to be processed by an instruction interpreter or a first kernel
US5790874A (en) * 1994-09-30 1998-08-04 Kabushiki Kaisha Toshiba Information processing apparatus for reducing power consumption by minimizing hamming distance between consecutive instruction
WO1997041501A1 (en) * 1996-04-29 1997-11-06 Atmel Corporation Signal processing system and method with rom storing instructions encoded for reducing power consumption during reads
US6157997A (en) * 1997-03-13 2000-12-05 Kabushiki Kaisha Toshiba Processor and information processing apparatus with a reconfigurable circuit
US6081888A (en) * 1997-08-21 2000-06-27 Advanced Micro Devices Inc. Adaptive microprocessor with dynamically reconfigurable microcode responsive to external signals to initiate microcode reloading
US8316191B2 (en) 1999-08-31 2012-11-20 Intel Corporation Memory controllers for processor having multiple programmable units
US6983350B1 (en) 1999-08-31 2006-01-03 Intel Corporation SDRAM controller for parallel processor architecture
US7305500B2 (en) 1999-08-31 2007-12-04 Intel Corporation Sram controller for parallel processor architecture including a read queue and an order queue for handling requests
US7424579B2 (en) 1999-08-31 2008-09-09 Intel Corporation Memory controller for processor having multiple multithreaded programmable units
US6606704B1 (en) * 1999-08-31 2003-08-12 Intel Corporation Parallel multithreaded processor with plural microengines executing multiple threads each microengine having loadable microcode
US7191321B2 (en) 1999-08-31 2007-03-13 Intel Corporation Microengine for parallel processor architecture
US7991983B2 (en) 1999-09-01 2011-08-02 Intel Corporation Register set used in multithreaded parallel processor architecture
US7546444B1 (en) 1999-09-01 2009-06-09 Intel Corporation Register set used in multithreaded parallel processor architecture
US7421572B1 (en) 1999-09-01 2008-09-02 Intel Corporation Branch instruction for processor with branching dependent on a specified bit in a register
US7191309B1 (en) 1999-09-01 2007-03-13 Intel Corporation Double shift instruction for micro engine used in multithreaded parallel processor architecture
US7103759B1 (en) * 1999-10-28 2006-09-05 Imsys Technologies Ab Microcontroller architecture supporting microcode-implemented peripheral devices
USRE41849E1 (en) 1999-12-22 2010-10-19 Intel Corporation Parallel multi-threaded processing
US8738886B2 (en) 1999-12-27 2014-05-27 Intel Corporation Memory mapping in a processor having multiple programmable units
US9128818B2 (en) 1999-12-27 2015-09-08 Intel Corporation Memory mapping in a processor having multiple programmable units
US9824037B2 (en) 1999-12-27 2017-11-21 Intel Corporation Memory mapping in a processor having multiple programmable units
US9824038B2 (en) 1999-12-27 2017-11-21 Intel Corporation Memory mapping in a processor having multiple programmable units
US9830284B2 (en) 1999-12-27 2017-11-28 Intel Corporation Memory mapping in a processor having multiple programmable units
US9830285B2 (en) 1999-12-27 2017-11-28 Intel Corporation Memory mapping in a processor having multiple programmable units
US6895457B2 (en) 1999-12-28 2005-05-17 Intel Corporation Bus interface with a first-in-first-out memory
US7111296B2 (en) 1999-12-28 2006-09-19 Intel Corporation Thread signaling in multi-threaded processor
US6876561B2 (en) 1999-12-28 2005-04-05 Intel Corporation Scratchpad memory
US7620702B1 (en) 1999-12-28 2009-11-17 Intel Corporation Providing real-time control data for a network processor
US7751402B2 (en) 1999-12-29 2010-07-06 Intel Corporation Method and apparatus for gigabit packet assignment for multithreaded packet processing
US6976095B1 (en) 1999-12-30 2005-12-13 Intel Corporation Port blocking technique for maintaining receive packet ordering for a multiple ethernet port switch
US7480706B1 (en) 1999-12-30 2009-01-20 Intel Corporation Multi-threaded round-robin receive for fast network port
US7434221B2 (en) 1999-12-30 2008-10-07 Intel Corporation Multi-threaded sequenced receive for fast network port stream of packets
US7328289B2 (en) 1999-12-30 2008-02-05 Intel Corporation Communication between processors
US20020056037A1 (en) * 2000-08-31 2002-05-09 Gilbert Wolrich Method and apparatus for providing large register address space while maximizing cycletime performance for a multi-threaded register file set
US7743235B2 (en) 2000-08-31 2010-06-22 Intel Corporation Processor having a dedicated hash unit integrated within
US7681018B2 (en) 2000-08-31 2010-03-16 Intel Corporation Method and apparatus for providing large register address space while maximizing cycletime performance for a multi-threaded register file set
US20020053017A1 (en) * 2000-09-01 2002-05-02 Adiletta Matthew J. Register instructions for a multithreaded processor
US7020871B2 (en) 2000-12-21 2006-03-28 Intel Corporation Breakpoint method for parallel hardware threads in multithreaded processor
US20040205747A1 (en) * 2000-12-21 2004-10-14 Debra Bernstein Breakpoint for parallel hardware threads in multithreaded processor
US7487505B2 (en) 2001-08-27 2009-02-03 Intel Corporation Multithreaded microprocessor with register allocation based on number of active threads
US20030041216A1 (en) * 2001-08-27 2003-02-27 Rosenbluth Mark B. Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment
US7216204B2 (en) 2001-08-27 2007-05-08 Intel Corporation Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment
US7225281B2 (en) 2001-08-27 2007-05-29 Intel Corporation Multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms
US7246197B2 (en) 2001-08-27 2007-07-17 Intel Corporation Software controlled content addressable memory in a general purpose execution datapath
US6868476B2 (en) 2001-08-27 2005-03-15 Intel Corporation Software controlled content addressable memory in a general purpose execution datapath
US7126952B2 (en) 2001-09-28 2006-10-24 Intel Corporation Multiprotocol decapsulation/encapsulation control structure and packet protocol conversion method
US7158964B2 (en) 2001-12-12 2007-01-02 Intel Corporation Queue management
US20030110166A1 (en) * 2001-12-12 2003-06-12 Gilbert Wolrich Queue management
US20030115426A1 (en) * 2001-12-17 2003-06-19 Rosenbluth Mark B. Congestion management for high speed queuing
US7107413B2 (en) 2001-12-17 2006-09-12 Intel Corporation Write queue descriptor count instruction for high speed queuing
US20030115347A1 (en) * 2001-12-18 2003-06-19 Gilbert Wolrich Control mechanisms for enqueue and dequeue operations in a pipelined network processor
US7269179B2 (en) 2001-12-18 2007-09-11 Intel Corporation Control mechanisms for enqueue and dequeue operations in a pipelined network processor
US7895239B2 (en) 2002-01-04 2011-02-22 Intel Corporation Queue arrays in network devices
US20030131022A1 (en) * 2002-01-04 2003-07-10 Gilbert Wolrich Queue arrays in network devices
US8380923B2 (en) 2002-01-04 2013-02-19 Intel Corporation Queue arrays in network devices
US20030131198A1 (en) * 2002-01-07 2003-07-10 Gilbert Wolrich Queue array caching in network devices
US7181573B2 (en) 2002-01-07 2007-02-20 Intel Corporation Queue array caching in network devices
US6934951B2 (en) 2002-01-17 2005-08-23 Intel Corporation Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section
US7302549B2 (en) 2002-01-17 2007-11-27 Intel Corporation Processing packet sequence using same function set pipelined multiple threads spanning over multiple processing engines and having exclusive data access
US7181594B2 (en) 2002-01-25 2007-02-20 Intel Corporation Context pipelines
US7610451B2 (en) 2002-01-25 2009-10-27 Intel Corporation Data transfer mechanism using unidirectional pull bus and push bus
US20030145173A1 (en) * 2002-01-25 2003-07-31 Wilkinson Hugh M. Context pipelines
US20030147409A1 (en) * 2002-02-01 2003-08-07 Gilbert Wolrich Processing data packets
US7149226B2 (en) 2002-02-01 2006-12-12 Intel Corporation Processing data packets
US20030191866A1 (en) * 2002-04-03 2003-10-09 Gilbert Wolrich Registers for data transfers
US7437724B2 (en) 2002-04-03 2008-10-14 Intel Corporation Registers for data transfers
US7471688B2 (en) 2002-06-18 2008-12-30 Intel Corporation Scheduling system for transmission of cells to ATM virtual circuits and DSL ports
US7337275B2 (en) 2002-08-13 2008-02-26 Intel Corporation Free list and ring data structure management
US7352769B2 (en) 2002-09-12 2008-04-01 Intel Corporation Multiple calendar schedule reservation structure and method
US7433307B2 (en) 2002-11-05 2008-10-07 Intel Corporation Flow control in a network environment
US20040139290A1 (en) * 2003-01-10 2004-07-15 Gilbert Wolrich Memory interleaving
US7418571B2 (en) 2003-01-10 2008-08-26 Intel Corporation Memory interleaving
US6941438B2 (en) 2003-01-10 2005-09-06 Intel Corporation Memory interleaving
US7443836B2 (en) 2003-06-16 2008-10-28 Intel Corporation Processing a data packet
EP1510915A1 (en) * 2003-08-26 2005-03-02 Siemens Aktiengesellschaft Apparatus and method to adapt a hardware platform to any application program
US7213099B2 (en) 2003-12-30 2007-05-01 Intel Corporation Method and apparatus utilizing non-uniformly distributed DRAM configurations and to detect in-range memory address matches

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DE1774296C2 (en) 1986-11-13 grant
GB1154299A (en) 1969-06-04 application
NL6806737A (en) 1968-11-25 application
DE1774296A1 (en) 1971-08-19 application
DE1774296B2 (en) 1979-08-02 application
NL159209B (en) 1979-01-15 application
FR1558879A (en) 1969-02-28 grant

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