US3428946A - Means for merging data - Google Patents

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US3428946A
US3428946A US3428946DA US3428946A US 3428946 A US3428946 A US 3428946A US 3428946D A US3428946D A US 3428946DA US 3428946 A US3428946 A US 3428946A
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data
order
sequence
means
datum
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Kenneth E Batcher
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Goodyear Aerospace Corp
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Goodyear Aerospace Corp
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/15Interconnection of switching modules
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/22Arrangements for sorting or merging computer data on continuous record carriers, e.g. tape, drum, disc
    • G06F7/32Merging, i.e. combining data contained in ordered sequence on at least two record carriers to produce a single carrier or set of carriers having all the original data in the ordered sequence merging methods in general
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/22Arrangements for sorting or merging computer data on continuous record carriers, e.g. tape, drum, disc
    • G06F7/36Combined merging and sorting
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/40Physical details, e.g. power supply, mechanical construction or backplane
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S707/00Data processing: database and file management or data structures
    • Y10S707/99931Database or file accessing
    • Y10S707/99937Sorting

Description

KENNETH E. BATCHER mlm..

ATTGRNEYS Feb. 18, 1969 I E. BATcI-IER 3,428,946

MEANS FDR MERDING DATA Filed Sept. 19, 1967 Sheet C c!" HOLDING MEANS 50j 'L Code AMW H A II i* w w H- mwN-hm New YORK s `I Ian .L L f, LL .L HN LME H E H E+ cI-IIcAso 7 Lw., H\L H L V H .L y. L, CLEVELAND e D-- L f W L -IxIf LLw E H Los ANGELES 5 j* ICsIIad y EU M HLA-1 H W-JII H I A- DETROIT 4 f'cmes I L L i H" E L-m H H PHILADELPHIA 3 I G.V HVX. H LN" H v y L 'Y L ST. LOUS 2 l H L Y---` i W# -ff DALLAS l /J L-TELEGRAPH LINE INPuTs 151 |9 MEM I A I L 2|I 2e LL L MEL 2O I Ie "EDEN I l I w y I Fb* 22? I LLLLA I I I 275 I "-L n II Lnwd 7 v 243 cLocK .*2 I

Y I A l 252 RESET INVENTOR KENNETH E 5A TG5/: P

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ATTORNEYS Feb. 18, 1969 K. E. aATcHl-:R 3,428,946

MEANS FOR MERGING DATA :NvENToR KENNETH E BATCH/:7?

ATTORNEYS mvsmon KENNETH E. BA TCHE/w BYI www.

ATTORNEYS United States Patent Ofice 3,428,946 Patented Feb. 18, 1969 3,428,946 MEANS FOR MERGING DATA Kenneth E. Batcher, Akron, Ohio, assignor to Goodyear Aerospace Corporation, Akron, Ohio, a corporation of Delaware i Continuation-impart of application Ser. No. 482,695, Aug. 26, 1965. This application Sept. 19, 1967, Ser. No. 668,809 U.S. CI. 34th-146.2 5 Claims Int. Cl. G08b 5/00 ABSTRACT 0F THE DISCLOSURE This invention relates to a merging means, and more particularly to a unique arrangement of basic elements each adapted to receive two data, compare their magnitudes, and present the greater ofthe two at one output, the lesser at another output, and whereby data in random order, or ordered sequences of various numbers, can be arranged into one sequence in ascending order.

It is a continuation-in-part of patent application Ser. N0. 482,695, led Aug. 26, 1965.

Heretofore, it has been well known that there have been many and various types of merging means adapted to merge groups of numbers, but these prior art systems have been unduly cumbersome, extremely expensive, dilicult to construct, and requiring many cornponents. Various of these prior art method are mentioned in the parent application.

lt is the general object of the present invention to overcome the detects in the prior art, and to provide an improvement in the apparatus defined in the parent application by providing a sorting and/or merging work which can effectively arrange randomly presented data into sequence.

A further object of the invention is to provide a network wherein positive completion of the comparison circuits can be selectively incorporated to facilitate the circuit for adaptation to selective circuit switching and control, rather than arrangement of data into merged sequences.

A further object of the invention is to provide an alternative merging network which is not limited to input sets of sequentially arranged data of fixed size but rather can be used to merge any two sets of sequentially arranged data of any size as long as the total number of data items does not exceed a predetermined limit.

For a better understanding of the invention reference should be had to the accompanying drawings wherein:

FIG. l is a schematic illustration of a basic comparison element to arrange two random input data into known ascending order;

FIG. 2 is a schematic block diagram of five of the eley ments of FIG. 1 arranged to merge four data at random into one group of four data in ascending order;

FIG. 3 is a schematic block diagram utilizing the basic components taught by FIG. l to `arrange eight data at random into one group of data in ascending order;

FIG. 4 is a schematic block diagram illustrating the same merging ability as FIG. 3 except broken down to illustrate how the random data are rst arranged into ascending groups and the ascending groups then merged into a single ascending group;

FIG. 5 illustrates the basic block diagram of FIGS. 3 and 4 with the incorporation of holding means and application to a practical usage in a telegraph network;

FIG. 6 illustrates a basic comparison element utilizing NOR logic elements; and

FIG. 7, 8 and 9 illustrate schematic block diagrams of novel merging networks.

There are many basic elements which will compare two data and present the highest of the two on one output, the lowest on another output. For example, if the data are represented by analog voltages, then a well known diode bridge circuit can be used to arrange them in the desired order. lf the data are represented by digital numbers there are well known logic circuits existing for cornparing such number representations and presenting the higher on one output, the lower on another. For example, the circuit of FIG. 6 would meet these requirements if the bits of the numbers are presented sequentially, mostsignicant bit rst.

The operation of the logic circuit of FIG. 6 is as follows. It consists of thirteen NOR logic elements. (The output of a NOR logic element is a zero level if one or more of its inputs has a one level and the output is a one level if all the inputs have zero levels.)

The clock input 24 is for the purpose of disabling the levels on wires 11 and 12 during the transients of levels applied to the A(26) and B(27) input terminals. A one level is applied to the clock input 24 during transients and a zero level is applied when the A and B inputs, 26 and 27 wires 15, 16, 17, 18, 19, 20, and 21 all have steady levels.

Initially the circuit is put in the reset state by applying a one pulse to the reset input 25. This puts one levels on wires 17 and 18 and zero levels on wires 15, 16, 22 and 23.

Then the bits of one of the numbers to be compared are applied, one at a time, most-significant bit rst, to input A(26) while the corresponding bits of the other number are applied to input B(27). A zero pulse is applied to the clock input 24 for each bit applied to input A after the circuit levels have steadied.

As long as each bit applied to input A equals the corresponding bit applied to input B wires 29, 19 and 20 will have levels opposite that of the input bits, wires 28 and 21 will have the same levels as the inputs, and wires 11, 12, 15 and 16 remain at the zero level while wires 17 and 18 remain at the one level. Thus the bits seen on the H(28) and L(21) inputs will be the same as the input bits and in the same sequence.

If the two numbers being compared differ then the following action occurs the first time that the input A bit differs from the input B bit. Wire 29 has a zero level since one of the input bits is a one and the H output (wire 28) has a one level. Wires 19 and 20 will be at opposite levels so the L output (wire 21) has a zero level. When the clock input changes to zero either wire 11 or wire 12 will change to the one level. If the input A bit is one and the input B bit is zero then wire 12 changes to the one level with the clock pulse and wires 17 and 15 will change to the zero and one levels, respectively. The circuit is then in the A greater than B" state. Conversely, if the input A bit is zero and the input B bit is one, then wire 11 changes to the one level with the clock pulse and wires 18 and 16 change to the zero and one levels, respectively. The circuit is then in the A less than B state.

It the circuit is in the A greater than B" state it will remain in the A greater than B" state for all succeeding bits until another reset pulse is applied. During this time the wire 22 level will be opposite that of the input A bits and the H output (wire 28) level will be the same as that of the input A bits. The wire 20 level will be opposite that of input B and the L output (wire 21) will be the same as that of input B. Wires 11, 19, 23, 16, and 17 stay in the zero state and wires 1S and 18 stay in the one state.

Similarly, if the circuit is in the A less than B state it will stay in that state until another reset pulse is applied. The H output (wire 28) level will be the same as the input B level and the L output (wire 2l) level will be the same as the input A level.

It is a well-known property of binary numbers that to compare two numbers one merely has to observe the mostsignificant place where the two numbers disagree. The number with the one bit in this place is higher than the number with the zero bit in this place. Thus the comparison circuit described above will put the bits of the higher number on its H output and the bits of the lower number on its L output. The bits are put out in the same sequence as the input numbers; one at a time, mostsignicant bit first.

A circuit such as that of FIG. 6 which compares two data and presents the higher on one output and the lower on another output is called hereinafter a comparison circuit. In the figures (see FIG. l) it is represented by a block 10 with two inputs and two outputs. The higher output is labeled H while the lower output is labeled L. If the two data to be compared happen to be equal then it is immaterial which of the data is presented on which output.

In order to sort or arrange into order four random data A, B, C, and D, a circuit such as that illustrated in FIG. 2 is utilized. In the rst level or first tier 12A any two numbers are compared in elements 14A and 16A to provide outputs now arranged in ascending order as desired. In the second tier indicated by dotted block 18A the highest output of the first `merge in the first tier 12A is compared with the highest output of the second merge. Similarly, the lower output from the first merge is compared with the lower output from the second merge. This automatically provides the highest and lowest values. Then, by simply comparing the lower output of the first merge in the second tier 18A with the higher output of the second merge in the second tier 18A, the determined order of the four data is achieved. In other words, the rule to be followed in the second tier is that the second output of the first merge, namely output 20A is combined with the first output of the second merge, namely output 22A, in an element 24A. These outputs, in combination with the outputs 26A and 28A from elements 30 and 32, respectively, arrange the random data into ascending order C1 through C4. This can be called a four-item sorting network.

FIG. 3 illustrates the arrangement of eight data at random designated A through H into sequential order. Essentially, two of the circuits of FIG. 2 are utilized as indicated by dotted blocks 34 and 36. The resultant outputs from these four-item sorting networks are then arranged in sequential order. These outputs are fed to a four by four merging network indicated by dotted block 38. In effect the highest output from block 34 is compared with the highest output from block 36 and so on in the first tier 40 of block 38. This then automatically produces the highest and lowest outputs. Considering the top two elements in the first tier as the first merging group, and the bottom two elements as the second merging group the resultant outputs `from the merges in both groups are then sent to a second tier of elements 42 where the general rule set forth above is followed. Specifically, the lower output of the first merge in the first group is compared to the higher output of the second merge in the first group while the same process takes place in the second group. The invention then contemplates a third tier 44 wherein the following merges or comparisons take place. Specifically, the first element merges the higher of the first group second merge to the higher of the second group first merge. The second element merges the lower of the first group second merge to the higher of the second group second merge, and the third element merges the lower of the first group second merge to the lower of the second group second merge. This then results in a complete arrangement of the random data A through H into arranged data C1 through C8. This is called an eight-item sorting network.

In general, a sorting network for any given number of items can be constructed by dividing the plurality of items to be sorted into two groups of approximately equal size, using two sorting means to arrange each group into monotonic order and using the merging means of the parent application to merge the two ordered pluralities into one ordered plurality. Each of the sorting means for each of two groups can in turn be constructed by dividing each group into two smaller groups and using the same principle of sorting each smaller group separately and using the merging means of the parent application to merge the two ordered smaller groups into one ordered group. By us-V ing this same principle over and over a sorting network for any number of items can eventually be reduced to the case of sorting several groups each with one or two datums. A two-item group can be sorted by a comparison element (FIG. 1) while a one-item group needs no sorting. Thus, several of the merging means of the parent application can be used to effect a sorting means for any given number of items.

FIG. 4 illustrates the same element arrangement as FIG. 3 except that it is illustrated how the eight random data are first broken into two groups of four in arranged sequence and then merged into a single sequence. These basic structural components to merge two with two or four with four can then be used to build any size data arrangement circuit and merging circuit with a small number of comparison elements.

The invention contemplates that if this same circuit is utilized with holding means incorporated in the comparison elements, a very practical, and flexible circuit arrangement can `be achieved. Specifically, this set up is illustrated in FIG. 5 and indicates the holding means by numeral 50 associated with each tier of elements in the circuit network. For practical purposes, this circuit is illustrated as a telegraph line connection circuit for connecting eight telegraph lines to various cities in a random arrangement over the same circuit pattern.

Each city is given a code number and connected to one side of the network in the order of their code numbers. Specifically, if it is desired to connect telegraph line A to Los Angeles, line B to Chicago, line C to Cleveland, line D to Detroit, line E to Dallas, line F to Philadelphia, line G to St. Louis, and line H to New York, then each line should first send the code number for the specific city it is calling, that is, line A sends Code 5, line B sends Code 7, line C sends Code 6, line D sends Code 4, line E sends Code 1, line F sends Code 3, line G sends Code 2, and line H sends Code 8. The network of comparison elements with holding means 50 will order the codes so each code arrives at the right end of the network on the line connected to its corresponding city. The holding means preserve the paths each code took through the network allowing tele-graph messages to be sent from each line to its called city. When a change is desired the code numbers on the telegraph lines are changed and all codes sent in again after the holding means 50 are released to permit the network to change state, for example if after the aforementioned connection it is desired to connect line A to Philadelphia and line F to Los Angeles keeping all other connections fixed then the code numbers on lines A and F are changed to 3 `and 5, respectively, and all code numbers sent into the network again. This will effect the desired change. The comparison element of FIG. 6 has holding means already incorporated in. After comparing the two numbers presented serially over inputs A(26) and B(27) and presenting the lower number on output L(21) and the higher number on output H(28) the circuit will remain in the A greater than B state or the A less than B state until a reset pulse is applied as described in the circuit description above; thus it can hold the paths the numbers took through the element and allow other data such as telegraph messages to be transmitted over the same paths.

It is readily seen that a mere instantaneous switching of the code numbers and the holding means in association with the elements will allow very rapid circuit changes to connect desired calling cities to connection cities, providing a considerable lmprovement in the present telegraph switchboard design.

To help describe `an alternative construction of a merging means the following definition must be understood:

A sequence of data is said to be bi-tonie if it satisfies at least one of the following five conditions:

(l) It consists of an aseendingly-ordered part followed by a deseendingly-ordered part.

(2) It consists of a descendingly-ordered part followed by an ascendingly-ordered part.

(3) It consists of an ascendingly-ordered part followed by a descendingly-ordered part followed by an aseendingly-ordered part in which the last datum is not greater than the first datum.

(4) It consists of a descendingly-ordered part followed by an ascendingly-ordered part followed by a descendingly-ordered part in which the last datum is not less than the first datum.

(5) It is monotonie.

It should be understood that one or more of the sequence parts in the definition may consist of only one datum and a onedatum part is regarded to be both ascendingly-ordered and descendingly-ordered.

As an example, the sequence S, 9, 12, l5, 20, 19, 7, 2, 3. 4 is bi-tonic since it satisfies condition (3) while if the first datum in this sequence was a l instead of a 5 then the sequence would not be bi-tonic since 4 is greater than 1.

If we divide the example sequence into two parts:

5, 9, 12, 15, and

and compare corresponding items in the two parts, i.e., 5 with 19, 9 `with 7, l2 with 2, l5 with 3, and 20 with 4, and if we interchange the items of any corresponding pair where the item in the second half is less than the corresponding item in the first half, we obtain the two sequences 5, 7, 2, 3, 4 and 19, 9, 12, 15, 20. Notice that both of these sequences are bi-tonic and furthermore that the greatest item in the first half (7) is not more than the least item in the second half (9). This holds true for any bi-tonic sequence of an even number of data. When a bitonic sequence of an even number of data is split into a first half and a second half and corresponding items in the halves interchanged wherever the datum in the second half is less than the corresponding datum in the first half, the two halves are each bi-tonic and the greatest datum in the first half is never more than the least datum in the second half. Thus, to arrange such a `bi-tonic belongs in the first half of the final monotonie order. The

fact that each of these halves is also bi-tonie can be used to help arrange 'each of these halves in monotonie order if the halves contain an even number of data since they in turn can be split in halves (quarters of the original sequence) and comparisons and interchanges made between their halves to obtain four quarters of the original sequence wherein each datum in a quarter belongs in the same quarter in the final monotonie order. The quarters are bi-tonic so the process could be repeated if each quarter contains an even number of data.

If the number of data in the original sequence is an exact power of two the above process could be iterated fully to arrange the data in monotonie order. If the number of data is not a power of two dummy data could be added to the sequence to round it out to a power of two, the sequence arranged in monotonie order by the above process and the dummy data removed. The dummy data has to be of such magnitude as to preserve the bitonic property of the original sequence.

FIG, 7 illustrates the construction of a means for arranging a bi-tonic sequence of four data into monotonie order using comparison elements as taught in FIG. l. The bitonic sequence, a1, a2, a3, a4 is placed on the input lines and comparison elements 101 and 102 compare datum a1 (the first datum of the first half of the sequence) with datum a3 (the first datum of the second half) and datum a2 with datum n.1 (the second data in each of the two halves). The data on the L outputs of elements 101 and 102 are compared in element 103 to place them in monotonie order and form the first half of the final monotonie order, c1 and c2. The data on the H outputs of elements 101 and 102 are compared in element 104 to form the second half of the final monotonie orde, c3 and c4.

FIG. 8 illustrates the construction of a means for arranging an 8-datum bi-tonic sequence into monotonie order using the elements taught in FIG. l and the construction taught in FIG. 7. The bi-tonic sequence, a1, a2, a3, a4, a5, a6, a7, a8 is placed on the input lines, cornparison elements 110, 111, 112, and 113 compare datum a1 with datum a5, datum a2 with datum as, datum a3 with datum a, and datum a4 with datum a, respectively. A construction as taught in FIG. 7 enclosed in dotted box 114 in FIG. 8 is used to arrange the 4-datum bi-tonic sequence on the L outputs of comparison elements 110, 111, 112, and 113 into monotonie order to form the first half, c1, c2, c3, c4 of the final monotonie order, Similarly dotted box 115, also a construction of FIG. 7, arranges the data on the H outputs of comparison elements 110, 11.1, 112, and 113 into monotonie order to form the second half, c5, c6, c7, and c3 of the final monotonie order.

FIG. 9 illustrates the construction of a means for arranging a l6-datum bi-tonic sequence, a1, a2, a3, a4, a5, as, 117, as, Us, aro, a11, t11a, a13, 014, 115, 11e into mOflOOllC order using the comparison elements taught in FIG. l and the construction of FIG. 8. Comparison elements through 127, inclusive compare corresponding data in the first and second half of the sequence, that is, element 120 compares a1 with a9, element 121 compares a2 with am, etc. A construction taught in FIG. 8 shown in dotted box 128 of FIG. 9 arranges the S-datum bitonic sequence on the L outputs of comparison elements 120 through 127, inclusive, into monotonie order to form the first half, c1, c2, e3, c4, c5, c6, c1, cs of the final monotonic order. Similarly the second half, C9, C10, C11, C12, C13, C14, C15, C15 of the final monotonie order is formed by another eonstruction of FIG. 8, dotted box 129 of FIG. 9, from the S-datum bi-tonic sequence on the H outputs of comparison elements 120 through `127, inclusive.

FIGS. 7, 8, and 9 are examples of the general rule to be followed to construct a means for arranging a bi-tonic sequence with a number of data equal to a power of two into monotonie order. The general rule is to use comparison elements, such as that of FIG. l, to compare corresponding data in the first and second half of the sequence group the data appearing on the L outputs of the comparison elements to form a bi-tonie sequence of half as many data as the original sequence, arrange this sequence into monotonie order to form the first half of the final monotonie order and similarly group the data on the H outputs of the comparison elements and arrange this sequence into monotonie order to form the second half of the final monotonie order.

A means for arranging bi-tonic sequences into monotonic order can be used as a merging means to merge two ordered sequences into one ordered sequence by inverting one of the two ordered input sequences so that one is in ascending order and the other is in descending order and then placing the two sequences together to form a bi-tonic sequence which can then be arranged into monotonie order. If the total number of data is not an exact power of two dummy data can be added to the sequence to make it an exact power of two. To preserve the bi-tonic property of the sequence, each dummy datum should either equal the smallest possible datum, if the second sequence is in decreasing order, or equal the largest possible datum if the second sequence is in increasing order. After the sequence is put in monotonie order all such dummy data will be either at the start or the end of the sequence since they equal either the smallest possible datum or the largest possible datum and the dummy data can be easily removed.

A merging means which first forms a bitonic sequence and then arranges the bitonic sequence into monotonie order is hereinafter called a bitonic merging means. They have the advantage over the merging means taught in the above-identified parent application of flexibility, that is, the same construction can be used to merge any two ordered sequences as long as the total number of data can be handled. For example, the construction of FIG. 9 can be used to merge an 8-datum sequence with an 8- datum sequence, or a 10-datum sequence with a 6-datum sequence, etc. The construction taught in the parent application would have to be changed every time the number of data in either sequence changes. This advantage is counterbalanced by the fact that more comparison elements are used in bitonic merging means. For example, the construction of the parent application for a merge of 8-datum and 8-datum requires only 25 comparison elements while the bitonic merging means of FIG. 9 uses 32 comparison elements.

Bitonic merging means can be used in place of the merging means of the parent application in the sorting means and communication networks set forth with reference to FIG. 5 above since they are alternative constructions of merging means using the same comparison elements.

While in accordance with the patent statutes only one best known embodiment of the invention has been illustrated and described in detail, it is to be particularly understood that the invention is not limited thereto or thereby.

What is claimed is:

1. A means for arranging into monotonie order a sequence of an even number of eight or more data initially arranged into an ascendingly-ordered part followed by a descendingly-ordered part, or into a descendingly-ordered part followed by an ascendingly-ordered part, or into an aseendingly-ordered part followed by descendingly-ordered part followed by an ascendingly-ordered part in which the last datum in the sequence is not greater than the first datum in the sequence, or into a descendingly-ordered part followed by an ascendingly-ordered part followed by a descendingly-ordered part in which the last datum is not less than the rst datum in the sequence, or into monotonie order which consists of a first plurality of electrical means for sorting or arranging into monotonie order the first, third, fifth,

and so on items of the plurality with each other, a second plurality of electrical means for sorting or arranging into monotonie order the second, fourth,

sixth, and so on items of the plurality with each other, and a third plurality of electrical means for comparing,

the least item of those treated by the rst means to the least item of those treated by the second means and placing the two items in order in the least and second least places of the final monotonie order, the second least item of those treated by the first means to the second least item of those treated by the second means and placing the two items in order in the third least and forth least places of the final monotonie order, the third least item of those treated by the first means to the third least item of those treated by the second means and placing the two items in order in the fifth least and sixth least places of the nal monotonie order and so on, until each item treated by the first means is compared to a corresponding item treated by the second means and is placed together with its corresponding item in order in the final monotonie order.

2. A means according to claim 1 where the two parts of the even plurality are initially arranged in just the reverse order.

3. A means for sorting or arranging into monotonie order a randomly-ordered plurality of ten or more data according to claim `1 which includes a primary means for arranging into monotonie order part of the randomly-ordered plurality,

a secondary means for arranging into monotonie order that part of the randomly-ordered plurality not treated by the primary means, and

a merging means according to claim l to arrange the ordered data of the primary means with the ordered data of the secondary means to arrange all data in monotonie order.

4. A means according to claim 3 where the elements include holding means to preserve the paths the data took through the network so that other data may be transmitted over the same paths in any direction.

5. A network according to claim 3 where the relay holds function on the driving of a clock pulse, and a reset pulse is provided to allow resetting of the elements when desired.

References Cited UNITED STATES PATENTS 3,015,089 12/1961 Armstrong 340-1725 MALCOLM A. MORRISON, Primary Examiner.

DAVID H. MALZAHN, Assistant Examiner.

U.S. C1. X.R.

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Cited By (36)

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US3685024A (en) * 1970-11-02 1972-08-15 Singer Co Two stage sorting system using two-line sorting switches
US3696343A (en) * 1971-07-29 1972-10-03 Ibm Method of merging data on a two tape drive system
US3740538A (en) * 1971-07-28 1973-06-19 Us Air Force Digital sorter and ranker
US3750111A (en) * 1972-08-23 1973-07-31 Gte Automatic Electric Lab Inc Modular digital detector circuit arrangement
US3775753A (en) * 1971-01-04 1973-11-27 Texas Instruments Inc Vector order computing system
US3781822A (en) * 1972-08-09 1973-12-25 Bell Telephone Labor Inc Data rate-changing and reordering circuits
US4030077A (en) * 1975-10-16 1977-06-14 The Singer Company Multistage sorter having pushdown stacks for arranging an input list into numerical order
US4135248A (en) * 1977-10-11 1979-01-16 Westinghouse Electric Corp. Median extractor
US4210961A (en) * 1971-10-08 1980-07-01 Whitlow Computer Services, Inc. Sorting system
US4321670A (en) * 1975-07-31 1982-03-23 Schlumberger Technology Corporation Method of merging information on storage media
US4410960A (en) * 1980-02-05 1983-10-18 Nippon Electric Co., Ltd. Sorting circuit for three or more inputs
US4439840A (en) * 1981-09-28 1984-03-27 Hughes Aircraft Company Real-time ordinal-value filters utilizing partial intra-data comparisons
US4441165A (en) * 1981-09-28 1984-04-03 Hughes Aircraft Company Real-time ordinal-value filters utilizing complete intra-data comparisons
US4456968A (en) * 1981-09-28 1984-06-26 Hughes Aircraft Company Real-time ordinal-value filter utilizing half-interval ranking
US4472801A (en) * 1983-03-28 1984-09-18 At&T Bell Laboratories Distributed prioritized concentrator
WO1984004015A1 (en) * 1983-03-28 1984-10-11 American Telephone & Telegraph A self-routing switching network
WO1984004011A1 (en) * 1983-03-28 1984-10-11 American Telephone & Telegraph A wideband digital switching network
US4498189A (en) * 1981-02-18 1985-02-05 Nippon Electric Co., Ltd. Comparator suitable for a character recognition system
US4531209A (en) * 1983-03-28 1985-07-23 At&T Bell Laboratories Self-routing steering network
EP0186595A2 (en) * 1984-12-24 1986-07-02 SGS-THOMSON MICROELECTRONICS, INC. (a Delaware corp.) Routing technique
EP0186589A2 (en) * 1984-12-24 1986-07-02 SGS-THOMSON MICROELECTRONICS, INC. (a Delaware corp.) Routing element
US4628483A (en) * 1982-06-03 1986-12-09 Nelson Raymond J One level sorting network
US4679190A (en) * 1986-04-28 1987-07-07 International Business Machines Corporation Distributed voice-data switching on multi-stage interconnection networks
US4797880A (en) * 1987-10-07 1989-01-10 Bell Communications Research, Inc. Non-blocking, self-routing packet switch
US4890220A (en) * 1984-12-12 1989-12-26 Hitachi, Ltd. Vector processing apparatus for incrementing indices of vector operands of different length according to arithmetic operation results
US4891803A (en) * 1988-11-07 1990-01-02 American Telephone And Telegraph Company Packet switching network
US4905224A (en) * 1987-09-30 1990-02-27 Siemens Aktiengesellschaft Sorting unit for a switching node comprising a plurality of digital switching matrix networks for fast, asynchronous packet switching networks
US4910730A (en) * 1988-03-14 1990-03-20 Bell Communications Research, Inc. Batcher-banyan network
US4970637A (en) * 1987-06-22 1990-11-13 Kabushiki Kaisha Toshiba Digital anti-aliasing filter
US5043980A (en) * 1988-03-14 1991-08-27 Bell Communications Research, Inc. Switching cell for packet switching network
US5091848A (en) * 1987-04-10 1992-02-25 Hitachi, Ltd. Vector processor for merging vector elements in ascending order merging operation or descending order merging operation
US5287347A (en) * 1992-06-11 1994-02-15 At&T Bell Laboratories Arrangement for bounding jitter in a priority-based switching system
US5293489A (en) * 1985-01-24 1994-03-08 Nec Corporation Circuit arrangement capable of centralizing control of a switching network
US5455701A (en) * 1991-09-16 1995-10-03 At&T Corp. Packet switching apparatus using pipeline controller
US5721809A (en) * 1995-05-12 1998-02-24 Lg Semicon Co., Ltd. Maximum value selector

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Cited By (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3685024A (en) * 1970-11-02 1972-08-15 Singer Co Two stage sorting system using two-line sorting switches
US3662402A (en) * 1970-12-04 1972-05-09 Honeywell Inf Systems Data sort method utilizing finite difference tables
US3775753A (en) * 1971-01-04 1973-11-27 Texas Instruments Inc Vector order computing system
US3740538A (en) * 1971-07-28 1973-06-19 Us Air Force Digital sorter and ranker
US3696343A (en) * 1971-07-29 1972-10-03 Ibm Method of merging data on a two tape drive system
US4210961A (en) * 1971-10-08 1980-07-01 Whitlow Computer Services, Inc. Sorting system
US3781822A (en) * 1972-08-09 1973-12-25 Bell Telephone Labor Inc Data rate-changing and reordering circuits
US3750111A (en) * 1972-08-23 1973-07-31 Gte Automatic Electric Lab Inc Modular digital detector circuit arrangement
US4321670A (en) * 1975-07-31 1982-03-23 Schlumberger Technology Corporation Method of merging information on storage media
US4030077A (en) * 1975-10-16 1977-06-14 The Singer Company Multistage sorter having pushdown stacks for arranging an input list into numerical order
US4135248A (en) * 1977-10-11 1979-01-16 Westinghouse Electric Corp. Median extractor
US4410960A (en) * 1980-02-05 1983-10-18 Nippon Electric Co., Ltd. Sorting circuit for three or more inputs
US4498189A (en) * 1981-02-18 1985-02-05 Nippon Electric Co., Ltd. Comparator suitable for a character recognition system
US4439840A (en) * 1981-09-28 1984-03-27 Hughes Aircraft Company Real-time ordinal-value filters utilizing partial intra-data comparisons
US4441165A (en) * 1981-09-28 1984-04-03 Hughes Aircraft Company Real-time ordinal-value filters utilizing complete intra-data comparisons
US4456968A (en) * 1981-09-28 1984-06-26 Hughes Aircraft Company Real-time ordinal-value filter utilizing half-interval ranking
US4628483A (en) * 1982-06-03 1986-12-09 Nelson Raymond J One level sorting network
WO1984004014A1 (en) * 1983-03-28 1984-10-11 American Telephone & Telegraph A distributed prioritized concentrator
WO1984004011A1 (en) * 1983-03-28 1984-10-11 American Telephone & Telegraph A wideband digital switching network
WO1984004015A1 (en) * 1983-03-28 1984-10-11 American Telephone & Telegraph A self-routing switching network
US4516238A (en) * 1983-03-28 1985-05-07 At&T Bell Laboratories Self-routing switching network
US4472801A (en) * 1983-03-28 1984-09-18 At&T Bell Laboratories Distributed prioritized concentrator
US4542497A (en) * 1983-03-28 1985-09-17 At&T Bell Laboratories Wideband digital switching network
JPH0681154B2 (en) * 1983-03-28 1994-10-12 アメリカン テレフオン アンド テレグラフ カムパニ− Self routes specified replacement Netsutowa - click
US4531209A (en) * 1983-03-28 1985-07-23 At&T Bell Laboratories Self-routing steering network
US4890220A (en) * 1984-12-12 1989-12-26 Hitachi, Ltd. Vector processing apparatus for incrementing indices of vector operands of different length according to arithmetic operation results
EP0186595A2 (en) * 1984-12-24 1986-07-02 SGS-THOMSON MICROELECTRONICS, INC. (a Delaware corp.) Routing technique
US4685128A (en) * 1984-12-24 1987-08-04 Thomson Components-Mostek Corp. Method and network for transmitting addressed signal samples from any network input to an addressed network output
EP0186589A3 (en) * 1984-12-24 1988-04-20 Thomson Components-Mostek Corporation Routing element
EP0186595A3 (en) * 1984-12-24 1988-04-20 Thomson Components-Mostek Corporation Routing technique
EP0186589A2 (en) * 1984-12-24 1986-07-02 SGS-THOMSON MICROELECTRONICS, INC. (a Delaware corp.) Routing element
US5293489A (en) * 1985-01-24 1994-03-08 Nec Corporation Circuit arrangement capable of centralizing control of a switching network
US4679190A (en) * 1986-04-28 1987-07-07 International Business Machines Corporation Distributed voice-data switching on multi-stage interconnection networks
US5091848A (en) * 1987-04-10 1992-02-25 Hitachi, Ltd. Vector processor for merging vector elements in ascending order merging operation or descending order merging operation
US4970637A (en) * 1987-06-22 1990-11-13 Kabushiki Kaisha Toshiba Digital anti-aliasing filter
US4905224A (en) * 1987-09-30 1990-02-27 Siemens Aktiengesellschaft Sorting unit for a switching node comprising a plurality of digital switching matrix networks for fast, asynchronous packet switching networks
US4797880A (en) * 1987-10-07 1989-01-10 Bell Communications Research, Inc. Non-blocking, self-routing packet switch
US4910730A (en) * 1988-03-14 1990-03-20 Bell Communications Research, Inc. Batcher-banyan network
US5043980A (en) * 1988-03-14 1991-08-27 Bell Communications Research, Inc. Switching cell for packet switching network
US4891803A (en) * 1988-11-07 1990-01-02 American Telephone And Telegraph Company Packet switching network
US5455701A (en) * 1991-09-16 1995-10-03 At&T Corp. Packet switching apparatus using pipeline controller
US5287347A (en) * 1992-06-11 1994-02-15 At&T Bell Laboratories Arrangement for bounding jitter in a priority-based switching system
US5721809A (en) * 1995-05-12 1998-02-24 Lg Semicon Co., Ltd. Maximum value selector

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