US3323450A - Fully checked electronic printing system - Google Patents

Fully checked electronic printing system Download PDF

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US3323450A
US3323450A US393678A US39367864A US3323450A US 3323450 A US3323450 A US 3323450A US 393678 A US393678 A US 393678A US 39367864 A US39367864 A US 39367864A US 3323450 A US3323450 A US 3323450A
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character
signal
code
print
pulse
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David F Sweeney
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ANELEX CORP
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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B41PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41JTYPEWRITERS; SELECTIVE PRINTING MECHANISMS, e.g. INK-JET PRINTERS, THERMAL PRINTERS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J29/00Details of, or accessories for, typewriters or selective printing mechanisms not otherwise provided for
    • B41J29/38Drives, motors, controls or automatic cut-off devices for the entire printing mechanism
    • B41J29/393Devices for controlling or analysing the entire machine ; Controlling or analysing mechanical parameters involving printing of test patterns
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06KRECOGNITION OF DATA; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K15/00Arrangements for producing a permanent visual presentation of the output data, e.g. computer output printers
    • G06K15/02Arrangements for producing a permanent visual presentation of the output data, e.g. computer output printers using printers
    • G06K15/06Arrangements for producing a permanent visual presentation of the output data, e.g. computer output printers using printers by type-wheel printers
    • G06K15/07Arrangements for producing a permanent visual presentation of the output data, e.g. computer output printers using printers by type-wheel printers by continuously-rotating-type-wheel printers, e.g. rotating-type-drum printers

Description

June 6, 1967 D. F. SWEENEY 3,323,450

FULLY CHECKED ELECTRONIC PRINTING SYSTEM Filed Sept. 1, 1964 3 heets-Sheet 1 FIG. I

Chgrocier Pulse Purity I INVENTOR. DAVID E SWEENEY hrorr Coce BY 41M, HM

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A I vmo 2.52 mwzma v 522$. om. wwcj @231 onom EmEEo INVENTOR DAVID E SWEENEY ATTORNEYS United States Patent 3,323,450 FULLY CHECKED ELECTRONIC PRINTING SYSTEM David F. Sweeney, Wellesley, Mass., assignor to Anelex Corporation, Boston, Mass, a corporation of New Hampshire Filed Sept. 1, 1964, Ser. No. 393,678 11 Claims. (Cl. 101-93) My invention relates to high speed printers, and more particularly to a system for checking the operation of a serially operated high speed printer to detect errors which may occur during aprinting cycle.

Serially operable highspeed printers have been developed in which a selected group of character type faces are serially presented to a printing location at which they may be impacted by a print hammer to form an impression of the character on a recording sheet. Ordinarily, a set of characters is provided for each column to be printed on the recording sheet, and the characters are arranged in axially spaced fonts along the surface of a constantly rotating print wheel, the fonts being skewed circumferentially so that a given character arrived in printing position successively for the successive columns to be printed. Means is provided for storing a group of character codes, one for each column in a line to be printed, each identifying the character to be printed in the associated column. As each skewed row of characters of a given kind approaches the printing position for the first column, the storage means is scanned, the character code for a given column being scanned as the character for that column in the row under consideration approaches the printing position, and all of the stored characters for the line to be printed which agree with the character in the row coming into position are printed by actuating their associated print hammers. The stored characters being scanned are rewritten in the storage unit after comparison with the character then coming into position, and the scanning is repeated as the next skewed row of characters comes into position.

In such a system, it is possible that a print hammer will fail to be actuated even though a true comparison has been made between a character stored for that column and a character coming into printing position. It is also possible that, even though a stored character may agree with a character coming into position, the agreement will not be registered and the hammer will fail to be actuated. Further, it may occasionally occur that a hammer is fired which should not have been fired. It is the object of my invention to facilitate the detection of errors of this kind, so that information erroneously recorded may be easily detected and the machine may be stopped for necessary repairs when indicated by the occurrence of persistent errors.

Briefly, an error checking system for a serially operated printer in accordance with my invention comprises apparatus for checking that a hammer has been actuated each time agreement is detected between a stored character code and a character code corresponding to a character coming into printing position, and also checking that no hammer has been fired unless agreement has been found. The system of my invention also includes apparatus for producing an alarm signal if a print cycle is started but not properly completed by the printing of each stored character and the erasing of the character from the storage system. The apparatus is controlled by signals which are normally provided for print cycle control purposes, or which may be readily made available in a high speed printing system. In accordance with one embodiment of my invention, I provide a timer which is started in response to a start print signal at the beginning of a 3,323,456 Patented June 6, 1967 "ice printing cycle, and which produces a sampling pulse at the end of a period corresponding to a full revolution of the print roll. The start print signal is also used to set a bistable circuit to a first state. During the printing cycle, characters which have been printed are erased from the memory, and when all characters have been erased from the memory, a signal is produced which indicates that printing has been completed. This signal is employed to reset the bistable circuit to an opposite state. Apparatus is provided for producing an alarm signal if the bistable circuit has not been reset when the timer produces its sampling pulse, and for resetting the timer when the bistable circuit is reset.

Apparatus is also provided for checking the operation of the printer during a printing cycle. In a serially operable high speed printer, an agreement pulse is produced each time a stored character is found to be the same as a character type face coming into printing position.'These agreement pulses are employed in the apparatus of my invention to set a suitable bistable circuit, such as a center-tripped flip-flop, to a reference state. Means is provided for detecting the operation of each hammer actuating circuit, to produce a hammer echo pulse each time a hammer is actuated. These hammer echo pulses are used to set the bistable circuit to its opposite state. A suitable sampling pulse is provided, following each time in which an agreement pulse may be produced by a time permitting the actuation of a hammer, to sample the state of the bistable circuit and produce an alarm signal if it is in its reference state. The circuit is so arranged that whether an agreement pulse occurs without a hammer actuating pulse, or a hammer actuating pulse occurs Without an agreement pulse, the bistable circuit will be set in its reference state when the sampling pulse occurs.

The apparatus of my invention will best be understood by reference to the following detailed description, together with the accompanying drawings, of a prefer-red embodiment thereof.

In the drawings,

FIG. 1 is a schematic elevational view of a portion of a high speed printer, showing the relation of the print roll and print hammers;

FIG. 2 is a schematic perspective sketch of the portion of the high speed printer shown in FIG. 1 and also showing the manner in which character codes may be generated as various characters come into printing position;

FIGS. 3a and 3b, when arranged horizontally side by side with FIG. 3a at the left, comprise a schematic wiring diagram of an error checking system for a high speed printer in accordance with my invention.

Referring first to FIGS. 1 and 2, I have shown a portion of a high speed printer comprising a series of print hammers such as the hammer 1, each provided with an actuating coil such as the coil 2. The hammers are disposed in a row defining a printing station adjacent the surface of a constantly rotating print roll 3. A carbon ribbon such as 4 and a recording means such as a sheet of paper 5 may be disposed between the hammers and the print roll in the manner indicated, and fed by conventional apparatus which stops the paper in printing position for each line to be printed.

As indicated in FIG. 2, a series of fonts of characters, one for each hammer corresponding to a column to be printed, is axially spaced along the surface of the print roll 3 and circumferentially staggered so that, for example, the letter A for the first column arrives in printing position slightly before the letter A for the second column, and so on. While various other techniques may be employed for serially delaying the arrival of characters for the successive columns in printing position, such as skewing the print roll axis or progressively delaying the hammer actuating circuits, the arrangement shown is preferred.

As indicated schematically in FIG. 2, a shaft encoder 6 is provided which may comprise a disc 8 on the shaft 7 of the print roll 3, provided with a coded row of radial apertures for each character in the fonts of columns around the print roll, each row comprising six spaces each pierced with an aperture or not according as a corresponding bit in a character code defining the associated character is l or 0, a seventh space, if desired, to define a parity bit, an eighth space pierced with an aperture to indicate the location of the character. If desired, a special character comprising a symbol to be printed when an illegitimate character has been found in memory may be located in each font, and marked by a single aperture on the disc 8 radially displaced from the eightspaced rows just described.

The disc 8 is placed between a bank of nine lamps, not shown, and a corresponding bank of photocells schematically indicated at 9, to provide pulses comprising a character code group of seven pulses for each legitimate character to be printed, a single pulse for the special character, and a character pulse for each character. It will be apparent that more or fewer character code pulses could be provided if desired, to produce a code having a capacity consistent with the number of characters in each font, but for an alphanumeric font comprising sixtyfour characters six pulses are conveniently provided to define the characters using a full binary count, with a seventh output pulse provided to introduce a parity bit, by conventional techniques, for purposes of checking the parity of the stored character codes. As will appear, the parity bit is not essential because the apparatus of my invention is capable of checking parity, as well as illegitimate characters, without a special parity bit.

Referring next to FIGS. 3a and 312, I have shown, in connection with an operation checking system in accordance with my invention, so much only of a serially operable printer system as is necessary to understand the structure and operation of the apparatus of my invention. In particular, various circuits for timing and programming the storing and processing of information in a high speed printer, well known to those skilled in the art, have not been shown, and various functions necessarily performed in such a system and helpful in understanding the apparatus of my invention have been indicated quite schematically.

As shown, the system comprises a timing means 10 consisting of apparatus for producing control pulses for use in timing the operation of the system. While various conventional means may be employed for this purpose, I have shown an AND gate A1 of conventional construction enabled when three signals are simultaneously applied to its three input terminals to produce a signal at its output terminal for setting a conventional flip-flop FFl to a first state. The flip-flop FFl is set to its first state at the end of each print cycle, as will appear. A start print signal, generated in any known conventional manner to indicate that such operations as the feeding of paper and the loading of a new line of characters into memory are complete, is employed to set the flip-flop FFI to a second state at the beginning of each print cycle.

When the flip-fiop F1 1 is in its first state, it produces a signal at a selected one of its output terminals labelled clock-stop and serving to reset a conventional gated one-shot multivibrator CS1 by removing a gating level from its input terminal G to permit it to respond to trigger pulses applied to its input terminal T. Suitable gated one-shot multivibrators for use as 081, and other one-shot multivibrators to be described, are shown and described in copending US. application Ser. No. 358,853, filed on Apr. 10, 1964, by John C. Sims, Ir., for Variable Word Length Internally Programmed Information Processing System, and assigned to the assignee of my application.

Trigger pulses are at times applied to the one-shot multivibrator 051 by a conventional OR gate 0R1, which produces an output pulse when a suitable input signal is applied to either of its input terminals. A first input terminal at times receives a signal from a conventional AND gate A2, when suitable signals are simultaneously applied to its two input terminals. The second input terminal of the gate 0R1 at times receives a signal, labelled recycle from the output terminal of a conventional one-shot multivibrator CS2, in response to a triggering pulse from the output terminal of the multi vibrator 081. In practice, the time delays of the multivibrators OS1 and 082 might be, for example, 2 microseconds and 8 microseconds, respectively. As shown, two additional conventional one-shot multivibrators CS3 and 054 are connected in series, with the input trigger terminal of the multivibrator 053 connected to the output terminal of the multivibrator 081. Each of the multivibrators OS3 and 084 may have delays of 2 microseconds if the other time delays are as given above.

The operation of the timing means 10 will be apparent to those skilled in the art. Briefly, at the start of a print cycle the clock stop level will be removed by operation of the flip-flop FFl. A level in print cycle, produced as described below, will be applied to one input terminal of the AND gate A1. The first character pulse produced by the shaft encoder (FIG. 2) will cause the gate A2 to produce an output signal, applied through the gate 0R1 to trigger the multivibrator 051. Two microseconds later, assuming the values given above, an output pulse will be produced by the multivibrator 0S1, serving to trigger the multivibrators OS2 and CS3 and acting as the first of a series of read sample pulses. After a further delay of two microseconds, a pulse will be produced by the multivibrator 083, used as a write sample signal to allow the entry of a character into memory, as will appear, and also to step a conventional lO bit shift register SR1 serving to select one of ten memory address lines in a memory address matrix, to be described. Two microseconds later, the multivibrator 0S4 produces a delayed clock pulse, for purposes to be described. Finally, a new cycle is initiated by a recycle pulse produced by the multivibrator 0S2 eight microseconds after the initial triggering pulse from the multivibrator 051. The timing means 10 will continue to cycle in this manner until the clock stop signal is produced by the flip-flop FFI, in a manner to be described.

A core plane memory matrix 14 is provided which may be of a conventional type employing 840 ferrite cores arranged in a 7 x array, wired as shown for the four typical cores 16. Each core is provided with a vertical read line, which is adapted to be energized by a current of predetermined value to produce an output pulse on an output sense line if the core is saturated in one sense, and to produce no output pulse if the core is saturated in the opposite sense. Each core is also provided with a vertical write line and a horizontal input line, each adapted to be energized with half of the current necessary to saturate the core in the opposite sense from the sense to which it is driven by the read line, to set the core when half current is applied to both the write line and the input line for the particular core. Seven input lines are provided to the horizontal input windings of the core matrix, to which pulses representing characters identified by a code sequence of six bits followed by a parity bit may be applied.

Reading from and writing into the memory matrix 14 is controlled by a memory address matrix comprising the shift register SR1 described above and a second twelve bit shift register SR2, of conventional construction. The shift register SR1 has ten sequential states in each of which it enables one of ten output lines L1 through L19 to produce an output signal enabling one pair of a set of conventional AND gates labelled AR or AW, plus an address bit identifying numerical sufiix, such as the pair of gates AW1 and ARI. The enabled gate labelled AR- produces an output pulse at the read sample time, and the enabled gate labelled AW- produces an output pulse at the write sample time.

The output terminals of the AND gates AW- are each connected to the output terminals of a different one of ten write amplifiers such as WA1, WAZ, etc. Similarly, the AND gates AR are connected to control read amplifiers such as RAl, RA2, etc. These amplifiers may be of any known conventional construction. When actuated by a signal from the associated AND gate, the amplifiers such as WAl and RAl produce a current pulse on vertical write and read lines, respectively, in the memory matrix 14. The shift register SR2 selects the high ordered digit of the memory address from one of twelve groups of ten addresses and the shift register SR1 selects one of ten addresses within the group selected by the shift register SR2. To this end, the shift register SR2 has twelve sequential states in each of which a different line H1 through H12 is enabled in a conventional manner to control an associated gate WRAl through WRA12 to serve as a current sink. The gates such as WRAl may be of any conventional construction, but for example may be NOR gates of the type disclosed in the above cited copending application of John C. Sims, ]r., which have output terminals serving as ground level current sinks when a negative potential is applied to their input terminals.

Each of the gates WRAI through WRA12 is connected to a different set of ten vertical read lines and ten vertical write lines, isolated by diodes as shown. Within each group associated with a gate such as WRAl, each read line is connected to a different one of the ten read amplifiers RAl through RA10, and each write line is connected to a different one of the ten write amplifiers WA} through WA10, in the manner sufiiciently indicated in the drawing. Thus, in any given state of the shift register, at the read sample time full switching current is supplied by one of the read amplifiers such as RA1 and flows to the current sink provided by one of the gates such as WRAl, so that one column of the memory is read out in each state of the shift registers.

As indicated in the drawing, when the shift register SR1 is reset from its tenth state to its first state, a signal step high order is produced in a conventional manner and steps the shift register SR2 to its next state. As stepping proceeds, in response to successive write sample pulses, the memory will be scanned from column 1 through column 120. The write sample pulse following the processing of column 120 will produce a final step high order signal from the shift register SR1, restoring the shift register SR2 to its initial state. At the same time, with the lead H12 energized, the gate A1 in the timing means will produce an output signal to set the flipfiop FFl to produce its clock stop level, stopping the timing cycle. A new cycle will be commenced by the next character pulse, as described above.

The horizontal output lines of the core memory matrix 14 are applied in parallel through conventional sense amplifiers SA to a conventional seven bit register R1, which may comprise a series of flip-flops or the like. The output of the register R1 is applied in parallel to a clear memory detector 17, a code comparator 18, and a set of seven re-write gates 19. The construction and function of these units will next be described.

The clear memory detector 17 may comprise a conventional OR gate 0R2 to which are applied in parallel all of the output signals from the register R1. Assuming a code in which the presence of a signal capable of actuating the gate 0R2 indicates a 1 bit in the character in the register R1, the gate 0R2 will produce an output pulse each time any character is stored in the register R1.

The output of the gate 0R2 is connected to one input terminal of a bistable circuit here shown as a flip-flop FF2. This flip-flop may be of conventional construction, adapted to be set to a reference state by the output of the gate 0R2, and reset to an opposite state by an output pulse produced by a conventional AND gate A3. The AND gate A3 has two input terminals, to one of which the character pulses from the character pulse generator 8 in FIG. 2 are applied, and to another of which an in print cycle signal, to be described, is applied.

One output terminal of the flip-flop FFZ is connected to one input terminal of a conventional AND gate A4. A second input terminal of the AND gate A4 is connected to receive the clock stop signal, described above. If the flip-flop FFZ is in its reset state on count 121 of the counter, the AND gate A4 will produce a print-complete pulse to indicate that the memory has been cleared and all characters stored in it have been printed.

The shaft encoder 9 has itsoutput terminals connected to the input terminals of a conventional eight bit register R2, which may comprise a set of flip-flops or the like. The output terminals of the register R1 and the seven terminals of the register R2 representing data and parity are connected to the input terminals of a conventional code comparator 18, wherein apparatus of a conventional type well known in the art is provided for detecting agreement between the output of the shaft encoder 9 and the output of the core plane memory matrix 14. The eighth bit of the register R2, if provided, stores a bit indicating the approach of an illegitimate character symbol to printing position, for purposes to be described.

The code comparator 18 produces an agreement pulse when agreement is found between the characters stored in the registers R1 and R2. This agreement is applied, through an OR gate 0R4, to the input terminals of a conventional inverter 24, which, in the absence of an agreement pulse, produces an output signal indicating no agreement that is applied to each of the seven re-write gates 19. As will appear, a second input to the gate 0R4 provides a substitute agreement signal under certain circumstances. As indicated by the typical gates shown, these gates 19 may comprise an AND gate such as 25, having one terminal connected to the no agreement line and a second input terminal connected to one of the seven output lines of the register R1. The output terminal of each of the AND gates such as 25 is connected to the corresponding input terminal of the core plane memory matrix 14. The storage provided by the register R1 permits a character stored in the register at the read sample time, and not printed, to be rewritten in the same location in memory at the write sample time. Characters that have been printed are not rewritten in memory. However, where 000000 is a legitimate character code and parity is not checked, it may be desirable to restore locations in memory that have been printed to some selected code other than 000000, with consequent changes in the logic of the memory clear detector to ignore the selected code.

Referring to FIGS. 3a and 3b, the flip-flop FF3 is set to one state by the start print signal derived from the memory clear detector 17. The start print signal is also applied to start a timer 31, which may be of any suitable construction designed to produce an output pulse for each revolution of the print roll following the start print signal if not first reset by a print complete signal. Any of various known gated monostable circuits could be employed for this purpose, but as here shown, the timer comprises a conventional single shot multivibrator 0S5 followed by a conventional AND gate A5 enabled by an in print cycle level produced by the flip-flop FF3 when set by the start print signal and removed when the flip-flop FF? is reset by a print complete signal. Typically, the duration of the output pulse of the one-shot multivibrator OSS would be about 760 milliseconds in high speed printing systems operating at a drum speed of 1000 rpm.

The output pulse of the timer 31 is supplied to one input terminal of a conventional flip-flop FF4, the other input terminal of which is connected to any suitable resetting circuit, such as a current source controlled by a manual switch, to produce an alarm reset signal when desired. A selected output terminal of the flip-flop FF4 produces an alarm level labelled alarm 2 to energize any desired indicating or control equipment, here typified as an indicator lamp K2. The illumination of this lamp K2 indicates that a print cycle has been started and followed by a complete revolution of the print roll without the production of a print complete signal, indicating an error in operation.

The agreement pulse produced by the code comparator 18 is supplied to a distributor 38, which may be timed by the read sample signals to sequentially distribute agreement pulses to the appropriate one of 120 hammer driver circuits during a scanning cycle. As indicated, the distributor may comprise 120 gates such as the AND gate 39, each having one terminal connected to the agreement pulse line, another terminal connected to one of the ten low order address lines such as L1, and another input terminal connected to one of the twelve high order address lines such as H1. The hammer driver circuits may be of any conventional type known to those skilled in the -art,and are here shown as comprising a power amplifier 41 energized by the output of the corresponding AND gate 39 in the distributor 38. The output terminals of the amplifier 41 are connected through the coil 2 of the associated hammer, and are also connected through a coupling capacitor such as 42 to one of 120 hammer echo pulse lines. The hammer echo pulse lines are connected to an OR gate R3, of conventional construction, which also has an input terminal connected to the agreement pulse line. The gate 0R3 accordingly produces an output pulse each time a hammer is fired, and also each time an agreement pulse is produced. This output pulse is applied to a center-tripped terminal of a conventional center-tripped fiip-flop F FE, to change its state each time the OR gate 43 produces an output pulse. As shown, the fiipdlop FFS is also provided with a direct set terminal controlled by the start print signal to assure that the flip-flop will be in a reference state at the beginning of each print cycle. One output terminal of the fiip-flop FPS is connected to one input terminal of a conventional AND gate A6, which has a second input terminal connected to receive delayed clock pulses produced as described above. Thus, after each agreement pulse, followed by the firing of a corresponding hammer, the flip-flop FPS changes state twice and if it does so the arrival of the next delayed clock pulse will not cause the AND gate A6 to produce an output pulse. However, if one or the other of the setting pulses for the flip-flop FPS is missing, the delayed clock pulse will cause an output pulse to be produced by the AND gate A6 to set a conventional flip-flop P1 6 to produce an alarm 1 level, here shown as energizing an indicator lamp K1. The illumination of this lamp will indicate either that a hammer has been fired which should not have been fired or that a hammer has not been fired which should have been fired.

Having described the structure of one embodiment of my invention, its operation will next be described. Referring first to FIG. 3a, the memory is first loaded with 120 character signals in any conventional manner, not shown. After the memory has been loaded, a start print pulse may be produced in a conventional manner and the flip-flop F1 3 will be set to produce an in print cycle level to enable the AND gate A2 to start the timing means at the next character pulse. When the first character pulse appears following the setting of the flip-flop F1 3, it will provide a pulse to the gate CR1 and then trigger the multivibrator 083 to begin a scanning cycle. At the same time, the gate A3 will reset the flip-flop FFZ. As the first vertical read line is energized in the core plane memory matrix 14, the character stored for the first column is read into the register R1 and applied to the code comparator 18. Assuming that it is in agreement with the code produced by the shaft encoder 9,

an agreement pulse is applied to cut off the rewrite gates 19 and prevent the stored character from being rewritten in the memory, and also to actuate the first gate 39 in the distributor 3:8 to apply a hammer driving signal to actuate the amplifier 41 for the first column hammer in the hammer driver circuits 40. The firing of this hammer supplies an output pulse to the OR gate 0R3. As described above, the flip-flop FPS is first set by the agreement pulse, and then reset by a hammer echo pulse by the gate 0R3. Accordingly, when the delayed clock pulse following the read sample pulse which energized the first column read line occurs, the gate A6 will be disabled and the alarm flip-flop FF6 will not be set.

At the same time that the first character for the first column was read out to the code comparator 18, one or more pulses were applied in parallel to the OR gate 0R2 in the memory clear detector 17 to set the flip-flop FFZ. The scanning cycle will then continue, with each stored character in the memory matrix 14 being sequentially compared with the first character supplied by the shaft encoder 9, and whether or not any further outputs are produced by the OR gate 0R2, the memory clear detector will not respond during this cycle because the flip-flop FFZ has been set. However, any disagreement between an agreement pulse and a hammer echo pulse will cause the flip-flop FPS to be set to the state in which the gate A6 will be enabled to pass the next delayed clock pulse. If this occurs, the flip-flop F1 6 will be set to its alarm state and the indicator lamp K1 will be illumined. When count 121 is reached in the first scanning cycle, that is, when lead H12 is energized and the step high order signal is produced, the gate A1 in the timing means 10 will reset the flip-flop FFl to its clock stop state, and no further operation will take place until the next character pulse is received.

As each successive character is presented by the shaft encoder 9 to the code comparator 18, the scanning cycle just described will be repeated, with characters producing an agreement with the output of the shaft encoder being printed, and erased from the core plane memory matrix 14. When the last stored character has been printed, a final scanning cycle will take place, in response to the character pulse following the character pulse for the last character in the font. This character pulse will cause the timing means It) to be started as before, and begin its counting cycle. The flip-flop FFZ will also be set by the character pulse, and all the columns of the memory matrix 14 will be successively scanned on the counts of the counter from one to 120. Since all of the characters have been erased from memory, the OR gate 0R2 will produce no output pulse during this scanning cycle, and the flip-flop FFZ will remain set. Accordingly, when the clock stop level is produced, the flip-flop FFZ will enable the gate A4 to pass a print complete pulse. This print complete pulse will be applied to reset the flip-flop FFZ which was set by the start print signal. At the same time the start print signal was applied, the timer 31 was started by triggering the single shot multivibrator 085. When a complete revolution of the print roll has been made, the timer 31 will produce its output pulse to enable the AND gate A5. However, since the flip-flop F1 3 has been reset by the print complete signal, no output pulse will be produced. On the other hand, if the print complete level had not been produced, the gate A5 would set the flip-flop P1 4 to provide the alarm 2 level to energize the indicator lamp K2.

Various controls may be exercised in response to the alarm 2 signal provided by the flip-flop FF4. If desired, the printer may be stopped, or printing may be continued by ignoring the alarm indication or manually overriding it if the flip-flop FF! is normally connected to stop the printer. Alternatively, it may be desirable to locate an illegitimate character symbol in the font for each character on the print roll, and to follow the memory scan in which the flip-flop F1 4 was set by a scan in which the 9 illegitimate character symbol is printed in each column for which the gate R2 produces an output pulse. For this purpose, the outputs of the gate CR2 and the flip-flop FF4 in its alarm 2 state may be applied to an AND gate A7, the output of the AND gate A7 being combined in an OR gate 0R4 with the output of the comparator 18 to provide the agreement signal for the system. The location of the illegitimate character symbol on the print roll is immaterial, because printing may begin on any character pulse. However, to carry out the illegitimate character printing operation at the proper time, either a character code identifying the illegitimate character must be provided on the code wheel 8 in FIG. 2, to be detected by a decoding network controlled by the comparator 18, or preferably, a separate illegitimate character bit is produced by the shaft encoder 9' as described above, stored in the register R2 as the eighth bit, and applied as the third input to the gate A7, as shown.

It will be apparent that, while I have shown various logical functions implemented by AND, OR, and NOR gates, other implementing circuits could be substituted by applying appropriate known logical transformations.

While I have described my invention with reference to the details of a specific embodiment, many changes and variations will occur to those skilled in the art upon reading my description, and such can obviously be made without departing from the scope of any invention.

Having thus described my invention, what I claim is:

1. Apparatus for checking the operation of a serially operable high speed printer of the type comprising a plurality of print hammers, a character code generator for serially producing codes representing characters on a print roll successively arriving in printing position adjacent said hammers, storage means for storing a code representing a character to be printed for each hammer, code comparing means synchronized with a train of clock pulses for scanning said storage means once for each character code produced by said code generator and producing an agreement signal for each corresponding stored code, and means controlled by each agreement signal for actuating the corresponding hammer, said apparatus comprising, bistable circuit means alternately actuated to opposite states by a succession of applied signals, means for applying the agreement signals to said bistable circuit means, means responsive to the actuation of any of the hammers for applying a signal to said bistable circuit means, and means for sampling the state of the bistable circuit means, at a time after each clock pulse sufiicient to permit the actuation of a hammer, for producing an alarm signal if an odd number of signals have been applied to said bistable circuit means.

2. In a serially operable high speed printer, a plurality of printing transducers, one for each column in a line to be printed, recycling memory means for storing a series of character codes, one for each printing transducer, and responsive to a sequence of applied scanning signals for producing output code corresponding to the stored codes and rewriting them in the memory, encoding means for producing a series of character codes representing a series of characters available for printing by said transducer, means for producing a series of scanning signals for each code produced by said encoder means, code comparator means for producing an agreement signal in response to two applied codes having a predetermined relationship, means for applying the codes produced by said encoder means to said comparator means, means controlled by said scanning signals for sequentially applying the character codes stored in said recycling memory means to said comparator means, a gate means for each printing transducer operable when enabled for operating the transducer in response to an agreement signal from said comparator, means controlled by said scanning signals for sequentially enabling said g-ate means as each stored code corresponding to a transducer is applied to said comparator means to permit the corresponding transducer to be actuated if an agreement signal is produced, pulse generating means responsive to said transducers for producing an output signal for each transducer that is actuated, means for registering the parity of the sum of the agreement signals and the signals produced by said pulse generating means, means controlled by said scanning signals for producing a series of delayed signals, one for each scanning signal and occurring before the next scanning signal, and means controlled by said delayed scanning signals and said registering means for producing an alarm signal if the registered parity is odd.

3. In a high speed printing system, a plurality of printing transducers, one for each column in a line to be printed, means for producing a train of clock pulses, means synchronized with the clock pulse train for applying actuating signals to said transducers, means controlled by said transducers for producing an output signal in response to the actuation of a transducer, means controlled by said output signals and said actuating signals for registering the parity of the sum of said signals, means controlled by said clock pulse train for producing a delayed clock pulse for each clock pulse in said train, and means controlled by said delayed clock pulses and said registering means for producing an alarm signal when the registered parity is odd.

4. In a high speed printing system, a series of printing transducers arranged in a row defining a print station adjacent a rotating print roll bearing a font of characters for each transducer, storage means for storing a series of character codes, one for each transducer, shaft encoder means synchronized with the print roll for producing a series of character codes representing characters approaching the print station, means synchronized with the print roll for producing a series of character pulses, one for each code produced by said shaft encoder means, means controlled by said character pulses for producing a series of scanning signals, scanning means controlled by said scanning signals and operatively connected to said storage means for sequentially producing character codes coresponding to the codes stored for each transducer, code comparator means controlled by said shaft encoder means and said scanning means for producing an agreement signal for each stored code corresponding to the code produced by the shaft encoder means, a gate means for each transducer operable when enabled to actuate the transducer in response to an agreement signal produced by said comparator, means controlled by said scanning signals for sequentially enabling said gate means as corresponding stored characters are scanned, gate means controlled by said transducers for producing a signal each time a transducer is actuated, registering means controlled by said agreement signals and the signals produced by said gate means for'rcgistering the parity of their sum, delay means controlled by said scanning signals for producing a delayed signal for each scanning signal, and means controlled by said registering means and said delayed signals for producing an alarm signal when the registered parity is odd.

5. In a high speed printing system of the type comprising storage means for storing a code representing a character to be printed for each column in a line to be printed, a constantly rotating print roll bearing a font of characters for each column to be printed, a printing transducer adjacent each font and operable when energized to print the character then adjacent, a character code generator for producing a character code signal identifying each character coming into printing position, means for scanning said storage means once for each character code signal, and means controlled by said scanning means for comparing the character code signal with the stored character codes and producing a signal for energizing each transducer associated with a stored code which agrees with the character code signal, code checking apparatus comprising registering means controlled by said comparing means and said transducer means for l. l registering the parity of the sum of said energizing signals and the number of transducers energized by said signals, and delayed gate means controlled by said registering means and said scanning means for producing an alarm signal when the registered parity is odd.

6. In apparatus for checking the operation of a serially operated high speed printer of the type comprising a constantly rotating print roll bearing a plurality of fonts of characters sequentially presented to a print station defined by a row of print hammers, one for each font, the combination comprising storage means for storing a character code representing a character to be printed for each of said hammers, means for producing a start print signal, code comparing means enabled by said start print signal and actuated as each character on said fonts approaches the print station for sequentially removing the character codes from said storage means and comparing them with a comparison code representing the character coming into position, means controlled by said comparing means when a stored code agrees with the comparison code for actuating the hammer associated with the stored code, means controlled by said comparing means when a stored code does not agree with the comparison code for replacing the stored code in the storage means, a bistable circuit having first and second states, means controlled by said start print signal for setting said bistable circuit to its first state, means controlled by said storage means for producing a print complete signal when no codes remain in said storage means, means controlled by said print complete signal for setting said bistable circuit to its second state, and timing means controlled by said start print signal and said bistable circuit in its first state for producing an alarm signal at a time following the start print signal adequate to permit a line to be printed.

7. The apparatus of claim 6, in which each font of characters includes a selected character representing any illegitimate character, and further comprising means synchronized with said print roll for producing an illegitimate character signal when said selected characters approach the print station, a second bistable circuit, means controlled by said alarm signal for setting said second bistable circuit to a predetermined state, and means controlled by said sccond bistable circuit in said predetermined state, said storage means, and said illegitimate character signal for actuating each hammer for which any code is stored to print the selected character in the corresponding column.

8. In a high speed printer, a core plane memory matrix for storing a plurality of character codes, one for each column in a line to be printed, an array of printing means each sequentially operable to print one of a predetermined series of characters, code generating means synchronized with said printing means for producing a series of codes representing the different characters which may be printed as the printing means becomes operable to print them, means for producing a start signal, sequential comparator means enabled by said start signal and synchronized with the code generating means for sequentially reading the stored codes of the memory matrix and comparing them with the code produced by the code generating means, means for restoring to the memory matrix the codes read out of the matrix which do not agree with the code produced by the code generating means, means for detecting the presence of codes in said matrix and producing a print complete signal when no codes remain in the matrix, a bistable circuit, means controlled by said start print signal for setting said bistable circuit to a first state, means controlled by said print complete signal for setting said bistable circuit to a second state, and timing means controlled by said start print signal and said bistable circuit in its first state for producing an alarm signal after said code generating means has produced codes representing all characters 12 which may be printed if the print complete signal does not first set said bistable circuit to said second state.

9. Apparatus for checking the operation of a high speed printer of the type comprising means synchronized With a train of character pulses for comparing character codes stored for each column to be printed with character codes representing characters in printing position and producing signals for firing hammers associated with each column in which the stored code agrees with the code for the character in printing position, comprising a bistable circuit, means controlled by the signals produced by said comparing means for setting said bistable circuit to a first state, means controlled by the firing of any hammer for setting the bistable circuit to a second state, means for producing a series of delayed clock pulses lagging the system synchronizing train by an amount suificient to permit the firing of a hammer, and gate means controlled by said delayed clock pulses and said bistable circuit in its first state for producing an alarm signal.

10. Apparatus for checking the operation of a high speed printer of the type comprising a plurality of hammers, sequentially operable means for actuating the hammers as characters coming into printing position match character codes stored for the hammers, means for producing a start print signal, and means for producing a print complete signal, said apparatus comprising a bistable circuit, means controlled by said start print signal for setting said bistable circuit to a first state, means controlled by said print complete signal for setting said bistable circuit to a second state, and timing means controlled by said start print signal and said bistable circuit in its first state for producing an alarm signal delayed from the start print signal by an amount sufficient to permit all of said hammers to be actuated if said print complete signal is not first received.

11. A fully checked serially operable high speed printing system comprising an array of printing transducers, cyclically operable means for placing a series of characters successively in printing position relative to said transducers, means for producing a start print signal, memory means for storing a series of character codes, one for each transducer, scanning means enabled by said start print signal for sequentially reading out of the memory means all of the stored codes once for each character coming into position, code comparing means for comparing the codes read out with each character coming into printing position and producing an agreement signal for each agreement between a code read out of the memory means and the character coming into position, means controlled by said code comparing means for reading back into the memory means each code not in agreement with the character coming into position, means controlled by said scanning means and said agreement signals for actuating the transducer associated with a code read out of the memory means when an agreement signal is produced, means controlled by said transducers for producing an output signal for each transducer that is actuated, registering means controlled by said agreement signals and said output signals for registering the parity of their sum, means controlled by said scanning means for producing a series of delayed signals, one for each character code read out of the memory means, gate means controlled by said delayed signals and said reigstering means for producing a first alarm signal if the registered parity is odd, a bistable circuit, means controlled by said start print signals for setting said bistable circuit to a first state, means controlled by said memory means for producing a print complete signal when said memory means is cleared of stored characters, and timing means controlled by said start print signal and said bistable circuit in its first state for producing a second alarm signal delayed by an amount at References Cited UNITED STATES PATENTS 2,941,188 6/1960 Flechimer et a1. 340-174 3,064,561 11/1962 Mauduit 101-93 3,066,601 12/1962 Eden 101-93 1% Deerfield 101-93 X Sweeney 101-93 Marsh 340-1725 Barbagallo et a1. 101-93 X W00 101-93 X W'ILLIAM B. PENN, Primary Examiner.

P. R. WOODS, Assistant Examiner.

Claims (1)

1. APPARATUS FOR CHECKING THE OPERATION OF A SERIALLY OPERABLE HIGH SPEED PRINTER OF THE TYPE COMPRISING A PLURALITY OF PRINT HAMMERS, A CHARACTER CODE GENERATOR FOR SERIALLY PRODUCING CODES REPRESENTING CHARACTERS ON A PRINT ROLL SUCCESSIVELY ARRIVING IN PRINTING POSITION ADJACENT SAID HAMMERS, STORAGE MEANS FOR STORING A CODE REPRESENTING A CHARACTER TO BE PRINTED FOR EACH HAMMER, CODE COMPRARING MEANS SYNCHRONIZED WITH A TRAIN OF CLOCK PULSES FOR SCANNING SAID STORAGE MEANS ONCE FOR EACH CHARACTER CODE PRODUCED BY SAID CODE GENERATOR AND PRODUCING AN AGREEMENT SIGNAL FOR EACH CORRESPONDING STORED CODE, AND MEANS CONTROLLED BY EACH AGREEMENT SIGNAL FOR ACTUATING THE CORRESPONDING HAMMER, SAID APPARATUS COMPRISING, BISTABLE CIRCUIT MEANS ALTERNATELY ACTUATED TO OPPOSITE STATES BY A SUCCESSION OF APPLIED SIGNALS, MEANS FOR APPLYING THE AGREEMENT SIGNALS TO SAID BISTABLE CIRCUIT MEANS, MEANS RESPONSIVE TO THE ACTUATION OF ANY OF THE HAMMERS FOR APPLYING A SIGNAL TO SAID BISTABLE CIRCUIT MEANS, AND MEANS FOR SAMPLING THE STATE OF THE BISTABLE CIRCUIT MEANS, AT A TIME AFTER EACH CLOCK PULSE SUFFICIENT TO PERMIT THE ACTUATION OF A HAMMER, FOR PRODUCING AN ALARM SIGNAL IF AN ODD NUMBER OF SIGNALS HAVE BEEN APPLIED TO SAID BISTABLE CIRCUIT MEANS.
US393678A 1964-09-01 1964-09-01 Fully checked electronic printing system Expired - Lifetime US3323450A (en)

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US393678A US3323450A (en) 1964-09-01 1964-09-01 Fully checked electronic printing system
FR22314A FR1455175A (en) 1964-09-01 1965-06-25 System fully controlled electronic printing
GB27629/65A GB1056906A (en) 1964-09-01 1965-06-30 Fully checked electronic printing system
DE19651499351 DE1499351B1 (en) 1964-09-01 1965-08-04 Line printer for data-processing machines

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FR1455175A (en) 1966-04-01
DE1499351B1 (en) 1970-08-20

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