US3299291A - Logic elements using field-effect transistors in source follower configuration - Google Patents

Logic elements using field-effect transistors in source follower configuration Download PDF

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US3299291A
US3299291A US345667A US34566764A US3299291A US 3299291 A US3299291 A US 3299291A US 345667 A US345667 A US 345667A US 34566764 A US34566764 A US 34566764A US 3299291 A US3299291 A US 3299291A
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field
transistor
voltage
effect transistor
source
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Jr Raymond M Warner
Csanky Geza
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Motorola Solutions Inc
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Motorola Inc
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Priority to BE659569D priority patent/BE659569A/xx
Priority to CH187065A priority patent/CH425893A/fr
Priority to NL6501915A priority patent/NL6501915A/xx
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09403—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using junction field-effect transistors
    • H03K19/09407—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using junction field-effect transistors of the same canal type

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  • This invention relates to logic elements, and in particular to logic circuit elements employing field-effect transistors.
  • a logic element is herein defined as a specific combination of individual circuit components to provide an output capable of rapid transition between two discrete voltage levels in response to a change in the voltage level of one or more inputs.
  • Such elements when appropriately fed with one or with a plurality of inputs provide a single output, thereby functioning as a buffer or functioning to perform AND, NAND, OR and NOR logic operations as may be required by an overall symbolic logic system.
  • the logic element For a logic element of the type under consideration to approach ideal conditions, it is desirable that its output change states or switch between two discrete voltage levels in response to a small change in input voltage level, and that this switching occur near the middle of the range of input voltage levels.
  • the logic element should exhibit high input impedance and low power drain, and be capable of receiving a number of direct coupled inputs without experiencing D.C. offset. It is also desirable. that the logic element have a good frequency response so that it may be cascaded without deterioration in switching performance, and for many applications should be capable of sharp, step-like output transitions so that a switching speed-up effect is realized.
  • a further consideration for a present day logic element is that it employs semiconductor devices as its active components and resistances as its passive components, requiring no inductors or capacitors, so that it may be readily integrated into a substrate of semiconductor material.
  • the circuit configuration making up the logic element should be simple and readily arranged so that circuit integration can be achieved by epitaxial and diffusion techniques.
  • field-effect transistors are easier to integrate than conventional transistors in that current flow therein is parallel to rather than normal to the major surfaces of the semiconductor substrate or wafer.
  • An additional advantage is the fact that an integrated circuit logic element can be fabricated using field-effect transistors of any type, including isolated gate fieldeffect transistors.
  • Another object of the invention is to provide improved logic elements exhibiting the foregoing desirable electrical proper-ties.
  • a further object is to provide improved logic elements that may be readily fabricated by integrated circuit techniques.
  • Still another object is to provide improved logic elements which may be of the inverting or non-inverting type, and which may be readily incorporated with a number of inputs to perform desired AND, OR, NAND and NOR logical functions.
  • a more specific object of the invention is to provide improved logic elements having a field-effect transistor with a semiconductor current-limiter load to provide switching action, and which is driven by a source follower field-effect transistor to allow direct coupling of a plurality of inputs and to provide a high input impedance and a low output impedance.
  • the logic elements of the present invention comprise a switching arrangement including a field-effect transistor with a semiconductor nonlinear resistance device as a current-limiter load.
  • the current-limiter load is a self-biased field-effect transistor (or a field-effect diode) having a drain current (I different from that of the first field-effect transistor. Varying the point of intersection between the current-voltage characteristics of the first field-effect transistor and the load line presented by the current-limiter load in response to an input voltage produces a rapid transition between widely separated output voltage levels.
  • a combination of a fieldeffect transistor with a current-limiter load, and having a source follower field-effect transistor input provides a basic logic element which may be used as a snapaction buffer, or which may be provided with an number of inputs for performing AND, OR, NAND and NOR logic functions.
  • FIG. 1 is a circuit diagram of an inverting logic element according to the invention
  • FIGS. 2 and 3 are curves useful in understanding the operation of the circuit of FIG. 1;
  • FIG. 4 is a circuit diagram of a non-inverting logic element according to the invention.
  • FIG. 5 is a circuit diagram of another embodiment of a non-inverting logic element according to the invention.
  • FIGS. 6 and 7 are schematic diagrams of the manner in which the logic elements of the invention may be modified to perform various logic functions.
  • FIG. 8 is a schematic representation of an additional embodiment of the invention for performing logic functions, and particularly adapted for high fan-in and fanout.
  • the inverting logic element shown at 10 includes field-effect (or unipolar) transistors 12, 14 and- 16.
  • Transistors of this type are known in the art and may briefly be described as a three-electrode semiconductor device having charged carriers of one polarity only, and wherein a signal applied to an input or control electrode modulates the electric field applied to a conducting channel to result in a variation in the effective crosssectional area of the channel.
  • the field-effect transistor is considered a high impedance or voltage device rather than a low impedance or current device as in the case of conventional transistors, and in some applications it provides characteristics similar to those of vacuum tube pentodes.
  • the three electrodes of a field-effect transistor are designated the gate (input), drain (output) and source (common) electrodes, and are identified by the numerals having the subscripts g, d, and s, respectively, in the circuit of FIG. 1.
  • the drain electrode 12 of transistor 12 is connected to a source of positive potential at terminal 13, and its source electrode 12 is connected to drain electrode14 of transistor 14.
  • the source electrode 14 of transistor 14 is returned through resistor 15 to a negative potential or to ground reference potential at terminal 17. With terminal 1'7 connected to ground as shown positive logic results, as hereinafter described.
  • Gate electrode 12 of transistor 12 is returned to its source electrode 12,, which point is further connected to output terminal 18.
  • Gate electrode 14 of transistor 14 receives an input Voltage from the junction point between resistors 22 and 24, which resistors are series connected between source electrode 16 of transistor 16 and terminal 17. Drain electrode 16,, of transistor 16 is returned to the positive potential at terminal 13, and its gate elect-rode 16 is connected to input terminal 26.
  • field-effect transistor 14 is controlled by transistor 16, and further has transistor 12 connected as a current-limiter load for its drain current.
  • Transistor 16 in turn, is connected in a source follower or source output configuration.
  • This connection is analogous to an emitter follower convention transistor circuit, or a cathode follower vacuum tube circuit, and may be considered an impedance transformer having a voltage gain less than unity.
  • a current-limiter of this type is described in an article by R. M. Warner, In, et al. entitled: A Semiconductor Current Limiter, Proceedings of the IRE, volume 47, pages 44-56, January 1959.
  • the drain current (I will become constant at a lower value in response to a negative-going voltage applied to its gate electrode.
  • the value of drain voltage (V at which I becomes constant is defined as the pinch-off voltage (V) It is to be understood, however, that P-type channel field-effect transistors may also be used, with appropriate polarity reversals, to produce the same operation.
  • FIGS. 2 and 3 there is illustrated the manner in which the load line of current-limiter fieldeifect transistor 12 and the characteristics of fieldeffect transistor 14 interact to provide the desired switching action (FIG. 2), and the resulting output voltage versus input voltage curve (FIG. 3) for logic element 10.
  • the drain current I for transistor 12, connected as a self-bias currentlimiter, provides the load line represented by curve 30.
  • I By biasing drain electrode of transistor 12 beyond pinchoif, I remains constant until a sufficiently high value of V is reached to cause avalanche breakdown. This operation is represented by curve 30, which may be considered a load line for transistor 14.
  • Transistor 14 is operated in a normal mode so that pinch-off occurs at a value V determinable by the voltage level of its gate electrode, with constant I thereafter.
  • V determinable by the voltage level of its gate electrode
  • I constant I thereafter.
  • one level of constant I for transistor 14 is shown by curve 32
  • a second level of constant I (caused by a negative-going gate signal) is shown by curve 34.
  • the output signal at terminal 18 exists at the level of V at which the I vs. V curves of transistor 14 cross load line 30 of transistor 12.
  • curve 38 is a plot of output voltage versus input voltage for logic element 10, that this transition is in output voltage very sharp to provide a step-like change in output voltage level in response to a slight change in input voltage from V to V Because the output voltage can exist only at two discrete levels a snap-action takes place and switching is faster than the rise-time of the input voltage. For example, assuming a sinusoidal input, switching time '1' is a constant percentage of the time of a complete cycle 1/ f and the product 1' (l/f) is constant over the operational frequency range of logic element 10, allowing a drive up to hundreds of kilocycles.
  • input voltages are app-lied to transistor 14 via source follower stage 16 rather than directly to the gate electrode of transistor 14.
  • the source follower input stage has a voltage gain of less than unity so that the equivalent Miller effect capacitance (or gate-drain cap-acitance) does not have a significant effect on the frequency response of the switching action.
  • This enables a number of logic elements to be cascaded Without deterioration in switching performance of the overall system.
  • the input to transistor 14 is developed by the voltage divider consisting of resistors 22 and 24, connected in the source return of transistor 16. Resistor 15 maintains the source electrode 14 of transistor 14 above the potential at terminal 17. This arrangement avoids D.C. offset for direct-coupled input voltages.
  • the non-inverting logic element 40 is provided by modifying the manner in which the source follower transistor 16 controls field-effect transistor 14 in response to a change in the input voltage level appearing at terminal 26.
  • the source electrode of transistor 16 is connected to the source electrode of transistor 14 by resist-or 44.
  • the source electrode of transistor 14 is returned by resistor 45 to ground reference potential at terminal 17.
  • the gate electrode of transistor 14 is also returned to terminal 17.
  • transistor 16 when a zero input voltage level is present at terminal 26 transistor 16 provides a current path through resistors 44 and 45.
  • the difierence of potential developed across resistor 45 provides a gate-to-source bias on transistor 14 that results in the I characteristic shown by curve 32 of FIG. 2.
  • the output voltage level at terminal 18 will be V
  • a positive-going voltage applied to input terminal 26 decreases the impedance of transistor 16 and results in an increase in the voltage drop across resistor 45, causing transistor 14'to pinch-01f at a lower level.
  • the voltage at terminal 18 in FIG. 1 in contrast with the circuit of FIG. 1 wherein the voltage at terminal 18 goes from V to V for a positivegoing input voltage, the voltage at terminal 18 in FIG.
  • FIG. 5 One such switching element 50 is shown in FIG. 5, wherein like reference numerals refer to like circuit elements as in FIGS. 1 and 4.
  • the drain electrode of field-effect transistor 14 is connected to a positive voltage at terminal 13, and its source electrode to a drain electrode of transistor 12.
  • Source electrode of transistor 12 is returned to ground reference potential and its gate electrode is connected to its source electrode to provide a current-limiter load for field-effect transistor 14 in the manner previously described.
  • Source follower transistor 16 has its drain electrode connected to terminal 13 and its source electrode to the gate electrode of transistor 14. The source electrode of transistor 16 is also returned to ground by resistor 52 to terminal 17.
  • Transistor 16 and resistor 52 provide a voltage dividing action to supply bias to the gate electrode of transistor 14. With transistor 16 in the high impedance state (as, for example, with a zero voltage level applied to terminal 26) transistor 14 is biased non-conducting and a low voltage level appears at terminal 18.
  • a positive-going voltage level at terminal 26 tends to make transistor 16 conducting to decrease its impedance, causing the gate electrode of transistor 14 to swing in a positive direction. This tends to make transistor 14 conduct to decrease its impedance, and the voltage at terminal 18 also swings in a positive direction.
  • transistor 12 providing a current-limiter load of the type previously discussed, the voltage level at terminal 18 swings between V and V (FIG. 2), but at a somewhat slower speed than in the previously discussed circuits since the output voltage transition tends to follow the input voltage transition.
  • input impedance is high, and output impedance is low so that the logic element 50 provides an excellent buffer.
  • a plurality of source follower input transistors 16A, 16B and 16C may be connected in parallel as shown in FIGS. 6 and 7 to perform prescribed logic functions.
  • the total current of transistors 16A, 16B and 16C develop the input voltage of transistor 14 in the voltage divider of resistors 22 and 24 in the inverting embodiment of FIG. 6, and across resistor 45 in the non-inverting embodiment of FIG. 7.
  • Transistors 16A, 16B and 16C are arranged so that with a Zero level input voltage (or binary 0) at all of their gate electrodes (and all in a high impedance state) the drain current of transistor 14 is at a level 34 of FIG. 2 (binary 1 out) for the inverting embodiment of FIG. 6, and the drain current of transistor 14 is at a level 32 (binary 0 out) for the non-inverting embodiment of FIG. 7. If transistors 16A, 16B and 160 are selected so that it requires a positive-going signal (binary l) to all their gate electrodes to cause curve 32 or curve 34 to cross load line 30, NAND and AND logic is possible. In the inverting embodiment of FIG. 6 NAND logic results and in the non-inverting embodiment of FIG.
  • FIG. 8 A further illustrative embodiment of NAND and NOR logic elements according to the invention, and particularly adapted to provide high fan-in and fan-out, is shown in FIG. 8.
  • a number of field-effect transistors 14A, 14B and 14C are connected in parallel and their total drain current is varied with respect to the load line provided by current-limiter transistor 12. It is to be understood that a number of field-effect transistors 14, greater than the three illustrated, may be utilized.
  • Transistors 14A, 14B and 14C are selected so that when all receive a Zero input voltage level at their gate electrode (binary O) the total drain current is at the level of curve 34 (FIG. 2), and with any one receiving a positive-going input at its gate electrode (binary 1) the total drain current rises to the level of curve 32.
  • This circuit arrangement eliminates the voltage dividing resistors supplying pinch-off voltage to the gate electrode of a single transistor 14 in the embodiment of FIGS. 6 and 7, which arrangement is a limiting factor to be considered for fan-in.
  • High fan-out may be achieved in the embodiment of FIG. 8 by further adding a source follower output stage.
  • the drain electrode of field-elfect transistor 60 is connected to the positive voltage at terminal 13, and its gate electrode connected to the commonly conn-ected drain electrodes of transistors 14A, 14B and 14C.
  • the source of electrode transistor 60 is returned to the negative voltage at terminal 17 by a load arrangement including zener diode 62 and resistor 64.
  • Terminal 68 is connected to the common point between zener diode 62 and resistor 64 to provide an output terminal.
  • Zener diode 62 acts as a level-translator voltage buffer so that full output voltage swing may be obtained at terminal 68. Because of the low output impedance provided by source follower output transistor 60, the circuit of FIG. 8 produces 'a logic element having extremely high fanout capabilities.
  • a logic element including in combination, first, second and third field-effect transistors each having drain, source and gate electrodes, means connecting the drain electrode of said first field-effect transistor to the source electrode of said second fieldeffect transistor, first resistor means connecting the source electrode of said first field-effect transistor to a first voltage source, means connecting the drain electrode of said second field-eifect transistor to a second voltage source, means connecting the source electrode of said second field-effect transistor to its gate electrode, means connecting the drain electrode of said third field-eifect transistor to said second voltage source, second resistor means connecting the source electrode of said third field-efiect transistor to the gate electrode of said first field-efiect transistor, third resistor means connecting the gate electrode of said first field-effect transistor to said first voltage source, at least one input terminal connected to the gate electrode of said third field-eflect transistor, and an output terminal connected to the drain electrode of said first field-effect transistor.
  • a logic element including in combination, first, second and third field-effect transistors each having drain, source, and gate electrodes, means connecting the drain electrode of said first field-effect transistor to the source electrode of said second field-effect transistor, first resistor means connecting the source electrode of said first field-effect transistor to a first voltage source, means connecting a drain electrode of said second field-effect transistor to a second voltage source, means connecting the source electrode of said second field-effect transistor to its gate electrode, means connecting the drain electrode of said third field-effect transistor to said second voltage source, second resistor means connecting the source electrode of said third field-effect transistor to the source electrode of said first field-effect transistor, means connecting the gate electrode of said first field-effect transistor to said first voltage source, at least one input terminal connected to the gate electrode of said third fieldelfect transistor, and an output terminal connected to the drain electrode of said first field-elfcct transistor.
  • a logic element including in combination, first, second and third field-elect transistors each having drain, source, and gate electrodes, means connecting the source electrode of said first field-effect transistor to drain electrode of said second field-effect transistor, means connecting the drain electrode of said first field-effect transistor to a first voltage source, means connecting the source electrode of said second field-effect transistor to a second voltage source, means connecting the gate electrode of said second field-effect transistor to its source electrode, means connecting the drain electrode of said third fieldeffect transistor to the first voltage source, means connecting the source electrode of said third field-effect transistor to the gate electrode of said first field-effect transistor, resistor means connecting the source electrode of said third field-effect transistor to said second voltage source, at least one input terminal connected to the gate electrode of said third field-effect transistor, and an output terminal connected to the source electrode of said first field-effect transistor.
  • a logic element including, in combination: a first field-effect transistor having source, gate and drain electrodes with said gate electrode connected to said source electrode, a second field-effect transistor having source, gate and drain electrodes with the drain electrode thereof connected to the source electrode of said first field-effect transistor, said drain electrode of said first field-effect transistor connectable to a voltage supply and said source electrode of said second field-effect transistor resistively connected to a point of reference potential, an input source follower field-elfect transistor having source, gate and drain electrodes, with the drain electrode thereof connectable to said voltage supply and the gate electrode thereof connected to an input terminal for receiving binary logic signals, said source electrode of said source follower resistively connected to the gate electrode of said second field-effect transistor for providing a Voltage 8 change at the gate electrode of said second field-effect transistor in response to changes in the voltage level of binary logic signals at said input terminal, thereby providing a substantial change in the output signal at said drain electrode of said second field-effect transistor.
  • said second field-effect transistor has a first discrete level of drain voltage corresponding to a first level of input voltage and operative to produce a second discrete level of drain voltage in response to a small deviation in level of voltage applied to the gate electrode thereof, said second discrete level of drain voltage being substantially less than said first discrete level of drain voltage, said binary logic signals applied to said source follower field-effect transistor producing said small deviation at the gate electrode of said second field-effect transistor.
  • a logic element including, in combination: a first field-effect transistor having source, gate and drain electrodes with said gate electrode connected to said source electrode and said drain electrode connectable to a voltage supply, a second field-effect transistor having source, gate and drain electrodes with the drain electrode thereof connected to the source electrode of said first field-effect transistor, said source electrode of said second field-effect transistor resistively connected to a point of reference potential, an input source follower field-effect transistor having source, gate and drain electrodes with the drain electrode thereof connectable to said voltage supply and the gate electrode thereof connected to an input terminal for receiving binary logic signals, said source electrode of said source follower field-effect transistor resistively connected to the source electrode of said second fieldeffect transistor and said gate electrode of said second field-effect transistor connected to a point of reference potential, said binary logic signals at said input terminal providing a voltage variation at the source electrode of said second field-effect transistor and producing relatively large change in voltage level at the drain electrode of said second field-effect transistor, said change in voltage level at said drain electrode of said second field-effect transistor being in the same direction as the

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US345667A 1964-02-18 1964-02-18 Logic elements using field-effect transistors in source follower configuration Expired - Lifetime US3299291A (en)

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US345667A US3299291A (en) 1964-02-18 1964-02-18 Logic elements using field-effect transistors in source follower configuration
FR4934A FR1429490A (fr) 1964-02-18 1965-02-10 éléments logiques à transistors à effet de champ
BE659569D BE659569A (US20110009641A1-20110113-C00160.png) 1964-02-18 1965-02-11
CH187065A CH425893A (fr) 1964-02-18 1965-02-11 Elément logique à transistors à effet de champ
NL6501915A NL6501915A (US20110009641A1-20110113-C00160.png) 1964-02-18 1965-02-16

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Cited By (19)

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US3427445A (en) * 1965-12-27 1969-02-11 Ibm Full adder using field effect transistor of the insulated gate type
US3471712A (en) * 1964-12-28 1969-10-07 Nippon Electric Co Logical circuit comprising field-effect transistors
US3517175A (en) * 1966-08-25 1970-06-23 Plessey Co Ltd Digital signal comparators
US3541353A (en) * 1967-09-13 1970-11-17 Motorola Inc Mosfet digital gate
US3597626A (en) * 1969-04-01 1971-08-03 Bell Telephone Labor Inc Threshold logic gate
US3604944A (en) * 1970-04-09 1971-09-14 Hughes Aircraft Co Mosfet comparator circuit
US3638036A (en) * 1970-04-27 1972-01-25 Gen Instrument Corp Four-phase logic circuit
US3875430A (en) * 1973-07-16 1975-04-01 Intersil Inc Current source biasing circuit
US3917958A (en) * 1972-08-25 1975-11-04 Hitachi Ltd Misfet (Metal -insulator-semiconductor field-effect transistor) logical circuit having depletion type load transistor
US4023047A (en) * 1976-02-19 1977-05-10 Data General Corporation MOS pulse-edge detector circuit
US4028556A (en) * 1974-03-12 1977-06-07 Thomson-Csf High-speed, low consumption integrated logic circuit
US4300064A (en) * 1979-02-12 1981-11-10 Rockwell International Corporation Schottky diode FET logic integrated circuit
US4405870A (en) * 1980-12-10 1983-09-20 Rockwell International Corporation Schottky diode-diode field effect transistor logic
WO1983004352A1 (en) * 1982-06-01 1983-12-08 Hughes Aircraft Company Current-driven enfet logic circuits
US4697110A (en) * 1982-11-27 1987-09-29 Hitachi, Ltd. Fluctuation-free input buffer
US4725743A (en) * 1986-04-25 1988-02-16 International Business Machines Corporation Two-stage digital logic circuits including an input switching stage and an output driving stage incorporating gallium arsenide FET devices
US5239208A (en) * 1988-09-05 1993-08-24 Matsushita Electric Industrial Co., Ltd. Constant current circuit employing transistors having specific gate dimensions
US5374862A (en) * 1992-02-28 1994-12-20 Sony Corporation Super buffer and DCFL circuits with Schottky barrier diode
RU2704748C1 (ru) * 2019-04-09 2019-10-30 Федеральное государственное бюджетное образовательное учреждение высшего образования "Юго-Западный государственный университет" (ЮЗГУ) Триггерный логический элемент НЕ на полевых транзисторах

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CH506920A (de) * 1969-08-04 1971-04-30 Ibm Halbleiterschaltung zur Verarbeitung binärer Signale
FR2230125A1 (en) * 1973-05-16 1974-12-13 Thomson Csf Intergrated FET voltage converter with FET in series with resistor - to give constant difference between input and output voltages

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US3100838A (en) * 1960-06-22 1963-08-13 Rca Corp Binary full adder utilizing integrated unipolar transistors
US3135926A (en) * 1960-09-19 1964-06-02 Gen Motors Corp Composite field effect transistor

Patent Citations (3)

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US3058007A (en) * 1958-08-28 1962-10-09 Burroughs Corp Logic diode and class-a operated logic transistor gates in tandem for rapid switching and signal amplification
US3100838A (en) * 1960-06-22 1963-08-13 Rca Corp Binary full adder utilizing integrated unipolar transistors
US3135926A (en) * 1960-09-19 1964-06-02 Gen Motors Corp Composite field effect transistor

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3471712A (en) * 1964-12-28 1969-10-07 Nippon Electric Co Logical circuit comprising field-effect transistors
US3427445A (en) * 1965-12-27 1969-02-11 Ibm Full adder using field effect transistor of the insulated gate type
US3517175A (en) * 1966-08-25 1970-06-23 Plessey Co Ltd Digital signal comparators
US3541353A (en) * 1967-09-13 1970-11-17 Motorola Inc Mosfet digital gate
US3597626A (en) * 1969-04-01 1971-08-03 Bell Telephone Labor Inc Threshold logic gate
US3604944A (en) * 1970-04-09 1971-09-14 Hughes Aircraft Co Mosfet comparator circuit
US3638036A (en) * 1970-04-27 1972-01-25 Gen Instrument Corp Four-phase logic circuit
US3917958A (en) * 1972-08-25 1975-11-04 Hitachi Ltd Misfet (Metal -insulator-semiconductor field-effect transistor) logical circuit having depletion type load transistor
US3875430A (en) * 1973-07-16 1975-04-01 Intersil Inc Current source biasing circuit
US4028556A (en) * 1974-03-12 1977-06-07 Thomson-Csf High-speed, low consumption integrated logic circuit
US4023047A (en) * 1976-02-19 1977-05-10 Data General Corporation MOS pulse-edge detector circuit
US4300064A (en) * 1979-02-12 1981-11-10 Rockwell International Corporation Schottky diode FET logic integrated circuit
US4405870A (en) * 1980-12-10 1983-09-20 Rockwell International Corporation Schottky diode-diode field effect transistor logic
WO1983004352A1 (en) * 1982-06-01 1983-12-08 Hughes Aircraft Company Current-driven enfet logic circuits
US4697110A (en) * 1982-11-27 1987-09-29 Hitachi, Ltd. Fluctuation-free input buffer
US4725743A (en) * 1986-04-25 1988-02-16 International Business Machines Corporation Two-stage digital logic circuits including an input switching stage and an output driving stage incorporating gallium arsenide FET devices
US5239208A (en) * 1988-09-05 1993-08-24 Matsushita Electric Industrial Co., Ltd. Constant current circuit employing transistors having specific gate dimensions
US5374862A (en) * 1992-02-28 1994-12-20 Sony Corporation Super buffer and DCFL circuits with Schottky barrier diode
RU2704748C1 (ru) * 2019-04-09 2019-10-30 Федеральное государственное бюджетное образовательное учреждение высшего образования "Юго-Западный государственный университет" (ЮЗГУ) Триггерный логический элемент НЕ на полевых транзисторах

Also Published As

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NL6501915A (US20110009641A1-20110113-C00160.png) 1965-08-19
FR1429490A (fr) 1966-02-25
BE659569A (US20110009641A1-20110113-C00160.png) 1965-05-28
CH425893A (fr) 1966-12-15

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