US3242394A - Voltage variable resistor - Google Patents

Description

March 22, 1966 J. R. BlARD 3,242,394

VOLTAGE VARIABLE RESISTOR Filed May 2, 1960 3 Sheets-Sheet 1 INVENTOR.

JAMES R. BIARD STEVENS, DAVIS, MILLER 8 MOSHER March 22, 1966 J. R. BIARD 3,242,394

VOLTAGE VARIABLE RES IS'I'OR Filed May 2, 1960 3 Sheets-Sheet 2 LL! 0 O I) C) 2 O O ...1 LL] 2 Z I O GATE VOLTAGE Fig. 3

Ohmic COMCICTS Source. Drain. 2| J 3:! (T -22 Gate.

Fig. 4

INVENTOR.

JAMES R. BIARD STEVENS, DAV/S, MILLER 8 MOSHER March 22, 1966 J. R. BIARD 3,242,394

VOLTAGE VARIABLE RESISTOR Filed May 2, 1960 3 Sheets-Sheet 5 IMPURITY I K m o I l J .l .2 .3 .4 .5 .6 .7 .8

DISTANCE IN MILS Fig. 5

INVENTOR.

JAMES R. BIARD STEVENS, DAVIS, MILLER 8 MOSHER United States Patent 3,242,394 VOLTAGE VARIABLE RESISTOR James R. Biard, Richardson, Tex., assignor to Texas Instruments, Incorporated, Dallas, Tex., a corporation of Delaware Filed May 2, 1960, Ser. No. 26,207 3 Claims. (Cl. 317-235) This invention relates to field-effect devices and more particularly to field-effect devices that operate as conductances (or resistances) which are themselves essentially linear and which are linearly variable over a greatly extended range.

Although the principles underlying the invention may find expression in a variety of structures, the particular example herein selected for illustrative description relates to a diffused device which exhibits a linear conductance.

Linearly variable resistors are broadly old in the art. Thus, for example, the common potentiometer can be produced to have a resistance characteristic linearly variable with shaft rotation. Other types of variable resistors have also been proposed. Some of these have taken the form of more refined and rapidly-responsive devices among which are, for example, photo-conductive elements in which the resistance between two terminals varies significantly as a function of incident light.

Still other types of voltage-variable resistors have been known. Thus, for example, it has been recognized that a conventional field-effect transistor can be operated as a voltage-variable resistor in the range below pinch-off Voltage. However, problems have been encountered when it has been desired to exploit field-effect transistors as voltage-variable resistors, for it has been found that only a small part of the range below breakdown voltage can be used if reasonable approximation to linearity is desired.

As a consequence of the above considerations, fieldeifect transistors have not found favor as voltage-variable resistors. An understanding of the present invention can perhaps be better gained if certain fundamentals are first discussed. Such fundamentals include the terms pinchoff, breakdown, source, drain, channel, and gate.

By field-effect device is meant an electronic element in which a conductive path between two terminals is changed in resistance by an effective change in the internal geometry of the conducting path. This change in internal geometry results from changes in depletion regions which result from variations in internal electric fields associated with p-n junctions. By channel is meant the aforementioned conductive path.

Source and drain are terms used to identify the end terminals of the channel, and gate is the region to which the controlling voltage is applied and which, under the influence of the controlling voltage, is effective to change the internal geometry of the conducting path.

Pinch-off is a term applied to characterize the condition that exists when a depletion region extends entirely across (across as contrasted to along) the channel; and breakdown characterizes the level of gate voltage at which significant amounts of current begin to flow between gate and channel.

All of the above terms are well understood to men skilled in the art of field-effect transistors.

Conventional field-effect transistors have heretofore been proposed principally for amplification and constant current functions. Consequently, the characteristics thereof have been such as to severely limit use as voltage-variable resistors. Thus, for example, pinch-off has occurred at relatively low bias values, while breakdown voltage has been very significantly greater. These characteristics have been desirable in prior art structures because they have made it possible to achieve very high dynamic impedances,

results which accrue because of exceedingly great changes in source-to-drain voltages with exceedingly small changes in current.

Departing radically from the teachings of the prior art, it has been discovered that the useable range of a fieldefi'ect device as a voltage-variable resistor can be extended severalfold by exploiting a unique combination of doping levels, gradients and physical geometries to produce a field-effect transistor in which the pinch-off voltage occurs at very nearly the same point as the breakdown voltage. Thus, not only is the useable range extended severalfold, but, as will be hereinafter explained, the greatly extended range is itself significantly more linear and much less sen sitive to undesired self-biasing than the corresponding small range of conventional field-eliect devices.

It is one general object of this invention to improve voltage-variable resistance devices.

It is another object of this invention to prove linearities in voltage-variable resistance devices. In this connection, the subject matter of this invention is particularly advantageous in two respects: first, because the useable range is greatly extended, the ratio between the controlling volt age and any voltage internally developed (i.e., self-bias voltage) is greatly enlarged, with a consequent decrease in adverse effects. Second, the change in conductance through the device with change in control (gate) voltage is rendered more significantly uniform, thereby resulting in a more linear response.

These and other objects and features of the invention will be apparent from the following detailed description, by way of example, with reference to the drawing in which FIGURE 1 is a graphical plot of conventional field-effect transistor curves;

FIGURE 2 is a corresponding plot of curves which represent the device of this invention;

FIGURE 3 is a composite plot of channel conductance versus gate voltage for both the device of this invention and a representative device of the prior art;

FIGURE 4 is a cross sectional view of one type of physical construction embodying the features of the invention; and

FIGURE 5 is a chart which illustrates impurity concentrations in the regions of the structure of FIGURE 4.

Now turning more particularly to a discussion of the prior art in order that the present invention may be more clearly emphasized, it will be recognized that FIGURE 1 is a plot of the characteristics of a conventional fieldeffect transistor. Drain current is plotted against drain voltage, with the various individual curves representing operating conditions with the indicated gate voltages. For the purposes of this description and the graph of FIGURE 1, drain voltage is considered to be that voltage which exists between the source and drain terminals. Correspondingly, the gate voltages are those which exist between the gate and source terminals.

Reference to FIGURE 1 results in the observation of certain characteristics which distinguish the curves. Thus, there is significant curvature at relatively low drain voltages, and there are extended regions in which the curves are almost flat. These characteristics are exceedingly desirable in conventional field-effect transistors, for it is the fiat regions of the curves that give rise to high mutual conductance.

The pinch-off voltages applying to the curves of FIG- URE l are shown as dashed-line intersections with the solid curves; and it is deemed of particular significance that they all fall well within the left-hand portion of the graph. Thus, it will be apparent that the pinch-off voltages occur at values greatly less than those of breakdown (indicated V in the graph); and, for reasons that will be later appreciated, the occurrence of pinch-off at relatively low values greatly limits the range of useable voltages which may be applied to control a field-effect device as a voltage-variable resistor.

FIGURE 2 is seen to differ very significantly from FIGURE 1. Here, the curves are more nearly straight, for they represent structures in which pinch-off and breakdown occur at essentially the same point. For the purposes of this description and in order to simplify an understanding of the inventive principles, it will be assumed that channel current is maintained at a relatively low value.

As will be apparent from the above discussion, the self-biasing effect that results from a flow of current through the channel will have an effect upon operation of a field-effect device. Consequently, while in the ensuing description of FIGURE 3 a single curve is compared with a corresponding single curve, it should be understood that a general case treatment would include an entire family of curves individually representing various external and self-biasing values. However, the curves in FIGURE 3 merely depict two corresponding plots (both with the drain current near zero) which point up the significant distinctions of the present invention over the prior art.

Now observing FIGURE 3 in more detail, it will be observed that it includes two plots 10 and 11 of channel conductance versus gate voltage. Curve 10 represents the prior art and is seen to have a very steep slope which exhibits an appreciable amount of curvature. Moreover, it will be observed that it intersects the X axis at a relatively low gate voltage, a fact which (as mentioned above) severely limits the useable range. Also, as mentioned above, such prior art curve necessarily occurs as a result of design considerations necessary to impart favorable characteristics to a field-effect transistor.

Curve 11 in FIGURE 3 characterizes applicants invention. It will be observed to be essentially linear over a major portion of its range. Moreover, it intersects the X axis at a relatively high gate voltage, a fact which graphically represents the severalfold increase in operating range to which reference was made above. Additionally, since the relatively straight-line portion of curve 11 is less steeply sloped than that of curve 10, there is less sensitivity to changes in gate voltage, a fact which gives rise to the above-mentioned feature in which the device of this invention is substantially less sensitive to changes in self-induced bias than that of the prior art.

One representative structure embodying the principles of the invention is portrayed in FIGURE 4. There, it will be observed, is depicted a slice of semiconductor material which contains a lower region 12 of one conductivity type, an adjacent region 13 of opposite conductivity type, and a top layer 14 of conductivity type similar to that of lower region 12. The particular structure illustrated may be made by diffusing selected impurities to give predetermined impurity concentrations and gradients. The manner in which this is accomplished can be more clearly understood by referring to FIGURE which portrays related impurity concentration profiles. In FIG- URE 5, the ordinate is the absolute value (without regard to sign) of the algebraic sum of donor and acceptor impurities, while the abscissa is the distance in mils downward from the top surface of the semiconductor wafer shown in FIGURE 4.

Horizontal line 15 extends horizontally across the graph parallel to the X axis and represents an initial homogeneous doping of the wafer to a level of atoms per cc. The wafer may be of any suitable semiconductor material such as, for example, germanium or silicon, although the material contemplated in this preferred embodiment is silicon. The initial doping impurity may be one of the conventional donor or acceptor materials, although in this description it is assumed that an acceptor such as boron, aluminum, gallium or indium is used. Into the top surface of the doped wafer is diffused an opposite type impurity which in this example would be a donor such as phosphorus, arsenic, or antimony. This diffusion is preferably accomplished from a very low surface concentration such as 10 atoms per cc. shown at the intersection of curve 16 with the Y axis. From an observation of this curve, it will be noted that the concentration drops off with distance into the wafer according to a co-error function which conventionally results from vapor diffusion.

The specific times, temperatures, and vapor pressures required to accomplish the diffusion of curve 16 will depend upon the impurity involved. However, one set of suitable conditions envisions vapor diffusing the impurity material in accordance with data given in an article by C. S. Fuller and J. Ditzenberger entitled, Diffusion of Donor and Acceptor Elements in Silicon, appearing at pages 543-553 of the Journal of Applied Physics, volume 27, May, 1956. Times and temperatures may also be correlated by reference to the classical formula for impurity diffusion, namely,

where N is equal to the impurity concentration at any depth, erfc is the co-error function, X is the depth from the surface of the wafer, D is the diffusion coefficient of the material employed and t is the time, and N is the surface concentration.

After the initial diffusion, a suitable impurity of the type originally employed in doping the wafer (in this example, an acceptor) is diffused into the upper surface to form layer 14 (FIGURE 4). This latter diffusion is characterized by curve 17 (FIGURE 5) which is observed to be almost vertical. The diffusion represented by curve 17 is accomplished from a high impurity concentration and during a very brief period of time for two reasons. The first is so as not to disturb significantly the profile of curve 16; and the second is to produce a very thin layer of highly doped material. Again, times and temperature may be obtained by referring to the foregoing reference.

The net impurity concentrations in the wafer are the algebraic sums of the distributions given by the three curves 15, 16, and 17. The net values have been plotted for the three regions of the wafer, that portion of the net curve which represents region 14 being identified with the symbol 18, that portion which represents region 13 being identified with the symbol 19, and that portion of the curve which represents region 12 being identified with the symbol 20. Thus, it will be noted that the net impurity concentration drops very rapidly from a high value at the upper surface to the first p-n junction which is located slightly less than one-tenth of a m-il inside the wafer. Then, proceeding further downwardly, the net impurity concentration rises along curve 19 until it reaches a maximum 23, after which it declines to zero at four-tenths of a mil below the wafer surface and then rises gradually to .the original value of the homogeneously doped wafer.

As mentioned above, the principles underlying this invention may be applied to produce either a device having a linear resistance characteristics or one having a linear conductance characteristic. For purposes of this illustrative description, the latter is portrayed. The considerations which give rise to linearity in conductance may be observed from referencve to FIGURE 5 and a recognition of the significances of the curves therein displayed.

FIGURE 4 shows layers 12 and 14 to be connected as gate terminals, while source and drain terminals 21 and 22 are connected through ohmic contacts to layer 13. It is the channel (i.e., region 13) whose conductance is under consideration, and it will be recognized that changes in effective internal geometries of the channel are the factors which result in changing device conductance.

As is well known in the art, when a reverse-bias voltage is applied to a p-n junction, a depletion region exists ad- N=N erfc jacent the junction. The boundary of the depletion region moves as a direct function of the absolute value of the applied reverse bias and an inverse function of the doping level.

When a gate bias is applied to the device of FIGURE 4, a depletion region is formed within all three of the layers 12, 13 and 14. However, because layer 14 is highly doped, the penetration of the depletion region into that layer is negligible and can be ignored. However, because layer 13 is much more lightly doped, penetration of the depletion region into that layer is significant and, with increasing bias voltage will extend beyond the peak 23 of curve 19 in FIGURE 5. Thereafter, if gate voltage is increased, the depletion region will extend into the downwardly sloping region. At the same time, depletion is occurring at the junction between layers 12 and 13, and since the concentration in layer 12 is low compared to that of layer 13, significant penetration of the depletion region into both layers 12 and 13 results.

The shape of the negatively sloped portion of curve 19 is particularly significant with respect to .two factors. First, once the depletion about the junction between layers 13 and 14 has passed the peak 23, the leading edge progresses incrementally into more lightly doped material. However, at the same time, the leading edge of the depletion layer extending into region 13 from below incrementally extends into more richly doped material; and these two tend to oflFset each other thereby effectively to change the channel geometry without changing average resistivity.

Second, the nonhomogeneity of doping within the channel region itself is important. Thus, for example, if channel 13 were uniformly doped throughout, each successive incremental amount of voltage applied to the gate would advance the leading edge of the depletion area a smaller amount. Thus, the internal geometry of the channel would not be linearly constricted as a function of gate voltage. However, if the channel is not uniformly doped throughout but is doped to produce a properly shaped profile, then each successive incremental change in gate voltage will advance the leading edge of the depletion area an essentially equal distance, thereby resulting in a uniform constriction.

It will be appreciated that linearities according to this invention may not be exact, although results obtained have been extremely close approximations. In this connection it will be observed that the shape of curve 19 is such that with each increment of applied gate voltage, the leading edge of the depletion area adjacent the upper p-n junction advances down curve 19 .an essentially equal distance with each increment of applied gate voltage. Although such distance is not exactly equal for each increment, the initial doping level in the wafer is selected such that a corresponding advance of the depletion layer from the lower p-n junction essentially offsets any nonlinearity in that of the upper layer advance, thereby resulting in a net uniform constriction of the channel with a consequent uniform change in channel conductance.

In summary, it will be observed that the two abovementioned significant factors are both present. Thus, not only does the net resistivity of the channel remain essentially constant with changes in gate voltage, but the net changes in channel geometry occur linearly as a function of the gate voltage. Consequently, it will be seen that channel conductance will change as a linear function of the applied gate voltage.

As heretofore mentioned, the operable range of the device is greatly extended by characterizing the construction so that the breakdown and pinch-off voltages occur at substantially the same point. This can be accomplished by properly relating the width of the channel to the absolute doping levels.

It will be recalled that pinch-off occurs when the depletion region extends entirely across the channel, and the voltage at which this occurs is a direct function of channel width. Moreover, the rate at which the depletion region advarnces with applied voltage is an inverse function of impurity concentration. The breakdown voltage, on the other hand, is a function not of channel width but of doping levels immediately adjacent the gate-channel junction. Consequently, although pinch-off and breakdown are both impurity concentration dependent, channel Width over the range contemplated influences pinchoff only. Thus, with an optimized doping condition, channel width can be varied sufiiciently to condition pinch-off at a value essentially equal to breakdown.

Although the subjectinvention has been illustrated by a particular embodiment thereof, it is not to be limited to the specific device herein disclosed. Various applications, modifications and arrangements of the invention will readily occur to those skilled in the art. For example, by the advantageous employment of the principles herein illustrated, devices having channels whose resistance varies linearly as a function of applied gate voltage could be readily fabricated. Moreover, various other structural arrangements could be employed to embody the principles of the invention.

The terms and expressions herein used in reference to the invention are terms of description and not of limitation, and there is no intention in the use of such terms and expressions of excluding equivalents of the features shown and described or parts thereof, but on the contrary it is intended to include therein any and all equivalents, modifications and adaptations which can be employed without departing from the spirit and scope of the invention.

What is claimed is:

1. A monocrystalline field-effect device comprising a first zone of one conductivity-type having an exposed crystal surface, a second zone of opposite conductivitytype, and a PN junction between said first and second zones, said first Zone comprising impurities of said one and said opposite types, said one type impurity having a value of concentration at least ten times greater than the value of concentration of the opposite type impurity at said exposed crystal surface, the value of concentration of said one type impurity at all depths intermediate said surface and said junction being greater than the value of concentration of said opposite type impurity at that depth, said opposite type impurity having a co-error function distribution of decreasing concentration from said exposed crystal surface toward said PN junction and in said first and second zones, said one type impurity having a value of concentration decreasing with depth at a rate of at least ten times the rate of decrease in the value of concentration of said opposite conductivity type impurity in said first zone, said second zone comprising source and drain electrodes with a channel region disposed therebetween, said first zone constituting a gate region having an ohmic electrode disposed between said source and drain electrodes.

2. A semiconductor field-effect device comprising:

(a) a wafer of monocrystalline silicon;

(b) a first P-type gate region defined in the wafer adjacent one major face thereof having an acceptor impurity concentration at least ten times greater than 10 atoms per cubic centimeter and having a depth below the surface of said one major face of less than one-tenth mil;

( c) an N-type channel region defined in the wafer adjacent said one major face thereof, an intermediate portion of the channel region underlying the first gate region so that source and drain portions of the channel region are provided which are connected to one another only by said intermediate portion, the donor impurity concentration in said intermediate portion varying from a value of about 10 atoms per cubic centimeter adjacent said gate region to a value of about 10 atoms per cubic centimeter adjacent the lowermost boundary of said intermediate portion;

((1) a second P-type gate region defined in the wafer adjacent said one major face thereof underlying the channel region and having an acceptor impurity concentration of about 10 atoms per cubic centimeter, the second gate region being uniformly spaced from the first gate region by about three-tenths mil;

(e) ohmic contacts on said gate regions and ohmic contacts on said source and drain portions of said channel region;

(f) means including a voltage source connected to the ohmic contacts on the gate regions and to the ohmic contact on said source portion of said channel to apply a reverse voltage between said gate regions and said source portion of said channel;

(g) the impurity concentrations and gradients thereof and the physical dimensions of the regions providing a predetermined breakdown voltage between the gate regions and thetchannel regions, the breakdown voltage being essentially equal to the pinchoff voltage, and such that successive applications of equal increments of voltage to the gate contacts produce essentially linear changes in the conductance of the channel region between the source and drain portions.

3. A field-effect device comprising a wafer of monocrystalline semiconductor material, a gate region having a net dopant concentration of one type conductivity defined in the wafer adjacent one major face thereof, an ohmic contact on said gate region, a channel region having a net dopant concentration of opposite type conductivity defined in the wafer adjacent said one major face and underlying said gate region, a pair of ohmic contacts on opposite ends of the channel region providing source and drain connections, means including a voltage source connected to the ohmic contact on the gate region and to one of said pair of ohmic contacts to apply a reverse voltage between said gate region and said channel region, the net dopant concentration in said gate region being large relative to the net dopant concentration in said channel region, said channel region having means including a net dopant concentration gradient decreasing away from said gate region such that in response to successive applications of equal increments of said reverse voltage to said gate the electrical conductance between said pair of ohmic contacts changes essentially linearly, the net dopant concentrations in said gate region and in said channel region and the net dopant concentration gradient in said channel region being selected to provide a predetermined breakdown value for said reverse voltage between the gate and channel regions, and the physical dimensions of the channel being selected to provide a pinch-off voltage for the device which is essentially equal to said predetermined breakdown voltage.

References Cited by the Examiner UNITED STATES PATENTS 2,744,970 5/1956 Shockley 179-171 2,754,431 7/1956 Johnson 307-885 2,936,425 5/1960 Schockley 330-39 2,940,022 6/1960 Pankove 317--235 2,951,191 8/1960 Herzog 317-235 2,979,427 4/1961 Schockley 1481.5 3,028,655 4/1962 Dacey et al. 29--25.3 3,152,294 10/1964 Siebertz et al. 317--235 JOHN W. HUCKERT, Primary Examiner.

LLOYD MCCOLLUM, DAVID J. GALVIN, Examiners.

Claims (1)

1. 3. A FIELD-EFFECT DEVICE COMPRISING A WAFER OF MONOCRYSTALLINE SEMICONDUCTOR MATERIAL, A GATE REGION HAVING A NET DOPANT CONCENTRATION OF ONE TYPE CONDUCTIVITY DEFINED IN THE WAFER ADJACENT ONE MAJOR FACE THEREOF, AN OHMIC CONTACT ON SAID GATE REGION, A CHANNEL REGION HAVING A NET DOPANT CONCENTRATION OF OPPOSITE TYPE CONDUCTIVITY DEFINED IN THE WAFER ADJACENT SAID ONE MAJOR FACE AND UNDERLYING SAID GATE REGION, A PAIR OF OHMIC CONTACTS ON OPPOSITE ENDS OF THE CHANNEL REGION PROVIDING SOURCE AND DRAIN CONNECTIONS, MEANS INCLUDING A VOLTAGE SOURCE CONNECTED TO THE OHMIC CONTACT ON THE GATE REGION AND TO ONE OF SAID PAIR OF OHMIC CONTACTS TO APPLY A REVERSE VOLTAGE BETWEEN SAID GATE REGION AND SAID CHANNEL REGION, THE NET DOPANT CONCENTRATION IN SAID GATE REGION BEING LARGE RELATIVE TO THE NET DOPANT CONCENTRATION IN SAID CHANNEL REGION, SAID CHANNEL REGION HAVING MEANS INCLUDING A NET DOPANT CONCENTRATION GRADIENT DECREASING AWAY FROM SAID GATE REGION SUCH THAT IN RESPONSE TO SUC-

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