US3220895A - Fabrication of barrier material devices - Google Patents

Description

Nov. 30, 1965 A. J. CAGGIANO 2 FABRICATION OF BARRIER MATERIAL DEVICES Filed Aug. 25, 1961 3 Sheets-Sheet 1 F/G 1b /0 ANTHONY J. CAG'G/A/VO ATTORNEY Nov. 30, 1965 A. J. CAGGIANO FABRICATION OF BARRIER MATERIAL DEVICES 3 Sheets-Sheet 5 Filed Aug. 25, 1961 lNVE/VTOR V w M m R wflwm m .A K 0 m M6 w United States Patent 3,220,895 FABRICATIGN 0F BARRIER MATERIAL DEVICES Anthony J. Caggiano, Newtonville, Mass., assignor to Raytheon Company, Lexington, Mass, a corporation of Delaware Filed Aug. 25, 1961, Ser. No. 133,906 7 Claims. (Cl. 148-333) This invention relates generally to electrical translating devices and to methods of their manufacture and, more particularly, to barrier or semiconductive devices in which junctions are formed in the body of the barrier or semiconductive material.

A number of problems inherently reside in the fabrication of semiconductive devices, such as transistors, by the gaseous diffusion process. For example, in the prior art gaseous diffusion process, the semiconductive slice is impregnated with the gaseous impurity on both surfaces resulting in the formation of two P-N junctions or transition layers, one on each side, and during the fabrication of a transistor from such a diffused slice one of these P-N junctions must be removed by grinding or lapping resulting in the loss of material approximating one half of the original slice. Further, if the diffused junction is found to be faulty the semiconductive slice cannot be reprocessed. Still further, the diffusion process requires bulky, expensive equipment and a process time ranging from two to four hours. In addition, a problem exists in properly attaching and positioning the extrinsic base resistance of the device to as low a value as possible consistent with other device parameters without causing shorting between the emitter and base regions. Such diffusion techniques also require reliance upon variable factors such as diffusion depth penetration, emitter depth penetration and penetration of the base contact into the body of the semiconductive material. All these factors require control and militate against the reproducibility of a given device structure.

Accordingly, the present invention is directed toward the realization of a semiconductive device structure, which from its normal construction method, minimizes or completely eliminates the effect of the variable emitter and base depth penetrations and achieves more closely controlled electrical parameters. Other benefits over those of the diffusion process also occur; for example, since only one surface is processed no material is lost through grinding or lapping and if improperly processed the semiconductive slice can be quickly and easily salvaged. Also less expensive equipment is used and the time required for processing is reduced to approximately twenty minutes. Further, the beneficial results achieved by epitaxial growth can be realized without the necessity of following the epitaxial growth process. Still further, in devices of the present invention the semiconductive body is provided with a low-resistance metallic surface layer resulting in a low resistance path which extends in close proximity to the emitter junction or transition layer and does not require accurate positioning of a base connection to the layer. Preferably, these and other benefits are accomplished by fabricating the device from a body of semiconductive material which is provided with a relatively thin surface layer of high conductivity material. An emitter element containing an impurity material of opposite con- 'ice ductivity type from that of the surface layer is positioned on the surface layer. The assembly is then heated to a temperature sufficient to melt both the surface layer and the emitter element (but not to melt the semiconductive body) to cause them to penetrate or alloy into the chip to produce the desired emitter and collector junctions or transition layers having a base region between them which remains in electrical contact with a highly conductive surface layer. It is believed that during alloying and regrowth process the metallic materials comprising the base region and the emitter region tend to remain substantially segregated from each other such that little or no clean-up by chemical or electrolytic etching between these two regions are necessary to provide proper operation.

The invention will be better understood as the following description proceeds taken in conjunction with the ac companying drawings wherein:

FIGS. 1a through 1h show a semiconductive device in various stages of fabrication in accordance with the present invention;

FIGS. 2a through 2d show an alternative embodiment of a device fabricated in accordance with the present invention;

FIGS. 3a through 30 show still another alternative embodiment of a semiconductive device in accordance with the present invention; and

FIG. 4 shows a pictorial view of a completed transistor after completion of the device has been effected by encapsulation of the device in a suitable housing.

Referring now to FIGS. 1a through 111, the process of fabrication of a semiconductive device will be describe in detail.

Although the particular example to be described has been found most beneficial when the semiconductive body comprises a silicon chip or wafer, it should be thoroughly understood that the invention can also be applied to any other kind of semiconductive or barrier material as, for example, germanium, germanium-silicon compounds, and other compounds known as inter-metallic compounds which are formed from element of Groups III and V of the Periodic Table as, for example, gallium arsenide, indium antimonide, indium arsenide and the like, which have resistivity ranges from 10- ohm-cm. to 10 ohm-cm. The term barrier material as used throughout the specification and claims is intended to include those materials having a forbidden energy band. In FIG. 1a there is shown a body of silicon 10 which has been doped with an appropriate N-type (Group V) impurity such as phosphorous, or antimony. In the example shown, the body 10 has a resistivity of approximately 2 ohm-centimeters. The chip is next coated with a thin layer or element of a P-type impurity material (Group III element), in this case, aluminum, to provide the layer 12 of highly conductive material on the surface of the chip 10. The aluminum layer may have a thickness ranging from about 500 A. to about 3000 A., but for the present embodiment, the thickness of the aluminum layer 12 (FIG. lb) is approximately 1000 A. It should be noted that the thickness of the aluminum layer is critical within limits since a layer which is too thick will smear with the emitter element during the subsequent heating process and will also act to lower the forward current gain d of the finished unit. On the other hand, if the aluminum layer 12 is too thin, the extrinsic base resistance and other parameters of the device will be deleteriously affected. The layer 12 may be applied to the body 10 by a vapor evaporation and deposition process in accordance with techniques well known in the art, or by any other suitable technique providing similar end results. For example, this may be accomplished by placing the body 14) into an evacuated chamber having a 1O mm. vacuum and vaporizing aluminum from a hot Wire in the evacuated space such that the vaporized aluminum deposits on the body 10. The thickness of the layer 12 being accurately controlled by controlling the deposition time and distance, or volume of the aluminum source.

After deposition of the aluminum layer 12, the semiconductive body is removed from the evacuated chamber and appears as shown in FIG. 1b in which the aluminum metal layer 12 is positioned on the upper surface of the body 10. If upon visual inspection this aluminum layer is found to be faulty, then the layer may be easily stripped from the slice and the slice recoated. The next step, as shown in FIG. 10, in the process consists in providing the body with an appropriate emitter element 13. To this end a pellet or dot 13 of an N-type impurity material (Group V element) is placed on the aluminum layer 12. In the process being described, the dot or pellet 13 comprises a small cylinder approximately .005 inch to .010 inch in diameter and .0025 inch thick of an alloy consisting of 99% silver and 1% arsenic. It should be thoroughly understood that the use of a pellet or dot in such a case is only descriptive of the particular embodiment and that the same results can be accomplished by vapor evaporation and deportion process or by other suitable techniques in which appropriately doped materials are placed upon the surface of the layer 12 in the same manner as if a doped pellet were placed thereon. With the pellet 13 positioned in place, the assembly is inserted into a conventional firing furnace and heated to a temperature of about 1150 C. for approximately five minutes at which time both the pellet 13 and the aluminum layer 12 are changed into a molten state. This temperature is above the eutectic point of the layer 12 and the body 10. This phase of the process may be described as essentially an alloying phase. The temperature in the furnace is then reduced to approximately 1100 C., which is below the eutectic temperature of the layer 12 and the body 10 but over the melting point of the layer 12 and the pellet 13, and held at this temperature for a time period of approximately twenty minutes. After the above-described heating cycle the assembly appears as 'shown in FIG. 1d in which the aluminum layer 12 has penetrated into the body 10' not only at the surface region but also under the emitter pellet 13. The portion 14 (FIG. 1e) under the pellet 13 comprises the active base region of the device and merges continuously into the surface layer portions thereby providing a highly conductive appropriately doped metallic layer 12a at the surface of the body 10 to which a subsequent base connection may be easily made. It has been found that the width of the base region 12a is substantially the same at the surface of the device and in the portion 14 under the pellet 13. In the particular example in which the layer 12 was approximately 1000 A. thick, the thickness of the resulting base region 14 is approximately 20,000 A. thick.

Although the action which takes place during the alloying phase of the heating process to form the emitter and base regions is not completely understood, it is known that the greater portion of the base region is formed by a process of diffusion with the result that the base region is provided with an impurity gradient across its width which enhances the high frequency response of the device due to the built-in electric field resulting from the distribution of the impurities. However, as to the alloying phase, it is believed that the layer of aluminum metal beneath the emitter 13 appears to stay substantially segregated from the material composing the dot 13 and hence mony, tantalum or bismuth.

moves into the semiconductive body ahead of the emitter material.

While the mechanism by which this is accomplished is not completely understood, it is believed that the following process occurs.

As the structure depicted by FIG. 1c is heated, the molten aluminum layer 12 commences to dissolve the silicon immediately below it. This process continues throughout this aluminum layer 12 until this layer 12 becomes saturated with silicon. At this point, no further penetration of the aluminum into the silicon 10 occurs, due to alloying. However, the aluminum layer 14 immediately under the emitter 13 is also undergoing a similar process of dissolving silicon but does not become saturated with silicon as rapidly as the surrounding layer. This is because of the effect of the molten emitter 13 which becomes a sink for the dissolved silicon in the aluminum layer 12 below it and therefore, by diffusion, enables silicon to flow through this base layer 14 into the-emitter. As the emitter alloy becomes saturated with silicon, no further flowing of silicon through the base region 14 occurs, thus permitting the base region 14 to become saturated with silicon. At this point, no appreciable penetration by the aluminum base region 14 and the emitter 13 occurs by the alloying process. The temperature is next reduced (a) to stop additional penetration and possible mixing of these metals, and (b) to provide a suitable junction or transition layer through regrowth and diffusion. It is during this latter step that considerable parameter improvement occurs, thus providing addition- 211 control over the subsequent characteristics of these devices. Experience with this process indicates little or no absorption by the emitter 13 of the aluminum base layer 14 immediately below the emitter 1 3. This is evidenced by a relatively constant thickness of the base 14 and surface 12 aluminum regions. This latter condition is also extremely important in the control of base width, and hence transistor performance by initial control of the aluminum evaporated thickness.

At this point in the process, a layer of material 15, impervious to etching, is applied to the emitter 13 and for a distance of approximately .005 inch to .010 inch beyond the emitter edge (FIGS. 1e and 1 The purpose of this coating is to permit the removal of excess surface (FIG. lg) and the clean up of the collector to base diode. Essentially, this etching operation forms a pedestal 0r mesa of a height slightly greater than the maximum penetration of the aluminum doped base layer. The layer 15 (FIG. 1e) may be any suitable masking material, as, for example, a lacquer or wax. With the layer 15 in position, the chip 10 may be immersed in an etching solution in order to remove the material outside the masked area and form the pedestal region 16 shown in FIG. 1g. The etching solution may comprise one part hydrofluoric acid, one part nitric acid solution and the chip may be immersed for a time period on the order of three seconds. After removal from the etching solution, the assembly is cleaned preferably in a four step process which comprises dipping the chip successively into a solution of permachlor, then into an ethyl acetate solution, then into the permachlor solution and finally into an alcohol rinse. After the clean-up procedure, appropriate leads (17, 18 and 11), as shown in FIG. 1h, may be attached to the chip in order to form the external conducting leads of the device. The leads may comprise, for example, .005 inch diameter gold wires which are bonded to the emitter, base and collector regions.

Although there has been described herein a specific embodiment of an NPN transistor, it should be thoroughly understood that PNP devices may also be made in the same manner using a slice of semiconductive material which is properly doped and evaporating thereon a layer of suitable N-type doping material such as anti- It should also be understood that similar devices may be made by using any barrier material.

Instead of separately forming the emitter base and collector electrodes of a device in accordance with FIGS. la through Ie, the process depicted in FIGS. 2a through 2d may be utilized. In this process, a semiconductive chip 20 is provided with a deposited layer of aluminum 21 in a manner similar to that described with respect to FIGS. 11: through 1g. An appropriate emitter pellet 22 as described above, is then placed on top of the layer 21 and a base pellet 23 of a suitable P-type material, for example of substantially pure aluminum is placed on top of layer 21 at a point adjacent to the pellet 22. The aluminum pellet 23 can be the form of a small cylinder approximately .005 inch in diameter and .001 inch thick. The chip 20 is placed upon a suitable conducting element 24 which will form the collector connection of the finished device. The element 24 may be a molybdenum tab. Between the tab 24 and the body 20 a suitable impurity-doped preform may be placed comprising, for example, an element 25 comprised of tin and arsenic in order to provide a substantially ohmic connection to the body 20. With the assembly arraged as shown in FIG. 2a it is then placed into a suitable furnace and sent through the alloying and diffusion heating cycles described above with respect to FIG. 1 in order to cause the layer 21 and pellets 22 and 23 to become molten and alloy with the body 20.

After the heating cycles are completed and the unit has cooled, it appears as shown in FIG. 2b in which the emitter pellet 22 and the base pellet 23 have alloyed into the body 20. The region 26 below the emitter pellet 22 comprises a diffused base region merging into the surface layer 21a similar to the region 14 (FIG. 1) which merges into the surface layer 12a. As with the embodiment shown in FIGS. 1a through 1g, the emitter pellet 22 and the base pellet 23 is next masked with a layer of wax 27, and then subjected to the previously described etching step. After the etching step is completed, the wax layer is removed and the unit appears as shown in FIG. 2d in which the emitter and base pellets rest on the pedestal 28 formed on the top surface of the chip 20. Leads 29 and 30 may then be attached to the pellets in order to provide external connections.

As an alternate embodiment of the present invention a device may be provided in which the area of the evaporated surface layer and the area of the emitter layer is restricted prior to the heating cycle and on which an oxide layer is produced to protect the collector base junction and the emitter base junction and to provide a lower C To this end a semiconductive ohip 40, as shown in FIG. 3a, is provided with a layer of aluminum 41 which extends only over a limited surface area of the base 40. This may be accomplished in one approach by vapor plating the layer 41 onto the surface of the base 40 through a mask 42 which has an opening 43 through which the vaporized aluminum is directed. In this manner only the portion of the chip 40 immediately below the opening 43 becomes plated. After this plating is completed, the mask 42 is removed and a second mask 45, as shown in FIG. 3b, with an opening 46 is placed thereon. An emitter element 44 is then deposited on the layer 41 in the same manner in which the layer 41 was deposited on the body 40. The entire assembly is then placed in a furnace and put through the alloying and diffusion heating cycle previously described in conjunction with FIG. 1. After the heating cycle is completed the unit appears as shown in FIG. 3!: in which the emitter 44 and the base 41 have alloyed into the chip 40 and produced the diffused base region 51 below the emitter 44. As can be seen, the surface or base layer 41 now extends only a limited distance across the top surface of the base 40 thereby reducing the total area of the collector base junction 52 which produces the same effect as the pedestal etching step described with respect to the previous embodiments. Following this heating cycle, a heavy oxide layer 47, as shown in FIG. 3d, is placed over the entire surface of the device. This may be accomplished in any convenient manner such as feeding into the furnace an atmosphere of wet hydrogen. The device is then treated so as to reduce its temperature after which it is removed from the furnace. Thus, the method of FIGS. 3a through 30 eliminates the etching step which is necessary to form the pedestal on the top surface of the chip 40 and the oxide layer prevents any surface inversion layers or other contaminants from adhering to the surface and destroying the P-N junctions formed in the device. The oxide layer 47 is then broken away at selected portions over the emitter area 44 and the base area 41 so that appropriate conducting leads 48, 49 and 50 may be attached to the various regions to provide the connections to the external conducting leads. In such an event the oxide layer 47 must be carefully cut away so that the collector to base junction 52 and the emitter to base junction 53 is not exposed to the ambient.

Referring now to FIG. 4, there is shown a pictorial view of a transistor after completion of the device has been effected by encapsulating the device within a suitable housing. The device could be any of those shown in the previous embodiments, but for the purposes of this description a unit such as described in FIGS. 2a through 2b is shown. In this device the chip 20 attached to the molybdenum tab 24 is mounted on a pair of supporting posts and 61. One of these posts 60 extends through the stem portion 63 of the device. Conducting posts 64 and 65 also extend through the stem 63 and leads 29 and 30 are connected thereto in any suitable manner as by soldering or welding. The housing 66 is attached to the flange 63a of the stem portion 63 at the bottom thereof in order to hermetically seal the device 20 within the outer housing. The external leads 60, 64 and 65 are suitably insulated from the stem 63 by a glass medium 31 around each lead.

This completes the description of the preferred embodiment of the invention. However, many modifications of the invention will be apparent to persons skilled in the art. Accordingly, it is desired that this invention not be limited except as defined by the appended claims.

What is claimed is:

1. A transistor device comprising a body of semiconductor material of one conductivity type comprising a collector region, said body having a surface, a base region of a different conductivity type positioned within said body, said base region and collector region forming a junction at their point of intersection, said collector-tobase junction having its terminus at said surface of said body, an alloyed emitter region of the same conductivity type as said collector region positioned within said base region and said body, said emitter region forming a j-unction with said base region, said base-to-emitter junction having its terminus at said surface of said body, said base region having a partially diffused portion underlying the emitter region and the remainder of said base region having an alloyed portion with a top exposed surface having the resistivity of a conductor which merges into said partially diffused portion, a contaminative protective coating covering said junction terminus, and contacts connected to said regions.

2. A device according to claim 1 wherein said base region comprises a metallic conducting material.

3. A device according to claim 1 wherein said surface is a plane surface.

4. A device according to claim 3 wherein said coating is an oxide layer.

5. A device according to claim 4 wherein said base and emitter contacts pass through openings in said oxide layer to form base and emitter connections with said base and emitter regions, respectively.

6. A device according to claim 5 wherein said base region underlying said emitter region comprises a partially diffused and partially alloyed impurity gradient structure.

7. A device according to claim 1 wherein said base region underlying said emitter region comprises a .pa1'- tially diffused and partially alloyed impurity gradient portion.

References Cited by the Examiner UNITED STATES PATENTS 4/1956 Barnes 14833 2,899,344 8/1959 Atalla 14'8-l-.5 2,970,896 2/1961 Cornelison 1481.5

' 3,010,855 11/1961 'Barson 1481.5

, 3,029,170 4/1962 Lamming 1481.5 5 3,074,826 1/1963 Tum-mers 148-1.5

OTHER REFERENCES Jochems et al.: Construction and Electrical Properties of a Germanium Alloy-Diffused Transistor}? Proceedings 10 of the IRE, June 1958, pages 11611165.

DAVID L. RECK, Primary Examiner. -WINSTON A. DOUGLAS, Examiner.

Claims (1)

1. A TRANSISTOR DEVICE COMPRISING A BODY OF SEMICONDUCTOR MATERIAL OF ONE CONDUCTIVITY TYPE COMPRISING A COLLECTOR REGION, SAID BODY HAVING A SURFACE, A BASE REGION OF A DIFFERENT CONDUCTIVITY TYPE POSITIONED WITHIN SAID BODY, SAID BASE REGION AND COLLECTOR REGION FORMING A JUNCTION AT THEIR POINT OF INTERSECTION, SAID COLLECTOR TOBASE JUNCTION HAVING ITS TERMINUS AT SAID SURFACE OF SAID BODY, AN ALLOYED EMITTER REGION OF THE SAME CONDUCTIVITY TYPE AS SAID COLLECTOR REGION POSITIONED WITHIN SAID BASE REGION AND SAID BODY, SAID EMITTER REGION FORMING A JUNCTION WITH SAID BASE REGION, SAID BASE-TO-EMITTER JUNCTION HAVING ITS TERMINUS AT SAID SURFACE OF SAID BODY, SAID BASE REGION HAVING A PARTIALLY DIFFUSED PORTION UNDERLYING THE EMITTER REGION AND THE REMAINDER OF SAID BASE REGION HAVING AN ALLOYED PORTION WITH A TOP EXPOSED SURFACE HAVING THE RESISTIVITY OF A CONDUCTOR WHICH MERGES INTO SAID PARTIALLY DIFFUSED PORTION, A CONTAMINATIVE PROTECTIVE COATING COVERING SAID JUNCTION TERMINUS, AND CONTACTS CONNECTED TO SAID REGIONS.

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