US3178662A

US3178662A - Large inductance element utilizing avalanche multiplication negative resistance which cancels equal positive resistance

Info

Publication number: US3178662A
Application number: US97196A
Authority: US
Inventors: Johann G Dill; Zuleeg Rainer
Original assignee: Hughes Aircraft Co
Current assignee: Raytheon Co
Priority date: 1961-03-21
Filing date: 1961-03-21
Publication date: 1965-04-13
Anticipated expiration: 1982-04-13

Description

April 13, 1965 J. G. DILL ETAL 3,178,662

LARGE INDUCTANCE ELEMENT UTILIZING AVALANCHE MULTIPLICATION NEGATIVE RESISTANCE WHICH CANGELS EQUAL POSITIVE RESISTANCE Filed Maren 21. 1961 5 Sheets-Sheet l April 1965 J. G. DILL ETAL 3,178,662

LARGE INDUCTANGE ELEMENT UTILIZING AVALANCHE MULTIPLICATION NEGATIVE RESISTANCE WHICH CANCELS EQUAL POSITIVE RESISTANCE Filed March 21. 1961 5 Sheets-Sheet 2 wi w M/II/VF April 1955 J. G. DILL ETAL LARGE INDUCTANCE ELEMENT UTILIZING AVALANCHE MULTIPLICATION NEGATIVE RESISTANCE WHICH CANCELS EQUAL POSITIVE RESISTANCE Filed March 21. 1961 5 Sheets-Sheet 3 Ava m1 Jalawv 0/44, [4/A/A'Z Zazzaa wamv ,1 QM

April 13, 1965 J. DILL ETAL. 3,173,662 LARGE INDUCTANCE ELEMENT UTILIZING AVALANCHE MULTIPLICATION NEGATIVE RESISTANCE WHICH CANCELS EQUAL POSITIVE RESISTANCE Filed March 21. 1961 5 Sheets-Sheet 4 April 13, 1965 J G. DILL ETAL 3,178,662 LARGE INDUCTANCE ELEMENT UTILIZING AVALANCHE MULTIPLICATION NEGATIVE RESISTANCE WHICH CANCELS EQUAL POSITIVE RESISTANCE Filed March 21. 1961 5 Sheets-Sheet 5 A14 Z I MIA Awmwrae United States Patent LARGE INDUCTANCE ELEMENT UTILIZING AVALANCHE MULTIPLICATION NEGATIVE RE- SISTANCE WHICH CANCELS EQUAL POSITIVE RESISTANCE Johann G. Dill and Rainer Zuleeg, Costa Mesa, Calif., assignors to Hughes Aircraft Company, Culver City, Calif., a corporation of Delaware Filed Mar. 21, 1961, Ser. No. 97,196 4 Claims. (Cl. 33380) This invention relates to inductive elements and particularly to an improved semiconductor element that develops a relatively large inductive reactance.

Conventional coil type inductive elements because of the disadvantage of excessive weight and size are impractical for micro miniaturized circuitry. Two terminal inductance elements in the form of diodes may have inductive properties but have the disadvantage of developing a very small inductive reactance. A conventional transistor develops only a limited inductance and then only when the collector is shorted. Also, the capacitive effects of the transistor prevent utilization of this inductance. Another disadvantage of conventional solid state elements that exhibit inductive properties is that they provide a low Q, that is, the ratio of inductive reactance to resistance is low as to be impractical for most applications.

It is therefore an object of this invention to provide a three terminal transistor device that exhibits a relatively large inductive reactance between two selected terminals.

It is a further object of this invention to provide a transistor device that has the base resistance, base width and base cutofi frequency selected to develop a relatively large inductive reactance.

It is a still further object of this invention to provide a semiconductor inductive element operable with a biasing arrangement to develop inductance with a high quality factor Q.

It is another object of this invention to' provide a circuit arrangement utilizing the high Q inductive element to develop very large inductive reactances with a high Q factor.

Briefly, this invention is a transistor device that develops an inductive reactance between the emitter and base. The device has a relatively wide base width so that the ratio of selected operating frequency to base cutoff frequency is sufliciently small to develop a complex current amplification factor oz. selected relatively large within a limited range to develop a large inductive reactance. The transistor device has avalanche multiplication properties so that when properly biased the resistance components are effectively cancelled by the negative resistance properties of the avalanche region to provide an inductance with a high Q factor. To develop very high inductance values also with a high Q factor, a circuit including an impedance multiplying emitter follower arrangement is provided.

The novel features of this invention, as well as the invention itself, both as to its organization and method of operation, will best be understood from the accompanying description taken in connection with the accompanying drawings, in which:

FIG. 1 is a schematic circuit diagram for explaining the inductive element in accordance with this invention;

FIG. 2 is a schematic equivalent circuit diagram of the inductive transistor device of FIG. 1 operating with a high Q factor in accordance with this invention;

FIG. 3 is a schematic equivalent circuit diagram for explaining the properties of the transistor utilized in FIG. 1;

FIG. 4 is a graph of inductive reactance versus base resistance for explaining the limits of the base resistance of the transistor device of FIG. 1 g

The base resistance is t A lfIG. 5 is a Nyquist diagram of inductive reactance and resistance as a function of operating frequency for explainmg the inductive transistor device utilized in FIG. 1;

FIG. 6 is a graph of inductive reactance and resistance as a function of the ratio of operating frequency to base cutolf frequency for explaining the characteristics of the inductive and the resistive components developed by the transistor device of FIG. 1

FIG. 7 is a graph of inductive reactance versus the ratio of operating frequency to base cutoff frequency and inductance versus operating frequency for further explaining the properties of the transistor device of FIG. 1; 1

FIG. 8 is a graph of collector current versus collector voltage for explaining the operating region of the high Q transistor device of FIG. 1;

FIG. 9 is a graph of the Q factor versus collector voltage at selected base resistances and emitter currents for explaining the properties of the high Q transistor device of FIG. 1;

FIG. 10 is a perspective partially sectional view of the structure of one arrangement of an inductive transistor device in accordance with this invention;

FIG. 11 is a perspective view of another arrangement of the inductive transistor device in accordance with this invention;

FIG. 12 is a schematic circuit diagram of an impedance multiplying emitter follower arrangement for developing very high inductive reactances in accordance with this invention; and

FIG. 13 is a schematic view of a semiconductor element in accordance with this invention to be utilized as the transistor devices of FIG. 12.

Referring first to the circuit diagram of FIG. 1, a transistor device 10 which may be of the p-n-p type has an emitter coupled to a first terminal 12 and a base coupled through a base resistor 14 to ground in a grounded base configuration. The resistor 14 is also coupled through a lead 18 to a second terminal 20. The base resistor 14 has a value r which includes the value of the intrinsic base resistance r (FIG. 3) of the transistor 10 as well as the value of any external resistance. One feature of the transistor device in accordance with this invention is to provide the selected base resistance t in the semiconductor structure thereof to eliminate the bulky external resistor.

The emitter of the transistor 10 is biased from a source of potential such as a battery 22 developing a potential +V and having a negative terminal coupled to ground and a positive terminal coupled through a resistor 24 to the emitter to provide asubstantially constant current source for emitter current I The collector of the transistor 10 is coupled through a lead 26 to a suitable source of biasing potential such as a negative terminal of a battery 30 having a positive terminal coupled to ground and providing a potential -V For providing an AC. (alternating current) short to ground, a capacitor 32 is coupled between the lead 26 and ground.

Between the terminals 12 and 21 the transistor device in accordance with the invention develops an inductive reactance Z as shown between

terminals

36 and 38 of the equivalent circuit of FIG. 2. When biased in one region of operation, the transistor 10 develops in series an inductance L of an inductor 42 and a resistance R of a resistor 44. When the transistor 10 has avalanche multiplication characteristics and is biased as determined by the batteries 22 and 30, a negative resistance R;; shown by a resistor 46 is developed with an efiectively large value in series with the inductor 42 and resistor 44. As will be explained subsequently, this negative resistance resulting from avalanche multiplication characteristics of the transistor effectively cancels the resistance R Thus, the Q factor of the impedance developed between the terminals 12 and 20 is relatively large.

Referring to the equivalent circuit diagram of FIG. 3 for further explaining the inductive characteristics of the transistor device 10, the input impedance Z as a first approximation neglecting collector capacitance may be expressed as:

e e+ b[ where r is the emitter resistance, r is the intrinsic-base resistance r of FIG. 3 as well as external resistance of the resistor 14 of FIG. 1 and a is the current amplification factor of the transistor 10. The collector resistance r is shown in parallel with a current generator providing a current of al The current amplification factor a may be expressed as:

where f is the operating frequency of the transistor, f is the base diffusion cutoff frequency which for a diffusion transistor may be expressed as:

22D fb Tv T where D is the diffusion coefficient and has a value of approximately 100 cm. /sec. For a germanium p-n-p type transistor, W is the effective base width (FIG. 10) and a is the grounded base current amplification factor at very low frequency.

One requirement of the transistor of the invention is that the base width W of Equation 3 be sufficiently large to develop the required phase shift of the signal applied thereacross. Thus, the base cutoff frequency f is suffieiently small relative to the operating frequency 3 so that or has a complex characteristic to develop a large inductive reactance. It is to be noted that the base width W is limited to a maximum value because recombination of minority carriers increases with an excessively wide base region.

From the simplified assumption, the input impedance Z may be expressed as:

where is the resistive or real part of the input impedance and .0; 'i'j b'-% 1+ ft) is the inductive reactance or imaginary part of the input impedance. It is to be noted at this time that the base resistance r must have a large value in order to develop a large inductive reactance. Thus, the input impedance Z includes the resistance or real component R and the inductance component L of FIG. 2 at a selected frequency Another requirement of the transistor device in accordance with this invention is that the a factor be substantially equal to unity to develop a relatively large inductive reactance. Also, as shown in Equation 4 a large or increases the term 4 so that the resistance component R (FIG. 2) of the input impedance Z is a minimum. Also, to minimize the resistance R the base resistance r must have a minimum value.

where:

K is Boltzmans constant,

q is the charge in coulombs of an electron, T is temperature in degrees Kelvin, and I is the emitter current of FIG. 2.

Thus, to provide a relatively small emitter resistance r the emitter current I of FIG. 2 is selected to be relatively large.

The Q of the inductive transistor using the first approximation for Z may be expressed as:

ft. 2 m G.)

Thus, a large value of the resistance r and a low value of 0: limits the value of Q in Equation 5. It is believed that when the transistor 10 in accordance with the invention is operating in the normal region, the 01 may develop a negative resistance component which increases the Q factor a small amount.

A more detailed solution for the input impedance Z by using the correct frequency dependence of a is:

where m is the excessive phase shift of a diffusion transistor at the cutoff frequency and corresponds to 0.21 in radians. The input impedance will now be:

fo where 1 f0 27l'7 C Thus, it can be seen that the collector cutoff frequency f must be relatively large. This requirement provides an upper limit to the value of the base resistance of the transistor in accordance with the invention. Also, it is desirable to have a low value of collector capacitance C A curve 47 of FIG. 4 shows the limits of the base resistance r of the transistor of the invention. In a linear region 48 the inductive reactance X increases substantially linearly with increasing base resistance r However, above the linear region 48, the inductive reactance X increases at a slow rate with increasing r and even decreases at high values of 1' because of the effect of the collector cutoff frequency f of Equation 7. A curve 49 shows the linear increase of resistance with increasing r Thus, r is selected to be relatively large but in the linear region 48 to provide a relatively large inductance with a desirable high Q.

A curve 50 of FIG. 5, which has the configuration of.

a semicircle, shows the inductive reactance X and resistance R as a function of operating frequency f of the transistor as determined by Equation 4. The curve 50 has a radius equal to /za r and has a center point 52 on the real axis at a point where the value of R is equal to r +r /za r It is also to be noted that the distance where the circle 50 crosses the real axis to the right of graph is at a resistance value of r +r Thus, the transistor in accordance with this invention has an inductive reactance varying with applied frequency 1 along a curve 50 which has a location independent of frequency and defined by r r and 04 Therefore, it can be seen that the relatively large ca and r increases the radius of the curve 50 and the value of inductive reactance X However, the curve 50 because of the relatively high resistance from the r and r has a relatively low Q characteristic.

To further consider the operating regions of the transistor having the characteristics of the curve 50 of FIG. 5, a curve 56 of FIG. 6 shows the variation of inductive reactance X and resistance R (R of FIG. 2) with an increasing ratio f/f A generally useful region of the curve 56 is in the region where f/f =0.05 to 0.3 as R is relatively low and X and R are substantially constant with frequency variations. Regions with f/f 0.3 which have a relatively high Q maybe utilized for special applications but have a high degree of dependence of X and R with operating frequency. Operating at a point 58 where f/f is equal to 1 at the peak of curve 56 provides a relatively high X with a substantial independence from minor variations of the operating frequency 1 but with a relatively low Q factor. The region where f/f is greater than 1 provides a very high resistance R and a very low Q factor. Thus, the desirable operating region for the transistor in accordance with the invention having the characteristics of the curve 56 is when f/f is selected between 0.1 and approximately 0.3.

of the Equation 4 varying to a peak value when f/f is equal to 1. The larger the selected value of r within the limits of the collector cutofi frequency f the larger is the inductive reactance X developed by the transistor. The inductance L shown by a curve 61 hasa maximum value at a selected value of r when the ratio f/f is between 0.1 and approximately 0.3. Thus, the transistor having the properties described above develops a maximum inductance with a minimum resistance component when the ratio f/f is in the range of 0.1 to 0.3.

Now that the transistor device of the invention has been explained for developing a large inductance value, a further arrangement in accordance with this invention developing a large inductance but with a very high Q .factor will be explained. The properties of the high Q transistor include those described for the transistor above, that is, a selected base width W to provide the required f/f ratio, a small emitter resistance r a close to unity .and a base resistance r selected to provide a maximum inductance. The emitter resistance r may only be decreased to a limit because a very large emitter current I .being developed in the transistor described above.

In order to increase the Q in the transistor in accordance with the invention, the d of Equation .5 is

effectively increased by providing an avalanche multiplication factor so as to develop a negative resistance R of FIG. 2 to effectively cancel the resistance R As shown in FIGS. 8 and 9 the transistor 10 of FIG. 1 has a negative resistance region shown with a collector voltage V to the right or more negative than approximately 20 volts. It is to be noted that for developing the high inductance but low Q characteristic the transistor described above is biased with a collector voltage to the left or less negative than -10 volts. For satisfactory operation of the high Q transistor, the emitter is biased relative to the base so that only a moderate amount of avalanche multiplication is developed. As a result, the transistor develops a minimum amount of flicker noise, that is, noise resulting from imperfect avalanche breakdown in the base region. The transistor is thus maintained in a negative resistance region below a collector voltage of approximately 41 volts in the example of FIG. 8 by selecting the potential V of the battery 30 of FIG. 1. The input impedance Z developed when the transistor 10 is biased in the avalanche multiplication region may be expressed as:

OZQT M .a T M b Z.=rs+rb +,7f (9) where M is the avalanche multiplication factor having a value greater than one.

7 The effect of M is to cause the negative resistance term fb +f to have a sufficiently large value to effectively cancel r and r For example, r may be as small as 5 ohms as a result of a relatively large I as shown in FIG. 1, r may be 500 ohms to provide a required large inductance. Thus, a negative resistance term up to 505 ohms is necessary to compensate for the damping resistance. The effective resistance between terminals 12 and 20 is then zero and a theoretically infinite Q is developed. It is to be noted that the negative resistance term may have a larger value than r +r and still be stable at a selected frequency because of additional resistance from circuits coupled to the terminals 1- 2 and 20. At the same time that a high Q is developed, the multiplication factor M increases the value of the inductance term of Equation 9.

The curve 50 of FIG. 5 shows the inductance and resistance characteristics of the transistor in accordance with the invention without the multiplication factor M decreasing the effective resistance, that is, when M is equal to l. A semicircular curve 62 shows the inductive reactance and resistance variation with frequency for a value of M greater than 1. The curve 62 has a center point 66 at a distance on the resistance R axis equal to (r +r /2a M r and has a radius equal to 0 1 1) Thus, the factor M both decreases the distance of the center point of the characteristic curve such as 62 along the resistance axis and increases the radius of the semicircular curve.

The curve 62 crosses the X axis into a negative resistance -R or unstable region. The operating region at which the highest Q factor is developed is in a region indicated by an arrow 68 between zero resistance and a small positive resistance R. In order to obtain the high Q of the region indicated by the arrow 68, the operating frequency 1 applied to the terminals 12 and 20 of FIG. 1 is selected thereat. It is to be noted that the distance that the curve 62 extends into the R region determines the value of the multiplication factor M. It has been found that when the curve 62 falls in the region indicated by the arrow 68 with the ratio f/f from between 0.1 to 0.3, stable operation is obtained.

A semicircular curve 70 shows the characteristics of the inductive transistor when the collector voltage V is biased more negative as shown in FIG. 8 so that a larger multiplication factor M is obtained. The curve 70 has a center point 74 at a distance along the resistance axis equal to (r +e /za M r and a radius equal to o z b) Thus, by increasing the avalanche multiplication factor M, the center point of the characteristic semicircular curve such as 70 is moved closer to the X axis and the radius of the semicircular curve is increased. The result is a larger value of X in the high Q region indicated by the arrow 68. Also varying the value of M allows selection of a desired frequency f in the high Q region. It is to be again noted that it is not desirable that the value of M be increased so that a net negative resistance is developed as shown by Equation 9 or an unstable operating condition may be present.

To further consider the properties of the high Q transistor in accordance with this invention, a low resistivity material for the base region, but also providing a negligible combination rate of minority carriers in the base region, is preferable to minimize the reduction of the effective base width W by the depletion region. As discussed above, the effective base region W must be relatively large so that the base cutoff frequency f is relatively small. The grounded base amplification factor a must be large, that is, close to unity. Preferably, the 0: must be greater than 0.99. The emitter resistance r must be selected low which results from a high emitter current 1 The base resistance r must be relatively large to develop a large inductance but below the limit established by the collector cutoff frequency. The transistor must have avalanche multiplication characteristics and an M large enough so that a M is greater than 1.

Although the transistor has been discussed relative to a diffusion type transistor, the principles of the invention are equally applicable to drift type transistors. Another desirable characteristic of the high Q transistor is that the avalanche breakdown be with a minimum amount of noise and that the transistor develop a high multiplication factor M at low values of V,,. The multiplication factor M may be expressed as:

where V is the voltage applied to the base of the transistor 10 of FIG. 1 and n is a characteristic of the transistor and is selected as relatively low. As discussed above, the transistor must be maintained below the avalanche breakdown potential so that a minimum amount of noise is developed. Also, to minimize power dissipation, the collector voltage V and the emitter I must not be excessively large.

The transistor in accordance with the invention has a minimum temperature sensitivity because of the high base resistance r The parameters that are temperature sensitive are the base cutoff frequency f because of the diffusion constant D, the emitter resistance r which is directly dependent on temperature, and the base resistance r which is a function of p where p is the resistivity and has a temperature variation.

Referring now to FIG. 9 the values of Q and X may be selected by varying the parameters of the transistor in accordance with this invention. A curve 71 shows the Q factor developed when the transistor 10 of FIG. 1 has an I of milliamperes and a base resistance r of 570 ohms so that a relatively large inductance X is developed. Thus, when the transistor is biased with a collector voltage between 20 and 32 volts, a large Q and a large inductance is developed. A curve 72 shows the decrease of the Q factor when the transistor has a base resistance r equal to zero. It is to be noted that with the small r of the curve 72, the inductance developed between the terminals 12 and 20 is relatively small. A curve 73 shows that by reducing the emitter current I so that the emitter resistance r increases, the Q factor is decreased and the collector of the transistor 10 must be biased with a more negative V to increase the value of M. When both the emitter current I and the base resistance r are decreased to respectively increase r. and decrease the inductance, a curve 75 shows the decrease of the Q factor. Also, the curve 75 shows that with a relatively large value of r and small value of r the transistor 10 must be biased close to the noise region of FIG. 6. A small value of r decreases the negative term of Equation 9.

As an example of the principles of the invention, the transistor may have a C of 100 pico-farads, an r of 300 ohms, a selected operating frequency f of 200 kc., and a base cutoff frequency f of 1 mc. resulting from a base width of 2 mils. Thus, the ratio of f/ f is 0.2 and f is approximately 5 me. so that the effect of the collector cutoff frequency does not substantially lower the value of the inductive reactance X The multiplication factor is selected to have a value consistent with the discussion relevant to FIG. 5.

\A specific transistor structure having the characteristics of the invention is shown in FIG. 10 with a base region 78 which may be an elongated block of an n type semiconductor material such as germanium. Alloyed into a first side of the base region 78 is a collector 80 which may be of a 17 type material such as a gallium impurity. The collector 80 is positioned at one end of the base 78. On the other side of the base 78 from the collector 80, an emitter 82 of a p type material is alloyed into the base '78. The emitter 82 may be formed from indium containing a small percentage of gallium, for example. Connected to the collector 80 and emitter 82 such as by thermal compression bonding, are respective terminal leads 84 and 86.

Alloyed to the end of the base 78 opposite from the emitter and collector junction is a base ohmic contact 88 having a terminal lead 89 attached thereto such as by thermal compression bonding. The base region 78 has an elongated rectangular shape so that the distance between the emitter 82 and the base ohmic contact 88 is relatively long. It is also to be noted that the area of the base region 78 between the emitter 82 and the base ohmic contact 88 may be reduced to increase the base resistance r Thus, the selected base resistance r of the transistor is developed in the semi-conductor structure of the transistor as m. Other properties as discussed above of the transistor of FIG. 1 are designed into the structure so that the high Q and high inductance are present. The effective :base width W is shown relatively large. The Width W of the depletion region may be relatively small by utilizing a low resistivity material for the base region 78.

Another structure in accordance with the invention shown in FIG. 11 includes a semi-conductor block having a base region 90 which may be of an n type material and which has

slots

91, 92 and 93 formed therein so as to provide a long distance from an emitter 94 to a base ohmic contact 95. The emitter 94 of a p type material may be alloyed into the block 90 by conventional techniques. A collector 96 which may be of p type semiconductor material may be alloyed into the block 90 on the side opposite to the emitter 94. Suitable emitter base and collector leads may be provided.

Now that the inductive element in accordance with this invention has been described, a circuit arrangement will be described utilizing an impedance multiplying emitter follower transistor 94 (FIG. 12) combined with an inductive transistor device 96 to develop very large inductive values. The inductive transistor 96 which may be of the p-n-p type has a large base resistance r a wide base region, a low emitter resistance r and a relatively high f/f as discussed above. Also for developing with a high Q factor, the transistor 96 has avalanche characteristics, as discussed above. A first terminal 100 is coupled to the base of the transistor 94. For biasing the transistor 94, a source ot potential such as a battery 104 has a negative terminal coupled to ground and a positive terminal coupled through a lead 106 to the collector of the transistor 94. 1A resistor M is coupled between the lead 108 and the base of the transistor 94 to provide a biasing source so the transistor 94 is maintained in the amplification region. A capacitor 112 coupled between the lead 108 and ground provides a short circuit for AC. components.

The emitter of the transistor 94 is coupled to the emitter of the transistor 96 which in turn has a base coupled through a resistor 114 to a second terminal v116. The terminal 1116 may be coupled to ground. it is to be noted that in accordance with the principles of this invention, the resistor 1&14 may be incorporated in the semiconductor material of the transistor device 96. A source of potential such as a battery 118 has a positive terminal coupled to ground and a negative terminal coupled through a limiting resistor 1 19 .to the collector of the transistor '96 tor providing a negative potential 'V thereto relative to the grounded base so that the transistor 96 operates in the avalanche region. A capacitor 120 is coupled to the collector of the transistor 96 to provide an AC. byapass to ground.

The emitter follower transistor 94 which operates in the cutofi region is selected with a large f so as to operate in the normal mode. The impedance Z developed across the terminals 100 and M6 may be expressed as:

and

T OL M 21rfL is The input impedance Z may also be expressed as:

where ,8 is the grounded emitter amplification factor which is equal to Thus, the circuit of FIG. provides an inductance that is amplified by the factor [3 and with a large Q factor. It has been found that the circuit of FIG. 12 may develop inductance values greater than henry.

A semiconductor device 124 of FIG. 13 provides a single semiconductor element that includes the

transistors

94 and 96. The collector, base and emitter of the transistor 94 is formed from respective n-p-n regions 126, 128 and 130 and the emitter, base and collector regions of the transistor 96 are formed from respective p-mp regions 134, 166 and 138. An ohmic contact 140 is alloyed between the regions 130 and 134- so that a compact and simple semiconductor element is formed. The regions 1*34, 136 and 138 have the properties described above to develop the high Q inductive characteristics. Suitable terminal electrodes are bonded to the regions 1 26, 128, 1136 and 138 to complete the circuit of FIG. 12. It is to be noted that the required base resistance n, is constructed into the base region 166 in accordance with the principles of the invention so that the resistance 114 of FIG. 12 is not required.

It is to be noted that although the transistor device has been described as a p-n-p type, the principles of the invention are equally applicable to n-p-n type transistor devices. Also, opposite type transitsors from those shown may be utilized in the circuit of FIG. 12 within the principles of the invention. I

Thus, there has been described an inductive transistor device that provides a two terminal inductive element.

The transistor for developing an inductive reactance has a large base resistance r to provide a sufficiently large inductance, a wide base region, a relatively low emitter resistance r and a high f/f ratio. For also developing a large Q factor the transistor has avalanche characteristics and is biased to operate in that region so that the negative resistance e'lfectively cancels the series resistance. Specific structures in accordance with the invention have a relatively long distance and small area in the base region between the emitter and the base ohmic contact so that the desired base resistance r is provided. In another form of the invention, an impedance multiplying emitter follower is combined with the inductive transistor so that the inductive reactance is multiplied by the ,8 of the emitter follower transistor.

What is claimed is:

l. A circuit for providing a high Q inductive reactance between first and second terminals comprising: a transistor having an emitter electrode, a base electrode, and a collector electrode; the emitter electrode being coupled to said first terminal and the base electrode being coupled to said second terminal with the overall resistance in the base circuit being relatively large; means for providing essentially a short circuit for alternating current between said collector electrode and said second terminal; means for biasing said collector electrode to a potential producing avalanche multiplication such that the resultant negative resistance in the emitter-base circuit is substantially equal in magnitude to the positive resistance in said emitter-base circuit measured between said first and second terminals; and power supply means having a series resistance much grater than said positive resistance coupled between said first and second terminals.

2. A circuit for providing a high Q inductive reactance between first and second terminals comprising: a transis tor having an emitter electrode, a base electrode, and a collector electrode; the emitter electrode being coupled to said first terminal and the base electrode being coupled to said second terminal with the overall resistance in the base circuit being relatively large; a capacitor coupled between said collector electrode and said second terminal; means for biasing said collector electrode to a potential sufiicient to operate said transistor with an avalanche multiplication factor greater than one but insufiicient to produce in its emitter-base circuit a negative resistance of a magnitude which exceeds that of the positive resistance between said first and second terminals; and means for supplying an essentially constant current to the emitter of said transistor.

3. A circuit according to claim 2 wherein said transistor comprises a block of semiconductive material having first and second oppositely disposed broad faces, said block defining a plurality of interleaved slots extending between said broad faces to provide a substantially serpentine path of semiconductive material, an emitter region alloyed to said first broad face of said block near one end of said path, a collector region alloyed to said second broad face of said block near said one end of said path, and an ohmic base contact alloyed to said block near the other end of said path.

4. A circuit for providing a high Q inductive reactance between first and second terminals comprising: first and second transistors of complementary conductivity types, each having an emitter electrode, a base electrode, and a collector electrode; the emitter electrodes being connected together; the base electrode of said first transistor being coupled to said first terminal; the base electrode of said second transistor being coupled to said second terminal, with the overall resistance in the base circuit of said second transistor being substantially greater than that in the base circuit of said first transistor; means for biasing said first transistor to operate it in its amplification mode; means for providing an alternating current path of low impedance between said second terminal and each of said collector electrodes; and means for biasing the collector electrode of said second transistor to a potential producing avalanche multiplication in said second transistor such that the resultant negative resistance in its emitter-base circuit is substantially equal in magnitude to the positive resistance measured between said first and second terminals.

References Cited by the Examiner UNITED STATES PATENTS 2,870,421 1/59 Goodrich 333-80 2,886,748 5/59 Barton 317-235 2,904,758 9/59 De Miranda 333-80 2,913,541 11/59 Suran 333-80 2,930,950 3 /60 Teszner 317-235 E. 2 2,930,996 3/60 Chow 333- 2,941,131 6/60 Williams 317-235 2,965,820 12/60 Barton 317-235 2,979,428 4/61 Jenny et a1. 317-235 3,018,392 1/62 Jones et a1. 317-235 3,023,347 2/62 Strull 317-235 3,042,884 7/62 Ladany 307-885 OTHER REFERENCES Transistors, Principles, Design and Applications, Gartner, D. Van Nostrand Co., Inc., 1960, pages 305-310 relied upon.

Transistor Technology, volume I, Bridgers, Scafi, and Shive, D. Van Nostrand Co., Inc., 1958, pages 216-217 relied upon.

Macario: Avalanche Transistors Electronic Engineering, May 1959, pages 262-267 relied upon.

Schenkel: Nat. Electronics Cont. vol. X, February 8, 1955, TK 7801 No. 3, pages 614-625.

HERMAN KARL SAALBACH, Primary Examiner.

RUDOLPH V. ROLINEC, Examiner.

Claims

1. A CIRCUIT FOR PROVIDING A HIGH Q INDUCTIVE REACTANCE BETWEEN FIRST AND SECOND TERMINALS COMPRISING: A TRANSISTOR HAVING AN EMITTER ELECTRODE, A BASE ELECTRODE, AND A COLLECTOR ELECTRODE; THE EMITTER ELECTRODE BEING COUPLED TO SAID FIRST TERMINAL AND THE BASE ELECTRODE BEING COUPLED TO SAID SECOND TERMINAL WITH THE OVERALL RESISTANCE IN THE BASE CIRCUIT BEING RELATIVELY LARGE; MEANS FOR PROVIDING ESSENTIALLY A SHORT CIRCUIT FOR ALTERNATING CURRENT BETWEEN SAID COLLECTOR ELECTRODE AND SAID SECOND TERMINAL; MEANS FOR BIASING SAID COLLECTOR ELECTRODE TO A POTENTIAL PRODUCING AVALANCHE MULTIPLICATION SUCH THAT THE RESULTANT NEGATIVE RESISTANCE IN THE EMITTER-BASE CIRCUIT IN SUBSTANTIALY EQUAL IN MAGNITUDE TO THE POSITIVE RESISTANCE IN SAID EMITER-BASE CIRCUIT MEASURED BETWEEN SAID FIRST AND SECOND TERMINALS; AND POWER SUPPLY MEANS HAVING A SERIES RESISTANCE MUCH GRATER THAN SAID POSITIVE RESISTANCE COUPLED BETWEEN SAID FIRSTG AND SECOND TERMINALS.