US3045194A - Active multiport networks - Google Patents

Description

July 17, 1962 l. w. SANDBERG 3,045,194

ACTIVE MULTIPORT NETWORKS Filed Nov. 2, 1960 4 Sheets-Sheet 1 FIG.

INVENTOR m SA/VOBERG ATTORNEY 1. w. SANDBERG 3,045,194

ACTIVE MULTIPORT NETWORKS July 17, 1962 Filed NOV. 2. 1960 4 Sheets-Sheet 2 CURRENT-TO-VOLTAGE VOLTAGE-TO-CURRENT FIG. 2C FIG. 20

CURRENT-TO-CURRENT o VOLTAGE-TO- VOLTAGE F I? a FIG. 3

FIG. 4B

'0 FIG. 4,4 0 M Q RI RI m 6/ H /C/ R0 C I c, c, c,,

INVENTOR W SANDBERG ATTORNEY July 17, 1962 l. w. SANDBERG ACTIVE MULTIPORT NETWORKS 4 Sheets-Sheet 3 Filed NOV- 2, 1960 FIG. 5

m Ne N R u \AM J- w 5 n U N I M INVENTOR m SANDBERG ATTORNEY Unite This invention relates to wave transmission networks and, more particularly, to active n-port networks without inductors in which all of the driving point and transfer parameters may be preselected without restriction.

In many signal transmission networks, it is often desirable to obtain certain driving-point and transmission parameters without the use of inductors,.particularly at low frequencies. This arises from the fact that inductors at these frequencies are generally large, cumbersome, expensive, and are usually far from ideal components. Resistors and capacitors, on the other hand, are small, inexpensive,.and much more nearly ideal components. A large amount of work has therefore been done in synthesizing networks having desirable parameters but having no inductors. I. G. Linvill, for example, in an article entitled RC Active Filters, Proceedings of the Institute of Radio Engineers, volume 42, page 555, March 1954, suggests a technique for realizing one arbitrarily chosen parameter of the four parameters of an inductorless twoport active network. Similarly, in the copending application of I. M. Sipress, Serial No. 46,285, filed July 29,

. 1960, since matured into U.S. Patent 2,998,580, issued August 29, 1961, there is'disclosed a structure for realizing any of certain specific groups of n of the n shortcircuit admittance parameters of an n-port network. The difficulties with such synthesizing techniques are, of course, the inability to realize an arbitrary group of 11 parameters and, even more important,'the inabilityrto control the remaining n n parameters.

The object of the present invention is to synthesize n-port transmission networks for which all of the parameters may be arbitrarily chosen, and which includes no inductors.

In accordance with the present invention, a generalized multi-port transmission network is obtained, including only resistors, capacitors, and amplifiers, in which all of the parameters may be preselected without restriction. The network comprises at least n amplifiers and a 3n-port network, including only resistors and capacitors, interconnecting the n external ports to the 11 inputs of the amplifiers and the n outputs of the amplifiers. In the simplest case, this 3n-port network includes two-port networks, each including only resistors and capacitors, by means of which each of the n ports is connected to each amplifier input and each of the n ports is also connected to each amplifier output. The parameters of the individual resistance-capacitance networks are chosen according to the method to be described below so as to realize any arbitrarily chosen overall network parameters.

The advantage of the present invention over previous ly known circuit synthesis techniques isthe ability to generate arbitrarily all of the parameters of an n-port network without restriction and without the use of inductors.

In the drawings:

FIG. 1 is a schematic block diagram of an n-port network in accordance with the present invention including only resistors, capacitors and amplifiers;

FIGS. 2A, 2B, 2C and 2D are circuit diagrams of four different types of amplifiers suitable for use in the network of FIG. 1; 1

FIG. 3 is a generalized block diagram of a two-port lattice type network suitable for all of the two-port networks of FIG. 1;

ttes, Patent sistors and capacitors.

10 includes (2n -l-n) two-port networks each of which: These individual 3,045,194- Patented July 17, 1962 generalized two-terminal resistance-capacitance networks suitable for realizing each of the impedances of FIG. 3;

FIG. 5 is a schematic block diagram of one possible modification of the network of FIG. 1; and

FIG. 6 is a circuit diagram of one possible two-port network constructed in accordance with the present invention.

Referring more particularly to FIG. 1, there is shown a schematic block diagram of a generic n-port network in accordance with the present invention in which the parameters as seen from each of the n ports or sets of terminals may be chosen arbitrarily. It will be noted that FIG. 1 is a line drawing which, for convenience, represents each pair of conductors in an actual circuit as a. The ports 11, 12, 13 therefore each single line.

represent a pair of terminals to which two-wire connections may be made. For simplicity, the term port will hereafter be used to denote such a pairof terminals.

The network of FIG. 1- comprises a subnetwork 10,

within the dashed rectangle, which includes only resistive and capacitive elements. Subnetwork 10 has 3n ports, n of which comprise the n ports of the overall network. Thus ports 11, 12, 13 in FIG. 1 comprise the ports of the overall network. Another n of the 3n ports of subnetwork 10 provides access to the input of n active circuit elements 14, 15, 16, and the remaining n ports provide access to the outputs of the n active circuit elements 14, 15, 16. Active elements 14, 15,

16 may be characterized as controlled sources and, more specifically, amplifiers. Amplifiers 14, 15, 16 may take the form of any one of four different types which can be termed current-to-voltage amplifiers, voltage-tocurrent amplifiers, current-to-current amplifiers and voltage-to-voltage amplifiers. These various types of amplifiers will be discussed more fully below in connection with FIGS. 2A, 2B, 2C and 2D.

Referring again to FIG. 1, it can be seen that, in accordance with the present invention, an n-port network may be synthesized with arbitrarily chosen parameters and including no inductances by interconnecting'at least 11 active elements 14, 15, 16 and the n ports 11, 12, 13 with a subnetwork 10 including only re- In the simplest case, subnetwork includes only resistors and capacitors. two-port networks are connected as follows: A two-port network is connected between each of the 11 ports 11,

12,. 13 and the input of each of activeelements 14, 15, 16.

Thus two- port networks 17, 18, 19 connect port 11(P to the inputs of active elements- 14, 15, 16, respectively; two-port networks 20,

21, .22 connect port 12(P to the same respective active element inputs; and two- port networks 23, 24, 25 connect port 13(P to these same respective active element inputs.

Similarly, a two-port network is connected between each of the n ports 11, 12, 13 and the outputj of each of active elements '14, 15, 16. Thus two- port networks 26, 27, 28 connect port 11(P to the out-- puts of active elements 14, 15, 16, respectively; two- port networks 29, 30, '31 connect port 12(P to the same respective active element outputs; and two-' port networks 32, 33, 34 connect port '13(P to these same respective active element outputs.

Subnetwork 10 also includesn additional two-port networks 35, 36, 37 which also include only resistors and capacitors and which operate as individual feedback 1 networks for the active elements 14,15, 16,'respectively. In accordance with the present invention, a network of the form shown in FIG. 1 is realizable for synthesiz ing any possible combination of parameters at the :2 ports 11, 12, 13. Thus, for example, filter structures having different transfer functions for the opposite directions of transmission may be synthesized and, moreover, may be synthesized with any arbitrary input and output impedances. The present invention is therefore universally applicable for synthesizing network parameters without the use of inductors.

Referring then to FIG. 2, there are shown examples of the four possible active elements suitable for use in the network of FIG. 1. FIG. 2A, for example, shows one form of current-to-voltage amplifier which might be used in the block diagram of FIG. 1. The essential characteristics of this type of amplifier are a low input impedance (ideally Zero) and a low output impedance (also ideally zero). Such an amplifier may be characterized by a constant gain factor which represents the ratio of output voltage to input current. In the example in FIG. 2A, this constant is nearly equal to the total resistance value of resistors 40 and 41. Transistors 42 and 43 may be of the junction type and hence present a low emitterto-base input impedance over a useful portion of their operating ranges. Resistors 49 and 41, of course, are of low values in order to present a low output impedance.

FIG. 2B illustrates one form of voltage-to-current amplifier which might be used in the block diagram of FIG. 1. The essential characteristics of this type of amplifier are a high input impedance (ideally infinite) and a high output impedance (also ideally infinite). Tubes 44 and 45 are of the pentode type and hence have these properties. Again, this amplifier can be characterized by a constant gain factor relating the output current and input voltage.

FIGS. 2C and 2D each illustrate one form of a current-to-current amplifier and voltage-to-voltage amplifier, respectively, which might be used in FIG. 1. Each can be characterized by a constant gain factor. The current amplifier of FIG. 2C has low input and a high output impedance and the voltage amplifier of FIG. 2D has high input and a low output impedance.

It is to be understood that the electrodes of each of the amplifiers of FIGS. 2A through 2D must be energized from some source, omitted in the drawings for simplicity. These sources must, of course, be arranged so as not to destroy the necessary impedance levels noted above. The amplifiers shown are only illustrative and should not be taken as limiting inasmuch as many other amplifiers having the necessary properties will be obvious to those skilled in the art.

FIG. 3 is a generalized block diagram of a two-port (four terminal) network of the lattice type which is one form that is suitable for all of the two-port networks in subnetwork in FIG. 1. Proper choice of the individual impedances Z Z Z and Z provides an overall two-port network with all of the required properties. More specifically, each of the two-terminal networks Z Z Z and Z may have the form shown in FIGS. 4A or 4B.

In FIG. 4A there is shown a two-terminal resistivecapacitive (RC) network which, with proper choices of resistances and capacitances, will generate any impedance possible with only resistances and capacitances. The network of FIG. 4A is the so-called first Foster form and comprises a series resistance, a series capacitance and n parallel resistance-capacitance sections connected in series.

FIG. 4B illustrates another two-terminal resistancecapacitance network which will generate any possible RC impedance. This network is the so-called second Foster form and comprises a resistor and capacitor in parallel with n resistive-capacitive sections. The networks of FIGS. 4A and 4B are more fully discussed and analyzed in the text Synthesis of Passive Networks by E. A. Guillemin, Wiley and Sons, 1957, and will not be discussed furthcr here except to note that many other network forms could also be used for this purpose.

Returning to FIG. 1, it is possible to analyze this network mathematically most conveniently by means of matrix techniques. The 3n-port subnctwork 10 can be characterized in terms of its external behavior at the 31: ports, that is, in terms of the relationships between the 3n voltages and 311 currents at these ports. For this purpose, it is convenient to define an admittance matrix i such that where I and E are the column vectors of currents and voltages respectively, at the 3/2 ports of subnetwork 10. The matrix if is a 312 by 311 short-circuit admittance matrix relating I and E and having a total of 911 terms. Each of these terms may be written as a rational function of s, Where s is the complex frequency variable (s=jw where w is the radian frequency variable).

Each diagonal term in the 311 x 311 admittance matrix i is the short-circuit driving-point admittance at one of the 3n ports. Similarly, each off-diagonal term in the 3? matrix is the short-circuit transfer admittance between two of these 3n ports. More specifically, the term in the ith row and the jth column of the matrix Y is the shortcircuit transfer admittance between ports i and 1'. Hence the admittance matrix I? completely specifies subnetwork 10 and can be directly related to the individual two-port networks within subnetwork 10.

Thus, in FIG. 1, the first n of the 3n ports are labeled A A A and comprise the external ports 11, 12, 13; the second n of the 311 ports are labeled B B B and comprise the inputs to amplifiers 14, 15, 16 respectively; and the third n of the 311 ports are labeled C C C and comprise the outputs of amplifiers 14, 15, 16, respectively. Each of the two-port networks 17 through 37 is identified with two subscripts identifying the particular pair of the 311 ports between which it is connected. These two-port networks can therefore be directly identified with corresponding terms in the matrix I? and, indeed, can be designed to provide short-circuit transfer admittance expressed in the offdiagonal terms of Y.

It is, furthermore, convenient to partition the 9n items of the matrix Y into nine n by n submatrices as follows:

YAA YAB YAC YBA nn E es on 4 es i oo where each of the terms in the matrix is itself a matrix having 11 terms. Y for example, contains the n elements appearing in the first 11 columns and first n rows of Y and hence expresses all of the relations between the currents and voltages at ports A A A when all other ports are short-circuited. Similarly, Y also has n terms and expresses all of the transfer relations between the currents and voltages at ports A A A and B B B, when all other ports are short-circuited.

Returning to the overall network of FIG. 1, an admittance matrix Y representing the relationships of the currents and voltages at the n external ports 11, 12, 13, and hence the desired overall properties of the network of FIG. 1, may be expressed as follows:

Y=YAA+ xol RYBCTIRYBA where Y Y c, Y and Y are defined in Equation 2, U is the identity matrix of order n, and R is the diagonal matrix of current-to-voltage amplifier gain constants R R R corresponding to the n active elements 14, 15, 16.

It will be noted that the matrix Y is symmetrical and hence the submatrices Y Y and Y are uniquely the subm'atn'ces in Y:

. related to Y Y and Y appearing in Equation 3.

That is, once Y Y and Y are determined, Y Y and Y may be obtained merely by interchanging respective rows and columns. The submatrices Y and Y do not appear in Equation 3 and hence may be freely chosen to assist in the synthesis procedure. In accordance with the present invention, each of these submatrices will be chosen to (I) realize any desired Y, and (2) to render Y realizable with only resistors and capacitors.

An admittance matrix of the form of Y may be expressed in the following partial fraction form:

in the row in which the diagonal term appears. A general method for synthesizing resistance-capacitance networks that satisfy the dominant-diagonal condition is shown in detail in a paper by P. Slepian and L. Weinberg entitled Synthesis Applications of Paramount and Dominant Matrices appearing at pages 611630 in the Proceedings of the National .Electronics Conference, October 1958, and hence will not be discussed in detail here.

In order to synthesize Y with a'network including only resistances and capacitances, it is therefore sufficient to satisfy Equation 3 with submatrices Y Y Y and Y 'such that each of the diagonal terms in Y, when Y is expressed in the partial fraction form of Equation 4, satisfy the dominant-diagonal condition. It is assumed, of course, that Y, the desired and al bitrarily chosen admittance matrix for the overall network of FIG. 1, is expressed as a matrix of n real rational functions in s. This involves no loss of generality since, 'as is well known, the desired parameters can be expressed to as close an approximation as desired merely by increasing the degree of these polynomials.

Next it is necessary to factor Y so as to obtain a common denominator D, which is also a polynomial in s, such that where [N is an n X n matrix of polynomials in s.

The submatrix Y may also be expressed as an n x n matrix in ratios of polynomials in s such that Yip-zen 6) Where q is another common denominator polynomial in s having only distinct negative-real zeros and [x is an n x n matrix of polynomials in s.

With this nomenclature, Equation 3 may be rewritten The next step of the synthesis of Y is to define two n x n matrices of polynomials P and P such that 1 2 YACIZU RYBCTIR ea 7 Equation 9 will be satisfiedwith the following values for i zq where P and P are n x n matrices of polynomials in s as defined in Equation 8, q and D are polynomials in s as defined in Equations 5 and 6, respectively, a; and a are arbitrary real constants to be chosen as will be described below, and H is an arbitrary nonsingular n x n matrix of constants which also will be more fully discussed below.

In order to implement the synthesis technique implicit in Equations 8, 10, 11 and 12, it is first necessary to choose the submatrix Y such that- (1) Its coefficient matrices as defined inEquation 4 satisfy the dominant-diagonal condition with inequality,

that is, the diagonal elements are greater than the sums of the magnitudes of the off-diagonal terms in the corresponding rows. One simple way of assuring this result is to choose Y such that it has only diagonal terms (all each diagonal term in Y by a sufficiently large real positive constant.- It will be noted that the factors P and P of P can alwaysbe obtained if (1) the degree of each polynomial in [x is equal to the degree of q, and (2) the determinant of P has at least K distinct real zeros where K n Deg. q, n is the number of ports, and Deg. q is the degree of the polynomial q. Increasing the diagonal multiplier in Y has the effect of producing the proper zeros of the determinant of P for some finite value of the diagonal multiplier, and hence the above criterion can always be met.

If this procedure is followed, at each stage of an iterative decomposition n distinct real zeros of the determinant of P can be removed as a linear factor of the matrix polynomial P. The factor remaining is a matrix poly-- nomial with degree reduced by unity.

The parameters (x and 04 are then chosen sufficiently large to insure the satisfaction of the dominant-diagonal condition in the first 11 rows of the matrix Y as expressed in Equation 2. As can be seen-in Equations 2, 10and l1, increasing a and a reduces the Y and Y terms. They can be reduced until the diagonal terms in Y as chosen above satisfy the dominant-diagonal condition.

Since the matrices Y and Y are unrestricted by Equation 3 they may be chosen so that thedominant-diagonal condition is met in the last 2n rows of Y as expressed in Equation 2. I

It will be noted that the matrix Y, representing the overall network parameters for the network of FIG. 1, may be arbitrarily prescribed in all of its elements; Thus, in accordance with the present invention, it is possible to synthesize any conceivable network parameters. In addition, various other properties may be obtained by properly choosing the matrix H.

The structure of FIG. 1 is the simplest of .the many possible structures and hence has been considered first.

case Equations lO, ll and 12 reduce'to By choosing H in other ways, however, it is possible to realize other network advantages. In FIG. 5, for example, there is shown one modification of the network shown in FIG. 1 in which similar elements have like reference numerals. Subnetwork is shown in FIG. 5 in block form, it being understood that this subnetwork is identical to that shown in FIG. 1. In addition, 11 two- port networks 50, 51, 52, 53 are connected such that the it active networks 14, 15, 16 are connected in a ring with one of networks 50, 51, 52, S3 joining the output of each of the amplifiers in the ring to the input of the next succeeding amplifier. Thus network 50 connects the output of amplifier 14 to the input of amplifier 15, network 51 connects the output of amplifier 15 to the input of the next succeeding amplifier, not shown, network 52 connects the output of the (n1)st amplifier, not shown, to the input of the nth or last amplifier 16, and network 53 connects the output of the last amplifier 16 to the input of the first amplifier 14 to complete the ring.

It is apparent from Equation 12 that the diagonal terms in Y can be expressed as and the non-zero off-diagonal terms required by FIG. 5 as in+1.an= n+1,an-

i zq A D iyn+1+i.2n+i= n+i+i.2n+i-( t 1,2, n1) (15) The non-zero elements of H are chosen so that H is nonsiugular, that is, so that its determinant is not zero. The elements in Y can be calculated by Equations 14 and 15 and Y from Equation 11.

It is apparent that there are many more degrees of freedom in choosing the elements of Y. For example, the ofi-diagonal terms of Y may be specified, Y and Y may be specified, H may be differently specified, and so forth. It is clear that other desirable properties may be realized with networks of the form of FIGS. 1 and 5 and still utilizes only resistive and capacitive elements in subnetwork 10. It is to be understood that the abovedescribed synthesis techniques are merely illustrative of these many other variations which also come within' the spirit and scope of the present invention.

The following steps are suificient for realizing a subnetwork 10 (FIG. 1) which will (1) exhibit an arbitrarily chosen short-circuit admittance matrix for the overall network, (2) require only n active elements, and (3) require in addition only resistors and capacitors for its realization. These steps are:

(1) Choose Y such that- (a) Its coeflicient matrices satisfy the dominantdiagonal condition with inequality, and (b) The matrix [qN Dx can be factored into two matrices P and P having degrees not exceeding the degree of q. (2) Let 1 YAC equal 1 (3) Let 1 YBA equal FZQRTIPZ (4) Choose Y to satisfy the relationship (5) Choose (1 and a sufiiciently large to satisfy the dominant-diagonal condition in the first n rows of co efiicient matrices of Y.

(6) Specify Y and Y such that the dominant-diagonal condition is satisfied in the last 211 rows of the coefficient matrices of Y.

(7) Construct the resistance-capacitance subnetwork specified by it.

It is to be noted that when the above procedure is followed, the last step can always be achieved.

It will be further noted that the synthesis technique has been described with reference to current-to-voltage amplifiers. This procedure was chosen only for convenience and it is apparent that any of the four types of amplifiers shown in FIGS. 2A through 2D would be suitable. With the voltage-to-voltage amplifier of FIG. 2D, for example, Equation 3 takes the form Similar equations could be written for either of the other two forms of amplifiers and the realization techniques are similar in all essential respects.

To further illustrate the synthesis procedure, a particular two-port network will be synthesized, utilizing the structure shown in FIG. 1. The resulting structure is shown in FIG. 6 and is achieved in the following manner.

For simplicity, it is assumed that the gain constants of the active elements 60 and 61 are each unity, that is, R R- zl. Let the desired overall properties at the two external ports 62 and 63 be represented by the following matrix:

1 1 s+3l:(s3)

This expression for Y has been chosen because of the simplification in the mathematics thereby obtaining. In an actual network, each of the terms could be a polynominal in s of any degree. It is to be noted, however, that Equation 17 specifies a network of a type not heretofore realized without the use of inductors and having the following interesting properties: (1) the transmission from port A2 (terminals 63) to port A1 (terminals 62) is completely independent of frequency; (2) the transmission from port A1 to port A2 provides no changes in amplitude with frequency but a change of phase with frequency; and (3) the driving-point impedances at each of ports A1 and A2 are inductive and resistive.

To perform the synthesis, it is first necessary to choose a Y which satisfies the dominant-diagonal condition and, furthermore, permits the factoring of P and P The following matrix satisfies these conditions:

It is now necessary to expand Equation 18 in a form similar to Equation 4 in order to obtain coefficient matrices. The required expansion is:

9. From Equations 20, 2.1 and 23 it can be seen that the dominant-diagonal condition will be met with the constants a and having the values 2.70 and 1.35, respec tively. Using these values, the matrix 3? can be expanded in the form s Y K.,+K, 24)

with the following coefl'icient matrices:

It will be noted that no entries have been made in the diagonal positions in Y and Y Any entries desired may be made here provided only that they satisfy the dominant diagonal condition. For this reason we may synthesize the network Y without regard to these diagonal elements. In this example, these items will not be specified in order to simplify the mathematical problem but it is to be understood that in the general case, it may be desirable to specify them in some particular manner to obtain some panticuilar network properties in addition 'to those specified in Equation 17.

The values of the elements of the various two-port networks in FIG. 6 are easily obtainable from Equations 25 and 26 as described in the afore-mentioned article by Slepian and Weinberg. They are given below, with conductance values in :mhos and capacitances "in farads.

1: is to be understood that the above-described arrangements are merely illustrative of the numerous and varied other arrangements which might comprise applications of the principles of the invention. Such other arrangements may readily be devised by those skilled in the ant without departing from the spirit and scope of this invention;

What is claimed is:

1. A wave transmissionnetwork having n ports and comprising atleast 21 active elements and a 3n-port passive network including only resistors and capacitors,

where n is greater than one, a first n of said 3n ports comprising the ports of said wave transmission network, means for connecting another n of said 3n ports to the individual inputs of said n active elements, and means for connecting the remaining n of said 3n ports to'the said two-port networks between corresponding ones of said other n ports and said remaining n ports of said 3npont network.

3. The wave transmission network according to claim 2. further including means connecting one of said twoport networks between each of said other n ports and the one of said remaining n ports preceding the correspending one of said remaining 71 ports.

4. A wave transmission network including 11 ports, at least n active circuit elements, and circuit means including at least 2n +n two-port networks interconnecting said It ports, the inputs of said active circuit elements, and the outputs of said active circuit elements, said two-port networks each including only. resistors and capacitors.

5. The wave transmission network according to claim 4 wherein said active circuit elements comprise signal am-' 6. The wave transmission network according to claim 5 wherein said n active circuit elements are connected in a ring in which a two-port network including only resistors and capacitors connects the output of each of said active circuit elements to the input of the next succeeding active circuit element in said ring.

7. A wave transmission network including 71 ports and at least it active circuit elements, a twoaport network including only resistors and capacitors connecting each of said n ports and the inputs of each of said active circuit elements, a two-port network including only resistors and capacitors connecting each of said n ports and the outputs of each of said active circuit elements, and a two-port network including only resistors and capacitors connecting the output of each of said active circuit elements to the input of the corresponding active circuit element.

' 8. An active wave transmission network comprising 71 external ports having n arbitrarily chosen parameters associated therewith, where n is greater than one, at least 71 signal amplifiers each having a substantially constant gain factor, and a 3n-port passive transducer including only resistors and capacitors interconnecting said n ex ternal ports, the inputs of said amplifiers, andthe outputs of said amplifiers, said 3n-port passive transducer being constructed to realize said 72 arbitrarily chosen parameter s at said n external ports.

9. The active wave transmission network according to claim 8 wherein said amplifiers comprise current-to-voltage amplifiers.

10. The active wave transmission network according to claim 8 wherein said amplifiers comprise voltage-tocurrent amplifiers.

11. The active wave transmission network according 7,

to claim 8 wherein said amplifiers comprise current-tocurrent amplifiers.

12. The active wave transmission network according to claim 8 wherein said amplifiers comprise voltage-tovoltage amplifiers.

13. In combination, a passive network having 3npairs of terminals and including only resistors and capacitors, where n is greater than one, means for connecting an amplifier between each of a first n of said 3n pairs of terminals and a corresponding pair of a second n of said 3n pairs of terminals, utilization means having n pairs of terminals, and means for connecting said utilization means to the remaining n of said 311 pairs of terminals.

14. The combination according to claim 13 wherein said passive network includes a plurality of four-terminal networks each including only resistors and capacitors, means for connecting one of said four-terminal networks between each of said first n of said 3n pairs of terminals and said remaining n of said 3n pairs of terminals, and means for connecting one of said four-terminal networks between each of said second n of said 311 pairs of terminals and said remaining n of said 311 pairs of terminals.

15. The combination according to claim 13 including it four-terminal networks each including only resistors and capacitors, and means for connecting one of said four-terminal networks around each of said amplifiers in a feedback connection.

16. The combination according to claim 13 including 211 four-terminal networks each including only resistors and capacitors, means for connecting each of a first n of said four-terminal networks between the output of each of said amplifiers and the input of the next succeeding one of said amplifiers to form a major feedback loop including all of said amplifiers, and means for connecting each of the remaining 21 of said four-terminal networks in a minor feedback loop around a different one of said amplifiers.

References Cited in the file of this patent UNITED STATES PATENTS 2,817,822 Meyers Dec. 24, 1957 w amp

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