US3017101A - Electronic digital computing machines - Google Patents

Description

Jan. 16, 1962 Filed March 23, 1954 ELECTRONIC C. E. OWEN DIGITAL COMPUTING MACHINES 17 Sheets-Sheet l Q/RMLAJ MMQ Jan. 16, 1962 c. E. OWEN ELECTRONIC DIGITAL COMPUTING MACHINES l7 Sheets-Sheet 2 Filed March 23, 1954 n9 J E.

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.r m@ @0 005mm ONO) M20 vm mm mm 5 mm mm mm Filed March 23, 1954 INVENTOR CHARLES E. OVENX United States Patent dfillldl Patented .ian. 16, 1962 ice Yorlr Filed Mar. 23, 1954, Ser. No. 418,129 Claims priority, application Great Britain Mar. 2 1953 6 Claims. (Ci. 235--l76) This invention relates to electronic digital computing machines and is more particularly concerned with machines operating in the serial mode with number and instruction words signalled as electric pulse trains. The invention is particularly, although by no means exclusively, adapted to machines utilising word-length and other registers employing magneto-striction delay lines of the kind described in the specification of copending U.S.A. patent application Serial No. 303,552, filed August 1952 by R. Millership, now Patent No. 2,790,160.

One object of the invention is to provide an improved arithmetical system for such machines and in accordance therewith the machine includes a circuit arrangement for effecting addition of two numbers represented by simultaneously presented pulse signal trains and is characterised by the provision of means whereby said adding circuit arrangement is capable of being modified in its operation by an applied control signal so as to effect subtraction, instead of addition, of the numbers represented by said applied pulse signal trains.

In order that the invention may be more readily understood one embodiment thereof will now be described with reference to the accompanying drawings in which:

FIGS. 1A, 1B and 1C form a composite block schematic diagram of the principal elements of an electronic computin machine embodying the present invention and show the signal and control interconnections between the various parts.

PlGS. 2A, 3A and 4A show in symbolic form three different types of standard unit from which the machine is largely built up while FIGS. 23, 3B, 3C, 4B, 4C are detailed circuit diagrams of different parts of such units.

FIG. 5A shows the symbol used for a mixer device and PEG. 5% the circuit thereof.

FIGS. 6A, 7A, 8A and 9A illustrate in symbolic form the units which make up a word length register within the machine while FIGS. 6B, 7B, 8B and 9B are detailed circuit diagrams of such units.

FiG. 10A shows the symbol and FIG. 1013 the circuit details of another part of the machine.

FIGS. 11A, 11B, 11C, 11D, 11E, 11F and 116 show in block schematic form the detailed arrangements of the different parts of the control unit of the machine.

FIG 12A, 12B, 12C, 12D and 12E show in similar block schematic form the arrangements of the difierent parts of the arithmetic unit of the machine.

HS. 13 shows the reading and writing circuits of the machine, while FIG. 14 shows a number of electric waveform diagrams.

The machine to be described operates in the serial mode and in the binary scale of notation with a digit signalling period of 3 micro-seconds and a beat period of 102 micro-seconds to accommodate a word length of 32 digits plus a 2-digit period gap between adjacent beat or word signalling times. As illustrated in FIG. 14, diagram (A), the first 32 digit periods 1, 2 32 of each beat constitute the active digit periods and the remaining two periods, 33 and 34, the aforesaid gap. Unless otherwise stated, the active or operational potential level of the various electric pulse and other control waveforms is positive-going (usually approximately +8 v.) relative to a resting level which is negative to earth (usually approximately -l0 v.) Thus a gate circuit, for example, will be opened or made conductive when each of its various operative inputs is positive-going and will be closed or made non-conductive when any one or more of such operative inputs is/ are at negative level.

Both numbers and instructions are signalled by similar 32-digit word pulse trains wherein the binary value 1 is indicated by a positive-going pulse in any required digit period and the binary value 0 by the absence of any such pulse from such period, the signal waveform then remaining at its negative resting level. In number word signals the various signalling digit periods 1, 2 32 represent progressively increased binary powers such as 2, 2 2 in the usual way but in instruction words the various digit periods have the significance indicated in FIG. 14, diagram (B) as follows:

Digits 1 l0 First address number (A1).

Digits l1l3 Control function (CF).

Digits 14-16 Transfer from accumulator (TFA). Digits 17-19 Accumulator function (AF). Digits 20-22 Transfer to accumulator (TIA). Digits 23-32 Second address number (A2).

Referring now to the block schematic diagram of FIGS. 1A, 1B and 1C, the machine includes a store S for holding both number and instruction words, a control system CL for receiving signals including instruction words from the store S and providing therefrom a series of appropriate timing and control waveforms, an arithmetic unit AU which includes a number of word storage registers, a computing circuit and other ancillary parts for dealing with number word signals supplied thereto and input and output devices ID, OD by which data may be fed into and withdrawn from the machine. The last-mentioned input and output devices ID, OD can follow any of the now well known types by which input data can be supplied from perforated tape through the intermediary of a tape reader and by which output data can be derived by the operation of an electric typewriter: As these parts are in no way concerned with the present invention they will not be further described.

The store S comprises a magnetic disc or drum recording device MD providing a plurality of separate tracks each having a plurality of separate word storage locations and a decodder circuit DCD for selecting any one of the available tracks for use either in reading out from or writing into the store. This circuit DCD has a signal output lead M1 for supplying word-representing pulse signal trains to unit DC of the control system CL and to unit AG of the arithmetic unit AU. It also has a signal input lead Hi2 by which word-representing signal pulse trains derived from units ACCl, R, D and X of the arithmetic unit AU may be recorded in said recording device MD. Further output leads 103, ill-l supply respectively a continuous timing signal and a series of address indicating signals each occurring immediately prior to the period of availability of each word storage location. These signals are supplied to unit PGA of the control system CL.

The control system CL comprises a pulse generator unit PGA which is described in greater detail later with reference to FIG. 11A. This unit is supplied with the aforesaid timing and address signals from the store S over leads 103, 104. The address signals are supplied therefrom, after suitable amplification and shaping, to a subsequent unit BC of the control system over lead and are also used to provide a series of digit timing pulse waveforms 31, i, 32, E, 33, Q, 34 51, 1, 2, 3, 4, 5, 6,

7, 8 and 9 whose forms will be described in greater detail later and which are made available throughout the machine by means of bus-bars which are shown grouped together in a common multiple conductor supply cable GL1. The timing signals are used to derive a continuous series of timing waveforms known as the Clock, Reset and Strobe waveforms which are also applied to all units of the machine.

The control system CL also includes a delay chain DC with which is associated an instruction register ISR for retaining an applied instruction word signal until it has been obeyed. These units are described in greater detail later with reference to FIG. 11B. The delay chain is supplied with output signals from the store S over lead 101 and also with output signals from unit X of the arithmetic unit AU over lead 1117 and therefrom serves to provide a'series of signal outputs, each at different relative'tirnings and referred to respectively as the P11, P12, P113, P114, P115, P116, P117, P118, P119, P120, P121, P122 and P123 waveforms. These P11 P123 waveforms are likewise made available to units STR, BC, TSM and RWD of the control system over separate bus-bars which are shown grouped together as a multiple conductor cable GL3.

The control system also includes a staticisor unit STR whose form will be described in greater detail later with reference to FIG. 11C. This unit comprises four separate groups of staticisors, each group having three separate staticisor circuits, for dealing respectively with each of the aforementioned three-digit groups CF, TFA, AF and TIA of an instruction word. These staticisor groups are supplied with selected ones of the different digit timing pulse waveforms in cable GL1 and with selected ones of the delayed signal outputs of cable GL3 as well as a plurality of other controlling waveform inputs from other elements of the machine, as described later, and serve to provide four separate groups of function control Waveforms whose character is dependent upon the configuration of the related CF, TFA, AF and TTA digits of the current instruction word supplied to the control system. These groups of function control waveforms comprise the CF group of the i, i, k, F, l, 1 waveforms, the TFA group of the g, 5, h, h, i, i waveforms, the AF group of the d, F, e, E, f, T waveforms and the TTA group of the a, E, b, F, c, E waveforms. All of these waveforms are similarly made available to units DC, OS and RWD of the control system CL and units AG, COS, ACCl, R, D and X of the arithmetic unit AU by way of bus-bars shown as a multiple conductor cable GL2.

The control system CL further includes a beat circuit BC which will be described in greater detail later with reference to FIG. 11D and which includes a coincidence testing circuit for comparing the address signal provided over lead 105 from the pulse generator unit PGA with the first address number signal A1 or the second address number signal A2 included in an instruction and supplied from the outputs P12 and P114 from the delay chain DC. Upon the existence of the required coincidence, the circuit provides further control waveforms defining the various operative beats of the machine rhythm and including the z, E, C, E, B and B waveforms. This beat circuit BC is supplied with a number of digit pulse timing waveforms from the cable GL1 and the fi waveform from unit COS of the arithmetic unit AU as well as the P12 and P114 signals from the cable GL3 and receives also a control signal over lead 1136 from a further unit known as the single shot circuit OS which provides, upon the operation of suitable manual control keys, for the operation of the machine to deal only with one single instruction instead of the usual continuous and automatic operating rhythm. This single shot circuit OS, which is described in greater detail later with reference to FIG. 11E, is supplied with certain of the digit pulse timing wave- 4 forms from the cable GL1, with certain function control waveforms from the cable GL2 and with the C and B waveforms from circuit BC as well as a further control potential over lead 1118 derived from the input or output units 1D, OD.

The control system CL also comprises a further group of three staticisors known as the track selection staticisors TSM and described in greater detail later with reference to FIG. 11F. This group of staticisors is concerned with the selection of the required recording track of the device MD and provides a further group of six track selection waveforms m, E, n, E, 0, 5 which are made available in the store S over the multiple conductor cable GL4. This unit TSM is supplied with certain of the digit pulse timing waveforms in cable GL1 and with the P11 and P123 signal waveforms in cable GL3 as well as the B and B waveforms from circuit BC.

The control system CL finally comprises a unit RWD described in greater detail later with reference to FIG. 11G and consisting of read/ write decode circuits for providing output control waveforms R, and E which are supplied to the decoder circuit DCD of the store S for determining whether signals are to be read out from or are to be written into the device MD. This read/write decode circuit RWD is supplied with certain of the digit pulse timing waveforms of cable GL1, with certain of the signal waveforms of cable GL3 and with the B and 56 control waveforms from circuit BC.

The arithmetic unit AU comprises an accumulator input gate unit AG described in detail later with reference to FIG. 12F and by which any required one of a number of alternative signal inputs may be routed to a common output lead 110. The signal inputs available are those on lead 111 from the input device ID, on lead 101 from the store S, on lead 1117 from a word register X of the arithmetic unit, on lead 169 from another word register D of the arithmetic unit or on one or the other of leads 113, 115 from a further word register R. This accumulator input gate unit AG is controlled by certain of the function control waveforms of the cable GL2.

The output on lead from the accumulator input gate unit AG is applied to a first word register ACCl with which is associated a computing circuit AS adapted to perform the functions of either addition or subtraction with, or the determination of non-equivalence between, a first number representing signal held in the register ACC1 and a further number representing signal applied thereto. This register also has associated therewith a first shift circuit $111 by which an output signal train may be derived in any one of three different relative timings known respectively as the AcO, A01 and A02 outputs. These elements will be described in detail later with reference to FIG. 12A. A further output, having a timing identical with that of the A01 output, is fed to the lead 1112 connected to the further Word registers R, D and X and the store S. The operation of this word register ACC1 is controlled by a selection of the function control waveforms of cable GL2, by certain of the digit pulse timing waveforms on cable GL1 and by a further control waveform z derived from the beat circuit BC of the control system CL. Directly associated with this word register ACCI is a second Word register ACC2 which can, effectively, be included as part of the first register ACC1 by way of interconnecting leads 1211, 121, 122 and 123.

The further word register R has associated therewith a second shift circuit SH2 by which an output word signal, at one or other of two different timings, can be provided over the output leads 113 and 115 leading to the accumulator gate unit AG. The signal input to this register is derived over lead 102 as already stated. The operation of this word register is controlled by a selection of the function control waveforms of the cable GL2, by

a number of the digit pulse timing waveforms in cable GL1 and by the z and a waveforms from beat circuit BC of the control system.

The further word registers D and X are generally similar to the register R except that they are not provided with a shift circuit; each has a signal input from lead 102 as already stated and serves to provide respectively outputs over leads 109 and 107 to the accumulator gate unit AG. The control of each of these D and X registers is derived from selected function control signals in cable GL2.

The arithmetic unit finally includes a conditional order selector COS by which the further operation of the machine along a chosen one of two alternative series of programme steps can be made conditional upon a test operation effected upon a partial answer number which has previously been obtained. This conditional order selector COS is supplied with the differently timed output signals A00, A02 from the word register ACCI and with selected digit pulse timing and function control waveforms from the cables GL1 and GL2. In addition, it is supplied with the B waveform from beat circuit BC of the control system CL and provides two further control waveforms, known as the TCB and waveforms, which are applied to the delay chain DC and the beat circuit BC respectively.

The machine is largely made up of a number of separate plug-in units of three types which are described in detail in U.S.A. patent specification Serial No. 394,442, now abandoned. These three units are shown respectively in FIGS. 2A, 3A and 4A and comprise, firstly a unit consisting of two delay circuits each having a delay time of one digit period (hereafter called a unit delay), shown in FIG. 2A; secondly a unit consisting of a unit delay fed with the mixed or combined outputs from two multiple input coincidence gate circuits (hereafter called a gate), and, separately, an inverter fed with the output from a gate, shown in FIG. 3A; and thirdly, a unit having three separate gates and at least one separate cathode follower stage, shown in FIG. 4A.

Before dealing in greater detail with the construction and manner of operation of the various units of the store 5, control system CL and arithmetic unit AU referred to above, a description will first be given of a preferred form of each of the symbols used in the more detailed drawing FIGS. 11A, 11B, 11C, 11D, 11E, 11F, 11G, 12A, 12B, 12C, 12D, 12E and 13.

UNIT DELAY DEVICE Referring particularly to FIG. 2A, the symbol which is shown twice within the chain-dotted rectangle will hereafter be used to indicate a unit delay. Such unit delay has a single signal input terminal 20 and two alternative signal output terminals 21, 22 both of which provide similar output signals.

FIG. 2B shows the detailed circuit arrangement of such unit delay. This circuit comprises a pentode valve V200 which has its anode coupled through capacitor C201 to the control grid of a second pentode valve V201 by way of a closed loop containing, in series, an inductance L200, a capacitor C200 and two germanium rectifiers X200 and X201. Valve V201 is arranged as a cathode follower. The signal input to the control grid of valve V200 is applied from input terminal 20 through resistor R200. Germanium rectifier X202 is connected between the control grid of valve V200 and a bus-bar (not shown) carrying the Clock pulse waveform which is shown in FIG. 14, diagram (C) and which is provided, as already stated, by the pulse generator unit PGA of the control system CL (FIG. 1B). Capacitor C200 and control grid of valve V201 are connected through a pair of germanium rectifiers X203 to a further bus-bar (not shown) carrying the Reset pulse waveform which is shown in FIG. 14, diagram (D) and which is also derived from said pulse generator unit PGA (FIG. 1B).

The control grid of valve V201 is also connected through resistor R202 to source of negative potential l50 v. while the control grid of valve V200 is likewise connected to the same source through resistor R201. The cathode of valve V201 is connected also to such source l50 v. through resistor R203 and is additionally connected direct to output terminal 21 and through blocking rectifier X205 to alternative output terminal 22. Rectifier X204 connected between the cathode of valve V201 and source of negative potential 10 v. acts as a clamp diode to prevent the cathode of that valve falling below 10 v. potential.

In the operation of this arrangement the arrival of a positive Clock pulse at the control grid of valve V200 during the time when a positive signal pulse is present through input terminal 20 produces a ring in the inductance L200. Whilst the valve is conducting a current builds up in the inductance but as the resulting voltage across the latter is negative-going, rectifiers X200, X201 prevent discharge of the capacitor C200. However, when the valve again ceases to conduct, at the end of the positive Clock pulse, the continuance of the current in the inductance makes the voltage across the latter positive-going so that this current then charges capacitor C200 through rectifiers X200, X201.

The potential at the control grid of valve V201, which is normally held down, accordingly rises to initiate a positive-going output pulse at its cathode. This output pulse persists until capacitor C200 is discharged at the end of the next following Clock pulse period by the appropriate Reset pulse, FIG. 14, diagram (D), applied through rectifiers X203. It will be appreciated that there was also a Reset pulse applied at the time just after the valve V2d0 ceased to conduct, i.e. when the current in the inductance L200 was about to charge the capacitor C200. However, this merely had the effect of deferring the initiation of the charging of the capacitor until after such first Reset pulse had terminaEd, the current in the inductance L200 flowing in the meantime through the rectifiers X200, X201, and X203.

The voltage waveform appearing at the output terminals 2t, 22 is shown in PEG. l4, diagram (F) relative to an input pulse train as shown in FIG. 14, diagram (E).

Referring now to FIG. 3A, that part of the unit shown in symbolic form therein lying at the left hand side comprises two coincidence gates G whose respective outputs are combined and applied to a unit delay D. FIG. 3B shows the circuit of such a combined double gate and delay unit. The first gate G is of conventional form constituted by rectifiers X300, X301 and X302 connected by one terminal respectively to input terminals 30, 31 and 32 and having their other terminals interconnected and joined by way of resistor R301 to the positive supply source v. and also by way of rectifier X306 to the control grid of valve V200. The other gate G is similarly constituted by rectifiers X303, X304 and X305 having one of their terminals connected respectively to input terminals 33, 34 and 35 and having their opposite terminals interconnected and joined by way of resistor R302 to the positive supply source +100 v. Such common connection is also joined by way of rectifier X307 to the control grid of valve V200.

The unit delay is constituted by valves V200 and V202 and associated parts in identical manner to that already described in connection with FIG. 2B. in view of the identity similar reference numerals have been given and the unit delay will not be further described.

In the operation of such device, a positive-going potential must be present on each of the input terminals 30, 31 and 32 simultaneously before any corresponding positivegoing potential is applied to the control grid of valve V200. Similarly a positive-potential must be present at each of the input terminals 33, 34 and 35 before any corresponding positive potential is applied to the control grid

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