US2926848A - Counting device - Google Patents
Counting device Download PDFInfo
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- US2926848A US2926848A US542625A US54262555A US2926848A US 2926848 A US2926848 A US 2926848A US 542625 A US542625 A US 542625A US 54262555 A US54262555 A US 54262555A US 2926848 A US2926848 A US 2926848A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/68—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using pulse rate multipliers or dividers pulse rate multipliers or dividers per se
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Description
March 1, 1960 B. M. GORDON COUNTING DEVICE Filed OCL. 25, 1955 N mm N 0 6. m M W Xu i W 0+ X0* XHn w Hin m# m M fnvxo* #0*Tm .vXonr D zoEwon. z Etam Q zoEmon. z. .tm 52.5
T l m m E wm@ wm SY wb Il.lo 52:00 QM. b\ 55 .65200 m S ww/ o bw/ y $32532 S QN mt/Sou MEE 225 www 53mm @w QW Q H A a A H s@ NU s rllk United States Patent 'e 2,926,848 coUNTING DEVICE Bernard" M. Gordon, Newton, Mass., assigner to Epseo,V l incorporated, Boston, Mass., a corporation of Massachusetts Application ctober 2S, 1955, Serial No. 542,625
11 Claims. (Cl. 23S- 164) The `invention relates to counting devices, and more particularly to counting devices for performing multiply- `in`g` and dividing operations.
Heret'ofore computers have used complex devices and circuits `for performing multiplying and dividing operations. Such devices have also required separate circuits forjperfor'ming either multiplying or dividing functions. Il'fhis of course has increased the complexities and number of circuits required thereby increasing the costs of manufacturing and reducing the `efficiency of operation and maintenance.
It is therefore a primary object of this invention to provide a new and improved counting device for performing multiplying operations. ".Another object ofthe invention is to provide a new andimproved counting device for performing dividing operations; Another object of the invention is to provide a new andimproved counting device selectively performing multiplying and dividing operations utilizing the same components.
Another object of the invention is to provide a new and improved counting device for multiplying and di* viding operations which is simple in construction, low in cost and eicient in operation. `-`vAnother *object of the invention is to provide a new and improved counting device which may be made entirely electrical in operation.
1Another object of the invention is to provide a new and improved counting device having high operating speed andeiciency.
Another object of the invention is to provide a new andimproved countingr device which may be switched from a "multiplying operation to a dividing operation atgreat speed.
`Another object of the invention is to provide a new and improved counting device which is highly adaptable to various design circumstances and requirements.
The above objects of the invention as well as other objects will be apparent when the following description is"`read in conjunction with the drawing annexed hereto showing the invention in block form.
The input terminal receives a train of actuating pulse signals which may occur at a frequency fo. The inputterminal 10 is connected to the rst input 12 of a `gate 114 which has a second input 16 and an output 13.
:When the second input 16 is energized, the gate 14 passes pulse signals from the terminal 10 to the output `18. l if The output.` 18 of the tgate .14 is connected to the input r Y ice 2,926,848
The output from the multiplier 22 is delivered to the armature of the two position `switch 24. In its first position which is shown bythe drawing, the switch 24 delivers the output signal from the multiplier 22 to a result counter 26. The counter 26 may be of the cascade binary type. Although the' switch 24 is shown in mechanical form for simplicity, it may take the form of a high speed electronic switching device, many of which are Well known in the art., 4
The output signals of the rate multiplier 22 comprise atrain or sequence of pulsesignals having a frequency or occurrence rate fUX which is the product of the rate fo of the input signals `at the lead 'V20 and the input information signal X at the rate control leads A1, A2 An. The value X equals 0.7 may be `represented in binary form by 0111, in which a zero (0) represents the absence of a signal and a one (l) represents the presence of a signal on respective control leads A1, A2 A11 of the multiplier 22. Similarly the value X equals zero may be represented by 0000 in binary form and X equals 1.0 maybe represented by 1010 as is well known in the art.
As also will be clearly evident from Figure 8 of the above published article of the inventor, when the nformation signal `X to the rate multiplier is lequal to zero (0), the rate of the output signals will also. be zero.
When the signal X has another value such as 0.2 (or `001O in binary form) the rate of output signals will be 0.2fo, where fo is the rate of input actuating signals. Thus the-value of the information signal'X to the rate control leads A1, A2 An of the rate multiplier unit 22 controls the rate of its output pulse signals. The rate of the output signals, therefore, may be represented as the product foX.
The result counter 26may be reset to its starting or zero position by a signal delivered to its input terminal 28 before the initiation of a multiplying or dividing operation. During the multiplying or dividing operation the result counter 26 registers the count of the signals delivered to it.
The signals from the output 18 of the gate 14 are also delivered to the armature of a two position switch 30 which is linked to operate unitarily with the switch 24. In its rst position (shown by the drawing), the switch 30 delivers the output signals from the gate 14 to `a control counter 32.
The control counter 32 is provided with a preset input terminal 34 which adjusts the counter 32 so that it delivers an output carry signal over its output line 3 6 upon the receipt by the control counter 32 of input signals ofa predetermined number Y.
The output line V36 of the control counter 32 delivers a Patented Maf. 1 leapV carry signal to the input terminal 38 of a bi-stable or hip-flop circuit 40 placing it in its reset condition.
The ip-op 40 is also provided with an input lead 42 for placing it in its set condition. The output line 44 of the ip-op 40 is energized only when the flip-Hop 40 is in its set condition and delivers a gating signal to the second input 16 of the gate 14.
When the switches 24, 30 are in their first positions they condition the counting device for a multiplying operation.
When the switches 24, 30 are placed in their second positions, the counting device is conditioned for a dividing operation. In their second positions, the switches 24, 30 interchange. the connections of the input leads of the result counter 26 and the control counter 32. Thus, in the second position, the output signal from the multiplier 22 is delivered to the input of the control counter 32, while the output from the gate 18 is delivered to the input of the result counter 26.
In the operation of the counting device, the result counter 26 is first reset by a reset or clear signal delivered to its input terminal 28. An information signal Y is delivered to the input terminal 34 which presets the control counter 32. Thus, if the control counter 32 is a backward-forward binary counter, a series of input pulses on the input terminal 34 representing the value Y may be delivered to its backward input terminal causing it to deliver a carry output signal only upon the delivery of Y signals to its forward input terminal.
The flip-flop 4G which has been in its reset state, is now placed in its set condition by a start signal delivered to its input terminal 42. This results in the delivery of a gating signal to the second input 16 of the gate 14 allowing the passage of a series of impulses from the input terminal to the binary rate multiplier 22 as well as to the control counter 32.
The output signals from the multiplier 22 are delivered i to the counter 26 which registers their number. As soon as the control counter 32, however, has received Y pulses it delivers a carrying signal, resetting the flip-flop and preventing passage of impulse signals through the gate 14. This terminates the counting operation.
The number registered in the result counter 26 is the product or quotient of the input information signals X and Y depending upon the position of the switches 24, 30.
In a multiplying operation when the switches 24, 30 are placed in their rst position, the result R registered in the counter 26 equals the frequency fo of pulse signals delivered to the injut terminal 10 multiplied by the rate control value 'signal X delivered to the multiplier 22 multiplied by the period of time t during which the gate 14 passes pulse signals. Bearing in mind that the frequency of actuating pulses fo multiplied by the period t during which they pass through the gate 14 is equal to the information signal Y, by substitution, it is evident that the result R in counter 26 equals the product XY of the information signals delivered to the multiplier 22 and the information signals presetting the control counter 32.
When the counting device is set to perform a dividing operation with its control switches 24, 30 in their second position, the number R registered by the result counter 26 equals the frequency fo of signals passing through the gate 1-4 multiplied by the period of time 't during which they pass through the gate 14. The rate fo of impulse actuating signals multiplied by the information signal X (controlling the multiplier 22) multiplied by the time t during which the actuating signals pass through the gate 14 equals the number Y by which the control counter 32 is preset. The time l during which signals pass through the gate 14 equals Y divided by the product of fo and X. By substitution the number R registered in the counter 22 equals the product of fo and Y divided 4 by the product of fo and X. By cancellation of fo', R i: equal to Y divided by X.
Although counting device is illustrated using an actuating signal fu at its input terminal 10 having a predetermined constant frequency, the device will also operate and in the same manner when the frequency fo varies and is not constant, and will produce the same results R in the counter 26.
Although the invention has been illustrated with regard to a particular embodiment, it will be evident to those skilled in the art that appropriate modifications may be made in accordance with design requirements Without departing from the spirit of the invention.
- What is claimed is:
1. A counting device comprising an input terminal for receiving actuating signals, a binary rate multiplier unit controllably connected with said input terminal and adapted to receive rate control information signals in parallel binary form to deliver output signals having a rate which is the product of the rate of said actuating signals and the quantity represented by said signals in parallel binary form, a rst counter excited by the output of said multiplier unit, and a second counter responsive to said actuating signals for controlling the period of delivery of actuating signals from said input terminal t0 said binary rate multiplier unit.
2. A counting device comprising an input terminal for receiving actuating signals, a binary rate multiplier unit controllably connected with said input terminal and adapted to receive rate control information signals in parallel binary form to deliver output signals having a rate which is the product of the rate of said actuating signals and the quantity represented by said signals in parallel binary form, a result counter excited by the output of said multiplier unit, and a control counter having an input lead controllably connected with said input terminal, said control counter controlling the period of delivery of actuating signals from said input terminal to its input lead and to said multiplier unit.
3. A counting device comprising an input terminal for receiving actuating signals, a binary rate multiplier unit controllably connected with said input terminal and adapted to receive rate control information signals in parallel binary form to deliver output signals having a rate which is the product of the rate of said actuating signals and the quantity represented by said signals in parallel binary form, a result counter excited by the output of said multiplier unit, and a presettable control counter having an input lead controllably connected with said input terminal, said control counter controlling the period of delivery of actuating signals from said input terminal to its input lead and to said multiplier unit.
4. A counting device comprising an input terminal for receiving actuating signals, a binary rate multiplier unit adapted to receive rate control information signals in parallel binary form to deliver output signals having a rate which is the product of the rate of said actuating signal and the quantity represented by said signals in parallel binary form, a result counter excited by the output of said multiplier unit, a presettable control counter providing a carry signal in response to a predetermined number of said actuating signals, and a signal gating unit actuated by said control counter carry signal for terminating the delivery of said actuating signals to said multiplier unit and said control counter.
5. A counting device comprising an input terminal for receiving pulse signals; a gate circuit having a first input connected with said terminal, a second input, and an output; a binary rate multiplier unit having a pulse input lead, a plurality of rate control leads for receiving information signals in parallel binary form, and an output lead; a result counter connected with the output lead of said multiplier unit; a control counter having an input count line connected with the output of said gate circuit, a preset control line, and an output carry line; and a LA.. L M
Hip-flop circuit havinga set lead, areset `leadjoined with the output carry line of said control counter, and an output line joined with the second input of said gate circuit, the output of said `rate `multiplier `unit deliveringa train of output pulse signals-having a rate which is the product of the rate ofthe pulse signals received at its pulse input lead andthe quantity represented by ,said
, information signals received at said rate control leads.
6. A counting `device comprising a first set of input terminals for receiving a first information signal in parallel binary forni, a second input terminal for receiving asecondinformationsignal, a third input terminal for receiving actuating signalspa binary rate multiplier unit joined with said first set of input terminals and controllably connected with said third terminal and having an output lead, a result counter connected with the output lead of said multiplier unit for registering `the product of the information signals delivered by said first and second terminals, a control counter joined with said second`terminal for presetting its count and controllably connected with said third terminal, said control counter responsive to said actuating signals for controlling theV connection of said third terminal with said multiplier unit and `said control counter, the output lead of said rate multiplier unit delivering a train of signals having a rate which is the product of the rate of said actuating signals received from said third terminal and the quantity represented by said information signals received at said first set of input terminals.
7. A multiplying device comprising a first set of input terminals for receiving first information signals in parallel binary form representing a value X; a second input terminal for receiving second information signals representing a value Y; a third input terminal for receiving actuating pulse signals; a binary rate multiplier unit joined with said first set of terminals for receiving said information signals, and having an input lead and an output lead; a result counter connected with the output lead of said multiplier unit for registering the product XY of the information signals delivered by said first and second terminals, and having an input conductor for clearing the counter; a control counter joined with said second terminal for presetting its count to deliver a carry signal after receiving Y signals from said third input terminal; a flip-Hop circuit having a set` lead, a reset lead energized by the carry signal from said control counter, and an output lead energized when the circuit is in its set condition; and a gate circuit having a first input connected with said third terminal, a second input connected with the output lead of said flip-op circuit, and an output lead for delivering signals to said multiplier unit and said control counter, the output lead of said rate multiplier unit delivering a train of output pulse signals which is the product of the rate of said actuating signals received by its input lead and said value X represented by said information signals in parallel binary form.
8. A dividing means comprising a first set of input terminals for receiving first information signals representing a value X in parallel binary form; a second input terminal for receiving second information signals representing a value Y; a third input terminal for receiving actuating signals having a rate fu; a binary rate multiplier unit joined with said first set of terminals, and having an input lead and an output lead; a result counter for registering the quotient Y/X of the information signals delivered by said first and second terminals, and having an input conductor for clearing the counter; a control counter joined with said second terminal for presetting its countto deliver a carry signal after receiving Y signals from the output lead of said multiplier unit; a flip-nop circuit having a set lead, a reset lead energized by the carry signal from said controlcounter, and an output lead energized when the circuit is in its set condition; and a gate circuit having a first input connected with saidfthirdvterminal, a'second input-connected with lthe output.leadofrrsaidlipiiop circuit, and an output lead for `delivering,pulselsignals to said multiplier unit. and saidtresult counter, the output lead of said rate multiplier unit delivering` a train of signals having a rate foX which is thenproductfofthe actuating signals .received byits input lead and the information signal of value X received from said first set of terminals. v
SLAf counting apparatus comprising an input terminal for receiving pulsesignals; a gate circuit having a first input connected `withvsaid terminal, a second input, and an output;a binary rate multiplier unit having: apulse inputlead; a plurality'of rate control. leads, and anoutput lead; a result counter having an input lead; a control counter having an input count line, a preset control line, and an output carry line; a flip-flop circuit having a set lead joined with the output carry line of said control counter, and an output line joined with the second input of said gate circuit; and switching means having a first position connecting the output of said multiplier unit with the input lead of said result counter and the output of said gate circuit with the input count line of said control counter, and a second position connecting the output of said multiplier unit with the input count line of said control counter and the output of said gate circuit with the input lead of said result counter.
l0. A multiplying-dividing apparatus comprising a first set of input terminals for receiving first information signals representing a value X; a second input terminal for receiving second information signals representing a value Y; a third input terminal for receiving actuating pulse signals; a binary rate multiplier unit joined with said first set of-terminals, and having an input lead and an output lead; a result counter for registering selectively the product XY and the quotient Y/X of the information signals delivered by said first and second terminals and having an input lead; a control counter having an output line, a first input line, a second input line joined with said second terminal for presetting its count to deliver an output signal upon receiving Y pulse signals at its first input line; a flip-flop circuit having a set lead, a reset lead connected with the output line of said control counter, and an output lead energized when the circuit is in its set condition; a gate circuit having a first input connected with said third terminal, a second input connected with the output leadV of said fiip-fiop circuit, and an output lead; and switching means having a first position connecting the output lead of said multiplier unit with the input lead of said result counter and the output lead of said gate circuit with the first input line of said control counter causing said. result counter to register the product XY, and a second position connectng the output lead of said multiplier unit with the first input line of said control counter and the output lead of said gate circuit with the input lead of said result counter causing said result counter to register the quotient Y/X. t
l1. Apparatus for providing a digital output indication of the combination of a first quantity represented by a first signal in parallel binary form with a second quantity represented by a second input signal comprising gating means having first and second inputs and an output, a source of a reference signal having a reference rate, means for coupling said reference signal source to said gating means first input, a binary rate multiplier having a rate input terminal coupled to said gating means output, an output terminal and rate control leads, means for applying a conditioning signal to said gating means second input to couple said reference signal from said source to said binary rate multiplier rate input through said gating means, means for applying said rst signal in parallel binary form to said rate control leads to alter said reference rate whereby the rate of the signal on said binary rate multiplier output equals the product of said reference rate with sadgrst quantity, a result counter Yhaving an input, a controlY counter having an advancing input, a preset input, and delivering a carry pulse after a predetermined number of signals are received at said advancing input, means for applying said second signal to the preset input of said control counter to select said predetermined number, selective means for coupling the output of said binary rate multiplier and the output of said gating means to respective ones of said result counter input and'said control counter input, and means responsive to a carry pulse delivered from the outputof said control counter for removing said conditioning signal from said gating means second input.
References Cited in the ile of this patent UNITED STATES PATENTS 2,543,442 lDenchV Feb. 27, 1951 2,641,407 Dickinson June 9, 1953 `2,685,407 Robinson Aug. 3, 1954 2,702,666 Dickinson Feb. 22, 1955 2,725,191 Harn 'Nov. 29, 1955 2,769,595 Bagley Nov. 6, 1956 OTHER REFERENCES Meyer et a1.: An operational Digital Feedback Divider, I.R.E. Transactions, Computer Group, March 1954, ECS #1, pages 17 to 19.Y
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US542625A US2926848A (en) | 1955-10-25 | 1955-10-25 | Counting device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US542625A US2926848A (en) | 1955-10-25 | 1955-10-25 | Counting device |
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| Publication Number | Publication Date |
|---|---|
| US2926848A true US2926848A (en) | 1960-03-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US542625A Expired - Lifetime US2926848A (en) | 1955-10-25 | 1955-10-25 | Counting device |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3052412A (en) * | 1961-01-26 | 1962-09-04 | Ibm | Multiplier circuit |
| US3126476A (en) * | 1959-03-31 | 1964-03-24 | Binary rate multiplier | |
| US3327100A (en) * | 1963-11-07 | 1967-06-20 | Intelligent Instr Inc | Logarithmic computer |
| US3480910A (en) * | 1963-11-04 | 1969-11-25 | Ibm | Pulse value determining receiver |
| US3566096A (en) * | 1966-07-25 | 1971-02-23 | Pacific Ind Inc | Digital ratiometer |
| US3676656A (en) * | 1969-06-30 | 1972-07-11 | Gen Electric | Electronic digital slide rule |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US2543442A (en) * | 1948-04-20 | 1951-02-27 | Interchem Corp | Electrical multiplying apparatus |
| US2641407A (en) * | 1949-06-18 | 1953-06-09 | Ibm | Electronic multiplier |
| US2685407A (en) * | 1948-12-23 | 1954-08-03 | Nat Res Dev | Circuit for multiplying binary numbers |
| US2702666A (en) * | 1949-12-08 | 1955-02-22 | Ibm | Multifrequency electronic multiplier |
| US2725191A (en) * | 1948-12-27 | 1955-11-29 | Ham James Milton | Apparatus for general electronic integration |
| US2769595A (en) * | 1952-07-23 | 1956-11-06 | Hewlett Packard Co | Frequency counter |
-
1955
- 1955-10-25 US US542625A patent/US2926848A/en not_active Expired - Lifetime
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US2543442A (en) * | 1948-04-20 | 1951-02-27 | Interchem Corp | Electrical multiplying apparatus |
| US2685407A (en) * | 1948-12-23 | 1954-08-03 | Nat Res Dev | Circuit for multiplying binary numbers |
| US2725191A (en) * | 1948-12-27 | 1955-11-29 | Ham James Milton | Apparatus for general electronic integration |
| US2641407A (en) * | 1949-06-18 | 1953-06-09 | Ibm | Electronic multiplier |
| US2702666A (en) * | 1949-12-08 | 1955-02-22 | Ibm | Multifrequency electronic multiplier |
| US2769595A (en) * | 1952-07-23 | 1956-11-06 | Hewlett Packard Co | Frequency counter |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3126476A (en) * | 1959-03-31 | 1964-03-24 | Binary rate multiplier | |
| US3052412A (en) * | 1961-01-26 | 1962-09-04 | Ibm | Multiplier circuit |
| US3480910A (en) * | 1963-11-04 | 1969-11-25 | Ibm | Pulse value determining receiver |
| US3327100A (en) * | 1963-11-07 | 1967-06-20 | Intelligent Instr Inc | Logarithmic computer |
| US3566096A (en) * | 1966-07-25 | 1971-02-23 | Pacific Ind Inc | Digital ratiometer |
| US3676656A (en) * | 1969-06-30 | 1972-07-11 | Gen Electric | Electronic digital slide rule |
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