US2861260A - Reading saturable cores - Google Patents

Description

Nov. 18, 1958 R; E. wEssLuND ET AL 2,861,260

READING SATURABLE coREs Filed Feb. '1, 1957 /NPARALLEL READOUT STAGE STAGE I I A'JVANE RESET fc m STORAGE zounTER`4o A 5&1-

A2 Al A2 Al A2 I NPuT To LINE 24 s J f ADVANCE PuLsEs |02 H8 125 READouT BIAS |08 22 |30 AFROM TUBE 4a BUFFER ouTPuT |04 |20 V27 4 |32 READouT ouTPuT ya M28 n INVENTORS ROBE/PT E WESSLUND .LYLE W, MADE/i GORDON W. JOHNSON ATTORNEY hub v READING SATLE CORES Robert E. Wesslund, St. Paul, Minn., Lyle W. Mader,

Silver Spring, Md., and Gordon W. Johnson, Minneapolis, Minn., assignors to Sperry Rand Corporation, New York, N. Y., a corporation of Delaware Application February 7, 1957, Serial No. 638,770 ZSCIams. (Cl. 340-174) This invention relates to magnetic devices which utilize the hysteresis characteristic of magnetic materials as a means for gating digital information.

The value of saturable reactors comprised of suitably wound small cores of ferromagnetic material for use as storage and logical elements in electronic data handling systems is being increasingly recognized, particularly because of their miniature size, low power requirements, dependability, and their ability to retain stored information for long periods of time in spite of power failure. The cores of such reactor elements are able tostore binary information in the form of residual magnetization after the cores are magnetized to saturation in either of two directions. The saturation can be achieved by passing a current through a winding on the core. When the magnetomotive force thus created is opposite in polarity to-the direction of the pre-existing residual magnetic induction, the direction of the static residual magnetization of the core is reversed. The resultant change in uX produces a sizable voltage pulse across every winding on the core, which pulse may be utilized in avariety of Ways such as to drive a second saturable reactor element to saturation in a predetermined polarity. On

.the other'hand, the application of a magnetomotive'force which merely drives a reactor element further into saturation in the same direction as that of the residual flux produces a change in flux which is small compared to that created in a reversal of flux polarity so that a correspondingly small voltage pulse is induced in each winding on the core.

In order to achieve a large ratio between voltage pulses induced in switching the polarity of a saturable reactor element as compared to that obtained in driving it further into saturation in the direction of its pre-existing residual magnetization, the core material is preferably f one having at least a quasi-rectangular hysteresis characteristic so that the residual flux density is a relatively large percentage of the ux density present during the application of a saturating magnetomotive force. A

number of suitable magnetic materials are available such as DeltamaX, 4-79 Permalloy, and certain ferromagnetic ferrites. In order to improve high frequency response by reducing eddy current losses, metallic ferro-alloysV are preferably used in thin strips which may be wrapped around ceramic spools while ferrite cores may be molded and windings placed directly thereon, inasmuch as .ferr-ites are relatively free from eddy current effects.

While.saturable reactor elements can be used eXtensively as storage and switching elements inelectronic data handling systems, they cannot by themselves entirely eliminate vacuum tubes or transistors and the like, because saturable reactor elements are current driven devices and so must be associated with suitable current generating means. Accordingly, a great many logical circuits employing reactor elements and vacuum tubes or transistors in close interrelation are being utilized. With the reactor elements serving to store information nited States arent rice and the vacuum tubes or transistors usedto switch the information.

In circuits employing closely related saturable reactor elements and vacuum tubes or transistors, a major problem has been to read out'the information stored in the reactor elements without causing one or more tubes or transistors to generate an unwanted current.V This problem exists both where itis desired to read out the stored information While retaining it in the saturable reactor storage elements, so-called non-destructive readout, and where the readout operation may leave one or more of the storage elements with a different stored digit, so-called destructive readout. Unwanted currents generated in the associated vacuum tubes or transistors in the readout operation invariably prevent non-destructive readout and may produce errors, even in destructive readout.

It is accordingly an object of this invention to provide a novel system for reading out information from saturable reactor elements.

It is a further object of this invention to provide means for reading out digital information non-destructively from circuits composed of interrelated saturable reactor elements andcurrent-generating devices. It is another object of this invention to provide novel means for destructively reading out digital information from saturable reactor elements which are closely associated with current-generating devices.

lt is a more specific object of this invention to provide means for reading out information either destructively or non-destructively from a binary-coded counter composed of interrelated saturable reactor elements and vacuum tubes. n

These and other objects of the invention as well as the invention itself will be best understood from the following description and claims when taken in connection with the drawings in which:

Figure 1 is a fractional circuit diagram of a conventional, vacuum tube, magnetic counter which is modified according to the principles of this invention to obtain non-destructive readout. l

Figure 2 is a timing diagram illustrating the readout from one stage of the counter of Figure 1.

Figure 3 is a fragmentary diagram showing the manner in which the circuit of Figure 1 may be modified for purposes o-f economy if destructive readout is permissible.

Figure 4 shows another modification of Figure 1 whereby the saturable reactor buffer elements are switched only under no-load conditions and the feature of non-destructive readout is retained.

The cores of the saturable reactor elements are shown in the drawings to be toroidal in shape. However, the shape of the cores is not critical so long as adequate coupling is achieved between the core and its windings. Toroidal cores are especially satisfactory in this respect and incidentally produce a minimum external field.

Reference is now made to Figure l which shows the Vfirst two stages of a multi-stage binary-coded counter .which is provided with means for gating out informationstored thereby in parallel, non-destructively. The counter per se is shown and described on pages 42 and 43 of an article by Bernard M. Gordon and Renato N.

Nicola entitled Special-Purpose Digital Data-Processing and each of the reactor cores is provided with five Windings. An additional transistor or triode 18 is utilized at the input of the rst stage to initiate the counting action. It should be noted, however, that the counter has been modified by the inclusion in each stage of an inductive impedance such as choke 28, 22, etc., respectively, having a value in the order of one millihenry. The choke is not essential but has been found to improve the reliability of the counter, .especially at the very high frequencies made possible by. the availability of improved ferromagnetic materials.

Although vacuum tubes have been used in illustration with the counter herein, it will be understood, as in keeping with vthe above cited article, that transistors may be used` in Atheir stead.

Briefly, 'the operation of the lmagnetic counter apart from 'its readout modification is as follows. Assuming that storage elements 14, 16 are initially in the state of residual 'magnetization Iwhich was arbitrarily designated as the O or 'counter-clockwise ux state, a positive voltage pulse indicative, of a binary l on input lead 24 is lfedgover a first unidirectional path to input circuit means including triode 18 which causes triode 18 to conduct current through winding 26 on storage element 14. The resultant magnetomotive force switches element 14 to the l or clockwise flux state, inducing a sizable voltage pulse across every winding thereon. The voltage induced across winding 28 counteracts the input pulse on leads 24 and 25 via the second input circuit means and unidirectional path to prevent the raising of grid 27 and vthereby prevent the triggering of triode 10, while the voltage induced across winding 30 merely drives the grid 29 of triode 12 more negative.

A second positive input pulse on line 24 again causes triode 18 to conduct, ybut storage element 14 is already in `the l state so that the back E. M. F. induced across winding 2S is insufiicient to prevent the input pulse on line '25 from passing through winding 28 and choke 28 to raise grid 27 to trigger tube 1t) to conduction. The output of tube is applied to winding 32 and because of the transformer coupling between windings 32 and 28, the grid of tube 18 takes a negative swing in the manner -of a lblocking oscillator. This allows the plate current from tube 10 to increase, since the plate current from tube 18 decreases with -a negative swing towards cutoff and produces a positive swing on the grid of tube 10 by transformer action between windings 26 and 28. Therefore, storage `element 14 is driven to the G stage. The blocking-oscillator action is modified by the choke 20 to assure the saturation of element 14 in the 0 state, and by virtue of the plate current in lines 34, 36, the `saturation of storage element 16 is assured of being in =a state arbitrarily designated the l or clockwise flux state. The switching of element 16 to l creates a back E. M. F. across winding 38 which blocks the voltage pulse generated across winding 39 from raising grid 29 and =thereby from triggering tube v12.

A third positive pulse on input lead 24 again causes plate current to flow through winding 26 to switch element 14 .to the l state while transformer coupling between windings 26 and 28 prevents succeeding stages from being affected. A fourth pulse, as did the second pulse, switches element 14 to the 0 state and causes plate current from triode 10 to flow through winding 46, but since element 16 is already in the l state, the voltage. induced across winding 30 by the output of tube 10 through winding 32 raises grid 29 to trigger triode 12. Element 16 is accordingly returned to the 0 state by the output of tube 12, and a carry pulse on line 42 switches the state of the sto-rage element of the third stage (not shown) to an arbitrarily designated l state, etc.

Parallel non-destructive readout from the binary .counter may be achieved by addingtwo saturable reactor :elements toi-each .stage ofthe counter and by supplying a single readout control circuit 44 comprised of a cathode CII follower 46 and agate tube 48. One saturable reactor element Si), 52, etc., respectively, in each stage may be conveniently referred to as the readout element and the other additional elements 54, 56, etc., respectively, serve as buffers between the storage and readout elements. It will be appreciated that buffer elements S4, 56 will assume the same polarity as sto- rage element 14, 16 at all times in the absence of magnetomotive forces not yet considered. For instance, when plate current through winding 26 switches storage velement 14 to the l state, the plate current also ows through winding 58 to switch buler element 54 to a l or clockwise flux state. T hen when blocking oscillator action increases the plate current from tube 10 while cutting off .the plate current from tube 18, the predominant current through winding 60 will switch buffer element 54 to the 0 or counter-clockwise linx state. Y

In order to effect parallel readout, a two-phase, interlaced sequence of current pulses are utilized, their alternate periods of time vin the sequence being conveniently designated as A1 and A2 periods. The A2 periods are reserved for the input and output of information while A1 periods are used to shift the 'information from the buffer elements 54, 56 to the readout elements 50, 52. An advance pulse may then be passed through windings 62, 64 only during an A1 period. The advance pulse may conveniently, but does not necessarily, have a relativelysquare waveform of duration slightly shorter than one A1 period, and `when applied to buffer elements 54, 56, always drives those elements to the 0 or counterclockwise ux state.

Readout control is effected from circuit 44; the gate tube 48 thereof is normally biased to conduction so that a constant current flows through windings 66, 68, and like windings in other stages (not shown) to produce la magnetomotive force in elements 50, 52, etc., which sets these elements in the arbitrarily designated 0 or counter-clockwise flux polarity. The amplitude of this current can be readily adjusted so that the magneto- -motive force is 'large enough to prevent any pulses in windings 70, 72 from switching elements 50, 52, respectively, to the 1 or clockwise `flux state. The biasing current can be removed by applying a negative -voltage on line 74 Vto cut off the normally conducting cathode follower tube 46 so that the vpotential of lead `76 going to the control grid of pentode 48 takes a negative swing, cutting off pentode 48. By removing the negative voltage on lead 74, cathode follower tube 46 again becomes conducting, thereby causing the potential lof line 76 to go positive, and current again ktlows through windings 66, 68. However, A. C, coupling by condenser 78 between cath- Vode follower 46 and the control grid of tube 48 gives a sharp increase to the vplate current pulse of tube 48 when it is brought to conduction. This surge of current may be several times the amplitude of the steady biasing current, and thus it can apply sufficient magnetomotive force to sa-t-urable reactor elements 50, v52 to return them to the 0 state if they were switched tothe l state during removal fof the biasing current. This current surge quickly falls off Vto the lower steady value which is preferably just sufficient toretain readout elements 50, 52 at 0 to hold power losses to a minimum. It will 'be appreciated bythose skilled in the art that the .amplitude rand duration'of the current surge on reapplica'tion of the biasing current is dependentupon the RC time constant of capacitor 78 and potentiometer 80 and so can be varied Eby adjusting either or the latter as shown. It has been found that a steady biasing current in the order of `30 -milliamperes and la current surge on its reapplication of milliamperes are satisfactory.

The method of reading out information from the magnetic vcounter in parallel, non-destructively, may-best vbe understood with reference to the timing diagram of Figu re 2 considered in wconnection with the rst stage of FigureV l. For exemplary purposes, an input of three successive pulses representing binary ls followed by a continuous stream of Os or the absence of pulses is applied to the first stage of the counter which was initially cleared. The first 1 pulse 100 is applied during an A2 time period to set storage element 14 and buffer element 54 to the 1 state. This 1 may be read out in parallel by applying during the next A1 period an advance pulse 102 to winding 62 of buffer element 54 while simultaneously reducing or removing the bias current from winding 66 of readout element 50. The advance current drives buffer element 54 to the 0 or counter-clockwise iiux state and induces a pulse 104 across winding 106V to switch readout element 50 to its l or clockwise ux'state. The current surge 108 through winding 66 on,

re-application of the bias current resets element 50 to 0, inducing a voltage pulse across windings '70 and 110. The pulse 112 across winding 110 as read out on line 114 maybe used for a variety of purposes including the switching of a saturable reactor element in another counter or register. The readout pulse across winding 70, in turn, effectively maintains correspondence between the states of the buffer core 54 and the storage element '14 in thetabsence of otheriinputs on line 24, and in this particular instance the readout pulse tends to return the buffer core 54 to the l state, but the second 1 pulse '116' appears simultaneously onlead 24. This pulse 116 resetsstorage element 14 to 0 as was explained above in connection with the'counter action and a relatively large current pulse flows through winding 60 on buffer 'element 54. The current through Vwinding 60 and the current owing through winding 106 produce opposing magnetomotive forces with the result that buffer element 54 remains in the O state and so again corresponds to the residual state of storage element 14. The application o f an advance pulse 118 at the next A1 period merely drives buffer element 54 further into the 0 state and so induces an insignificant pulse 120 across winding 106 so that readout element 50 remains at 0 even though the bias current was removed, `and re-application of the bias at 122 neither affects buffer element 54 nor generates a readout pulse on line 114 other than the relatively small blip 124 produced in driving element 50 further into saturation in the 0 direction. The next input pulse 126 finds both storage and buffer elements 14, 54 at 0 and so switches them to 1.

V'The contents of the magnetic counter are retained indefinitely until the next input pulse arrives on line 24 regardless of VWhether readout is `initiated by removing the bias current and simultaneously applying an advance pulse or regardless of how many times the stored information is read out. In the example illustrated by vFigure V2, lno readout is further called for after blip 124 until the second succeeding A1 period, at which time the 1 stored in buffer element 54 isrtransferred by applying advancepulse` 125 to cause pulse 127 to be presented to readout element 50 for readout at the beginning of the next A2 period on line 1714 as pulse 128. The current surge 130 alsov returns buffer element 54 to the l state so that a readout operation during the succeeding cycle produces another 1 pulse 132 on line 114. c While the discussion of readout from the counter of `Figure 1 has been'confined to itsY first stage, itwill be appreciated that a practical application may call for `simultaneous readout from the entire counter. Accordingly, asingle advancepulse may berapplied to allbuffer elements and the biasing currentpwill iiow through, a Y*winding `on each readout element. Of course, each stage ,or groups of stages could be individually controlled vwithout diiiiculty in the event thatsuch control were desirable. i It should also be 'noted that the application of fan l" advancei'curr'ent to'a'buffer element and the resetting of 'the Vbuffer element from the readout elements in noway affect the storageor saturablecore counting elements 14,

' circuit 44 of Figure l.

16vbecause each line 34, 150, for example, coupling a winding on a buffer element to a winding on a storage elcrnent is in a unidirectional path including a unidirectional current conducting device such as a vacuum tube or -transister and is therefore open-circuited as by vacuum tubes 1t) and 12. For this reason, no voltages are induced which would drive a tube to conduction except as a result of the counting action. v By the same token the application of a reset pulse to the storage elements does not affect the buffer elements so that an advance pulse must also be snppiicd thereto without removing the bias current'in order to clear the circuit of Figure l completely. It should be noted that except when clearing the counter, advance pulses are applied to the buffer elements only when the bias from tube 43 is simultaneously reduced or removed from the readout elements, so that the information sto-red in the buffer elements is not destroyed.

Reference is now made to Figure 3 to illustrate the manner in which the circuit of Figure l could be modified if destructive readout from a binary-coded magnetic counter is permissible. However, as modified by Figure 3, the readout is destructive only in the sense that a sub'- sequent readout from any stage could not be effected until the information stored in that stage had been altered by the receipt of new information. Since this embodiment of the invention does not affect the magnetic counter, only a fragmentary view of the first stage is shown in Figure 3 beginning with leads 34 and 150 from windings on Storage element 144of Figure 1V and extending to lead 36 to a succeeding storage element, for example, element 16 `of stage 2.' lf magnetic element 54 is in the l state, a positive current applied to advance winding 62 drives element S4 to the 0 state to induce a sizable voltage pulse across winding 106. To this pulse, rectifier 152 presents a low forward impedance while rectifier 154 would normally present a high forward impedance. However, the advance current flows from winding 62 through rectifier 154 to ground to bias it to conduction so that rectifier 154 also presents a low impedance and allows a reverse current flow in the form of the induced pulse, and a signal representing the 1 appears on line 114. No current is induced in windings 5S and 60 since their input lines 150 and 34, respectively, are open-circuited by vacuum tubes such as tubes V18 and 10 of Figure l. Unidirectional device 154 may be forwardly Vbiased in any other manner, but is preferably biased by the advance pulses as shown. When readout is called for while magnetic element 54 stores a 0, the advance pulse merely drives element 54 further into the 0 direction so that virtually no pulse is generated across Winding 106. It should be noted that rectifiers 152, 154 as well as other rectiiiers included in the circuits used to illustrate this invention are preferably semi-conducting diodes.

While the reading out of a l from magnetic element 54 of Figure 3 leaves that element'in the 0 state in the absence of provision for feedback of the 1 from the device to which line 114 transmits that 1, the counting or storage element connected to lines and 34 (e. g., element 14 ofFigure l) is not affected so that the l information, is not lost. However, no means is provided for placing the 1 still stored by element 14 back into buffer element 54; therefore, a subsequent, accurate, parallel readout cannot be obtained without inserting enough new informatio-n to put every stage of the counter through at least one change in state. Accordingly,tread out uaingrthe modification cfFigure 3 is considered to be destructive, though not wholly so.

The readout device of Figure 3, however, offers certain advantages over that of Figure l. It offers economy in circuit components in requiring one less saturable reactor element per stage and in eliminating 'the readout control 1t offers economy in power in eliminating the biasing current flowing from pentode 48 and the current owing through the normally conducting cathode'V follower 46. Another consideration is the no- 7 load switching of buer element 54 in the modification of Figure 3 since rectifiers 152, 154 block any current caused by the voltage which may be generated across output winding 106 while driving buier element 54 with pulses on either of lines 34 or 150. On the other hand, when the buffer element 54 of Figure 1 is driven by a current on line 34 to the 0 state, the voltage pulse across winding 106 of Figure 1 generates a current which passes through the rectifier 160 in its direction of low impedance and so is limited only by resistor 152. This additional loading requires a substantial increase in the power output of tube 10. If the additional power required is too large for a particular application, a second rectifier 164 may be included in series opposition with rectifier 16u in the leads between winding 106 on the buffer element and winding 70 on the readout element as indicated in Figure d, which is a fragmentary modification of the circuit of Figure 1. Rectifier 164 is then enabled for reverse current flow by advance current pulses iiowing through winding 62 in a manner similar to rectifier 154 of Figure 3. However, since there is no advance pulse flowing in winding 106 at the time core 50 is read out, diode 164 appears to be disabled; thus the readout from core 54 is destructive. In certain applications where a reduction lin the loading of the storage (or buffer) core is important, this alternative form of circuit (Fig. 4) may be useful.

It will be appreciated that numerous modifications could be made in the circuits used to illustrate this invention and various other embodiments thereof could be designed by one skilled yin the art without departing from the scope of the invention. Therefore, it is intended that the matter contained in the foregoing description and illustrated by the appurtenant drawings be considered as illustrative and not limitative, the scope of the invention being dened by the appended claims.

We claim:

1. Apparatus for reading without destroying the state of a bistable saturable core element operablealternately between two states in response to succeeding input signals comprising bistable saturable core buffer means coupled with said core element in such a manner that said input signals cause correspondence in the states of the buffer means and said core element, said buffer means having input means for receiving advance signals which when applied allow an output from the buffer means which is indicative of the state thereof, and readout means including output winding means associated with said buffer means for reading the output from the buffer means,

said output being ineffective to change the state of said saturable core element.

2. Apparatus as in claim l wherein said readout means includes two opposing unidirectional current conducting devices, one of 'said devices being biased for reverse cur rent flow to pass said output during the time when an advance signal is applied.

'3. Apparatus as in claim 2 wherein said one unidirectional device is connected with the advance signal input means for biasing of said one device by an advance signal.

4. Apparatus as in claim l wherein said readout means includes bistable readout saturable core means and coupling means including unidirectional means for coupling said output winding means to the readout core means,- the arrangement being such that said output from the buffer means permits a readout from the readout core means, said readout being indicative of the state of said core element and operating in effect at least on said buffer means to maintain correspondence of states between said core element and the buffer means.

8 means includes a single unidirectional current conducting` device.

7. Apparatus as in claim 4 wherein said unidirectional means includes two opposing unidirectional current con. ducting devices, one of, which is biased for reverse curr. rent flow to pass said output from the buffer means dur-4 ing the time when an advance signal is applied.

8. Apparatus as in claim 7 wherein said .one unidirectional device is connected to the advance signal input means for biasing of said one device by an advance signal.

9. Apparatus for reading without destroying the state of a bistable saturable core element having two input circuit means each including a unidirectional current path, comprising bistable saturable core buffer means coupled with said core element in said unidirectionalvpaths so that succeeding input signals delivered to said two input circuit means cause correspondence in the states of the buffer means and said core element, said buffer means having input means for receiving advance signals which when applied allow an output from the buffer means, said output being indicative of the state of the bufer means, and readout means including output winding means associated with said buffer means for reading the output of the buffer means while said unidirectional paths prevent said reading from changing the state of the saturable core element.

10. A bistable saturable core binary counting element comprising said bistable saturable core having at least first, second, third, and fourth windings, two circuit paths each including a unidirectional current conducting device and said first and fourth windings, respectively, an inductive impedance coupling said second winding'with the unidirectional device associated with said fourth winding, the first and second windings being further coupled t0 receive input signals one of which operates via said first and second windings to shift said counting element to a first state and a successive one of which operates via said second and fourth windings to shift the counting element to a second state, the arrangement being such that said third and fourth windings provide outputs for every second input signal.

11. Apparatus for reading in parallel without destroying the contents of a counter, said counter including a plurality of bistable saturable core elements connected in cascade by associated circuitry so that each element provides an output signal for every second input signal Yapplied at its input, each of said core elements comprising a stage of the counter, the output signal of any one stage being the input signal of the succeeding stage, each stage further including bistable saturable core buffer means coupled with its associated core element in such a manner that the input signals thereto cause correspondence in the stable states of the respective buffer means and core elements, each of said buffer means having input means for receiving advance signals which when applied allow outputs from the buffer means indicative respectively of the stable state thereof, and readout means for each stage including output winding means associated with each buffer means for reading simultaneously the respective outputs from the buffer means, said outputs being ineffective to change the states of the core elements.

12. Apparatus for reading without destroying the state of a bistable saturable core counting element in a stage of a multi-stage saturable core signal counter, comprising said saturable core counting element with first and second input means, each of which includes unidirectional circuit means, said counting element being operable between first and second flux states in response to successive countable signals effectively received alternately by said first and second input means respectively, said second input means partially forming also output means for providing an output signal to be counted by a succeeding stage when a countable signal passes through said second input means and shifts the counting element to its sec- 9 ond state, and bistable saturable core buffer means having read-out means associated therewith, said buffer means being shiftable between first and second states and having first, second and third inputs and an output, the rst and second inputs being coupled respectively into the unidirectional circuits of said first and second input means of the counting element so that said successive countable signals shift the buffer means between two states in correspondence with the state of the counting element, said third input being adapted to receive advance signals which when applied are interleaved in time with the countable signals, the arrangements being such that to provide readout, an advance signal is applied to produce an output from the buffer means through said readout means for reading the indication ofthe state of the buffer means and of the counting element, the readout being ineffective to change the state of the counting element because of said unidirectional circuit means.

13. Apparatus as in claim 12 wherein said readout means includes two unidirectional current conducting devices connected in series opposition with the output of said buffer means, one of said devices being biased for reverse current flow to pass the buffer means output during the time when an advance signal is applied.

14. Apparatus as in claim 13 wherein said one unidirectional device is connected with the third input of the buffer means for biasing of said one device by an advance signal.

l5. Apparatus as in claim 12 wherein s'aid readout means includes a bistable readout saturable core having an output, a first input for receiving controllable bias, a second input and unidirectional means coupling the output of said buffer means to the second input of the readout means, 4the arrangement being such that an application of an advance signal permits a readout from the output of said readout means during an increase of the bias at said first input following a reduction thereof during an advance signal application, said readout then allowing the state of the buffer means to correspond to the state of said counting element.

16. Apparatus as in claim 15 wherein said unidirectional means includes two opposing unidirectional current conducting devices, one of which is biased for reverse current flow to pass the buffer means output during the time when an advance signal is applied.

17. Apparatus as in claim 16 wherein said one unidirectional device is connected with the third input of the buffer means for biasing of said one device by said advance signals.

18. Apparatus for reading without destroying the state of a bistable saturable core counting element in a stage of a multi-stage saturable core signal counter, comprising said saturable core counting element having at least first, second, third, and fourth windings, two circuit paths each including a unidirectional current conducting device and said first and fourth windings respectively, the second winding being coupled to the fourth winding by its associated unidirectional device, first and second windings being further coupled to receive input signals, one of which operates via said first and second windings to shift said counting element to a first state and a succes'sive one of which operates via said second and fourthy windings to shift the counting element to a second state for supplying input signals from said fourth winding to a homologue of said first winding in a succeeding stage, said third winding operating by transformer action with the fourth winding to supply like input signals for a homologue of said second winding in said succeeding stage, and a bistable saturable core buffer element having first and fourth windings connected in said circuit paths respectively with the first and fourth windings of said counting element so that the state of the buffer element shifts with the state of the counting element and corresponds thereto, and readout means including an output winding on said buffer element for reading the state p asenaeoof said counting element, said buffer element further including an advance winding for receiving advance pulses which when applied provide a binary output for said readout means while said unidirectional devices prevent an applied advance pulse from inducing a change of state in said counting element.

l19. Apparatus as in claim 18 further including an inductive impedance in circuit between said second winding of the counting element and its lassociated unidirec-` Y tional device.

20. Apparatus as in claim 18 wherein said readout means includes two opposing unidirectional current conducting devices connected in series with said output winding, one of said devices being biased for reverse current flow to pass said buffer element output during the time when an advance signal is applied.

21. Apparatus as in claim 20, wherein said one unidirectional device is connected with said advance winding for biasing of said one device by an advance pulse.

22. Apparatus as in claim 18, wherein said readout means includes a bistable readout saturable core element having an output winding and a unidirectional element in circuit therewith, a first input winding, coupling means including unidirectional means for coupling the first input winding to said output winding of the buffer element, and a second input winding for receiving controlled bias, the arrangement being such that said output from the buffer element permits a readout from the readout output winding, said readout being indicative of the state of the counting element and operating in effect at least on said buffer element to maintain correspondence of states between said counting element and the buffer element following the application of an advance pulse.

23. Apparatus as in claim 22 wherein said unidirectional -means includes a single unidirectional current conducting device.

24. Apparatus as in claim 22, wherein said unidirectional means includes two opposing unidirectional current conducting devices connected in series with said output winding on the buffer element, one Vof said devices being biased for reverse current flow Vto pass said buffer element output during the time when an advance signal is applied.

25. Apparatus as in claim 24, wherein said one unidirectional device is connected with said advance winding for biasing of said one device by an advance pulse.

26. In apparatus for reading without destroying the binary contents of at least one stage of a multi-stage signal counter having a bistable saturable core counting element in each stage, bistable saturable core buffer means having first and second input means unidirectionally associated respectively with first and second input means of said saturable counting element, the first and second input means of the counting element being adapted to receive alternately, in effect, the signals to be counted, the counting element and the saturable buffer means being shiftable between first and second states in4 response to signals at the first and second input means of the counting element, respectively, said buffer means having further a third input means for receiving advance signals which cause said buffer means to be in its second state and output means for providing an output signal from the buffer means upon receipt of an advance signal if the core means was then in said first state, bistable readout saturable core means having an output and two'V inputs, one of which is coupled to the output means of the buffer means, the other readout input being controllably biased by a normal biasing signal large enough to counteract said output signal from the buffer means, the arrangement being such that to provide readout, the normal biasing signal is reduced While an advance signal is applied to provide an output signal if the buffer means changes its state thereby, following which the resumption of at least said normal biasing signal at the readout 1l means lcauses. a. realnntoutput. isiilt '9i ille. 'get-.G of the huief means., .Said buier mean. b nemen teturned, if neessaw,k 1Q eorrespend itl e i@ the t??? 0fthe Counting element by an input -ffm the @dem means to said Youtput means of* they bnier means.

27. Apparatus as in claim 26, whegein sai@ gne input of the readout core means is .cgoupled` teo the Qntpnt means of the buffer means by two opposing n n etuignal ,cnrrent conducting devices, `one of said devi being biased 12 fet-tenets@ ement Qw to PLISS Said buffer Output Signal during the when an advance, Signal is appli@ ZSJApprams as in daim 2,7, wherein said Qne uni.- di'rect'inonal device i s yccmnected'with the third input means Qi v tllle buffer means for biasing of said one Vdevice by an advance lsrigllzlal.

V No ,references Cited-

Images