US2734185A - Magnetic switch - Google Patents

Magnetic switch Download PDF

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US2734185A
US2734185A US2734185DA US2734185A US 2734185 A US2734185 A US 2734185A US 2734185D A US2734185D A US 2734185DA US 2734185 A US2734185 A US 2734185A
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/06Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using single-aperture storage elements, e.g. ring core; using multi-aperture plates in which each individual aperture forms a storage element
    • G11C11/06007Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using single-aperture storage elements, e.g. ring core; using multi-aperture plates in which each individual aperture forms a storage element using a single aperture or single magnetic closed circuit
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/16Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using saturable magnetic devices

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  • This invention relates to magnetic devices, and particularly to noise-cancellation in such devices.
  • Magnetic switches and memories employing magnetic cores are known.
  • An example or" such a magnetic switch is a coincidentecurrent switch.
  • a coincident-current switch is operated to produce a relatively large output voltage in response to a predetermined number of input signals.
  • a relatively small output voltage termed a noise voltage is produced in response to less than a predetermined number of input signals.
  • the noise signal is undesirable because in certain situations it may cause an ambiguity in the switch output.
  • the amplitude of this noise signal is a function of the rectangularity of the hysteresis curve defining the magnetic properties of the material. In general, the more nearly the hysteresis characteristic approaches the ideal rectangular shape, the more nearly the amplitude of the noise signal approaches zero value.
  • a relatively expensive rectangular type material whose hysteresis characteristic closely approximates the ideal rectangular shape has been employed in coincident-current magnetic switches.
  • Another object of the present invention is to provide an improved magnetic device by means of which magnetic switch material, whose hysteresis curve deviates substantially from the ideal rectangular shape, may be utilized.
  • a further object of the present invention is to provide a magnetic switching circuit by means of which noise voltages substantially cancel each other.
  • main cores which, for example, may be switch cores, and at least two dummy cores. Each core is biased to saturation in one direction.
  • Two different input windings are provided. Each of the input windings is linked to aswitch core and a diierent one of the dummy cores in the same sense. That is, an excitation current flowing in an input winding tends to drive the switch core and a dummy core toward saturation in a given direction.
  • An output winding links each of the dummy cores in one sense and the switch core in the opposite sense.
  • Fig. l is a schematic drawing of one arrangement of a magnetic switch according to the invention.
  • Fig. 2 is a schematic drawing of another embodiment of the present invention in a coincident-current matrix
  • Fig. 3 is a modified arrangement of the matrix of Fig. 2 employing a plurality of switch cores and only two dummy cores,
  • Fig. 4 is a schematic drawing illustrating the use of a plurality of magnetic cores whereby voltage cancellation is obtained in a magnetic matrix switch
  • Fig. 5 is a schematic drawing illustrating the use of a plurality of magnetic cores to obtain noise voltage cancellation in a magnetic memory array.
  • the magnetic elements 1 and 3 of the switch 1) are dummy cores, and the magnetic element 2 is a switch core.
  • the hysteresis characteristic of these cores may deviate from the ideal rectangular shape.
  • the cores conveniently, may be fabricated in a toroidal shape.
  • Each of the dummy cores is linked by at least three different coils.
  • the core l is linked by a bias coil 5', an input coil 7, and an output coil 17.
  • the core 3 is linked by a bias coil v5', an input coil 11', and an output coil 17.
  • the switch core 2 is linked by a bias coil 5', a iirst input coil 7', a second input coil 1l', and the outputcoil 17.
  • the relative senses of linkage of the different coils is indicated by a dot adjacent one or the other of its terminals.
  • Current flowing into a coil at a dot-marked terminal is arbitrarily assumed to pro- .duce a clockwise flux (as viewed in the drawing) in a core.
  • the input coils 7 are connected in series aiding relationship to form a iirst input winding 7.
  • rthe dotmar'ked terminal of the input coil 7 of the core l is connected to a rst current source 9.
  • the other terminal of the coil 7 of the core 1 is connected to the dot4 marked terminal of the coil 7 of the switch core
  • the unmarked terminal of the coil 7 of the switch core 2 is connected to ground.
  • the input coils 11 are connected in series aiding relationship to form a second inu put winding 11.
  • the dot-marked terminal of the input coil ⁇ 11 of the switch core 2 is connected to a current source 13.
  • the other terminal of the coil l1' of the switch core 2 is connected to the dot-marked terminal of the coil 11 of the core 3.
  • the other terminal of the coil 11 of the core 3 is connected to ground.
  • Both the current source 9 and the current source 13 may be comprised of a conventional electronic current source such asa vacuum tube which is selectively triggered by an input pulse.
  • the current sources 9 and 13 may be other magnetic cores.
  • the bias coils 5 are connected in series aiding relationship to form a bias winding 5 by connecting the unmarked terminal of a bias coil 5 of one core to vthe dot-marked terminal of the bias coil of the neXt core.
  • the dot-marked terminal of the bias coil 5' of the core 1 is connected to a current source such as a battery and a series connected resistor 12.
  • the unmarked terminal of the bias coil 5 of the core 3 is connected to ground.
  • the output coil 17' of the switch core 2. is connected in series opposition with the output coils 17 of the dummy cores 1 and 3 to form an output winding 17.
  • the dotmarked terminal of the output coil 17 of the core 1 is connected to an input of a utilization device 16.
  • the unmarked terminal of the output coil 17 of the core 1 is connected to the unmarked terminal of the output coil 17 of the switch core 2.
  • the dot-marked terminal of the output coil 17 of the switch core 2 is connected to the dot-marked terminal of the output coil 17' of the core 3.
  • the unmarked terminal of the output coil 17 of the core 3 is connected to the other input of the utilization device 16.
  • the utilization device 16 may be any device responsive to an output voltage induced in the output windings 17 by a substantial change of flux in the respective cores.
  • the switch core 2 and the dummy cores 1 and 3 are respectively biased to one direction of saturation by the D. C. current flowing in the bias winding 5.
  • the current flowing in the winding 5 produces a counterclockwise saturating flux in the respective cores.
  • an input signal in the form of a current pulse, is applied by the current source 9 to the first input winding 7.
  • the amplitude of this current pulse is regulated such that it is approximately one-half the amplitude required to overcome the D. C. bias and to produce a saturating ilux in the clockwise sense in the cores 1 and 2.
  • the polarity of each of these induced voltages is more positive at the dot-marked terminal of the respective output coils 17 of the cores 1 and 2. Consequently, the voltages in the output winding 17 substantially cancel each other due to the series opposition connection of the output coil 17' of the core 1 with the output coil 17' of the core 2.
  • an input signal in the form of a similar current pulse
  • the voltages induced in the output winding 17, by the clockwise changes of flux in the respective cores 2 and 3 substantially cancel each other.
  • an input signal is applied to either the lirst input winding 7 alone, or the second input winding 11 alone, there is a substantially complete cancellation of the voltages induced in the output winding 17.
  • the utilization device 16 may be easily arranged to discriminate between the relatively large, desired output voltage produced by the simultaneous occurrence of the two signals, and the Very small, or no, noise voltage produced by an individual one of the input signals.
  • the noise voltage induced in the output winding 17 by the presence of only one input signal is approximately of the same amplitude of the noise voltage caused by the air-pickup of extraneous voltages by the winding 17.
  • a similar voltage cancellation occurs in the output winding 17 when the input currents applied to the input windings 7 and 11 are terminated, and the bias current returns the cores to saturation in the one direction.
  • An advantage of the arrangement of the switch and dummy cores to provide voltage cancellation in the output winding is that, if desired, a full amplitude input signal can be applied to both input windings simultaneously.
  • the permissible tolerance in the amplitude of the input signal is larger than the permissible tolerance of the halfamplitude signals. Therefore, it is not necessaryy to regulate the full-amplitude signals as closely as the half-amplitude input signals.
  • the two opposite polarity voltages induced in the output winding 17 substantially cancel each other when a full amplitude input current is applied to only one of the input windings. Note, however, that in such case, the output voltage resulting from the simultaneous energization if both input windings is of a polarity opposite to that produced when the switch is operated by half-ampliture input signals.
  • a magnetic device comprising a coincident-current switch having four switch cores 2, two dummy cores 1, and two dummy cores 3.
  • the switch 26 is arranged in the form of a coincident-current matrix having two inputs which may, tor example, correspond to the rectangular coordinates X1 and X2, the two other, difterent inputs which may correspond to the coordinates Y1 and Y2.
  • One dummy core 3 is interposed between two adjacent switch cores 2 in each horizontal row, and a different dummy core is interposed between two adjacent switch cores 2 in each vertical column.
  • each dummy core compensates for the noise voltage generated by either one of two adjacent switch cores.
  • each core of the uppermost horizontal row as viewed in the drawing is linked by an input coil 21.
  • the input coils 21' are connected in series aiding relationship by connecting the unmarked terminal of the coil 21 of the switch core 2 at the XiYr intersect to the marked terminal of the coil 21 of the next core 3 of the row, and so on, to form an input winding 21.
  • the input winding Z1 is connected to a pulse source
  • Each core of the lowermost horizontal row is linked by an input coil 23.
  • the input coils Z3 are connected in series aiding relationsliip by connecting the unmarked terminal of the coil 23' of the switch core at the XzYl intersect to the marked terminal of the coil 23S of the next core 3, and so on, to form an input winding 23.
  • the input winding 23 is connected to a pulse source
  • Each core of the lettmost column is linked by an input coil 22.
  • the input coils 22 are connected in series aiding by connecting the unmarked terminal of one coil 22 to the marked terminal of the next succeeding coil 22', and so on, to form an input winding 22.
  • the input winding 22 is connected to a pulse source 40.
  • Each core of the rightmost column is linked by an input coil 24'.
  • the coils 24 are connected in series aiding relationship by connecting the unmarked terminal of one coil 24 to the marked terminal of the next succeeding coil 24', and so on, to form an input winding 24.
  • the input winding 24 is connected to a pulse source 41.
  • the pulse sources 38--41 may be any suitable device capable of furnishing a suitable current pulse, for example, an electron tube which is triggered by an input pulse applied to its control grid.
  • Each of the switch cores 2 is linked by one of the output coils 30-36 and each of the dummy cores is linked by a diierent pair of the output coils 30-36.
  • Four different output windings are provided. Each output winding corresponds to a diterent combination of X and Y input signals.
  • the output winding 30 connects the output coil 30 of the switch core 2 at the X1Y1 intersect and the output coil 30 of the adjacent dummy cores 1 and 3 in series opposition.
  • the output winding 32 connects the output coil 32 of the switch core 2 at the X2Y1 intersect and the output coil 32 of the adjacent dummy cores 1 and 3 in series opposition.
  • the output winding 36 connects the output coil 36' of the switch core 2 at the XiYi intersect and output coil 36 of the adjacent dummy cores 3 and 1 in series opposition.
  • the output winding 34 connects the output coil 34 of the switch core 2 at the XzYz intersect and the output coil 34 of the adjacent dummy cores 3 and 1 in series opposition.
  • Each of the cores is linked by a bias coil 28.
  • the bias coil 28 of each of the cores is connected in series aiding relationship by connecting the marked terminal of the bias coil 28' of one of the cores to the unmarked terminal of the bias coil 28 of the next succeeding core, and so on, to form the bias winding 28.
  • the bias winding 2S is connected to a D. C. current source such as a battery 25 and a series connected resistor 27. The direction of current flow in the various input windings and the bias winding is indicated by the respective arrows adjacent the individual windings.
  • One manner of operating the switching system, 20 may be as follows: a current flow in the bias winding 28 establishes a saturating flux in the counterclockwise sense in each of the cores of the swicth 2t).
  • the amplitude of the input current pulses applied to an individual one of the input windings 21-24 is regulated such that the resultant magnetizing force is insuilicient to produce a saturating iiux in the clockwise sense in any one of the cores.
  • the resultant magnetizing force exerted on the given core is suiiicient both to overcome the D. C. bias and to produce a saturating ilux in the clockwise sense in the given core.
  • a given switch core can be selected to furnish an output voltage by applying an excitation current to the two input windings which intersect 'in the given core.
  • a current pulse is furnished by the pulse source 38 to the input winding 21 and a current pulse is concurrently furnished by the pulse source 40 to the input winding 22.
  • the switch core 2 at the X1, Y1 intersect receives two, half-amplitude pulses, The resultant magnetizing force is suicient to produce a saturating flux in the clockwise sense in this core.
  • the adjacent dummy core 3 and the adjacent dummy core 1 each receive only a half-amplitude, current pulse and the magnetizing force exerted on these dummy cores is sufiicient to cause only a slight flux change in the clockwise sense. Due to the large ux change in the switch core 2 at the X1, Y1 intersect, a relatively large, output voltage is induced in the output wind- Again, the amplitude of this output voltage is reduced somewhat because of the relatively slight ux changes in the adjacent dummy cores 1 and 3. The current pulse in the input winding 21 produces a slight flux change in the switch core 2 at the X1, Y2 intersect and the adjacent dummy core 3. However, as described previously, the voltages induced thereby in the output winding 36 substantially cancel each other.
  • the current pulse in the winding 22 produces a slight llux change in the switch core 2 at the X2, Y1 intersect and the adjacent dummy core 1.
  • the output voltages induced in the output winding 32 by the slight linx changes in the switch and dummy cores also substantially cancel each other. Therefore, only the output winding 3) is selected to have an output voltage induced therein when the pulse sources 38 and v40 are energized at any one time. There is substantially no voltage induced in any of the remaining output windings. Consequently, the arrangement or the switch cores 2 and the dummy cores i and 3 provide a switching system which is substantially free of unwanted noise signals.
  • each dummy core is arranged in a noise-cancelling relationship with two adjacent switch cores.
  • the switch and dummy cores may be arranged in an array having a plurality of switch cores and only two dummy cores. For example, in the 2 x 2 array 33 ot Fig. 3, there are four switch cores 2 and two similar dummy cores and 3.
  • Each switch core 2 has two different input coils, an output coil and a bias coil (not shown).
  • Each dummy core has two different input coils, four different output coils and a bias coil (not shown).
  • the four different output windings are formed by connecting the output coil of each switch core in series opposition with a respective one of the output coils of each of the dummy cores. T he operation of the switch array 33 is similar to the operation of the switch array 20 previously described. It is apparent that a noise voltage produced by the two non-selected switch cores is cancelled in the respective two output windings by the equal amplitude and opposite polarity voltage induced in the output windings by the dummy core Il and the dummy core 3, respectively. Note, however, that in the arrangement of Fig. 3, each dummy core is linked by seven coils including the bias coil.
  • each ⁇ dune-ny core would be linked by thirteen different coils, i. c. four input coils, eight output coils and a bias coil.
  • the switch and dummy cores are often made small in order to reduce the driving current requirements, but the switch cores need not be of the same size as the dummy cores.
  • the arrangement of the array of Fig. 2, in which each dummy core is used to cancel the noise voltage produced oy a pair of switch cores, is presently preferred. However, other arrangements are useful.
  • the array illustrated in Fig. 2 is for the purpose of description only.
  • Other arrays such as rectangular or hexagonal arrays in accordance with the invention may be employed to provide a substantially noise free switch- 7 ing system.
  • the respective output windings may be arranged to link two different dummy cores ⁇ and one switch core for each row and column position of the array; each different input winding is then arranged to link both the switch and the dummy cores of the different rows, and the switch and dummy cores of the diferent columns.
  • the 2x2 array can be expanded into a larger', n x m array, where nm.
  • a particular one of the rz x m switch cores is selected by energizing the one n input winding and the one m input winding which intersect in the core.
  • the 4 x 4 array 5t) of Fig. 4 is comprised of an arrangement of four different 2 x 2 switching arrays 2'@ of Fig. 2.
  • the switch array 5@ has i6 different outputs; four outputs being associated with each of the switches 2G.
  • a different one of the row input windings 2l, 23, is used to represent an X coordinate and a different one of the column input windings 22, 24 is used to represent a Y coordinate.
  • Energization of the input windings is controlled by a separate 'one of the pulse sources 38, 39 and a separate one of the pulse sources 4t), di.
  • the input windings 21 and 25 are respectively extended to connect the input coils 2l and 23 of each of the switch and dummy cores located in alternate horizontal rows.
  • the input windings 22 and 24 are respectively extended to connect the input coils 22 and 24' of each of the switch and dummy cores located in alternate vertical columns.
  • a bias winding (not shown) is connected to the bias coils 28 of all the cores of the array in series in the manner described for the connection of the bias winding 2S of Fig. 2.
  • Each of the cores is biased by a current flow in the bias winding 2S in a given direction of saturation.
  • a particular one of the sixteen different output windings may be selected by energizing the one X input winding 21, 23 and the one Y input winding 22, 2d which intersect in the switch core which is linked by the desired output winding.
  • each output winding which links a switch core in the selected row and column also links, either a dummy core of the selected row, or a dummy core of the selected column in series opposition. Consequently, when a partcular one of the output windings is thus selected, there is substantially no output voltage induced in any of the remaining output windings which link the switch cores of the selected row and column.
  • Fig. 5 is a schematic diagram of an arrangement of a memory system 6d which includes a two-dimensional array 62 of memory cores 52, each said memory core 52 associated therewith having a pair of dummy cores 54 and S6.
  • the memory system 60 is similar to although of smaller capacity than the memory system described in Pat. No. 2,691,156 issued October 5, 1954, to Julian Salta and Charles S. Warren entitled Magnetic Memory Reading System but modified in accordance with the present invention.
  • a magnetic switch 64 has a plurality of row input windings 66 connected thereto, and a magnetic switch 6% has a plurality of column input windings tl connected thereto.
  • a magnetic register 72 which has a plurality of output windings 74 of the array 62 connected thereto.
  • An interrogation source 76 l is adapted to furnish current pulses to the winding 7S which is connected to the register 72.
  • a utilization device 8@ is connected to the register 72 by the winding S2. rThe device 89 is responsive to the output pulses furnished by the register 72.
  • the arrangement of the center of the array 62 is shown broken away to illustrate the manner of connecting two memory cores 52 and their associated dummy cores 5d and 56 to the respective input windings 66, 7d, and one output winding '74.
  • Each of the row input windings 66 is linked to all the memory cores 52 and the dummy cores 54 of a different row.
  • Each of the column input windings is linked to all the memory cores S2 and the dummy cores 56 of a different column.
  • Each of the output windings 74 links, in series opposition, a like number of memory cores 52 and the one row and the one column dummy core S/-l and 56 which are adjacent each memory core so linked.
  • the arrows show the direction of positive current ow.
  • Fig. 4 is similar to the memory system shown in Fig. 2 of the above-mentioned patent modified by the addition of the dummy cores 54 and 56, and by the manner of linking each of the output windings to a group of memory cores 52 and their respectively adjacent dummy cores 54 and 56.
  • the operation of the memory system of Fig. 4 is as follows: only one horizontal row winding 66 and only one vertical column winding 70 is excited at any one time by the respective magnetic switches 64 and 63.
  • Information is stored in the memory cores 52 in binary fashion. That is, a memory core 52 is driven to saturation at one polarity, for example, P to represent one binary digit and is driven to saturation at the opposite polarity or N, to represent a second binary digit.
  • Current is applied to the one row winding and the one column winding which are coupled to a memory core whose saturation polarity it is desired to change.
  • the amplitude of the currents applied to the selected row winding and the selected column winding is about half of that required to drive the selected memory core 52 from saturation at polarity N to saturation at polarity P. Only the selected memory core 52 receives a full amplitude driving current. The remaining memory cores 52 and the dummy cores 54 and 56 which are linked either to the selected row winding alone or to the selected column winding alone receive only half the required excitation, and therefore, do not change their remanent condition.
  • the dummy cores 52 and 56 can be set to one polarity of saturation, for example, N as a fabrication step.
  • each of the dummy cores is linked by only one input winding and the amplitude of the input current pulse is regulated, the dummy cores remain at the remanent N polarity.
  • information stored in any particular one of the memory cores 52 is read out by exciting this core to the l polarity. If the core 52 is already at polarity P, substantially no change occurs in its magnetic condition and no voltage is induced in the output winding coupled thereto. If, however, the core S2 is at polarity N, a large voltage is induced in the coupled output winding. This large output voltage is sufficient to turn over the register core which is coupled to the output winding 74.
  • a current pulse is applied to the winding 73 of the register 72 by the interrogation source 76. lf the register core was turned over, a rela tively large output voltage is induced in the winding 82. Conversely, if the register core was not turned over, a relatively small, or no output voltage is induced in the winding $2. Note, that when the memory core 52 is at polarity P, there is a small change in its magnetic condition. The resulting voltage which is induced in the coupled output winding 74, by the memory core 52 is substantially cancelled due to the opposite voltage which is induced in the same output winding 74 by the adjacent dummy cores 54 and 56.
  • the remaining memory and dummy cores which are coupled to the selected row and column windings also have their magnetic condition altered due to the half-amplitude excitation current pulses.
  • the output voltages induced in the respective output windings which are coupled to the half excitated memory cores and dummy cores are also cancelled due to the equal and opposite excursion in the magnetic condition of the respectively coupled dummy cores.
  • the net output voltage, if any, which is induced in the coupled output winding 74 of a selected memory core 52 is of a polarity which tends to drive the register core further into saturation. Therefore, the information read-out of the memory array is unambiguous.
  • the main and dummy cores of the present invention may be comprised of a lower grade rectangular material than was heretofore practical. Also, the present invention furnishes an improved magnetic switch in which relatively less expensive magnetic material may be employed in fabricating the cores. lt will be apparent to those skilled in the art that the embodiments of the present invention in a coincident-current switch are illustrative only, and other arrangements of the main and dummy cores in a combinatorial switch may be employed.
  • a magnetic device comprising a main magnetic element and two dummy magnetic elements, iirst input coil means linking said main and one of said dummy elements, second input coil means linking said main and the other of said dummy elements, bias coil means linking each of said elements, output coil means linking each of said elements, separate means respectively connecting said iirst input coil means, said second input coil means, and said bias coils each in series aiding relationship, and means connecting said output coil means of said main element in series opposition with each of said output coil means of said dummy elements.
  • a magnetic device as recited in claim l including means for applying a D. C. current to said means connecting said bias coil means for producing a saturating 'linx in a given sense in each of said elements, and means for selectively applying an input signal to said means connecting said first and second input means.
  • a magnetic switch comprising a plurality of magnetic elements capable of being saturated with flux in one or the other of two senses, said elements including a plurality of groups of switch elements and a plurality of dummy elements, first and second input coil means linked to each of said switch elements, first input coil means linked to certain ones of said dummy elements, second input coil means linked to the remaining ones of said dummy elements, bias coil means linked to each of said elements, separate means alternately connecting said first input coil means of each of said groups of switch elements and said rst input coil means of said dummy elements in series aiding relationship, separate means alternately connecting said second input coil means of each of said groups of switch elements and said second input coil means of said dummy elements in series aiding relationship, means connecting said bias coil means in series aiding relationship, output coil means linked to each of said elements, and means connecting the output coil means of each switch element of a group in series opposition with the output coil means of one said dummy element having a first input coil means and another said dummy element having a second input coil means
  • each of said dummy elements is linked by at least two different output coil means.
  • a magnetic switch comprising a plurality of magnetic switch elements and a plurality of dummy elements, said switch elements being arranged in electrical correspondence with the elements of a geometrical array arranged in rows and columns, a diierent one of said dummy elements being interposed respectively between each two switch elements corresponding to a row and each two switch elements corresponding to a column, a plurality of iirst input coils each different one linked to all the elements corresponding to an individual row, a plurality of second input coils each different one linked to all the elements corresponding to an individual column, a plurality of bias coils each different one linked to a different element, a plurality of output coils each of said eiements being linked by at least one output coil, means connecting said output coil of each switch element corresponding to the array element located at each row and column intersection in series opposition with said output coils of a pair of dummy elements, each dummy element of said pair being respectively adjacent the switch element at a respective row and column intersection.
  • a magnetic switch comprising a plurality of magnetic elements capable of being saturated with luX in one or the other of two senses, said elements including switch elements and dummy elements, said elements being arranged in electrical correspondence with the elements of a geometrical array arranged in rows and columns, a dummy element interposed between each two switch elements of a row and a different dummy element interposed between each two switch elements of a column, a rst input coil means linking each of the elements of a row, a second input coil means linking each of the elements of column, a bias coil means linking each of said elements, an output coil means linking each of said switch elements, two diiierent output coil means linking each of said dummy elements, separate means connecting the tirst input coil means of each row of elements in series aiding relationship, separate means connecting the second input coil means of each column of elements in series aiding relationship, means connecting the bias coil means of each of said elements in series aiding relationship, separate means connecting the output coil means of a switch element at each row and column intersection in series opposition with
  • a magnetic switch comprising switch elements and at least two dummy elements, at least two input coil means, a bias coil means, and an output coil means linked to each of said switch elements, a plurality of input coil means, a plurality of output coil means, and a bias coil means linked to each of said dummy elements, means connecting each of said bias coil means in series aiding relationship, means connecting one of said input coil means of a iirst group of switch elements in series aiding relationship respectively with an input coil means of a first dummy element, means individually connecting the output coil means of each of said iirst group of switch elements in series opposition with an output coil means of said first dummy element, means connecting the other of said input coil means of a second group of switch elements in series aiding relationship respectively with an input coil means of a second one of said dummy elements, and means individually connecting the output coil means of each of said second group of switch elements in series opposition with an output coil means of said second dummy element.

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Description

Feb. 7, 1956 Filed Oct. 28, 1954 Cl/@EN 7' SOURCE C. S. WARREN MAGNETIC SWITCH UNL/[1770# 2 Sheets-Sheet l PULSE 50K/KCE /A/ VEN TOR CMR/ is 5, WHR/mv /77' TURA/Ey Feb. 7, 1956 c. s. WARREN MAGNETIC SWITCH Filed Oct. 28, '1954 2 Sheets-Sheet 2 Edifici 50K/iff SUL/KCE United States Patent MAGNETIC SWITCH Charles S. Warren, Collingswood, N. J., assgnor to Radio Corporation of America, a corporation or' Deiaware Application October 28, 1954, Serial No. 465,347
Claims. (Cl. 340-166) This invention relates to magnetic devices, and particularly to noise-cancellation in such devices.
Magnetic switches and memories employing magnetic cores are known. An example or" such a magnetic switch is a coincidentecurrent switch. A coincident-current switch is operated to produce a relatively large output voltage in response to a predetermined number of input signals. In practice, a relatively small output voltage termed a noise voltage is produced in response to less than a predetermined number of input signals. The noise signal is undesirable because in certain situations it may cause an ambiguity in the switch output. The amplitude of this noise signal is a function of the rectangularity of the hysteresis curve defining the magnetic properties of the material. In general, the more nearly the hysteresis characteristic approaches the ideal rectangular shape, the more nearly the amplitude of the noise signal approaches zero value. Heretofore, a relatively expensive rectangular type material whose hysteresis characteristic closely approximates the ideal rectangular shape has been employed in coincident-current magnetic switches.
It is advantageous to utilize a relatively less expensive magnetic material whose hysteresis characteristic deviates from the ideal rectangular shape. Even in the case of rectangular material, however, the cores produce some noise Avoltage when one of the switch cores is selected. It is also desirable to be able to cancel the noise voltage produced by cores fabricated from rectangular material.
It is an object of the present invention lto -provide a coincident-current magnetic switch by means of which a relatively high signal-to-noise ratio can be obtained.
Another object of the present invention is to provide an improved magnetic device by means of which magnetic switch material, whose hysteresis curve deviates substantially from the ideal rectangular shape, may be utilized.
A further object of the present invention is to provide a magnetic switching circuit by means of which noise voltages substantially cancel each other.
The above and further objects of the vpresent invention are carried out by providing one or more main cores which, for example, may be switch cores, and at least two dummy cores. Each core is biased to saturation in one direction. Two different input windings are provided. Each of the input windings is linked to aswitch core and a diierent one of the dummy cores in the same sense. That is, an excitation current flowing in an input winding tends to drive the switch core and a dummy core toward saturation in a given direction. An output winding links each of the dummy cores in one sense and the switch core in the opposite sense. Accordingly, when an excitation current is applied to only one input winding, the voltages induced in the output winding by the one dummy and the switch core are substantially equal and opposite. Thus, a voltage cancellation occurs in the out- ,put winding. When an excitation current is applied at the same vtime to both input windings, the switch core is rice driven `to saturation in the given direction, while each of the dummy cores is only partially driven toward saturation in the Vgiven direction. Therefore, a relatively large output voltage is induced in the output winding. Likewise, a similar voltage cancellation occurs when the excitation currents are -removed and the bias returns each of the cores to saturation in the one direction opposite to the given direction of saturation.
Various embodiments of the magnetic devices according to the invention are described herein. The invention will be more fully understood, both as to its organization and method of operation, from the following detailed description when read in connection with the accompanying drawing in which;
Fig. l is a schematic drawing of one arrangement of a magnetic switch according to the invention,
Fig. 2 is a schematic drawing of another embodiment of the present invention in a coincident-current matrix,
Fig. 3 is a modified arrangement of the matrix of Fig. 2 employing a plurality of switch cores and only two dummy cores,
Fig. 4 is a schematic drawing illustrating the use of a plurality of magnetic cores whereby voltage cancellation is obtained in a magnetic matrix switch, and
Fig. 5 is a schematic drawing illustrating the use of a plurality of magnetic cores to obtain noise voltage cancellation in a magnetic memory array.
Throughout the drawings like elements will be designated by like reference numerals. With reference to Fig. l, the magnetic elements 1 and 3 of the switch 1) are dummy cores, and the magnetic element 2 is a switch core. The hysteresis characteristic of these cores may deviate from the ideal rectangular shape. There is a nonlinear variation of the magnetic induction produced in a core with respect to the magnetizing force applied to the core. The cores, conveniently, may be fabricated in a toroidal shape. Each of the dummy cores is linked by at least three different coils. The core lis linked by a bias coil 5', an input coil 7, and an output coil 17. The core 3 is linked by a bias coil v5', an input coil 11', and an output coil 17. The switch core 2 is linked by a bias coil 5', a iirst input coil 7', a second input coil 1l', and the outputcoil 17. The relative senses of linkage of the different coils is indicated by a dot adjacent one or the other of its terminals. Current flowing into a coil at a dot-marked terminal is arbitrarily assumed to pro- .duce a clockwise flux (as viewed in the drawing) in a core. Current ilowing out of a coil from a dot-marked terminal, then, produces a counter-clockwise iiux in the core. The input coils 7 are connected in series aiding relationship to form a iirst input winding 7. rthe dotmar'ked terminal of the input coil 7 of the core l is connected to a rst current source 9. The other terminal of the coil 7 of the core 1 is connected to the dot4 marked terminal of the coil 7 of the switch core The unmarked terminal of the coil 7 of the switch core 2 is connected to ground. The input coils 11 are connected in series aiding relationship to form a second inu put winding 11. The dot-marked terminal of the input coil `11 of the switch core 2 is connected to a current source 13. The other terminal of the coil l1' of the switch core 2 is connected to the dot-marked terminal of the coil 11 of the core 3. The other terminal of the coil 11 of the core 3 is connected to ground. Both the current source 9 and the current source 13 may be comprised of a conventional electronic current source such asa vacuum tube which is selectively triggered by an input pulse. Alternatively, the current sources 9 and 13 may be other magnetic cores. The bias coils 5 are connected in series aiding relationship to form a bias winding 5 by connecting the unmarked terminal of a bias coil 5 of one core to vthe dot-marked terminal of the bias coil of the neXt core. The dot-marked terminal of the bias coil 5' of the core 1 is connected to a current source such as a battery and a series connected resistor 12. The unmarked terminal of the bias coil 5 of the core 3 is connected to ground.
The output coil 17' of the switch core 2. is connected in series opposition with the output coils 17 of the dummy cores 1 and 3 to form an output winding 17. The dotmarked terminal of the output coil 17 of the core 1 is connected to an input of a utilization device 16. The unmarked terminal of the output coil 17 of the core 1 is connected to the unmarked terminal of the output coil 17 of the switch core 2. The dot-marked terminal of the output coil 17 of the switch core 2 is connected to the dot-marked terminal of the output coil 17' of the core 3. The unmarked terminal of the output coil 17 of the core 3 is connected to the other input of the utilization device 16. The utilization device 16 may be any device responsive to an output voltage induced in the output windings 17 by a substantial change of flux in the respective cores.
ln accordance with the convention heretofore adopted, it is assumed that a change of flux in the clockwise sense in a core induces a voltage in its output coil 17 such as to make the dot-marked terminal more positive than the unmarked terminal. The direction of current (conventional) in the input windings 7 and 11 is considered to flow from the respective current sources 9 and 13 to ground indicated by the respective arrows. The direction of current flow in the bias winding 5 is from the positive terminal of the battery 15 to ground as indicated by the arrow adjacent the winding 5.
ln operation, the switch core 2 and the dummy cores 1 and 3 are respectively biased to one direction of saturation by the D. C. current flowing in the bias winding 5. The current flowing in the winding 5 produces a counterclockwise saturating flux in the respective cores. Assume, now, that an input signal, in the form of a current pulse, is applied by the current source 9 to the first input winding 7. The amplitude of this current pulse is regulated such that it is approximately one-half the amplitude required to overcome the D. C. bias and to produce a saturating ilux in the clockwise sense in the cores 1 and 2. The tiux changes, produced in the respective cores 1 and 2 by the current in the winding '7 each induce a voltage of substantially the same amplitude in the output winding 17. The polarity of each of these induced voltages is more positive at the dot-marked terminal of the respective output coils 17 of the cores 1 and 2. Consequently, the voltages in the output winding 17 substantially cancel each other due to the series opposition connection of the output coil 17' of the core 1 with the output coil 17' of the core 2. Likewise, when an input signal, in the form of a similar current pulse, is applied to the input winding 11 by the source 13, the voltages induced in the output winding 17, by the clockwise changes of flux in the respective cores 2 and 3, substantially cancel each other. Thus, if an input signal is applied to either the lirst input winding 7 alone, or the second input winding 11 alone, there is a substantially complete cancellation of the voltages induced in the output winding 17.
Assume, now, that during the same time interval, a halt-amplitude, current pulse is applied by the current source 9 and the current source 13 to the respective input windings 7 and 11. The maguetizing force exerted on the switch core 2 which results from the half-amplitude, current pulse applied to the winding 7 and the halfamplitude, current pulse applied to the winding 11, reaches a plateau during the time interval and produces a saturating lux in the clockwise sense. This relatively large change of ilux, from saturation in the counterclockwise sense to saturation in the clockwise sense, induces a correspondingly large output voltage in the output winding 17. The relatively small changes of flux, resulting from a partial reduction of saturation in the counterclockwise sense in the dummy cores 1 and 3, induce correspondingly small amplitude, output voltages in the output winding 17. The polarity of these small, output voltages is opposite to the polarity of the large, output voltage. Thus, the amplitude of the large, output voltage furnished by the switch core 2, is somewhat decreased. However, in actual practice, the resultant large, output voltage induced in the output winding 17 when both input signals are present at the same time, is in the order of 2li or more times greater than the resultant voltage induced in the output winding 17 when only one of the input signals is present. Thus, the utilization device 16 may be easily arranged to discriminate between the relatively large, desired output voltage produced by the simultaneous occurrence of the two signals, and the Very small, or no, noise voltage produced by an individual one of the input signals. In speciic instances, Where the magnetic characteristics of the switch and dummy cores are substantially matched, the noise voltage induced in the output winding 17 by the presence of only one input signal is approximately of the same amplitude of the noise voltage caused by the air-pickup of extraneous voltages by the winding 17. A similar voltage cancellation occurs in the output winding 17 when the input currents applied to the input windings 7 and 11 are terminated, and the bias current returns the cores to saturation in the one direction.
An advantage of the arrangement of the switch and dummy cores to provide voltage cancellation in the output winding is that, if desired, a full amplitude input signal can be applied to both input windings simultaneously. The permissible tolerance in the amplitude of the input signal is larger than the permissible tolerance of the halfamplitude signals. Therefore, it is not necesary to regulate the full-amplitude signals as closely as the half-amplitude input signals. For example, when the response characteristics of the switch and dummy cores are nearly matched, the two opposite polarity voltages induced in the output winding 17 substantially cancel each other when a full amplitude input current is applied to only one of the input windings. Note, however, that in such case, the output voltage resulting from the simultaneous energization if both input windings is of a polarity opposite to that produced when the switch is operated by half-ampliture input signals.
In Fig. 2, there is provided a magnetic device comprising a coincident-current switch having four switch cores 2, two dummy cores 1, and two dummy cores 3. The switch 26 is arranged in the form of a coincident-current matrix having two inputs which may, tor example, correspond to the rectangular coordinates X1 and X2, the two other, difterent inputs which may correspond to the coordinates Y1 and Y2. One dummy core 3 is interposed between two adjacent switch cores 2 in each horizontal row, and a different dummy core is interposed between two adjacent switch cores 2 in each vertical column. In the arrangement of Fig. 2, each dummy core compensates for the noise voltage generated by either one of two adjacent switch cores.
lEach core of the uppermost horizontal row as viewed in the drawing) is linked by an input coil 21. The input coils 21' are connected in series aiding relationship by connecting the unmarked terminal of the coil 21 of the switch core 2 at the XiYr intersect to the marked terminal of the coil 21 of the next core 3 of the row, and so on, to form an input winding 21. The input winding Z1 is connected to a pulse source Each core of the lowermost horizontal row is linked by an input coil 23. The input coils Z3 are connected in series aiding relationsliip by connecting the unmarked terminal of the coil 23' of the switch core at the XzYl intersect to the marked terminal of the coil 23S of the next core 3, and so on, to form an input winding 23. The input winding 23 is connected to a pulse source Each core of the lettmost column is linked by an input coil 22. The input coils 22 are connected in series aiding by connecting the unmarked terminal of one coil 22 to the marked terminal of the next succeeding coil 22', and so on, to form an input winding 22. The input winding 22 is connected to a pulse source 40. Each core of the rightmost column is linked by an input coil 24'. The coils 24 are connected in series aiding relationship by connecting the unmarked terminal of one coil 24 to the marked terminal of the next succeeding coil 24', and so on, to form an input winding 24. The input winding 24 is connected to a pulse source 41. The pulse sources 38--41 may be any suitable device capable of furnishing a suitable current pulse, for example, an electron tube which is triggered by an input pulse applied to its control grid.
Each of the switch cores 2 is linked by one of the output coils 30-36 and each of the dummy cores is linked by a diierent pair of the output coils 30-36. Four different output windings are provided. Each output winding corresponds to a diterent combination of X and Y input signals. The output winding 30 connects the output coil 30 of the switch core 2 at the X1Y1 intersect and the output coil 30 of the adjacent dummy cores 1 and 3 in series opposition. The output winding 32 connects the output coil 32 of the switch core 2 at the X2Y1 intersect and the output coil 32 of the adjacent dummy cores 1 and 3 in series opposition. The output winding 36 connects the output coil 36' of the switch core 2 at the XiYi intersect and output coil 36 of the adjacent dummy cores 3 and 1 in series opposition. The output winding 34 connects the output coil 34 of the switch core 2 at the XzYz intersect and the output coil 34 of the adjacent dummy cores 3 and 1 in series opposition. Each of the cores is linked by a bias coil 28. The bias coil 28 of each of the cores is connected in series aiding relationship by connecting the marked terminal of the bias coil 28' of one of the cores to the unmarked terminal of the bias coil 28 of the next succeeding core, and so on, to form the bias winding 28. The bias winding 2S is connected to a D. C. current source such as a battery 25 and a series connected resistor 27. The direction of current flow in the various input windings and the bias winding is indicated by the respective arrows adjacent the individual windings.
One manner of operating the switching system, 20 may be as follows: a current flow in the bias winding 28 establishes a saturating flux in the counterclockwise sense in each of the cores of the swicth 2t). The amplitude of the input current pulses applied to an individual one of the input windings 21-24 is regulated such that the resultant magnetizing force is insuilicient to produce a saturating iiux in the clockwise sense in any one of the cores. However, when two different such current pulses are applied simultaneously to the respective two input windings of any given one of the cores, the resultant magnetizing force exerted on the given core is suiiicient both to overcome the D. C. bias and to produce a saturating ilux in the clockwise sense in the given core.
Assume, now, that a current pulse is applied by the pulse source 38 to the input winding 21. This current pulse causes a magnetizing force in the clockwise sense in each of the cores linked by the coils 21. The change of ux in the switch core 2 at the XiYi intersect and the adjacent dummy core 3 each induce an output voltage of substantially the same amplitude in the output winding 30. However, due to the series opposition connection of the output winding 30, the two voltages are of opposite polarity and, therefore cancel. Likewise, there are two equal amplitude and opposite polarity voltages induced in the output winding 36 by the change of flux in the switch core 2 at the X1Y2 intersect and the adjacent dummy core 3. These two voltages also cancel in the output winding 36 because of its series opposition connection. Consequently, there is substantially no output voltage induced in any output winding when an excitation currentis applied Vto only a single one of the input windings.
` ing 30.
A given switch core can be selected to furnish an output voltage by applying an excitation current to the two input windings which intersect 'in the given core. Thus, for example, assume that a current pulse is furnished by the pulse source 38 to the input winding 21 and a current pulse is concurrently furnished by the pulse source 40 to the input winding 22. Accordingly, only the switch core 2 at the X1, Y1 intersect receives two, half-amplitude pulses, The resultant magnetizing force is suicient to produce a saturating flux in the clockwise sense in this core. The adjacent dummy core 3 and the adjacent dummy core 1 each receive only a half-amplitude, current pulse and the magnetizing force exerted on these dummy cores is sufiicient to cause only a slight flux change in the clockwise sense. Due to the large ux change in the switch core 2 at the X1, Y1 intersect, a relatively large, output voltage is induced in the output wind- Again, the amplitude of this output voltage is reduced somewhat because of the relatively slight ux changes in the adjacent dummy cores 1 and 3. The current pulse in the input winding 21 produces a slight flux change in the switch core 2 at the X1, Y2 intersect and the adjacent dummy core 3. However, as described previously, the voltages induced thereby in the output winding 36 substantially cancel each other. Also, the current pulse in the winding 22 produces a slight llux change in the switch core 2 at the X2, Y1 intersect and the adjacent dummy core 1. Likewise, the output voltages induced in the output winding 32 by the slight linx changes in the switch and dummy cores also substantially cancel each other. Therefore, only the output winding 3) is selected to have an output voltage induced therein when the pulse sources 38 and v40 are energized at any one time. There is substantially no voltage induced in any of the remaining output windings. Consequently, the arrangement or the switch cores 2 and the dummy cores i and 3 provide a switching system which is substantially free of unwanted noise signals.
Vln the array of switch and dummy cores of Fig. 2, each dummy core is arranged in a noise-cancelling relationship with two adjacent switch cores. The switch and dummy cores may be arranged in an array having a plurality of switch cores and only two dummy cores. For example, in the 2 x 2 array 33 ot Fig. 3, there are four switch cores 2 and two similar dummy cores and 3. Each switch core 2 has two different input coils, an output coil and a bias coil (not shown). Each dummy core has two different input coils, four different output coils and a bias coil (not shown). The four different output windings are formed by connecting the output coil of each switch core in series opposition with a respective one of the output coils of each of the dummy cores. T he operation of the switch array 33 is similar to the operation of the switch array 20 previously described. it is apparent that a noise voltage produced by the two non-selected switch cores is cancelled in the respective two output windings by the equal amplitude and opposite polarity voltage induced in the output windings by the dummy core Il and the dummy core 3, respectively. Note, however, that in the arrangement of Fig. 3, each dummy core is linked by seven coils including the bias coil. ln a 4 array using only two dummy cores, each `dune-ny core would be linked by thirteen different coils, i. c. four input coils, eight output coils and a bias coil. ln practice, the switch and dummy cores are often made small in order to reduce the driving current requirements, but the switch cores need not be of the same size as the dummy cores. The arrangement of the array of Fig. 2, in which each dummy core is used to cancel the noise voltage produced oy a pair of switch cores, is presently preferred. However, other arrangements are useful.
The array illustrated in Fig. 2 is for the purpose of description only. Other arrays such as rectangular or hexagonal arrays in accordance with the invention may be employed to provide a substantially noise free switch- 7 ing system. In such case, the respective output windings may be arranged to link two different dummy cores` and one switch core for each row and column position of the array; each different input winding is then arranged to link both the switch and the dummy cores of the different rows, and the switch and dummy cores of the diferent columns. In View of the description of the switching system 2t) of Fig. 2, it is now apparent that the 2x2 array can be expanded into a larger', n x m array, where nm. In such case, a particular one of the rz x m switch cores is selected by energizing the one n input winding and the one m input winding which intersect in the core. For example, the 4 x 4 array 5t) of Fig. 4 is comprised of an arrangement of four different 2 x 2 switching arrays 2'@ of Fig. 2. The switch array 5@ has i6 different outputs; four outputs being associated with each of the switches 2G. A different one of the row input windings 2l, 23, is used to represent an X coordinate and a different one of the column input windings 22, 24 is used to represent a Y coordinate. Energization of the input windings is controlled by a separate 'one of the pulse sources 38, 39 and a separate one of the pulse sources 4t), di. The input windings 21 and 25 are respectively extended to connect the input coils 2l and 23 of each of the switch and dummy cores located in alternate horizontal rows. The input windings 22 and 24 are respectively extended to connect the input coils 22 and 24' of each of the switch and dummy cores located in alternate vertical columns. A bias winding (not shown) is connected to the bias coils 28 of all the cores of the array in series in the manner described for the connection of the bias winding 2S of Fig. 2. Each of the cores is biased by a current flow in the bias winding 2S in a given direction of saturation. A particular one of the sixteen different output windings may be selected by energizing the one X input winding 21, 23 and the one Y input winding 22, 2d which intersect in the switch core which is linked by the desired output winding. As described in connection with Fig. 2, each output winding which links a switch core in the selected row and column also links, either a dummy core of the selected row, or a dummy core of the selected column in series opposition. Consequently, when a partcular one of the output windings is thus selected, there is substantially no output voltage induced in any of the remaining output windings which link the switch cores of the selected row and column.
The principle of the present invention may be employed in other magnetic devices where it is desired to have a substantially noise-free output signal. For example, Fig. 5 is a schematic diagram of an arrangement of a memory system 6d which includes a two-dimensional array 62 of memory cores 52, each said memory core 52 associated therewith having a pair of dummy cores 54 and S6. The memory system 60 is similar to although of smaller capacity than the memory system described in Pat. No. 2,691,156 issued October 5, 1954, to Julian Salta and Charles S. Warren entitled Magnetic Memory Reading System but modified in accordance with the present invention. ln Fig. 5, a magnetic switch 64 has a plurality of row input windings 66 connected thereto, and a magnetic switch 6% has a plurality of column input windings tl connected thereto. There is also provided a magnetic register 72 which has a plurality of output windings 74 of the array 62 connected thereto. An interrogation source 76 lis adapted to furnish current pulses to the winding 7S which is connected to the register 72. A utilization device 8@ is connected to the register 72 by the winding S2. rThe device 89 is responsive to the output pulses furnished by the register 72. The arrangement of the center of the array 62 is shown broken away to illustrate the manner of connecting two memory cores 52 and their associated dummy cores 5d and 56 to the respective input windings 66, 7d, and one output winding '74. Each of the row input windings 66 is linked to all the memory cores 52 and the dummy cores 54 of a different row. Each of the column input windings is linked to all the memory cores S2 and the dummy cores 56 of a different column. Each of the output windings 74 links, in series opposition, a like number of memory cores 52 and the one row and the one column dummy core S/-l and 56 which are adjacent each memory core so linked. The arrows show the direction of positive current ow. It is apparent that the memory system of Fig. 4 is similar to the memory system shown in Fig. 2 of the above-mentioned patent modified by the addition of the dummy cores 54 and 56, and by the manner of linking each of the output windings to a group of memory cores 52 and their respectively adjacent dummy cores 54 and 56.
The operation of the memory system of Fig. 4 is as follows: only one horizontal row winding 66 and only one vertical column winding 70 is excited at any one time by the respective magnetic switches 64 and 63. Information is stored in the memory cores 52 in binary fashion. That is, a memory core 52 is driven to saturation at one polarity, for example, P to represent one binary digit and is driven to saturation at the opposite polarity or N, to represent a second binary digit. Current is applied to the one row winding and the one column winding which are coupled to a memory core whose saturation polarity it is desired to change. The amplitude of the currents applied to the selected row winding and the selected column winding is about half of that required to drive the selected memory core 52 from saturation at polarity N to saturation at polarity P. Only the selected memory core 52 receives a full amplitude driving current. The remaining memory cores 52 and the dummy cores 54 and 56 which are linked either to the selected row winding alone or to the selected column winding alone receive only half the required excitation, and therefore, do not change their remanent condition. The dummy cores 52 and 56 can be set to one polarity of saturation, for example, N as a fabrication step. Because, each of the dummy cores is linked by only one input winding and the amplitude of the input current pulse is regulated, the dummy cores remain at the remanent N polarity. information stored in any particular one of the memory cores 52 is read out by exciting this core to the l polarity. If the core 52 is already at polarity P, substantially no change occurs in its magnetic condition and no voltage is induced in the output winding coupled thereto. If, however, the core S2 is at polarity N, a large voltage is induced in the coupled output winding. This large output voltage is sufficient to turn over the register core which is coupled to the output winding 74. Following each read-out of information, a current pulse is applied to the winding 73 of the register 72 by the interrogation source 76. lf the register core was turned over, a rela tively large output voltage is induced in the winding 82. Conversely, if the register core was not turned over, a relatively small, or no output voltage is induced in the winding $2. Note, that when the memory core 52 is at polarity P, there is a small change in its magnetic condition. The resulting voltage which is induced in the coupled output winding 74, by the memory core 52 is substantially cancelled due to the opposite voltage which is induced in the same output winding 74 by the adjacent dummy cores 54 and 56. The remaining memory and dummy cores which are coupled to the selected row and column windings also have their magnetic condition altered due to the half-amplitude excitation current pulses. However, the output voltages induced in the respective output windings which are coupled to the half excitated memory cores and dummy cores are also cancelled due to the equal and opposite excursion in the magnetic condition of the respectively coupled dummy cores.
The net output voltage, if any, which is induced in the coupled output winding 74 of a selected memory core 52 is of a polarity which tends to drive the register core further into saturation. Therefore, the information read-out of the memory array is unambiguous.
There has been described herein a magnetic device which is characterized by a substantially noise-free output signal. The main and dummy cores of the present invention may be comprised of a lower grade rectangular material than was heretofore practical. Also, the present invention furnishes an improved magnetic switch in which relatively less expensive magnetic material may be employed in fabricating the cores. lt will be apparent to those skilled in the art that the embodiments of the present invention in a coincident-current switch are illustrative only, and other arrangements of the main and dummy cores in a combinatorial switch may be employed.
What is claimed is:
l. A magnetic device comprising a main magnetic element and two dummy magnetic elements, iirst input coil means linking said main and one of said dummy elements, second input coil means linking said main and the other of said dummy elements, bias coil means linking each of said elements, output coil means linking each of said elements, separate means respectively connecting said iirst input coil means, said second input coil means, and said bias coils each in series aiding relationship, and means connecting said output coil means of said main element in series opposition with each of said output coil means of said dummy elements.
2. A magnetic device as recited in claim l wherein said main element and said dummy elements are toroidal cores.
3. A magnetic device as recited in claim l wherein said main and said dummy elements are each comprised of magnetic material whose hysteresis characteristic substantially deviates from a rectangular shape.
4. A magnetic device as recited in claim l including means for applying a D. C. current to said means connecting said bias coil means for producing a saturating 'linx in a given sense in each of said elements, and means for selectively applying an input signal to said means connecting said first and second input means.
5. A magnetic switch comprising a plurality of magnetic elements capable of being saturated with flux in one or the other of two senses, said elements including a plurality of groups of switch elements and a plurality of dummy elements, first and second input coil means linked to each of said switch elements, first input coil means linked to certain ones of said dummy elements, second input coil means linked to the remaining ones of said dummy elements, bias coil means linked to each of said elements, separate means alternately connecting said first input coil means of each of said groups of switch elements and said rst input coil means of said dummy elements in series aiding relationship, separate means alternately connecting said second input coil means of each of said groups of switch elements and said second input coil means of said dummy elements in series aiding relationship, means connecting said bias coil means in series aiding relationship, output coil means linked to each of said elements, and means connecting the output coil means of each switch element of a group in series opposition with the output coil means of one said dummy element having a first input coil means and another said dummy element having a second input coil means.
6. A magnetic switch as recited in claim wherein each of said dummy elements is linked by at least two different output coil means.
7. A magnetic switch comprising a plurality of magnetic switch elements and a plurality of dummy elements, said switch elements being arranged in electrical correspondence with the elements of a geometrical array arranged in rows and columns, a diierent one of said dummy elements being interposed respectively between each two switch elements corresponding to a row and each two switch elements corresponding to a column, a plurality of iirst input coils each different one linked to all the elements corresponding to an individual row, a plurality of second input coils each different one linked to all the elements corresponding to an individual column, a plurality of bias coils each different one linked to a different element, a plurality of output coils each of said eiements being linked by at least one output coil, means connecting said output coil of each switch element corresponding to the array element located at each row and column intersection in series opposition with said output coils of a pair of dummy elements, each dummy element of said pair being respectively adjacent the switch element at a respective row and column intersection.
S. A magnetic switch as recited in claim 5, including means to apply a biasing current to said means connecting said bias coil means thereby to saturate each of said elements with flux in one of said two senses, and means to selectively excite one of said means connecting said first input coil means and one of said means connecting said second input coil means thereby to produce a saturating iiux in the sense opposite to said one sense in a selected one of said switch elements.
9. A magnetic switch comprising a plurality of magnetic elements capable of being saturated with luX in one or the other of two senses, said elements including switch elements and dummy elements, said elements being arranged in electrical correspondence with the elements of a geometrical array arranged in rows and columns, a dummy element interposed between each two switch elements of a row and a different dummy element interposed between each two switch elements of a column, a rst input coil means linking each of the elements of a row, a second input coil means linking each of the elements of column, a bias coil means linking each of said elements, an output coil means linking each of said switch elements, two diiierent output coil means linking each of said dummy elements, separate means connecting the tirst input coil means of each row of elements in series aiding relationship, separate means connecting the second input coil means of each column of elements in series aiding relationship, means connecting the bias coil means of each of said elements in series aiding relationship, separate means connecting the output coil means of a switch element at each row and column intersection in series opposition with one of said output coil means of the dummy elements of said intersecting row and one of said output coil means of the dummy elements of said intersecting column.
l0. A magnetic switch comprising switch elements and at least two dummy elements, at least two input coil means, a bias coil means, and an output coil means linked to each of said switch elements, a plurality of input coil means, a plurality of output coil means, and a bias coil means linked to each of said dummy elements, means connecting each of said bias coil means in series aiding relationship, means connecting one of said input coil means of a iirst group of switch elements in series aiding relationship respectively with an input coil means of a first dummy element, means individually connecting the output coil means of each of said iirst group of switch elements in series opposition with an output coil means of said first dummy element, means connecting the other of said input coil means of a second group of switch elements in series aiding relationship respectively with an input coil means of a second one of said dummy elements, and means individually connecting the output coil means of each of said second group of switch elements in series opposition with an output coil means of said second dummy element.
References Cited in the tile of this patent Publication entitled: A Magnetic Matrix Switch and Its Incorporation Into a Coincident-Current Memory, by Kenneth H. Olsen, published June 6, 1952, by the Digital Computer Laboratory; Mass. Institute of Technology. (Pgs. 20-22.)
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US3048827A (en) * 1955-01-14 1962-08-07 Int Standard Electric Corp Intelligence storage equipment with independent recording and reading facilities
US2909673A (en) * 1955-02-02 1959-10-20 Librascope Inc Push-pull magnetic element
US2958853A (en) * 1955-04-01 1960-11-01 Int Standard Electric Corp Intelligence storage devices with compensation for unwanted output current
US3105959A (en) * 1955-04-07 1963-10-01 Philips Corp Memory matrices including magnetic cores
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US3070707A (en) * 1957-10-12 1962-12-25 Ibm Magnetic driver device
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US2970297A (en) * 1957-12-23 1961-01-31 Ibm Magnetic branching circuit
US3110016A (en) * 1957-12-27 1963-11-05 Rca Corp Decoder circuits
US3174050A (en) * 1958-07-03 1965-03-16 Int Standard Electric Corp Electric pulse distributors
US3112470A (en) * 1958-11-10 1963-11-26 Sylvania Electric Prod Noise cancellation for magnetic memory devices
US3060418A (en) * 1959-10-09 1962-10-23 Ibm Core array temperature responsive apparatus

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