US2144015A - Delayed diode circuit - Google Patents

Description

17, 1939. D, FOSTER, 2,144,015

Q DELAYED DIODE CIRCUIT Filed Dec. 5, 1936 1. F- AMPUF/ER f5: 7-H r0 4.;- 1 vEwflF Le E M 70558 I j [WEN-ma 000m 5. FOSTER ATTORNEY Patented Jan. 17, I939 PATENT OFFICE DELAYED DIODE CIRCUIT Dudley E. Foster, Morristown, N. J., assignor to Radio Corporation of Delaware America, a corporation of Application December 3, 1936, Serial No. 113,976

1 Claim.

My present invention relates to diode circuits for radio receiving circuits, and more particularly to an improved type of delayed diode rectification circuit fora radio receiver.

One of the main objects of my present invention is to provide a diode rectification circuit for a radio receiver which is of the delayed type, and the delay bias is derived from the space current of a signal transmission tube preceding the diode rectifier.

Another important object of the invention is to provide a delayed AVC network for a receiver, wherein the delay bias for the AVG rectifier is derived from the space current of a signal am- 55 plifier controlled by the AVG circuit Still another object of the invention is to provide a receiver employing a diode rectifier to provide AVC bias for one, or more, preceding signal amplifiers, and a delay bias being impressed upon the diode electrodes in the absence of signal energy above a predetermined amplitude, the delay bias being derived from direct current voltage developed by space current flow through a resistor disposed in the space current path of one of the 23 signal amplifiers controlled by the AVG circuit.

Other objects of the invention are to improve generally the efficiency and simplicity of delayed AVC circuits for radio receivers, and more especially to provide a receiver which includes a de- 30 layed diode AVC circuit which is economically manufactured and assembled in a receiver.

The novel features which Ibelieve to be characteristic of my invention are set forth in particularity in the appended claim; the invention 35 itself, however, as to both its organization and method of operation will best be understood by reference to the following description taken in connection with the drawing in which I have indicated diagrammatically a circuit organization 40 whereby my invention may be carried into effect.

Referring to the accompanying drawing, there is shown that portion of a receiving system which is necessary to a proper understanding of the present invention. The receiving system is shown as of the superheterodyne type, since such type of receiver is in wide use at the present time for radio reception. The second detector tube l is of the diode type, and between its anode 2 and cathode 3 is connected a resonant input circuit 4 60 which is tuned to the operating I. F. The latter may have any frequency value chosen from a range of 75 to 465 kc., and the low alternating potential side thereof is connected to the cathode 3 by means of an I. F. by-pass condenser 5. The 05 load resistor B of the detector circuit is connected (01. cam-20) the amplified audio voltage.

The direct current voltage developed across the load resistor 6 is employed as the AVG bias, and is transmitted through the direct current connection 8, designated as AVC, to the signal grid of one, or more, of the preceding signal amplifiers. In order to preserve simplicity of disclosure only the circuit details of the I, F. amplifier stage preceding the second detector are shown. The preceding I. F. amplifier stage includes a tube 9, of the pentode type, between whose input electrodes is connected the resonant input circuit !0 which istuned to the operating I. F. The cathode of tube 9 is connected to'ground through the signal grid bias resistor R1, the latter being shunted by the I. F. by-pass condenser l I. The plate circuit of amplifier 9 includes the resonant output circuit l2 tuned to the operating I. F., and which latter circuit is magnetically coupled to the input circuit 4 of the second detector. a

The input circuit H) of I. F. amplifier tube 9 is 00 coupled to a preceding I. F. tuned circuit l0, and it is to be understood that the latter may be disposed in the plate circuit of a preceding I. F. amplifier; or it may be disposed in the plate circuit of the preceding first detector stage. In any case, it will be understood that the circuits preceding the amplifier tube 3 may comprise the customary signal collector, followed by one, or more, stages of tunable radio frequency amplification, and the amplified signals being fed to the tunable first detector. Of course, a tunable local oscillator will be provided to feed local oscillations to the first detector; the local oscillations differing at all times from the signals impressed on the first detector by the operating I. F. These circuit de- 40 tails are too well known to those skilled in the art to require any further explanation.

The AVC connection 8 is connected to the low alternating potential side of the input circuit ill of the I. F. amplifier tube 9, and the numeral 20 designates the usual filter resistor inserted in the AVG connection to suppress pulsating components in the AVG voltage. The grid side of filter resistor 20 is connected to ground through a condenser 2l, and the network 2[l 2l may be given a time constant such that carrier fading will be readily compensated. The cathode side of bias resistor R1 is connected by the lead 30 to the cathode 3 of diode i. It will, therefore, be seen that the direct current path between the anode 2 and cathode 3 of diode l includes the coil of input circuit 4, load resistor 6, bias resistor R1, and lead 30; these enumerated elements being in series between the diode electrodes.

Since the anode 2 is connected to the ground side of bias resistor R1, it will have a normal negative potential with respect to cathode 3 in the absence of signals whose amplitude does not exceed the voltage developed across resistor R1. Further, since the delay bias for the diode l is taken from the I. F. amplifier tube 9 which is controlled in gain by the AVG action of the diode rectifier, it follows that the delay bias will decrease in proportion to increase of signal carrier amplitude. As the received signal carrier amplitude increases the AVG action will commence. When the signal carrier amplitude exceeds the delay bias developed across resistor R1, the space current fiow of amplifier tube 9 is still further decreased. Until the AVG action starts the delay bias has a fixed, predetermined value which is the voltage drop across resistor R1.

As the signal carrier amplitude increases beyond that value required to start the AVG action, there is a progressive decrease in the voltage drop across resistor B1. In other words in the absence of received signals the diode I is biased to prevent detection. Hence, there is no AVC bias developed across load resistor 6, and the delay bias of diode l is the full voltage developed across resistor R1. As the signal carrier amplitude increases up to the predetermined carrier amplitude at which AVC action is to commence, there occurs a gradual decrease in the delay bias because of peak rectification by diode I. When the predetermined carrier amplitude has been exceeded, then the AVG action causes such a decrease in the voltage across resistor R1 thatthe diode I is fully operative to detect and has no delay bias impressed thereon.

This circuit arrangement increases the maximum AVC available by the amount of the delay, and where the delay is applied to the audio detector it eventually removes the delay and consequent possible distortion at high modulation depths. Of course after the predetermined signal carrier amplitude has been exceeded, then the AVG action is normal in the sense that the AVG bias increases proportionately with carrier amplitude. It is to be understood that While the delay bias is shown as being derived from a signal amplifier immediately preceding the AVG rectifier, the bias may also be taken from any other tube Whose gain is regulated by the AVG circuit. Furthermore, it is to be understood that the delay bias may be applied to a diode rectifier which functions solely as an AVC bias source, and

. does not provide audio signals for the audio net- Work.

While I have indicated and described a system for carrying my invention into eifect, it will be apparent to one skilled in the art that my invention is by no means limited to the particular organization shown and described, but that many modifications may be made without departing from the scope of my invention as set forth in the appended claim.

What I claim is:

In combination with a diode rectifier having a tuned input circuit and a load resistor for developing a direct current voltage from rectified signal energy, a signal amplifier feeding signals to said diode input circuit, a bias resistor in the cathode circuit of said amplifier for developing a direct current voltage which varies in magnitude with the space current intensity of the amplifier, means for impressing the voltage across the bias resistor between the electrodes of the diode in a sense such as to delay rectification for signals having less than a predetermined amplitude, and means for applying the voltage across the said load resistor to a gain control electrode of said amplifier.

DUDLEY E. FOSTER.

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