US20210391240A1 - Leadframe capacitors - Google Patents
Leadframe capacitors Download PDFInfo
- Publication number
- US20210391240A1 US20210391240A1 US16/901,310 US202016901310A US2021391240A1 US 20210391240 A1 US20210391240 A1 US 20210391240A1 US 202016901310 A US202016901310 A US 202016901310A US 2021391240 A1 US2021391240 A1 US 2021391240A1
- Authority
- US
- United States
- Prior art keywords
- conductive plate
- package structure
- conductive
- electronic device
- die
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 35
- 238000002955 isolation Methods 0.000 claims description 57
- 230000008878 coupling Effects 0.000 claims description 3
- 238000010168 coupling process Methods 0.000 claims description 3
- 238000005859 coupling reaction Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 description 39
- 230000008569 process Effects 0.000 description 28
- 238000004519 manufacturing process Methods 0.000 description 24
- 239000004065 semiconductor Substances 0.000 description 16
- 238000013461 design Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 6
- 238000000465 moulding Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000004804 winding Methods 0.000 description 5
- 230000010354 integration Effects 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012797 qualification Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49589—Capacitor integral with or on the leadframe
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/492—Bases or plates or solder therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
- H01L23/49551—Cross section geometry characterised by bent parts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/46—Structure, shape, material or disposition of the wire connectors prior to the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/564—Details not otherwise provided for, e.g. protection against moisture
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Definitions
- Signal isolation is used in various applications where signaling must cross an isolation barrier, for example, between circuits of different voltage domains.
- Integrating isolation components into fabricated semiconductor dies uses silicon dioxide as the dielectric material for a capacitive isolation barrier with galvanic isolation, and this integration adds cost and complexity to the manufacturing process.
- Capacitors are formed within silicon metal layers during silicon wafer fabrication process and the capacitor structure depends on the specific fabrication process node geometry and design rules.
- a device design often can only be manufactured using a subset of process nodes with qualified isolation components at a given fabrication facility. Isolation qualification and certification is needed for structures fabricated with each of the specified process nodes, resulting in high cost.
- Integrated isolation components often require special development by process teams and often employ special design rules.
- Some applications may use wafer fabrication processes optimized for specific needs like high power and/or high voltage, but these processes may not be compatible with robust isolation dielectric requirements.
- a new design often cannot utilize processes optimized for specific needs such as power and high voltage without redesign of isolation components for those fabrication process nodes, followed by isolation requalification and certification.
- integrating isolation components in a semiconductor wafer fabrication can lead to relatively large minimum die size for an isolation die.
- an electronic device includes isolation structures created using a patterned lead frame during IC manufacturing to provide a low cost compact isolation solution that does not impact semiconductor wafer fabrication processes and does not require extra board level components.
- an electronic device includes a package structure with conductive leads, first and second dies in the package structure, as well as first and second conductive plates electrically coupled to the respective first and second dies and having respective first and second sides spaced apart from and directly facing one another with a portion of the package structure extending between the first side of the first conductive plate and the second side of the second conductive plate to form a capacitor. No other side of the first conductive plate directly faces a side of the second conductive plate, and no other side of the second conductive plate directly faces a side of the first conductive plate.
- the first side of the first conductive plate extends in a first plane
- the second side of the second conductive plate extends in a second plane
- the first and second planes are parallel to one another.
- the first and second conductive plates are coplanar in a third plane that is perpendicular to the first and second planes.
- the package structure has first and second opposite sides spaced apart from one another along a first direction, and the conductive leads are spaced apart from one another along a perpendicular second direction, where the second side of the second conductive plate is spaced apart from the first side of the first conductive plate along one of the first and second directions.
- the second side of the second conductive plate is spaced apart from the first side of the first conductive plate along a third direction that is perpendicular to the first and second directions.
- the first conductive plate has a first portion having the first side, and a second portion; and the first and second portions of the first conductive plate are non-coplanar.
- the second conductive plate has a first portion having the second side, and a second portion; and the first and second portions of the second conductive plate are non-coplanar.
- the electronic device further includes an embedded dielectric insert in the package structure, and the first or second conductive plate is on or in the embedded dielectric insert. In one implementation, multiple conductive plates are on or in the embedded dielectric insert.
- Another aspect relates to a method that includes positioning a lead frame, performing connection and molding processes, and a separation process.
- the lead frame is positioned such that a first side of a first conductive plate is spaced apart from and directly facing a second side of a second conductive plate, where no other side of the first conductive plate directly faces a side of the second conductive plate, and no other side of the second conductive plate directly faces a side of the first conductive plate.
- the connection process in one example electrically connects a first bond wire to a first die and to the first conductive plate, and electrically connects a second bond wire to a second die and to the second conductive plate.
- the molding process forms a package structure which encloses the first and second dies, the first and second bond wires and portions of the first and second conductive plates.
- the separation process separates the first conductive plate, the second conductive plate, and conductive leads from a remaining portion of the lead frame.
- positioning the lead frame includes positioning a first lead frame relative to a second lead frame or relative to a dielectric insert such that the first side of the first conductive plate of the first lead frame is spaced apart from and directly facing the second side of the second conductive plate of the second lead frame or of the dielectric insert. In one implementation, positioning the lead frame includes positioning the first lead frame relative to the dielectric insert such that the first side of the first conductive plate of the first lead frame is spaced apart from and directly facing the second side of the second conductive plate of the dielectric insert.
- This implementation also includes positioning the second lead frame relative to the dielectric insert such that a first side of a third conductive plate of the second lead frame is spaced apart from and directly facing a second side of a fourth conductive plate of the dielectric insert, where no other side of the third conductive plate directly faces a side of the fourth conductive plate, and no other side of the fourth conductive plate directly faces a side of the third conductive plate.
- the isolation device includes a package structure with conductive leads, first and second dies in the package structure, as well as first and second conductive plates electrically coupled to the respective first and second dies and having respective first and second sides spaced apart from and directly facing one another with a portion of the package structure extending between the first side of the first conductive plate and the second side of the second conductive plate to form a capacitor. No other side of the first conductive plate directly faces a side of the second conductive plate, and no other side of the second conductive plate directly faces a side of the first conductive plate.
- the first side of the first conductive plate extends in a first plane; the second side of the second conductive plate extends in a second plane, the first and second planes are parallel to one another, and the first conductive plate and the second conductive plate are coplanar in a third plane that is perpendicular to the first and second planes.
- the first conductive plate has a first portion having the first side and a second portion, and the first and second portions of the first conductive plate are non-coplanar.
- the isolation device includes an embedded dielectric insert in the package structure, wherein one of the first conductive plate and the second conductive plate is on or in the embedded dielectric insert.
- FIG. 1 is a cutaway top plan view of a packaged electronic device with first and second semiconductor dies, and isolation capacitors formed by planar conductive plates from a starting lead frame.
- FIG. 2 is a schematic diagram of a circuit implemented in the semiconductor dies and isolation capacitors in the packaged electronic device of FIG. 1 .
- FIG. 3 is a flow diagram of a method of fabricating a packaged electronic device.
- FIGS. 4-7 are partial top plan views of the packaged electronic device of FIG. 1 at different stages of fabrication according to the method of FIG. 3 .
- FIG. 8 is a perspective view of the packaged electronic device of FIGS. 1, 2 and 4-7 .
- FIG. 9 is a top perspective view of another example packaged electronic device with first and second semiconductor dies and isolation capacitors with vertically spaced conductive plates from first and second starting lead frames.
- FIG. 10 is a top perspective view of first and second starting lead frames used in fabricating the packaged electronic device of FIG. 9 .
- FIG. 11 is a top perspective view of another example packaged electronic device with first and second semiconductor dies and isolation capacitors with vertically spaced conductive plates from first and second starting lead frames and an insert structure with additional conductive capacitor plates.
- FIG. 12 is a top perspective view of first and second starting lead frames and the insert structure used in fabricating the packaged electronic device of FIG. 11 .
- FIG. 13 is a schematic diagram of a power conversion system with isolated primary and secondary circuits and a control or feedback signal path including the packaged electronic device of FIG. 1 .
- Couple includes indirect or direct electrical or mechanical connection or combinations thereof. For example, if a first device couples to or is coupled with a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via one or more intervening devices and connections.
- One or more operational characteristics of various circuits, systems and/or components are hereinafter described in the context of functions which in some cases result from configuration and/or interconnection of various structures when circuitry is powered and operating.
- FIG. 1 shows a packaged electronic device 100 with conductive features formed from a starting lead frame 101 (e.g., copper, aluminum, etc.), including conductive leads 102 , a pair of first conductive plates 104 and a pair of second conductive plates 105 .
- a starting lead frame 101 e.g., copper, aluminum, etc.
- conductive leads 102 e.g., copper, aluminum, etc.
- first conductive plates 104 and a pair of second conductive plates 105 are included.
- more than two first conductive plates 104 and more than two respective second conductive plates 105 are included.
- the electronic device further includes a first die attach pad 106 in a second die attach pad 107 , which are also originally part of the starting lead frame 101 during manufacturing.
- the electronic device 100 includes a first die 108 mounted to the first die attach pad 106 , and a second die 109 mounted to the second die attach pad 107 .
- the first conductive plates 104 in this example each include a first side 110 .
- the dies 108 and 109 can be any suitable semiconductor-based circuit die, such as formed using semiconductor processing of a starting wafer, including transistors, resistors, capacitors, or other electronic components integrated into a die structure with conductive features (e.g., copper or aluminum bond pads, etc.) allowing bond wire or flip chip electrical connections.
- the electronic device 100 further includes electrical connections between the respective first and second dies 108 , 109 and various leads and conductive plates.
- bond wires 111 connect conductive features (e.g., bond pads) of the first die 108 to respective ones of a first set of the conductive leads 102 to make electrical circuit connections with a host printed circuit board (PCB, not shown) to which the electronic device 100 is soldered.
- Other ones of the bond wires 111 connect conductive features of the second die 109 to a second set of the conductive leads 102 .
- the first set of conductive leads 102 that are coupled to the first die 108 are on a first lateral side of the electronic device 100 (e.g., the left side in FIG.
- the electronic device 100 also includes a pair of first bond wires 112 , each of which are coupled between conductive features of the first die 108 and a respective one of the first conductive plates 104 .
- a pair of second bond wires 113 are each coupled between conductive features of the second die 109 and a respective one of the second conductive plates 105 .
- the second conductive plates 105 in this example each have a second side 114 .
- the first sides 110 of the respective conductive plates 104 in one example extend in a first plane (e.g., a Y-Z plane in FIG. 1 , where the Z direction is out of the page in the drawing).
- the second sides 114 of the respective second conductive plates 105 extend in a second plane (e.g., also a Y-Z plane), and the first and second planes are parallel to one another.
- the first and second planes are not strictly parallel to one another.
- one or both sides 110 and/or 114 is/are not planar.
- the second side 114 of each of the second conductive plates 105 is spaced apart from and directly faces the first side 110 of the respective first conductive plate 104 .
- no other side of the first conductive plates 104 directly faces a side of the respective second conductive plate 105
- no other side of the respective second conductive plates 105 directly faces a side of the respective first conductive plates 104 .
- Directly facing sides are conductive plate sides that face one another along a straight line with no intervening conductive structures.
- the electronic device 100 further includes a non-conductive package structure 120 .
- the package structure 120 is or includes molding compound.
- a portion of the package structure 120 extends between the first sides 110 of the respective first conductive plates 104 and the second sides 114 of the respective second conductive plates 105 to form respective capacitors C 1 and C 2 as schematically shown in dashed lines in FIG. 1 .
- the intervening package structure 120 between the respective plates sides 110 and 114 provides a dielectric which, in conjunction with the conductive material of the respective plates 104 and 105 , forms a capacitor structure that operates to isolate first and second circuits of the first and second dies 108 and 109 .
- the example capacitors C 1 and C 2 provide galvanic capacitive isolation between first and second voltage domains of the respective first and second dies 108 and 109 .
- a single isolation capacitor is provided in the electronic device 100 using corresponding first and second plates 104 and 105 with respective first and second sides 110 and 114 .
- more than two isolation capacitors are provided by arrangement of corresponding sides 110 and 114 of respective first and second plates 104 and 105 , in which the first side 110 of the first conductive plate 104 is spaced apart from and directly faces the second side 114 of the second conductive plate 105 , and where no other side of the first conductive plate 104 directly faces a side of the second conductive plate 105 and no other side of the second conductive plate 105 directly faces a side of the first conductive plate 104 .
- a single starting lead frame 101 is used to create the first and second conductive plates 104 and 105 .
- the first conductive plate 104 and the second conductive plate 105 are coplanar in a third plane (e.g., an X-Y plane) that is perpendicular to the first and second planes of the respective plate faces 110 and 114 , although not a requirement of all possible implementations.
- a third plane e.g., an X-Y plane
- the isolation between the respective plates 104 and 105 , and between the first and second voltage domains of the respective first and second dies 108 and 109 is provided along a lateral direction.
- the package structure 120 has first and second opposite sides along which the respective leads 102 are positioned, where the first and second sides of the package structure 120 are spaced apart from one another along a first direction (e.g., the X direction in FIG. 1 ), and portions of the conductive leads 102 are exposed outside the package structure 120 along the respective first and second sides of the package structure 120 .
- the leads are generally flush with the outer sides of the package structure 120 and partially exposed along the bottom and sides, such as for leadless package types including quad flat no lead (QFN) packages or premolded package like MIS, RLF etc.
- the conductive leads 102 are spaced from one another along a second direction (e.g., the Y direction in FIG. 1 ) along the respective first and second sides of the package structure 120 , where the second direction Y is perpendicular to the first direction X.
- a second direction e.g., the Y direction in FIG. 1
- the second side 114 of the second conductive plate 105 is spaced apart from the first side 110 of the first conductive plate 104 along the first direction X.
- lateral capacitor plate spacing is possible along a different direction in an X-Y plane, such as along the first (Y) direction.
- FIG. 2 shows an isolated communications circuit 200 implemented in the semiconductor dies 108 and 109 and isolation capacitors C 1 and C 2 in the packaged electronic device 100 of FIG. 1 .
- the capacitors C 1 and C 2 in FIG. 1 provide a single or multi-channel digital isolator that is created using a custom patterned lead frame 101 .
- one or more signals are transferred between different voltage domain circuits of the respective first and second dies 108 and 109 using lateral capacitive coupling between lead frame metal areas 104 and 105 .
- the isolated communications circuit 200 includes a high-frequency data channel, for example, with a bandwidth from 100 kbps up to 150 Mbps, as well as a low-frequency channel, for example, with a bandwidth from DC to 100 kbps.
- a single-ended input signal entering the high-frequency data channel is split into a differential signal via an inverter gate at the input.
- the following capacitor-resistor networks differentiate the signal into small and narrow transients, which then are converted into rail-to-rail differential pulses by two comparators.
- the comparator outputs drive a NOR-gate flip-flop having an output that feeds an output multiplexer.
- a decision logic (DCL) at the driving output of the flip-flop measures the durations between signal transients. If the duration between two consecutive transients exceeds a certain time limit (e.g., as in the case of a low-frequency signal) the DCL forces the output-multiplexer to switch from the high-frequency to the low-frequency channel.
- DCL decision logic
- the low-frequency input signals are pulse width modulated (PWM) with the carrier frequency of an internal oscillator to create a sufficiently high frequency capable of passing the capacitive barrier.
- a low-pass filter removes the high-frequency carrier from the actual data before passing it on to the output multiplexer.
- the mold compound or any other encapsulant used in forming the package structure 120 acts as an isolation dielectric barrier with designed isolation spacing to provide a robust high dielectric strength barrier across moisture, temperature, and reliability stress conditions.
- the starting lead frame 101 can be patterned with and desired custom design for mutual capacitance for circuit performance as needed for a given circuit application.
- the capacitor isolation can be combined with any process fabrication node for functional silicon or other semiconductor processing that is used to create the dies 108 and 109 .
- the lead frame 101 can be tailored to a particular isolation application without changing the fabrication processing used in manufacturing the dies 108 and 109 , and the semiconductor die fabrication can be simplified and cost effective compared with integrated isolation component solutions.
- the disclosed examples can be manufactured using existing package assembly processes and equipment, thereby providing a compact cost effective isolation solution.
- FIG. 3 shows a method 300 of fabricating a packaged electronic device
- FIGS. 4-7 show the packaged electronic device example 100 of FIG. 1 at different stages of fabrication according to the method 300 .
- the method 300 begins at 302 in FIG. 3 with positioning one or more lead frames, for example, the lead frame 101 in FIG. 4 , such that the first side 110 of the first conductive plate 104 is spaced apart from and directly faces the second side 114 of the second conductive plate 105 , no other side of the first conductive plate 104 directly faces a side of the second conductive plate 105 , and no other side of the second conductive plate 105 directly faces a side of the first conductive plate 104 .
- a die attach process is performed at 304 , which attaches the first die 108 to the first die attach pad 106 , and attaches the second die 109 to the second die attach pad 107 , as shown in FIG. 5 .
- the method 300 continues at 306 with performing a connection process.
- the connection process is a wire bonding process that electrically connects the first bond wire 112 to the first die 108 and to the first conductive plate 104 .
- the wire bonding process also electrically connects the second bond wire 113 to the second die 109 and to the second conductive plate 105 .
- the wire bonding process at 306 interconnects multiple bond wires 111 , 112 and 113 between conductive features (e.g., bond pads) of the dies 108 and 109 with the leads 102 and/or the conductive plates 104 and 105 to form electrical circuit that includes the isolation capacitors C 1 and C 2 .
- conductive features e.g., bond pads
- the method 300 continues at 308 in FIG. 3 with a molding process that forms the molded package structure 120 .
- the molding process creates separate molded package structures 120 for each prospective electronic device region of the lead frame assembly.
- the individual package structures 120 in this example each enclose the first die 108 , the second die 109 , the first bond wire 112 , the second bond wire 112 , a portion of the first conductive plate 104 , and a portion of the second conductive plate 105 .
- Certain examples also include lead trimming and forming operations at 310 in FIG. 3 , although not a strict requirement of all possible implementations.
- the method 300 further includes separating the first conductive plate 104 , the second conductive plate 105 , and the conductive leads 102 from a remaining portion of the lead frame 101 , for example, using laser cutting or sawing.
- FIG. 8 shows an example of the separated packaged electronic device 100 .
- another example packaged electronic device 900 in FIG. 9 includes lead frame-based isolation capacitors formed through the arrangement and positioning of conductive plates 104 and 105 of respective first and second starting lead frames 1001 and 1002 shown in FIG. 10 .
- This example provides vertical capacitor plate spacing along the Z direction, in which the respective first conductive plates 104 of the first lead frame 1001 have upwardly facing, generally planar first sides, and the corresponding respective second conductive plates 105 of the second lead frame 1002 have downwardly facing, generally planar second sides.
- the electronic device 900 in this example includes the above-described leads 102 , die attach pads 106 and 107 , semiconductor dies 108 and 109 , and molded package structure 120 , as well as bond wires (not shown in FIG. 9 ) to provide interconnections between the dies 108 and the leads 102 and conductive plates 104 and 105 to form an electrical circuit with two isolated voltage domains and capacitor connections via four capacitors created by the four conductive plates 104 and the four conductive plates 105 respectively separated by the dielectric material of the package structure 120 .
- each of the second conductive plates 105 is spaced apart from and directly faces the upwardly facing first side of the respective first conductive plate 104 .
- no other side of the first conductive plates 104 directly faces a side of the respective second conductive plate 105
- no other side of the respective second conductive plates 105 directly faces a side of the respective first conductive plates 104 .
- the package structure 120 has first and second opposite sides that are spaced apart from one another along the first direction X, and portions of the conductive leads 102 are exposed outside the package structure 120 along the respective first and second sides of the package structure 120 .
- the conductive leads 102 are spaced from one another along the second direction Y along the respective first and second sides of the package structure 120 .
- the second sides of the respective second conductive plates 105 are vertically spaced apart from the first sides of the respective first conductive plates 104 along the third direction Z that is perpendicular to the first direction X and to the second direction Y.
- first and second conductive plates are laterally spaced from one another, such as along the Y direction.
- the first conductive plates 104 each have a first portion having the first side, and a second portion joint to the first portion by a band, where the first and second portions of the respective first conductive plates 104 are non-coplanar.
- the respective second conductive plates 105 have a first portion that includes the second side, as well as a second portion joint to the first portion by a bend, and the first and second portions of the respective second conductive plates 105 are non-coplanar.
- the first lead frame 1001 is positioned relative to the second lead frame 1002 as shown in FIG.
- FIG. 11 shows another example packaged electronic device 1100 with first and second semiconductor dies 108 and 109 and isolation capacitors with vertically spaced conductive plates from first and second starting lead frames 1101 and 1102 , as well as a dielectric insert structure 1103 with additional respective first and second conductive capacitor plates 1104 and 1105 .
- FIG. 12 shows the first and second starting lead frames 1101 and 1102 and the insert structure 1103 used in fabricating the packaged electronic device 1100 of FIG. 11 .
- the insert structure 1103 in one example has respective first and second top side conductive plates 1104 and 1105 separated by a dielectric medium.
- the insert structure 1103 , 1104 , 1105 can be fabricated by a variety of techniques, including but not limited to dual level laminate construction, pre-molded lead frame (PMLF), MIS, etc. In various implementations, one or more of the first conductive plate 1104 and the second conductive plate 1105 is on or in the embedded dielectric insert 1103 .
- the electronic device 1100 has the above-described leads 102 , die attach pads 106 and 107 , semiconductor dies 108 and 109 , and molded package structure 120 , as well as bond wires 111 , 112 and 113 to provide interconnections between the dies 108 and the leads 102 and conductive plates 104 , 1104 , 105 and 1105 to form an electrical circuit with two isolated voltage domains and capacitor connections via four capacitors created by the four conductive plates 104 and the four conductive plates 105 and the associated conductive plates 1104 and 1105 of the insert structure 1103 , respectively separated by the dielectric material of the package structure 120 .
- the package structure 120 has first and second opposite sides spaced apart from one another along the first direction X, and portions of the conductive leads 102 are exposed outside the package structure 120 along the respective first and second package structure sides.
- the conductive leads 102 in this example are spaced from one another along the second direction Y, and the second sides of the respective second conductive plates 105 , 1105 are spaced apart from the first sides of the respective first conductive plates 104 , 1104 along the third direction Z.
- This example also provides vertical capacitor plate spacing, although not a strict requirement of all possible implementations that use an insert structure.
- the first lead frame 1101 , the second lead frame 1102 , and the dielectric insert structure 1103 are positioned relative to one another such that the first sides of the first conductive plates 104 of the first lead frame 1001 are spaced apart from and directly facing the respective second sides of the second conductive plates 1105 of the dielectric insert 1103 , no other side of the first conductive plate 104 directly faces a side of the second conductive plate 1105 , and no other side of the second conductive plate 1105 directly faces a side of the first conductive plate 104 .
- the relative positioning at 302 in this example also provides that the first side of a third conductive plate 105 of the second lead frame 1102 is spaced apart from and directly faces a second side of a fourth conductive plate 1104 of the dielectric insert 1103 , no other side of the third conductive plate 105 directly faces a side of the fourth conductive plate 1104 , and no other side of the fourth conductive plate 1104 directly faces a side of the third conductive plate 105 .
- FIG. 13 shows a power conversion system 1300 with isolated primary and secondary circuits and a control or feedback signal path including the packaged electronic device 100 of FIG. 1 .
- This example includes a DC supply 1302 with an output coupled to a first end of a primary winding of an isolation transformer 1304 . A second end of the primary winding is coupled to a primary site switching circuit 1306 .
- a secondary winding of the transformer 1304 is coupled to a secondary circuit 1308 , for example, to implement a flyback switching power conversion system 1300 .
- the secondary circuit 1308 is coupled to provide regulated output power to drive a load 1310 .
- the electronic device 100 in this example is an isolation device that provides a feedback signal or a switching control signal from the secondary circuit 1308 two the primary side switching circuit 1306 .
- the secondary circuit 1308 provides a signal to the isolation device 100 relative to an output or load side voltage domain, for example, representing a zero crossing of the switching circuit coupled to the secondary winding of the transformer 1304 .
- the isolation device 100 provides an isolated signal to the primary site switching circuit 1306 , and in response, the primary site switching circuit initiates a new switching cycle to close a switch to cause current flow in the primary winding of the transformer 1304 .
- the secondary circuit 1308 provides a feedback signal to the isolation device 100 that represents an output voltage or output current of the load 1310 , and the primary site switching circuit 1306 regulates the output voltage or current in closed-loop fashion according to the feedback signal from the isolation device 100 .
- the described examples provide a global low cost solution for signal isolation, with applicability across package types and footprints. These examples, moreover, can be used to provide high voltage isolation in a single package electronic device 100 , 900 , 1100 without requiring integration of capacitor isolation components on or in the semiconductor dies 108 and 109 , thereby reducing the cost and complexity of the die fabrication.
- the described electronic devices 100 , 900 , 1100 provide integration within the packaged electronic device itself, thereby mitigating or avoiding the extra cost and board space associated with using opto-couplers or other external isolation components.
- the described examples provide signal isolation using lead frame metal structures for a solution that is silicon fabrication process agnostic.
- the resulting solutions have much lower cost than integration of isolation components in a silicon fabrication process.
- the electronic devices 100 , 900 , and 1100 can be fabricated using existing lead frame manufacturing and assembly infrastructure and processes, allowing adaptation to a variety of different designs and use applications.
- These isolation solutions can be extended to all lead frame and/or laminate-based package types and form factors, while providing a robust isolation barrier.
- the described examples provide a technical solution to the previous problems of high cost, long cycle time and isolation technology based development limitations because of separate design, qualification, and certification requirements for each process node by removing isolation component dependency from silicon fabrication process nodes, and integrating the isolation solution into the lead frame itself.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
An electronic device having a package structure with conductive leads, first and second dies in the package structure, as well as first and second conductive plates electrically coupled to the respective first and second dies and having respective first and second sides spaced apart from and directly facing one another with a portion of the package structure extending between the first side of the first conductive plate and the second side of the second conductive plate to form a capacitor. No other side of the first conductive plate directly faces a side of the second conductive plate, and no other side of the second conductive plate directly faces a side of the first conductive plate.
Description
- Signal isolation is used in various applications where signaling must cross an isolation barrier, for example, between circuits of different voltage domains. Integrating isolation components into fabricated semiconductor dies uses silicon dioxide as the dielectric material for a capacitive isolation barrier with galvanic isolation, and this integration adds cost and complexity to the manufacturing process. Capacitors are formed within silicon metal layers during silicon wafer fabrication process and the capacitor structure depends on the specific fabrication process node geometry and design rules. In addition, a device design often can only be manufactured using a subset of process nodes with qualified isolation components at a given fabrication facility. Isolation qualification and certification is needed for structures fabricated with each of the specified process nodes, resulting in high cost. Integrated isolation components often require special development by process teams and often employ special design rules. Some applications may use wafer fabrication processes optimized for specific needs like high power and/or high voltage, but these processes may not be compatible with robust isolation dielectric requirements. A new design often cannot utilize processes optimized for specific needs such as power and high voltage without redesign of isolation components for those fabrication process nodes, followed by isolation requalification and certification. Moreover, integrating isolation components in a semiconductor wafer fabrication can lead to relatively large minimum die size for an isolation die.
- In one aspect, an electronic device includes isolation structures created using a patterned lead frame during IC manufacturing to provide a low cost compact isolation solution that does not impact semiconductor wafer fabrication processes and does not require extra board level components. In one example, an electronic device includes a package structure with conductive leads, first and second dies in the package structure, as well as first and second conductive plates electrically coupled to the respective first and second dies and having respective first and second sides spaced apart from and directly facing one another with a portion of the package structure extending between the first side of the first conductive plate and the second side of the second conductive plate to form a capacitor. No other side of the first conductive plate directly faces a side of the second conductive plate, and no other side of the second conductive plate directly faces a side of the first conductive plate.
- In one example, the first side of the first conductive plate extends in a first plane, the second side of the second conductive plate extends in a second plane, and the first and second planes are parallel to one another. In one example, the first and second conductive plates are coplanar in a third plane that is perpendicular to the first and second planes. In one implementation, the package structure has first and second opposite sides spaced apart from one another along a first direction, and the conductive leads are spaced apart from one another along a perpendicular second direction, where the second side of the second conductive plate is spaced apart from the first side of the first conductive plate along one of the first and second directions.
- In another example, the second side of the second conductive plate is spaced apart from the first side of the first conductive plate along a third direction that is perpendicular to the first and second directions. In one implementation, the first conductive plate has a first portion having the first side, and a second portion; and the first and second portions of the first conductive plate are non-coplanar. In one example, moreover, the second conductive plate has a first portion having the second side, and a second portion; and the first and second portions of the second conductive plate are non-coplanar. In another example, the electronic device further includes an embedded dielectric insert in the package structure, and the first or second conductive plate is on or in the embedded dielectric insert. In one implementation, multiple conductive plates are on or in the embedded dielectric insert.
- Another aspect relates to a method that includes positioning a lead frame, performing connection and molding processes, and a separation process. The lead frame is positioned such that a first side of a first conductive plate is spaced apart from and directly facing a second side of a second conductive plate, where no other side of the first conductive plate directly faces a side of the second conductive plate, and no other side of the second conductive plate directly faces a side of the first conductive plate. The connection process in one example electrically connects a first bond wire to a first die and to the first conductive plate, and electrically connects a second bond wire to a second die and to the second conductive plate. The molding process forms a package structure which encloses the first and second dies, the first and second bond wires and portions of the first and second conductive plates. The separation process separates the first conductive plate, the second conductive plate, and conductive leads from a remaining portion of the lead frame.
- In one example, positioning the lead frame includes positioning a first lead frame relative to a second lead frame or relative to a dielectric insert such that the first side of the first conductive plate of the first lead frame is spaced apart from and directly facing the second side of the second conductive plate of the second lead frame or of the dielectric insert. In one implementation, positioning the lead frame includes positioning the first lead frame relative to the dielectric insert such that the first side of the first conductive plate of the first lead frame is spaced apart from and directly facing the second side of the second conductive plate of the dielectric insert. This implementation also includes positioning the second lead frame relative to the dielectric insert such that a first side of a third conductive plate of the second lead frame is spaced apart from and directly facing a second side of a fourth conductive plate of the dielectric insert, where no other side of the third conductive plate directly faces a side of the fourth conductive plate, and no other side of the fourth conductive plate directly faces a side of the third conductive plate.
- Another aspect relates to a system having first and second electronic circuits or different voltage domains, as well as an isolation device coupled with the first and second electronic circuits. The isolation device includes a package structure with conductive leads, first and second dies in the package structure, as well as first and second conductive plates electrically coupled to the respective first and second dies and having respective first and second sides spaced apart from and directly facing one another with a portion of the package structure extending between the first side of the first conductive plate and the second side of the second conductive plate to form a capacitor. No other side of the first conductive plate directly faces a side of the second conductive plate, and no other side of the second conductive plate directly faces a side of the first conductive plate.
- In one example, the first side of the first conductive plate extends in a first plane; the second side of the second conductive plate extends in a second plane, the first and second planes are parallel to one another, and the first conductive plate and the second conductive plate are coplanar in a third plane that is perpendicular to the first and second planes.
- In another example, the first conductive plate has a first portion having the first side and a second portion, and the first and second portions of the first conductive plate are non-coplanar.
- In another example, the isolation device includes an embedded dielectric insert in the package structure, wherein one of the first conductive plate and the second conductive plate is on or in the embedded dielectric insert.
-
FIG. 1 is a cutaway top plan view of a packaged electronic device with first and second semiconductor dies, and isolation capacitors formed by planar conductive plates from a starting lead frame. -
FIG. 2 is a schematic diagram of a circuit implemented in the semiconductor dies and isolation capacitors in the packaged electronic device ofFIG. 1 . -
FIG. 3 is a flow diagram of a method of fabricating a packaged electronic device. -
FIGS. 4-7 are partial top plan views of the packaged electronic device ofFIG. 1 at different stages of fabrication according to the method ofFIG. 3 . -
FIG. 8 is a perspective view of the packaged electronic device ofFIGS. 1, 2 and 4-7 . -
FIG. 9 is a top perspective view of another example packaged electronic device with first and second semiconductor dies and isolation capacitors with vertically spaced conductive plates from first and second starting lead frames. -
FIG. 10 is a top perspective view of first and second starting lead frames used in fabricating the packaged electronic device ofFIG. 9 . -
FIG. 11 is a top perspective view of another example packaged electronic device with first and second semiconductor dies and isolation capacitors with vertically spaced conductive plates from first and second starting lead frames and an insert structure with additional conductive capacitor plates. -
FIG. 12 is a top perspective view of first and second starting lead frames and the insert structure used in fabricating the packaged electronic device ofFIG. 11 . -
FIG. 13 is a schematic diagram of a power conversion system with isolated primary and secondary circuits and a control or feedback signal path including the packaged electronic device ofFIG. 1 . - In the drawings, like reference numerals refer to like elements throughout, and the various features are not necessarily drawn to scale. Also, the term “couple” or “couples” includes indirect or direct electrical or mechanical connection or combinations thereof. For example, if a first device couples to or is coupled with a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via one or more intervening devices and connections. One or more operational characteristics of various circuits, systems and/or components are hereinafter described in the context of functions which in some cases result from configuration and/or interconnection of various structures when circuitry is powered and operating.
-
FIG. 1 shows a packagedelectronic device 100 with conductive features formed from a starting lead frame 101 (e.g., copper, aluminum, etc.), includingconductive leads 102, a pair of firstconductive plates 104 and a pair of secondconductive plates 105. In another example, only a single firstconductive plate 104 and a single secondconductive plate 105 are included. In other examples, more than two firstconductive plates 104 and more than two respective secondconductive plates 105 are included. The electronic device further includes a firstdie attach pad 106 in a seconddie attach pad 107, which are also originally part of the startinglead frame 101 during manufacturing. Theelectronic device 100 includes afirst die 108 mounted to the firstdie attach pad 106, and a second die 109 mounted to the seconddie attach pad 107. The firstconductive plates 104 in this example each include afirst side 110. Thedies - The
electronic device 100 further includes electrical connections between the respective first andsecond dies bond wires 111 connect conductive features (e.g., bond pads) of thefirst die 108 to respective ones of a first set of theconductive leads 102 to make electrical circuit connections with a host printed circuit board (PCB, not shown) to which theelectronic device 100 is soldered. Other ones of thebond wires 111 connect conductive features of thesecond die 109 to a second set of theconductive leads 102. In the illustrated example, the first set ofconductive leads 102 that are coupled to thefirst die 108 are on a first lateral side of the electronic device 100 (e.g., the left side inFIG. 1 ), and the second set ofconductive leads 102 that are coupled to thesecond die 109 are on an opposite second lateral side of the electronic device 100 (e.g., on the right side inFIG. 1 ), although not a strict requirement of all possible implementations. Theelectronic device 100 also includes a pair offirst bond wires 112, each of which are coupled between conductive features of thefirst die 108 and a respective one of the firstconductive plates 104. In addition, a pair ofsecond bond wires 113 are each coupled between conductive features of thesecond die 109 and a respective one of the secondconductive plates 105. - The second
conductive plates 105 in this example each have asecond side 114. Thefirst sides 110 of the respectiveconductive plates 104 in one example extend in a first plane (e.g., a Y-Z plane inFIG. 1 , where the Z direction is out of the page in the drawing). In this example, thesecond sides 114 of the respective secondconductive plates 105 extend in a second plane (e.g., also a Y-Z plane), and the first and second planes are parallel to one another. In other examples, the first and second planes are not strictly parallel to one another. In another example, one or bothsides 110 and/or 114 is/are not planar. In the illustrated implementation, thesecond side 114 of each of the secondconductive plates 105 is spaced apart from and directly faces thefirst side 110 of the respective firstconductive plate 104. In addition, no other side of the firstconductive plates 104 directly faces a side of the respective secondconductive plate 105, and no other side of the respective secondconductive plates 105 directly faces a side of the respective firstconductive plates 104. Directly facing sides, as used herein, are conductive plate sides that face one another along a straight line with no intervening conductive structures. Theelectronic device 100 further includes anon-conductive package structure 120. In one example, thepackage structure 120 is or includes molding compound. A portion of thepackage structure 120 extends between thefirst sides 110 of the respective firstconductive plates 104 and thesecond sides 114 of the respective secondconductive plates 105 to form respective capacitors C1 and C2 as schematically shown in dashed lines inFIG. 1 . The interveningpackage structure 120 between therespective plates sides respective plates electronic device 100, the example capacitors C1 and C2 provide galvanic capacitive isolation between first and second voltage domains of the respective first and second dies 108 and 109. - In other implementations, a single isolation capacitor is provided in the
electronic device 100 using corresponding first andsecond plates second sides sides second plates first side 110 of the firstconductive plate 104 is spaced apart from and directly faces thesecond side 114 of the secondconductive plate 105, and where no other side of the firstconductive plate 104 directly faces a side of the secondconductive plate 105 and no other side of the secondconductive plate 105 directly faces a side of the firstconductive plate 104. - In one example, as shown in
FIG. 1 , a singlestarting lead frame 101 is used to create the first and secondconductive plates conductive plate 104 and the secondconductive plate 105 are coplanar in a third plane (e.g., an X-Y plane) that is perpendicular to the first and second planes of the respective plate faces 110 and 114, although not a requirement of all possible implementations. In the example ofFIG. 1 , moreover, the isolation between therespective plates FIGS. 9-12 . In the example ofFIG. 1 , thepackage structure 120 has first and second opposite sides along which the respective leads 102 are positioned, where the first and second sides of thepackage structure 120 are spaced apart from one another along a first direction (e.g., the X direction inFIG. 1 ), and portions of the conductive leads 102 are exposed outside thepackage structure 120 along the respective first and second sides of thepackage structure 120. In one example, the leads are generally flush with the outer sides of thepackage structure 120 and partially exposed along the bottom and sides, such as for leadless package types including quad flat no lead (QFN) packages or premolded package like MIS, RLF etc. In this example, the conductive leads 102 are spaced from one another along a second direction (e.g., the Y direction inFIG. 1 ) along the respective first and second sides of thepackage structure 120, where the second direction Y is perpendicular to the first direction X. In the illustrated example, moreover, thesecond side 114 of the secondconductive plate 105 is spaced apart from thefirst side 110 of the firstconductive plate 104 along the first direction X. In other examples, lateral capacitor plate spacing is possible along a different direction in an X-Y plane, such as along the first (Y) direction. -
FIG. 2 shows anisolated communications circuit 200 implemented in the semiconductor dies 108 and 109 and isolation capacitors C1 and C2 in the packagedelectronic device 100 ofFIG. 1 . In certain applications, the capacitors C1 and C2 inFIG. 1 provide a single or multi-channel digital isolator that is created using a custom patternedlead frame 101. In operation, one or more signals are transferred between different voltage domain circuits of the respective first and second dies 108 and 109 using lateral capacitive coupling between leadframe metal areas isolated communications circuit 200 includes a high-frequency data channel, for example, with a bandwidth from 100 kbps up to 150 Mbps, as well as a low-frequency channel, for example, with a bandwidth from DC to 100 kbps. In one example implementation, a single-ended input signal entering the high-frequency data channel is split into a differential signal via an inverter gate at the input. The following capacitor-resistor networks differentiate the signal into small and narrow transients, which then are converted into rail-to-rail differential pulses by two comparators. The comparator outputs drive a NOR-gate flip-flop having an output that feeds an output multiplexer. A decision logic (DCL) at the driving output of the flip-flop measures the durations between signal transients. If the duration between two consecutive transients exceeds a certain time limit (e.g., as in the case of a low-frequency signal) the DCL forces the output-multiplexer to switch from the high-frequency to the low-frequency channel. In one example, the low-frequency input signals are pulse width modulated (PWM) with the carrier frequency of an internal oscillator to create a sufficiently high frequency capable of passing the capacitive barrier. As the input is modulated, a low-pass filter (LPF) removes the high-frequency carrier from the actual data before passing it on to the output multiplexer. In this example, the mold compound or any other encapsulant used in forming thepackage structure 120 acts as an isolation dielectric barrier with designed isolation spacing to provide a robust high dielectric strength barrier across moisture, temperature, and reliability stress conditions. The startinglead frame 101 can be patterned with and desired custom design for mutual capacitance for circuit performance as needed for a given circuit application. The capacitor isolation can be combined with any process fabrication node for functional silicon or other semiconductor processing that is used to create the dies 108 and 109. In this regard, thelead frame 101 can be tailored to a particular isolation application without changing the fabrication processing used in manufacturing the dies 108 and 109, and the semiconductor die fabrication can be simplified and cost effective compared with integrated isolation component solutions. Moreover, the disclosed examples can be manufactured using existing package assembly processes and equipment, thereby providing a compact cost effective isolation solution. - Referring also to
FIGS. 3-7 ,FIG. 3 shows amethod 300 of fabricating a packaged electronic device, andFIGS. 4-7 show the packaged electronic device example 100 ofFIG. 1 at different stages of fabrication according to themethod 300. Themethod 300 begins at 302 inFIG. 3 with positioning one or more lead frames, for example, thelead frame 101 inFIG. 4 , such that thefirst side 110 of the firstconductive plate 104 is spaced apart from and directly faces thesecond side 114 of the secondconductive plate 105, no other side of the firstconductive plate 104 directly faces a side of the secondconductive plate 105, and no other side of the secondconductive plate 105 directly faces a side of the firstconductive plate 104. A die attach process is performed at 304, which attaches thefirst die 108 to the first die attachpad 106, and attaches thesecond die 109 to the second die attachpad 107, as shown inFIG. 5 . Themethod 300 continues at 306 with performing a connection process. In one example shown inFIG. 6 , the connection process is a wire bonding process that electrically connects thefirst bond wire 112 to thefirst die 108 and to the firstconductive plate 104. The wire bonding process also electrically connects thesecond bond wire 113 to thesecond die 109 and to the secondconductive plate 105. In the example ofFIG. 6 , the wire bonding process at 306 interconnectsmultiple bond wires leads 102 and/or theconductive plates - The
method 300 continues at 308 inFIG. 3 with a molding process that forms the moldedpackage structure 120. In the example ofFIG. 7 , the molding process creates separate moldedpackage structures 120 for each prospective electronic device region of the lead frame assembly. Theindividual package structures 120 in this example each enclose thefirst die 108, thesecond die 109, thefirst bond wire 112, thesecond bond wire 112, a portion of the firstconductive plate 104, and a portion of the secondconductive plate 105. Certain examples also include lead trimming and forming operations at 310 inFIG. 3 , although not a strict requirement of all possible implementations. At 312, themethod 300 further includes separating the firstconductive plate 104, the secondconductive plate 105, and the conductive leads 102 from a remaining portion of thelead frame 101, for example, using laser cutting or sawing.FIG. 8 shows an example of the separated packagedelectronic device 100. - Referring also to
FIGS. 9 and 10 , another example packagedelectronic device 900 inFIG. 9 includes lead frame-based isolation capacitors formed through the arrangement and positioning ofconductive plates FIG. 10 . This example provides vertical capacitor plate spacing along the Z direction, in which the respective firstconductive plates 104 of thefirst lead frame 1001 have upwardly facing, generally planar first sides, and the corresponding respective secondconductive plates 105 of thesecond lead frame 1002 have downwardly facing, generally planar second sides. Theelectronic device 900 in this example includes the above-described leads 102, die attachpads package structure 120, as well as bond wires (not shown inFIG. 9 ) to provide interconnections between the dies 108 and theleads 102 andconductive plates conductive plates 104 and the fourconductive plates 105 respectively separated by the dielectric material of thepackage structure 120. - As with the
electronic device 100 ofFIG. 1 , the downwardly facing second sides of each of the secondconductive plates 105 is spaced apart from and directly faces the upwardly facing first side of the respective firstconductive plate 104. In addition, no other side of the firstconductive plates 104 directly faces a side of the respective secondconductive plate 105, and no other side of the respective secondconductive plates 105 directly faces a side of the respective firstconductive plates 104. In the example ofFIGS. 9 and 10 , moreover, thepackage structure 120 has first and second opposite sides that are spaced apart from one another along the first direction X, and portions of the conductive leads 102 are exposed outside thepackage structure 120 along the respective first and second sides of thepackage structure 120. In addition, the conductive leads 102 are spaced from one another along the second direction Y along the respective first and second sides of thepackage structure 120. In this example, the second sides of the respective secondconductive plates 105 are vertically spaced apart from the first sides of the respective firstconductive plates 104 along the third direction Z that is perpendicular to the first direction X and to the second direction Y. In other implementations, first and second conductive plates are laterally spaced from one another, such as along the Y direction. - As shown in
FIG. 10 , the firstconductive plates 104 each have a first portion having the first side, and a second portion joint to the first portion by a band, where the first and second portions of the respective firstconductive plates 104 are non-coplanar. Similarly, the respective secondconductive plates 105 have a first portion that includes the second side, as well as a second portion joint to the first portion by a bend, and the first and second portions of the respective secondconductive plates 105 are non-coplanar. During fabrication (e.g., at 302 according to theexample method 300 above), thefirst lead frame 1001 is positioned relative to thesecond lead frame 1002 as shown inFIG. 10 such that the first sides of the firstconductive plates 104 of thefirst lead frame 1001 are spaced apart from and directly facing the respective second sides of the secondconductive plate 105 of thesecond lead frame 1002, no other side of the firstconductive plate 104 directly faces a side of the respective secondconductive plate 105, and no other side of the secondconductive plate 105 directly faces a side of the firstconductive plate 104. - Referring also to
FIGS. 11 and 12 ,FIG. 11 shows another example packagedelectronic device 1100 with first and second semiconductor dies 108 and 109 and isolation capacitors with vertically spaced conductive plates from first and second starting lead frames 1101 and 1102, as well as adielectric insert structure 1103 with additional respective first and secondconductive capacitor plates FIG. 12 shows the first and second starting lead frames 1101 and 1102 and theinsert structure 1103 used in fabricating the packagedelectronic device 1100 ofFIG. 11 . Theinsert structure 1103 in one example has respective first and second top sideconductive plates insert structure conductive plate 1104 and the secondconductive plate 1105 is on or in the embeddeddielectric insert 1103. - The
electronic device 1100 has the above-described leads 102, die attachpads package structure 120, as well asbond wires leads 102 andconductive plates conductive plates 104 and the fourconductive plates 105 and the associatedconductive plates insert structure 1103, respectively separated by the dielectric material of thepackage structure 120. In this example, thepackage structure 120 has first and second opposite sides spaced apart from one another along the first direction X, and portions of the conductive leads 102 are exposed outside thepackage structure 120 along the respective first and second package structure sides. The conductive leads 102 in this example are spaced from one another along the second direction Y, and the second sides of the respective secondconductive plates conductive plates - During fabrication (e.g., at 302 according to the
example method 300 above), thefirst lead frame 1101, thesecond lead frame 1102, and thedielectric insert structure 1103 are positioned relative to one another such that the first sides of the firstconductive plates 104 of thefirst lead frame 1001 are spaced apart from and directly facing the respective second sides of the secondconductive plates 1105 of thedielectric insert 1103, no other side of the firstconductive plate 104 directly faces a side of the secondconductive plate 1105, and no other side of the secondconductive plate 1105 directly faces a side of the firstconductive plate 104. The relative positioning at 302 in this example also provides that the first side of a thirdconductive plate 105 of thesecond lead frame 1102 is spaced apart from and directly faces a second side of a fourthconductive plate 1104 of thedielectric insert 1103, no other side of the thirdconductive plate 105 directly faces a side of the fourthconductive plate 1104, and no other side of the fourthconductive plate 1104 directly faces a side of the thirdconductive plate 105. -
FIG. 13 shows apower conversion system 1300 with isolated primary and secondary circuits and a control or feedback signal path including the packagedelectronic device 100 ofFIG. 1 . This example includes aDC supply 1302 with an output coupled to a first end of a primary winding of anisolation transformer 1304. A second end of the primary winding is coupled to a primarysite switching circuit 1306. A secondary winding of thetransformer 1304 is coupled to asecondary circuit 1308, for example, to implement a flyback switchingpower conversion system 1300. Thesecondary circuit 1308 is coupled to provide regulated output power to drive aload 1310. Theelectronic device 100 in this example is an isolation device that provides a feedback signal or a switching control signal from thesecondary circuit 1308 two the primaryside switching circuit 1306. In one example, thesecondary circuit 1308 provides a signal to theisolation device 100 relative to an output or load side voltage domain, for example, representing a zero crossing of the switching circuit coupled to the secondary winding of thetransformer 1304. In this example, theisolation device 100 provides an isolated signal to the primarysite switching circuit 1306, and in response, the primary site switching circuit initiates a new switching cycle to close a switch to cause current flow in the primary winding of thetransformer 1304. In another example, thesecondary circuit 1308 provides a feedback signal to theisolation device 100 that represents an output voltage or output current of theload 1310, and the primarysite switching circuit 1306 regulates the output voltage or current in closed-loop fashion according to the feedback signal from theisolation device 100. - The described examples provide a global low cost solution for signal isolation, with applicability across package types and footprints. These examples, moreover, can be used to provide high voltage isolation in a single package
electronic device electronic devices electronic devices - Modifications are possible in the described examples, and other implementations are possible, within the scope of the claims.
Claims (21)
1. An electronic device, comprising:
a package structure;
conductive leads partially exposed outside the package structure;
a first die mounted to a first die attach pad in the package structure;
a second die mounted to a second die attach pad in the package structure;
a first conductive plate in the package structure, the first conductive plate having a first side;
a second conductive plate in the package structure, the second conductive plate having a second side;
a first bond wire coupled to the first die and to the first conductive plate in the package structure; and
a second bond wire coupled to the second die and to the second conductive plate in the package structure;
the second side of the second conductive plate being spaced apart from and directly facing the first side of the first conductive plate, a portion of the package structure extending between the first side of the first conductive plate and the second side of the second conductive plate to form a capacitor, no other side of the first conductive plate directly facing a side of the second conductive plate, and no other side of the second conductive plate directly facing a side of the first conductive plate.
2. The electronic device of claim 1 , wherein: the first side of the first conductive plate extends in a first plane; the second side of the second conductive plate extends in a second plane; and the first and second planes are parallel to one another.
3. The electronic device of claim 2 , wherein the first conductive plate and the second conductive plate are coplanar in a third plane that is perpendicular to the first and second planes.
4. The electronic device of claim 2 , wherein: the package structure has first and second opposite sides; the first and second sides of the package structure are spaced apart from one another along a first direction; portions of the conductive leads are exposed outside the package structure along the respective first and second sides of the package structure; the conductive leads are spaced from one another along a second direction along the respective first and second sides of the package structure; the second direction is perpendicular to the first direction; and the second side of the second conductive plate is spaced apart from the first side of the first conductive plate along one of the first and second directions.
5. The electronic device of claim 1 , wherein: the package structure has first and second opposite sides; the first and second sides of the package structure are spaced apart from one another along a first direction; portions of the conductive leads are exposed outside the package structure along the respective first and second sides of the package structure; the conductive leads are spaced from one another along a second direction along the respective first and second sides of the package structure; the second direction is perpendicular to the first direction; and the second side of the second conductive plate is spaced apart from the first side of the first conductive plate along a third direction that is perpendicular to the first direction and to the second direction.
6. The electronic device of claim 5 , wherein: the first conductive plate has a first portion having the first side, and a second portion; and the first and second portions of the first conductive plate are non-coplanar.
7. The electronic device of claim 6 , wherein: the second conductive plate has a first portion having the second side, and a second portion; and the first and second portions of the second conductive plate are non-coplanar.
8. The electronic device of claim 6 , wherein: the first side of the first conductive plate extends in a first plane; the second side of the second conductive plate extends in a second plane; and the first and second planes are parallel to one another.
9. The electronic device of claim 5 , further comprising an embedded dielectric insert in the package structure, wherein one of the first conductive plate and the second conductive plate is on or in the embedded dielectric insert.
10. The electronic device of claim 9 , comprising multiple conductive plates on or in the embedded dielectric insert.
11. The electronic device of claim 9 , wherein: the first side of the first conductive plate extends in a first plane; the second side of the second conductive plate extends in a second plane; and the first and second planes are parallel to one another.
12. The electronic device of claim 5 , wherein: the first side of the first conductive plate extends in a first plane; the second side of the second conductive plate extends in a second plane; and the first and second planes are parallel to one another.
13-16. (canceled)
17. A system, comprising:
a first electronic circuit of a first voltage domain;
a second electronic circuit of a second voltage domain; and
an isolation device coupled with the first and second electronic circuits, the isolation device comprising:
a package structure;
a first set of conductive leads partially exposed outside the package structure and coupled to the first electronic circuit;
a second set of conductive leads partially exposed outside the package structure and coupled to the second electronic circuit;
a first die mounted to a first die attach pad in the package structure and coupled to the first set of conductive leads;
a second die mounted to a second die attach pad in the package structure and coupled to the second set of conductive leads;
a first conductive plate in the package structure, the first conductive plate having a first side;
a second conductive plate in the package structure, the second conductive plate having a second side;
a first bond wire coupled to the first die and to the first conductive plate in the package structure; and
a second bond wire coupled to the second die and to the second conductive plate in the package structure;
the second side of the second conductive plate being spaced apart from and directly facing the first side of the first conductive plate, a portion of the package structure extending between the first side of the first conductive plate and the second side of the second conductive plate to form a capacitor, no other side of the first conductive plate directly facing a side of the second conductive plate, and no other side of the second conductive plate directly facing a side of the first conductive plate.
18. The system of claim 17 , wherein: the first side of the first conductive plate extends in a first plane; the second side of the second conductive plate extends in a second plane; the first and second planes are parallel to one another; and the first conductive plate and the second conductive plate are coplanar in a third plane that is perpendicular to the first and second planes.
19. The system of claim 17 , wherein: the first conductive plate has a first portion having the first side, and a second portion; and the first and second portions of the first conductive plate are non-coplanar.
20. The system of claim 17 , wherein the isolation device further comprises an embedded dielectric insert in the package structure, wherein one of the first conductive plate and the second conductive plate is on or in the embedded dielectric insert.
21. An apparatus, comprising:
a first side of a first conductive plate of a lead frame is spaced apart from and directly facing a second side of a second conductive plate of the lead frame, no other side of the first conductive plate directly faces a side of the second conductive plate and no other side of the second conductive plate directly faces a side of the first conductive plate;
a first bond wire coupling a first die and to the first conductive plate;
a second bond wire coupling a second die and to the second conductive plate;
a package structure which enclosing the first die, the second die, the first bond wire, the second bond wire, a portion of the first conductive plate and a portion of the second conductive plate; and
the first conductive plate, the second conductive plate, and conductive leads separated from a remaining portion of the lead frame.
22. The apparatus of claim 21 , wherein:
the first side of the first conductive plate of the first lead frame is spaced apart from and directly faces the second side of the second conductive plate of the second lead frame or the dielectric insert;
no other side of the first conductive plate directly faces a side of the second conductive plate; and
no other side of the second conductive plate directly faces a side of the first conductive plate.
23. The apparatus of claim 22 , wherein:
the first conductive plate of the first lead frame is spaced apart from and directly faces the second side of the second conductive plate of the dielectric insert;
no other side of the first conductive plate directly faces a side of the second conductive plate;
no other side of the second conductive plate directly faces a side of the first conductive plate;
a first side of a third conductive plate of the second lead frame is spaced apart from and directly facing a second side of a fourth conductive plate of the dielectric insert;
no other side of the third conductive plate directly faces a side of the fourth conductive plate; and
no other side of the fourth conductive plate directly faces a side of the third conductive plate.
24. The apparatus of claim 21 , wherein:
the first side of the first conductive plate of the first lead frame is spaced apart from and directly faces the second side of a second conductive plate of the dielectric insert;
no other side of the first conductive plate directly faces a side of the second conductive plate;
no other side of the second conductive plate directly faces a side of the first conductive plate;
a first side of a third conductive plate of the second lead frame is spaced apart from and directly facing a second side of a fourth conductive plate of the dielectric insert;
no other side of the third conductive plate directly faces a side of the fourth conductive plate; and
no other side of the fourth conductive plate directly faces a side of the third conductive plate.
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/901,310 US11205611B1 (en) | 2020-06-15 | 2020-06-15 | Leadframe capacitors |
CN202180042828.1A CN115702466A (en) | 2020-06-15 | 2021-06-15 | Lead frame capacitor |
EP21826874.6A EP4165666A4 (en) | 2020-06-15 | 2021-06-15 | Leadframe capacitors |
JP2022577256A JP2023530301A (en) | 2020-06-15 | 2021-06-15 | lead frame capacitor |
PCT/US2021/037410 WO2021257547A1 (en) | 2020-06-15 | 2021-06-15 | Leadframe capacitors |
US17/527,994 US11688672B2 (en) | 2020-06-15 | 2021-11-16 | Leadframe capacitors |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/901,310 US11205611B1 (en) | 2020-06-15 | 2020-06-15 | Leadframe capacitors |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US17/527,994 Division US11688672B2 (en) | 2020-06-15 | 2021-11-16 | Leadframe capacitors |
Publications (2)
Publication Number | Publication Date |
---|---|
US20210391240A1 true US20210391240A1 (en) | 2021-12-16 |
US11205611B1 US11205611B1 (en) | 2021-12-21 |
Family
ID=78825879
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/901,310 Active US11205611B1 (en) | 2020-06-15 | 2020-06-15 | Leadframe capacitors |
US17/527,994 Active US11688672B2 (en) | 2020-06-15 | 2021-11-16 | Leadframe capacitors |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US17/527,994 Active US11688672B2 (en) | 2020-06-15 | 2021-11-16 | Leadframe capacitors |
Country Status (5)
Country | Link |
---|---|
US (2) | US11205611B1 (en) |
EP (1) | EP4165666A4 (en) |
JP (1) | JP2023530301A (en) |
CN (1) | CN115702466A (en) |
WO (1) | WO2021257547A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20230326839A1 (en) * | 2019-07-16 | 2023-10-12 | Tdk Corporation | Electronic component package |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61108160A (en) * | 1984-11-01 | 1986-05-26 | Nec Corp | Semiconductor device with built-in capacitor and manufacture thereof |
US5444600A (en) | 1992-12-03 | 1995-08-22 | Linear Technology Corporation | Lead frame capacitor and capacitively-coupled isolator circuit using the same |
US7468547B2 (en) | 2007-05-11 | 2008-12-23 | Intersil Americas Inc. | RF-coupled digital isolator |
US8988142B2 (en) * | 2013-03-10 | 2015-03-24 | Microchip Technology Incorporated | Integrated high voltage isolation using low value capacitors |
US9035422B2 (en) | 2013-09-12 | 2015-05-19 | Texas Instruments Incorporated | Multilayer high voltage isolation barrier in an integrated circuit |
US10643929B2 (en) * | 2014-05-12 | 2020-05-05 | Texas Instruments Incorporated | Cantilevered leadframe support structure for magnetic wireless transfer between integrated circuit dies |
US9165873B1 (en) * | 2014-07-28 | 2015-10-20 | Texas Instruments Incorporated | Semiconductor package having etched foil capacitor integrated into leadframe |
DE112015003753T5 (en) * | 2014-08-14 | 2017-06-29 | Octavo Systems Llc | IMPROVED SUBSTRATE FOR SYSTEM-IN-PACKAGE (SIP) DEVICES |
US9704639B2 (en) * | 2014-11-07 | 2017-07-11 | Solantro Semiconductor Corp. | Non-planar inductive electrical elements in semiconductor package lead frame |
US10546847B2 (en) * | 2015-03-27 | 2020-01-28 | Fairchild Semiconductor Corporation | Substrate interposer on a leadframe |
US10497506B2 (en) | 2015-12-18 | 2019-12-03 | Texas Instruments Incorporated | Methods and apparatus for isolation barrier with integrated magnetics for high power modules |
US20170194088A1 (en) | 2015-12-30 | 2017-07-06 | Texas Instruments Incorporated | Isolation Transformer Topology |
US10819543B2 (en) | 2016-01-11 | 2020-10-27 | Texas Instruments Incorporated | Common mode transient immunity circuit for opto-isolator emulation |
US10447202B2 (en) | 2017-02-08 | 2019-10-15 | Texas Instruments Incorporated | Apparatus for communication across a capacitively coupled channel |
US10943855B2 (en) * | 2017-08-23 | 2021-03-09 | Semiconductor Components Industries, Llc | Electronic device packaging with galvanic isolation |
CN110098156B (en) * | 2018-01-29 | 2023-04-18 | 光宝新加坡有限公司 | Capacitive coupling packaging structure for capacitive coupling isolator |
US10840013B2 (en) | 2018-05-22 | 2020-11-17 | Texas Instruments Incorporated | Galvanic isolation in devices |
US20200168534A1 (en) | 2018-11-28 | 2020-05-28 | Texas Instruments Incorporated | Multi-chip module including standalone capacitors |
US10957655B2 (en) | 2018-12-11 | 2021-03-23 | Texas Instruments Incorporated | Integrated circuit with inductors having electrically split scribe seal |
-
2020
- 2020-06-15 US US16/901,310 patent/US11205611B1/en active Active
-
2021
- 2021-06-15 JP JP2022577256A patent/JP2023530301A/en active Pending
- 2021-06-15 EP EP21826874.6A patent/EP4165666A4/en active Pending
- 2021-06-15 CN CN202180042828.1A patent/CN115702466A/en active Pending
- 2021-06-15 WO PCT/US2021/037410 patent/WO2021257547A1/en unknown
- 2021-11-16 US US17/527,994 patent/US11688672B2/en active Active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20230326839A1 (en) * | 2019-07-16 | 2023-10-12 | Tdk Corporation | Electronic component package |
Also Published As
Publication number | Publication date |
---|---|
CN115702466A (en) | 2023-02-14 |
US11205611B1 (en) | 2021-12-21 |
WO2021257547A1 (en) | 2021-12-23 |
US11688672B2 (en) | 2023-06-27 |
EP4165666A1 (en) | 2023-04-19 |
EP4165666A4 (en) | 2023-12-20 |
JP2023530301A (en) | 2023-07-14 |
US20220077038A1 (en) | 2022-03-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9929079B2 (en) | Leadless electronic packages for GAN devices | |
TW201841337A (en) | Semiconductor device | |
EP3832862B1 (en) | Power conversion device | |
JP2019009158A (en) | Semiconductor device | |
US11908834B2 (en) | Multi-chip package with reinforced isolation | |
US20220254764A1 (en) | Semiconductor device | |
US20200211934A1 (en) | Leadframe for multichip devices with thinned die pad portions | |
US11688672B2 (en) | Leadframe capacitors | |
KR100621547B1 (en) | Multi-chip package | |
KR100637820B1 (en) | Hybrid integrated circuit device | |
US12051657B2 (en) | Transformer design with balanced interwinding capacitance for improved EMI performance | |
US20240029949A1 (en) | Insulating transformer | |
TWI697997B (en) | Package structure and method for fabricating the same | |
US11749578B2 (en) | Semiconductor module, power semiconductor module, and power electronic equipment using the semiconductor module or the power semiconductor module | |
JP2904123B2 (en) | Method for producing multilayer film carrier | |
TWI767145B (en) | Semiconductor device and manufacturing method of semiconductor device | |
JP4579040B2 (en) | Semiconductor amplifier | |
JP7399149B2 (en) | semiconductor equipment | |
US11817439B2 (en) | Semiconductor device having distinguishable electrodes | |
US20240266277A1 (en) | Semiconductor device and method of manufacturing the same | |
US20230369983A1 (en) | Monolithic half-bridge die | |
US20230245951A1 (en) | Semiconductor device | |
JP4014449B2 (en) | Circuit equipment | |
CN113474860A (en) | Isolation transformer with integrated shielding topology for reduced EMI | |
CN116417426A (en) | Packaging structure, packaging method, electronic element and electronic equipment |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FEPP | Fee payment procedure |
Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
AS | Assignment |
Owner name: TEXAS INSTRUMENTS INCORPORATED, TEXAS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KHANOLKAR, VIJAYLAXMI;NASUM, SREERAM SUBRAMANYAM;SINGH, TARUNVIR;SIGNING DATES FROM 20200615 TO 20201005;REEL/FRAME:054702/0377 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |