US20210375959A1 - Germanium-containing photodetector and methods of forming the same - Google Patents
Germanium-containing photodetector and methods of forming the same Download PDFInfo
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- US20210375959A1 US20210375959A1 US17/227,432 US202117227432A US2021375959A1 US 20210375959 A1 US20210375959 A1 US 20210375959A1 US 202117227432 A US202117227432 A US 202117227432A US 2021375959 A1 US2021375959 A1 US 2021375959A1
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- 229910052732 germanium Inorganic materials 0.000 title claims abstract description 297
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 title claims abstract description 297
- 238000000034 method Methods 0.000 title claims description 59
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Definitions
- CMOS image sensors may be used to sense electromagnetic radiation such as visible range light, infrared radiation, and/or ultraviolet light.
- Complementary metal-oxide-semiconductor (CMOS) image sensors (CIS) and charge-coupled device (CCD) sensors may be used in various applications such as digital cameras or cameras integrated in mobile devices. These devices utilize an array of pixels (which may include photodiodes and transistors) to detect radiation using photogeneration of electron-hole pairs.
- FIG. 1A is a plan view of a first configuration for an array of pixels of an image sensor according to an embodiment of the present disclosure.
- FIG. 1B is a plan view of a second configuration for an array of pixels of an image sensor according to another embodiment of the present disclosure.
- FIG. 2A-2K are sequential vertical cross-sectional views of a first exemplary structure during formation of a pixel of an image sensor according to a first embodiment of the present disclosure.
- FIG. 2L is a vertical cross-sectional view of an alternative configuration of the first exemplary structure according to the first embodiment of the present disclosure.
- FIGS. 3A and 3B are vertical cross-sectional views of configurations of a second exemplary structure including a pixel of an image sensor according to a second embodiment of the present disclosure.
- FIGS. 4A and 4B are vertical cross-sectional views of configurations of a third exemplary structure including a pixel of an image sensor according to a second embodiment of the present disclosure.
- FIG. 5A-5F are sequential vertical cross-sectional views of a fourth exemplary structure during formation of a pixel of an image sensor according to a fourth embodiment of the present disclosure.
- FIGS. 6A-6F are vertical cross-sectional views of alternative configurations of the fourth exemplary structure according to the fourth embodiment of the present disclosure.
- FIG. 7A-7G are sequential vertical cross-sectional views of a fifth exemplary structure during formation of a pixel of an image sensor according to a fifth embodiment of the present disclosure.
- FIG. 7H is a vertical cross-sectional view of an alternative configuration of the fifth exemplary structure according to the fifth embodiment of the present disclosure.
- FIG. 8 is a first process flow diagram illustrating an exemplary process sequence for forming an image sensor according to an embodiment of the present disclosure.
- FIG. 9 is a second process flow diagram illustrating an exemplary process sequence for forming an image sensor shown in FIG. 2K or in FIG. 2L .
- FIG. 10 is a third process flow diagram illustrating an exemplary process sequence for forming an image sensor shown in FIG. 3A or in FIG. 3B .
- FIG. 11 is a fourth process flow diagram illustrating an exemplary process sequence for forming an image sensor shown in FIG. 4A or in FIG. 4B .
- FIG. 12 is a fifth process flow diagram illustrating an exemplary process sequence for forming an image sensor shown in in FIGS. 5F and 6A-6F .
- FIG. 13 is a sixth process flow diagram illustrating an exemplary process sequence for forming an image sensor shown in FIGS. 7G and 7H .
- first and second features are formed in direct contact
- additional features may be formed between the first and second features, such that the first and second features may not be in direct contact
- present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It is presumed that elements having the same reference numeral have a same material composition.
- spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.
- the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
- the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- the structures and methods of the present disclosure may be used to manufacture a germanium-based photodetector and/or an image sensor incorporating array of germanium-based photodetectors.
- the structures and methods of the present disclosure may be used to manufacture a germanium-based photodetector formed on a silicon substrate, i.e., a germanium-in-silicon (GiS) photodetector and/or an image sensor including an array of GiS photodetectors.
- a photodetector or an image sensor may provide high quantum efficiency at near-infrared (NIR) spectrum for various sensing applications.
- NIR near-infrared
- silicon-based photodetectors display low sensitivity in the infrared range due to low quantum efficiency.
- Silicon-based photodetector provides poor optical performance in wavelength ranges greater than 1,000 nm due to low absorption of photons.
- Germanium provides higher absorption of photons in infrared wavelength ranges, but manufacture of complementary metal oxide semiconductor (CMOS) devices on a germanium substrate pose many challenges.
- CMOS complementary metal oxide semiconductor
- a germanium-based photodetector may be formed within a silicon substrate to provide use of standard CMOS manufacturing processes on the silicon substrate.
- a germanium-containing material portion including germanium or a silicon-germanium alloy may be passivated by enclosing walls of a silicon substrate around a trench, and by an overlying silicon-containing capping structure, which may include silicon nitride or crystalline silicon.
- Embodiments of the present disclosure provide a controlled height for the germanium-containing material portion relative to a top surface of silicon substrate.
- a dielectric material layer may be formed with a controlled thickness, and a chemical mechanical planarization may be used to form the germanium-containing material portion with a top surface at the height of the top surface of the dielectric mask layer.
- the germanium-containing material portion may be formed in a crystalline phase.
- the germanium-containing material portion may be single crystalline with epitaxial alignment with the single crystalline silicon material in the silicon substrate.
- selective epitaxial growth process may be used to maintain epitaxial alignment between the germanium-containing material portion and the single crystalline silicon material of the silicon substrate.
- the silicon-containing capping structure may include silicon.
- the silicon material of the silicon-containing capping structure may be formed as a single crystalline silicon material to enhance effectiveness as a passivation structure, i.e., as a diffusion barrier structure.
- the silicon-containing capping structure may include silicon nitride.
- FIG. 1A is a plan view of a first configuration for an array of pixels of an image sensor according to an embodiment of the present disclosure.
- FIG. 1B is a plan view of a second configuration for an array of pixels of an image sensor according to another embodiment of the present disclosure.
- a first configuration for an array 1000 of pixels 900 of an image sensor and a second configuration of an array 1000 of pixels 900 of an image sensor are illustrated in a respective plan view.
- the image sensor may be a backside illuminated (BSI) image sensor device.
- BSI backside illuminated
- FSI front-side illuminated
- Each pixel 900 represents a smallest unit area for the purpose of generating an image from the image sensor.
- the region including the array 1000 of pixels 900 is herein referred to as a pixel array region.
- the pixels 900 in the pixel array region may be arranged in rows and columns.
- the pixel array region may include M rows and N columns, in which M and N are integers in a range from 1 to 2 16 , such as from 2 8 to 2 14 .
- the rows of pixels 900 may be consecutively numbered with integers that range from 1 to M, and the columns of pixels 900 may be consecutively numbered with integers that range from 1 to N.
- a pixel P ij refers to a pixel 900 in the i-th row and in the j-th column.
- Each pixel 900 includes at least one photodetector that is configured to detect radiation of a given wavelength range.
- Each pixel 900 may include a plurality of photodetectors configured to detect radiation of a respective wavelength range, which may be different from each of the plurality of photodetectors.
- each pixel 900 may include a plurality of subpixels, each of which including a respective combination of a photodetector and an electronic circuit configured to detect radiation that impinged into the photodetector.
- a pixel 900 may include a subpixel configured to detect radiation in a red wavelength range (such as a range from 635 nm to 700 nm), a subpixel configured to detect radiation in a green wavelength range (such as a range from 520 nm to 560 nm), and a subpixel configured to detect radiation in a blue wavelength range (such as a range from 450 nm to 490 nm).
- a red wavelength range such as a range from 635 nm to 700 nm
- a subpixel configured to detect radiation in a green wavelength range (such as a range from 520 nm to 560 nm)
- a subpixel configured to detect radiation in a blue wavelength range (such as a range from 450 nm to 490 nm).
- Such subpixels are referred to as a red subpixel, green subpixel, and a blue subpixel, respectively.
- a pixel 900 generates information regarding the impinging radiation for a unit detection area.
- a subpixel generates information regarding the intensity of the impinging radiation within a specific wavelength range as detected within a region of the unit detection area.
- a monochromatic pixel 900 may include only a single subpixel.
- a pixel 900 configured to detect spectral distribution of impinging radiation includes multiple subpixels having at least two different detection wavelength ranges.
- Photodetectors in a pixel array region may include photodiodes, complimentary metal-oxide-semiconductor (CMOS) image sensors, charged coupling device (CCD) sensors, active sensors, passive sensors, other applicable sensors, or a combination thereof.
- CMOS complimentary metal-oxide-semiconductor
- CCD charged coupling device
- a subpixel within an image sensor may be formed using a germanium-containing well formed within a single crystalline silicon substrate as will be described below. While various exemplary structures described below describe only a single subpixel region including a photodetector region including a single germanium-based photodetector and a sensing circuit region containing a sensing circuit for the germanium-based photodetector, it is understood that multiple instances of the subpixel region may be arranged to provide a two-dimensional array of subpixels for an image sensor. Further, it is understood that additional subpixels, such as subpixels that include silicon-based photodetectors, may be optionally incorporated into the image sensor. Thus, embodiments in which instances of the various exemplary structures are multiplied to provide an image sensor including an array of pixels are expressly contemplated for each exemplary structure described below.
- FIG. 2A-2K are sequential vertical cross-sectional views of a first exemplary structure during formation of a pixel of an image sensor according to a first embodiment of the present disclosure.
- the first exemplary structure includes a semiconductor substrate 500 that includes a single crystalline silicon substrate 10 .
- the single crystalline silicon substrate 10 may have a pair of major horizontal surfaces.
- the major horizontal surface located on the top side is herein referred to as a proximal horizontal surface 7 .
- the major horizontal surface located on the backside is herein referred to as a distal horizontal surface 17 .
- the single crystalline silicon substrate 10 may be single crystalline, and may have a doping of a suitable conductivity type, which may be p-type or n-type.
- the single crystalline silicon substrate 10 may have a doping of a first conductivity type, and may include dopants of the first conductivity type at an atomic concentration in a range from 1.0 ⁇ 10 13 /cm 3 to 1.0 ⁇ 10 17 /cm 3 , although lesser and greater dopant concentrations may also be used.
- the first exemplary structure includes a photodetector region 510 in which a germanium-base photodetector is to be subsequently formed, and a sensing circuit region 520 in which a sensing circuit for the germanium-based photodetector is to be subsequently formed.
- a masked ion implantation processes may be performed to form various doped regions having various depths.
- a second-conductivity-type doped well 60 having a doping of the second conductivity type may be formed by ion implantation.
- the second-conductivity-type doped well 60 may be formed to laterally surround an enclosed region of the single crystalline silicon substrate 10 .
- the second conductivity type is the opposite of the first conductivity type.
- the second conductivity type is n-type, and vice versa.
- the depth of the second-conductivity-type doped well 60 may be in a range from 1 micron to 2 microns, although lesser and greater depths may also be used.
- the second-conductivity-type doped well 60 may include dopants of the second conductivity type at an atomic concentration in a range from 1.0 ⁇ 10 15 /cm 3 to 1.0 ⁇ 10 18 /cm 3 , although lesser and greater dopant concentrations may also be used.
- Doped well contact regions 68 having a doping of the second conductivity type may be formed in an upper portion of the second-conductivity-type doped well 60 by performing a masked ion implantation process.
- the doped well contact regions 68 may be heavily doped to reduce contact resistance.
- the doped well contact regions 68 may include dopants of the second conductivity type at an atomic concentration in a range from 1.0 ⁇ 10 19 /cm 3 to 1.0 ⁇ 10 22 /cm 3 , although lesser and greater dopant concentrations may also be used.
- a first doped photodiode contact region 28 having a doping of the first conductivity type may be formed under the proximal horizontal surface 7 of the single crystalline silicon substrate 10 within the area enclosed by the second-conductivity-type doped well 60 .
- the first doped photodiode contact region 28 may be heavily doped to reduce contact resistance.
- the first doped photodiode contact region 28 may include dopants of the first conductivity type at an atomic concentration in a range from 1.0 ⁇ 10 19 /cm 3 to 1.0 ⁇ 10 22 /cm 3 , although lesser and greater dopant concentrations may also be used.
- a dielectric mask layer 12 may be formed on the proximal horizontal surface 7 of the single crystalline silicon substrate 10 .
- the dielectric mask layer 12 includes a dielectric material such as silicon oxide. Other suitable materials are within the contemplated scope of disclosure.
- the dielectric mask layer 12 may be formed by deposition of a silicon oxide layer or by thermal oxidation of a surface of portion of the single crystalline silicon substrate 10 .
- the thickness of the dielectric mask layer 12 may be in a range from 50 nm to 300 nm, such as from 80 nm to 150 nm, although lesser and greater thicknesses may also be used.
- a photoresist layer 67 may be applied over the dielectric mask layer 12 .
- the photoresist layer 67 may be lithographically patterned to form an opening within the area laterally enclosed by the second-conductivity-type doped well 60 .
- An anisotropic etch process may be performed to transfer the pattern of the opening in the photoresist layer 67 through the dielectric mask layer 12 and into an upper portion of the single crystalline silicon substrate 10 .
- a trench 69 may be formed in the upper portion of the single crystalline silicon substrate 10 . The trench 69 is laterally enclosed by, and is laterally spaced inward from, the second-conductivity-type doped well 60 .
- the depth of the trench 69 may be greater than, the same as, or less than, the depth of the second-conductivity-type doped well 60 .
- the depth of the trench 69 may be in a range from 0.5 micron to 10 microns, such as from 1 micron to 6 microns, although lesser and greater depths may also be used.
- the lateral dimension of the trench 69 may be be in a range from 0.5 micron to 30 microns, such as from 1 micron to 15 microns, although lesser and greater lateral dimensions may also be used.
- the lateral dimension of the trench 69 may be the diameter or the major axis of the horizontal cross-sectional shape of the trench 69 in embodiments in which the trench 69 has a circular or an elliptical horizonal cross-sectional shape, or may be the length of a side of a rectangular shape in embodiments in which the horizontal cross-sectional shape of the trench 69 is the rectangular shape.
- the photoresist layer 67 may be subsequently removed, for example, by ashing.
- dopants of the first conductivity type may be implanted around the region of the trench 69 .
- the dopants of the first conductivity type are implanted at least within the area laterally enclosed by the second-conductivity-type doped well 60 .
- a multiple angled ion implantation processes may be performed to implant the dopants of the first conductivity type through sidewalls of the trench 69 .
- the dopants of the first conductivity type may be implanted into surface portion of the single crystalline silicon substrate 10 that underlies the proximal horizontal surface 7 of the single crystalline silicon substrate 10 .
- the dopants of the first conductivity type may be implanted into a horizontal portion of the single crystalline silicon substrate 10 that underlies the bottom surface of the trench 69 .
- a first-conductivity-type silicon region 21 may be formed within the single crystalline silicon substrate 10 .
- the first-conductivity-type silicon region 21 is connected to the first doped photodiode contact region 28 , which is the contact region for the first-conductivity-type silicon region 21 .
- the lateral width of the first-conductivity-type silicon region 21 around each sidewall of the trench 69 may be in a range from 100 nm to 1,000 nm, although lesser and greater lateral dimensions may also be used.
- the thickness of the horizontal portion of the first-conductivity-type silicon region 21 underneath the bottom surface of the trench 69 may be in a range from 100 nm to 1,000 nm, although lesser and greater thicknesses may also be used.
- a silicon liner 32 may be optionally grown from physically exposed surfaces of the first-conductivity-type silicon region 21 , which are surfaces of the trench 69 .
- the silicon liner 32 may be grown by a selective silicon epitaxy process that grows epitaxial silicon only from physically exposed semiconductor surfaces and does not grow silicon from dielectric surfaces.
- the silicon liner 32 may include epitaxially grown silicon, i.e., single crystalline silicon in epitaxial alignment with the single crystalline silicon material of the single crystalline silicon substrate 10 .
- the silicon liner 32 may be intrinsic, or may have a low level of doping.
- the atomic concentration of dopants within the silicon liner 32 may be in a range from 1.0 ⁇ 10 13 /cm 3 to 1.0 ⁇ 10 16 /cm 3 , although lesser and greater dopant concentrations may also be used.
- the conductivity type of the silicon liner 32 in embodiments in which the silicon liner 32 is not intrinsic, may be the first conductivity type or the second conductivity type.
- the thickness of the silicon liner 32 may be in a range from 5 nm to 200 nm, such as from 10 nm to 100 nm, although lesser and greater thicknesses may also be used.
- the silicon liner 32 if present, may function as a buffer between a germanium-containing material to be subsequently deposited and the first-conductivity-type silicon region 21 .
- a germanium-containing material may be grown from the physically exposed surfaces of the silicon liner 32 in embodiments that include the silicon liner 32 or from the physically exposed surfaces of the first-conductivity-type silicon region 21 in embodiments that do not include the silicon liner 32 .
- the germanium-containing material includes germanium at an atomic percentage greater than 50%.
- the germanium-containing material may include doped or undoped germanium such that the atomic percentage of germanium is at least 99%, and is essentially free of silicon.
- the germanium-containing material may include a silicon-germanium alloy in which the atomic percentage of germanium is greater than 50%, and the atomic percentage of silicon is less than 50%, such as from 5% to 30%.
- a germanium-containing material layer 30 L may be formed by the deposited germanium-containing material.
- the germanium-containing material layer 30 L may be formed by a selective deposition process or a non-selective deposition process.
- a selective deposition process is a process in which the germanium-containing material is grown from physically exposed semiconductor surfaces such as the physically exposed surfaces of the silicon liner 32 or the physically exposed surfaces of the first-conductivity-type silicon region 21 .
- a germanium-containing reactant such as germane or digermane
- an etchant gas such as hydrogen chloride.
- a semiconductor material such as a germanium-containing material
- the flow rates and the deposition temperature may be controlled such that the net deposition rate (i.e., the deposition rate less the etch rate) is positive on semiconductor surfaces, and is negative on dielectric surfaces during the selective deposition process.
- growth of the germanium-containing material occurs only on semiconductor surfaces.
- a non-selective deposition process is a deposition process in which the germanium-containing material grows from all physically exposed surfaces.
- the deposition process may use a germanium-containing reactant without use of an etchant gas.
- the selective deposition process or the non-selective deposition process that is used to deposit the germanium-containing material layer 30 L may be an epitaxial deposition process, i.e., a deposition process that provides alignment of crystallographic structure of the deposited germanium-containing material to the crystalline structure at the physically exposed surfaces of the underlying material portions.
- the portion of the germanium-containing material layer 30 L that is deposited in the trench 69 may be epitaxially aligned to the crystalline structure of the silicon liner 32 (in embodiments in which the silicon liner 32 is included) and/or the crystalline structure of the first-conductivity-type silicon region 21 .
- the material of the germanium-containing material layer 30 L grows from the physically exposed surfaces of the silicon liner 32 or the first-conductivity-type silicon region 21 .
- the entirety of the germanium-containing material layer 30 L may be single crystalline and may be in epitaxial alignment with the single crystalline silicon material of the single crystalline silicon substrate 8 .
- the material of the germanium-containing material layer 30 L grows from the physically exposed surfaces of the silicon liner 32 (in embodiments in which the silicon liner 32 is included) or the first-conductivity-type silicon region 21 , and from the physically exposed surfaces of the dielectric mask layer 12 .
- only the portion of the germanium-containing material layer 30 L that grows from the physically exposed surfaces of the silicon liner 32 (in embodiments in which the silicon liner 32 is included) or the first-conductivity-type silicon region 21 may be single crystalline, and the portions of the germanium-containing material layer 30 L that grows from the physically exposed surfaces of the dielectric mask layer 12 may be polycrystalline.
- an epitaxial deposition process may be performed to grow a single crystalline germanium-containing material inside the trench 69 .
- At least the portion of the germanium-containing material layer 30 L that grows within the trench 69 may be single crystalline, and may be formed with epitaxial alignment with the single crystalline silicon material of the single crystalline silicon substrate 10 ,.
- the entirety of the portion of the germanium-containing material layer 30 L located within the trench 69 may be single crystalline.
- the germanium-containing material layer 30 L may be intrinsic, or may have a low level of doping.
- the atomic concentration of dopants within the germanium-containing material layer 30 L may be in a range from 1.0 ⁇ 10 13 /cm 3 to 1.0 ⁇ 10 18 /cm 3 , although lesser and greater dopant concentrations may also be used.
- excess portions of the germanium-containing material may be removed from above the horizontal plane including the top surface of the dielectric mask layer 12 .
- a chemical mechanical planarization (CMP) process may be performed to remove portions of the germanium-containing material layer 30 L located above the horizontal plane including the top surface of the dielectric mask layer 12 .
- a remaining portion of the germanium-containing material layer 30 L located within the trench 69 comprises a germanium-containing material portion, which is herein referred to as a germanium-containing well 30 .
- the germanium-containing well 30 may have a top surface within the same horizontal plane as the top surface of the dielectric mask layer 12 .
- germanium-containing well 30 is formed as a single crystalline germanium-containing material portion
- germanium-containing well 30 may be formed as a polycrystalline material portion or as an amorphous material portion albeit at a reduced efficiency. Such variations are expressly contemplated herein.
- a remaining portion of the germanium-containing material may be vertically recessed within an opening in the dielectric mask layer 12 .
- the germanium-containing well 30 and optionally an upper portion of the optional silicon liner 32 may be vertically recessed, for example, by performing a recess etch process.
- the vertical recess distance may be greater than, the same as, or less than, the thickness of the dielectric mask layer 12 .
- the germanium-containing well 30 does not contact the dielectric mask layer 12
- the material of the germanium-containing well 30 does not contact any oxygen-containing material (such as silicon oxide) of the dielectric mask layer 12 .
- the vertical recess distance may be greater than the thickness of the dielectric mask layer 12 to prevent direct contact between the germanium-containing well 30 and the dielectric mask layer 12 .
- a silicon-containing capping material may be deposited on the physically exposed top surface of the germanium-containing well 30 .
- the silicon-containing capping material may be deposited on the top surface of the silicon liner 32 .
- the silicon-containing capping material may include, and/or may consist essentially of, a silicon-containing material that may prevent diffusion of oxygen.
- the silicon-containing capping material may include, and/or may consist essentially of, silicon or silicon nitride.
- a selective epitaxy process may be performed to grow silicon from the top surface of the germanium-containing well 30 .
- a passivation silicon region 340 including single crystalline silicon may be formed over the germanium-containing well 30 .
- a selective or non-selective silicon deposition process may be performed under conditions that forms polycrystalline silicon.
- the passivation silicon region 340 may include, and/or may consist essentially of, polysilicon.
- the passivation silicon region 340 may be formed only inside the opening in the dielectric mask layer 12 . In this embodiment, a planarization process is not necessary, and the top surface of the passivation silicon region 340 may be located at, below, or above, the horizontal plane including the top surface of the dielectric mask layer 12 . If a non-selective silicon deposition process is used, a planarization process such as a chemical mechanical planarization process may be performed to remove portions of the deposited silicon material from above the horizontal plane including the top surface of the dielectric mask layer 12 . In this embodiment, the top surface of the passivation silicon region 340 may be located within the same horizontal plane as the top surface of the dielectric mask layer 12 .
- the passivation silicon region 340 as formed may include intrinsic silicon or lightly doped silicon, i.e., silicon including electrical dopants at an atomic concentration in a range from 1.0 ⁇ 10 13 /cm 3 to 1.0 ⁇ 10 17 /cm 3 .
- the conductivity type of doping in the passivation silicon region 340 may be the first conductivity type or the second conductivity type.
- the passivation silicon region 340 may be formed as a single crystalline silicon portion, a polysilicon portion, a microcrystalline silicon portion, or an amorphous silicon portion depending on the deposition conditions.
- dopants of the second conductivity type may be implanted into the passivation silicon region 340 and an upper portion of the germanium-containing well 30 .
- the implanted portion of the germanium-containing well 30 may be converted into a second-conductivity-type germanium-containing region 302
- the passivation silicon region 340 may be converted into a second-conductivity-type silicon region 342 .
- the atomic concentration of electrical dopants of the second conductivity type in the second-conductivity-type germanium-containing region 302 and the second-conductivity-type silicon region 342 may be in a range from 1.0 ⁇ 10 18 /cm 3 to 1.0 ⁇ 10 21 /cm 3 , although lesser and greater atomic concentrations may also be used.
- the thickness of the second-conductivity-type germanium-containing region 302 may be in a range from 50 nm to 500 nm, although lesser and greater thicknesses may also be used.
- the thickness of the second-conductivity-type germanium-containing region 302 may be in a range from 50 nm to 300 nm, although lesser and greater thicknesses may also be used.
- the unimplanted portion of the germanium-containing well 30 is herein referred to as an intermediate germanium-containing region 308 .
- the intermediate germanium-containing region 308 may be intrinsic or may have a doping with an atomic concentration of dopants in a range from 1.0 ⁇ 10 13 /cm 3 to 1.0 ⁇ 10 18 /cm 3 .
- the intermediate germanium-containing region 308 contacts the second-conductivity-type germanium-containing region 302 , and is laterally surrounded by the first-conductivity-type silicon region 21 .
- the combination of the intermediate germanium-containing region 308 and the intermediate germanium-containing region 308 constitutes a germanium-containing well 30 .
- the first-conductivity-type silicon region 21 , the intermediate germanium-containing region 308 , and the second-conductivity-type germanium-containing region 302 collectively form a p-i-n type photovoltaic junction, i.e., a photovoltaic junction including a p-doped region, an n-doped region, and an intermediate semiconductor region located between the p-doped region and the n-doped region and including an intrinsic semiconductor material or a lightly-doped semiconductor material.
- the first conductivity type may be p-type and the second conductivity type may be n-type.
- the first conductivity type may be n-type and the first conductivity type may be p-type.
- the photovoltaic junction may be formed across the trench 69 , i.e., may spatially extend across the boundary of the trench 69 due to the presence of the first-conductivity-type silicon region 21 outside the trench 69 .
- the intermediate germanium-containing region 308 is located within the trench 69 , and functions as the intermediate semiconductor region including an intrinsic semiconductor material or a lightly-doped semiconductor material.
- the intermediate germanium-containing region 308 may have a doping of the second conductivity type, and the photovoltaic junction may include a p-n junction formed between the intermediate germanium-containing region 308 and the first-conductivity-type silicon region 21 .
- the intermediate germanium-containing region 308 may include dopants of the second conductivity type at an atomic concentration in arrange from 1.0 ⁇ 10 17 /cm 3 to 1.0 ⁇ 10 20 /cm 3 , although lesser and greater atomic concentrations may also be used.
- the p-n junction may be formed at the sidewall and the bottom surface of the trench 69 .
- the silicon liner 32 may be intrinsic, may be p-doped, or may be n-doped.
- the photovoltaic junction may comprise a p-i-n junction or a p-n junction formed across the germanium-containing well 30 and the single crystalline silicon substrate 10 that contains the first-conductivity-type silicon region 21 .
- the dielectric mask layer 12 may be removed, for example, by performing a wet etch process.
- a wet etch process using dilute hydrofluoric acid may be performed to remove the dielectric mask layer 12 .
- Shallow trench isolation structures 20 may be formed in an upper portion of the single crystalline silicon substrate 10 .
- the shallow trench isolation structures 20 may include a dielectric fill material such as silicon oxide, and provide electrical isolation from semiconductor devices to be subsequently formed.
- Various field effect transistors ( 610 , 630 , 640 ) may be formed in the photodetector region 510 and in the sensing circuit region 520 .
- a transfer transistor 610 may be formed in the photodetector region 510
- p-type field effect transistors 630 and n-type field effect transistors 640 may be formed in the sensing circuit region 520 .
- Each of the field effect transistors may include a respective gate dielectric 50 , a respective gate electrode 52 , and a respective pair of a source region and a drain region.
- the source regions and the drain regions are collectively referred to as source/drain regions.
- the p-type field effect transistors 630 may include p-doped source/drain regions 42
- the n-type field effect transistors 640 may include n-doped source/drain regions 44 .
- the transfer transistor 610 may include a source region 48 to be electrically connected to the second-conductivity-type germanium-containing region 302 , and a floating drain region 46 .
- the second-conductivity-type germanium-containing region 302 and the floating drain region 46 may have a doping of the second conductivity type.
- Various doped wells may be formed in the sensing circuit region 520 as needed. While the present disclosure illustrates only two field effect transistors in the sensing circuit region 520 , it is understood that a full set of field effect transistors for providing a sensing circuit for a subpixel may be formed in the sensing circuit region 520 .
- the field effect transistors in the sensing circuit region 520 may include transistors such as a reset transistor, a source follower transistor, and a select transistor. Any sensing circuit for sensing stored electrical charges in the second-conductivity-type germanium-containing region 302 may be formed.
- dielectric material layers 90 and metal interconnect structures 80 may be formed over the field effect transistors ( 610 , 630 , 640 ) and the second-conductivity-type silicon region 342 .
- Each of the dielectric material layers 90 includes a respective interlayer dielectric (ILD) material such as undoped silicate glass, a doped silicate glass, organosilicate glass, and/or a porous dielectric material.
- the dielectric material layers 90 may include dielectric liners such as silicon nitride dielectric liners, dielectric metal oxide dielectric liners, silicon carbide dielectric liners, and/or silicon oxynitride dielectric liners.
- the metal interconnect structures 80 may include metal via structures 82 and metal line structures 84 .
- the second-conductivity-type silicon region 342 may be electrically connected to the source region 48 of the transfer transistor 610 by a subset of the metal interconnect structures 80 .
- FIG. 2L is a vertical cross-sectional view of an alternative configuration of the first exemplary structure according to the first embodiment of the present disclosure.
- an alternative configuration of the first exemplary structure may be derived from the first exemplary structure of FIG. 2H by using silicon nitride as the material for a silicon-containing capping structure.
- a silicon nitride capping structure 41 including, and/or consisting essentially of, silicon nitride may be formed on the top surface of the germanium-containing well 30 .
- FIG. 2I may be performed to convert an upper portion of the germanium-containing well 30 into a second-conductivity-type germanium-containing region 302 .
- the processing steps of FIGS. 2J and 2K may be subsequently performed.
- a metal via structure 82 may be formed through the silicon nitride capping structure 41 (that includes silicon nitride) to contact the second-conductivity-type germanium-containing region 302 .
- a silicon-containing capping structure ( 342 or 41 ) may be located on a top surface of the germanium-containing well 30 .
- the silicon-containing capping structure ( 342 or 41 ) includes a silicon-containing diffusion barrier material, which may be silicon or silicon nitride. If the silicon-containing capping structure ( 342 or 41 ) include silicon (comprising the second-conductivity-type silicon region 342 ), the atomic percentage of silicon in the silicon-containing capping structure (comprising a second-conductivity-type silicon region 342 ) may be greater than 98%, and may be greater than 99%, the balance being electrical dopants of the second conductivity type.
- the silicon-containing capping structure (comprising a silicon nitride capping structure 41 ) includes silicon nitride
- the atomic percentage of silicon may be about 3/7 ⁇ 100%, which is about 42.8%.
- the silicon-containing capping structure ( 342 or 41 ) of the embodiments of the present disclosure may include silicon at an atomic percentage greater than 42%.
- FIGS. 3A and 3B are vertical cross-sectional views of configurations of a second exemplary structure including a pixel of an image sensor according to a second embodiment of the present disclosure.
- FIG. 3A illustrates a configuration in which the silicon-containing capping structure comprises a second-conductivity-type silicon region 342
- FIG. 3B illustrates a configuration in which the silicon-containing capping structure comprises a silicon nitride capping structure 41 .
- the photovoltaic junction of each subpixel may be formed in a first semiconductor substrate 110 .
- the first semiconductor substrate 110 may be a single crystalline silicon substrate that may be the same as the single crystalline silicon substrate 10 as described above.
- First dielectric material layers 190 containing a first subset of the metal interconnect structures 80 may be formed over the first semiconductor substrate 110 .
- First bonding pads 188 may be formed on the first dielectric material layers 190 .
- Through-substrate via structures 104 laterally surrounded by a respective insulating spacer 102 may be formed in the first semiconductor substrate 110 .
- the sensing circuit of each subpixel may be formed on a second semiconductor substrate 210 , which may be a silicon substrate.
- the transfer transistor 610 for the photodetector may be formed on the second semiconductor substrate 210 .
- Second dielectric material layers 290 containing a second subset of the metal interconnect structures 80 may be formed over the second semiconductor substrate 210 .
- Second bonding pads 288 may be formed on the second dielectric material layers 290 .
- a first wafer including the first semiconductor substrate 110 and the first dielectric material layers 190 may be bonded to a second wafer including the second semiconductor substrate 210 and the second dielectric material layers 290 by wafer-to-wafer bonding.
- the first bonding pads 188 and be aligned to, and disposed upon, the second bonding pads 288 , and metal-to-metal bonding may be induced on each mating pair of a first bonding pad 188 and a second bonding pad 288 .
- the backside of the first semiconductor substrate 110 may be thinned to physically expose top surfaces of the through-substrate via structures 104 .
- a backside dielectric layer 106 may be formed on the backside of the first semiconductor substrate 110 , and external bonding pads 198 may be formed through the backside dielectric layer 106 on a backside surface of a respective one of the through-substrate via structures 104 .
- the bonded assembly of the first wafer and the second wafer may be diced to provide bonded semiconductor dies.
- Each bonded semiconductor die may include a first semiconductor die 710 including diced portions of the first semiconductor substrate 110 and the first dielectric material layers 190 , and a second semiconductor die 720 including diced portions of the second semiconductor substrate 210 and the second dielectric material layers 290 .
- FIGS. 4A and 4B are vertical cross-sectional views of configurations of a third exemplary structure including a pixel of an image sensor according to a second embodiment of the present disclosure.
- FIG. 4A illustrates a configuration in which the silicon-containing capping comprises a second-conductivity-type silicon region 342
- FIG. 4B illustrates a configuration in which the silicon-containing capping structure comprises a silicon nitride capping structure 41 .
- the photovoltaic junction of each subpixel and at least a subset of the sensing circuit of each subpixel may be formed in a first semiconductor substrate 110 , which is a single crystalline silicon substrate that may be the same as the single crystalline silicon substrate 10 as described above.
- First dielectric material layers 190 containing a first subset of the metal interconnect structures 80 may be formed over the first semiconductor substrate 110 .
- Through-substrate via structures 104 laterally surrounded by a respective insulating spacer 102 may be formed in the first semiconductor substrate 110 .
- Additional semiconductor devices such as p-type field effect transistors 630 and n-type field effect transistors may be formed on a second semiconductor substrate 210 , which may be a silicon substrate.
- the additional semiconductor devices may, or may not, include components of a sensing circuit for a photovoltaic junction in the first semiconductor substrate 110 .
- the additional semiconductor devices may include additional semiconductor devices that may be used in conjunction with the subpixels of an image sensor.
- the additional semiconductor devices may include memory devices or logic devices that may support operation of the image sensor.
- the devices on the first semiconductor substrate 110 and the devices on the second semiconductor substrate 210 may be connected to each other front-to-front, back-to-back, or front-to-back.
- the illustrated configurations include embodiments in which the backside of the first semiconductor substrate 110 is thinned, a backside dielectric layer 106 is deposited on the backside of the first semiconductor substrate 110 , and first bonding pads 188 are formed through the backside dielectric layer 106 on bottom surfaces of the through-substrate via structures 104 .
- the first bonding pads 188 are bonded to second bonding pads 288 provided in the second dielectric material layers 290 overlying the second semiconductor substrate 210 .
- any type of photovoltaic junction may be formed within, or around, the germanium-containing well 30 .
- the photovoltaic junction may be a vertical p-i-n junction, a lateral p-i-n junction, a vertical p-n junction, or a lateral p-n junction.
- the configuration of a pinned diode using an pinning layer or the configuration of a single-photon avalanche diode (SPAD) may also be used.
- photovoltaic junction formed within, or around, a germanium-containing well 30 While specific embodiments of the photovoltaic junction formed within, or around, a germanium-containing well 30 are described herein, it is to be understood that the scope of the present disclosure is not limited by any particular configuration of a photovoltaic junction provided that a germanium-containing well 30 is used as a component of a photovoltaic junction.
- the germanium-containing material of the germanium-containing well 30 may be doped germanium or a doped silicon-germanium alloy including germanium at an atomic percentage greater than 50%.
- the germanium-containing well 30 may be completely encapsulated by a combination of the first-conductivity-type silicon region 21 and the silicon-containing capping structure ( 342 or 41 ), or by a combination of the silicon liner 32 and the silicon-containing capping structure ( 342 or 41 ).
- the germanium-containing well 30 may remain free of oxidation.
- a semiconductor structure including a photodetector comprises: germanium-containing well 30 embedded within a single crystalline silicon substrate ( 10 , 110 ) and extending to a proximal horizontal surface 7 of the single crystalline silicon substrate ( 9 , 10 ), wherein the germanium-containing well 30 includes germanium at an atomic percentage greater than 50% (such as from 50% to 100%); and a silicon-containing capping structure ( 342 or 41 ) located on a top surface of the germanium-containing well 30 and including silicon atoms at an atomic percentage greater than 42%.
- a portion of the single crystalline silicon substrate ( 10 , 110 ) that surrounds the trench 69 comprises a first-conductivity-type silicon region 21 .
- the germanium-containing well 30 comprises a second-conductivity-type germanium-containing region 302 .
- the photovoltaic junction may comprise a p-i-n junction ( 21 , 308 , 302 ); and the germanium-containing well 30 comprises an intermediate germanium-containing region 308 having an atomic concentration of dopants in a range from 1.0 ⁇ 10 13 /cm 3 to 1.0 ⁇ 10 18 /cm 3 , contacting the second-conductivity-type germanium-containing region 302 , and laterally surrounded by the first-conductivity-type silicon region 21 .
- the semiconductor structure may comprise a single crystalline silicon liner 32 contacting an inner sidewall of the first-conductivity-type silicon region 302 , laterally surrounding the germanium-containing well 30 , and epitaxially aligned to the single crystalline silicon substrate ( 9 , 10 ).
- the germanium-containing well 30 comprises a single crystalline germanium-containing semiconductor material in epitaxial alignment with the single crystalline silicon liner 32 and the single crystalline silicon substrate ( 9 , 10 ).
- the first-conductivity-type silicon region 21 continuously surrounds the germanium-containing well 30 and comprises a first horizontally-extending portion that contacts a bottom surface of the germanium-containing well 30 and a second horizontally-extending portion that extends outward from the germanium-containing well 30 under the proximal horizontal surface 7 of the single crystalline silicon substrate ( 9 , 10 ).
- the semiconductor structure may comprise: a sensing circuit located on the single crystalline silicon substrate ( 10 , 110 ) or on a semiconductor substrate 210 bonded to the single crystalline silicon substrate ( 10 , 110 ) through dielectric material layers ( 190 , 290 ) and bonding pads located ( 188 , 288 ) within the dielectric material layers ( 190 , 290 ); and metal interconnect structures 80 that provide electrical connection between the second-conductivity-type germanium-containing region 302 and the sensing circuit.
- FIG. 5A-5F are sequential vertical cross-sectional views of a fourth exemplary structure during formation of a pixel of an image sensor according to a fourth embodiment of the present disclosure.
- the fourth exemplary structure illustrated in FIG. 5A includes a first semiconductor substrate 110 , which may be a single crystalline silicon substrate.
- the first semiconductor substrate 110 may be the same as the single crystalline silicon substrate 10 in the first exemplary structure.
- a proximal horizontal surface 7 may be located on the top side of the first semiconductor substrate 110 .
- a dielectric mask layer 12 may be formed on the proximal horizontal surface, and the a trench 69 may be formed in an upper portion of the first semiconductor substrate 110 through an opening in the dielectric mask layer 12 .
- the fourth exemplary structure of FIG. 5A may be derived from the first exemplary structure of FIG. 2B by omitting formation of the first doped photodiode contact region 28 , the second-conductivity-type doped well 60 , and the doped well contact regions 68 .
- the processing steps of FIGS. 2D, 2E, 2F, and 2G may be sequentially performed to form a silicon liner 32 and a germanium-containing well 30 .
- the silicon liner 32 may have the same thickness and the same material composition as in the first embodiment.
- the germanium-containing well 30 may have the same material composition and the same crystallinity as in the first embodiment.
- the germanium-containing well 30 may be single crystalline and epitaxially aligned to the single crystalline semiconductor substrate of the first semiconductor substrate 110 , or may be polycrystalline or amorphous.
- silicon may be deposited on the top surface of the germanium-containing well 30 .
- deposited silicon may include undoped silicon.
- undoped silicon refers to silicon without intentionally introduced dopants during a deposition process.
- the level of electrical dopants in undoped silicon may at a residual level.
- undoped silicon may be intrinsic, or may include electrical dopants at a dopant concentration less than 1.0 ⁇ 10 16 /cm 3 , such as from 1.0 ⁇ 10 12 /cm 3 to 1.0 ⁇ 10 15 /cm 3 .
- Undoped silicon provides relatively high resistivity, and is effective in suppressing leakage current.
- Undoped silicon may be grown by a selective deposition process or a non-selective deposition process. In embodiments in which a non-selective deposition process is used, excess portions of the deposited undoped silicon material may be removed from above the horizontal plane including the top surface of the dielectric mask layer 12 . Remaining portions of the deposited undoped silicon comprises a passivation silicon region 340 . The top surface of the passivation silicon region 340 may be within the horizontal plane including the top surface of the dielectric mask layer 12 . In embodiments in which undoped silicon is deposited using a selective deposition process, a planarization process may not be necessary. The passivation silicon region 340 functions as a silicon-containing capping structure for the germanium-containing well 30 .
- dopants of the first conductivity type may be implanted into a portion of the passivation silicon region 340 and an upper portion of the germanium-containing well 30 using a first masked ion implantation process.
- the implanted portion of the passivation silicon region 340 comprises a first-conductivity-type silicon region 341
- the implanted portion of the germanium-containing well 30 comprises a first-conductivity-type germanium-containing region 301 .
- the first-conductivity-type silicon region 341 and the first-conductivity-type germanium-containing region 301 may be heavily doped.
- each of the first-conductivity-type silicon region 341 and the first-conductivity-type germanium-containing region 301 may include electrical dopants of the first conductivity type at an atomic concentration in a range from 1.0 ⁇ 10 19 /cm 3 to 2.0 ⁇ 10 21 /cm 3 .
- Dopants of the second conductivity type may be implanted into another portion of the passivation silicon region 340 and another upper portion of the germanium-containing well 30 using a second masked ion implantation process.
- the implanted portion of the passivation silicon region 340 comprises a second-conductivity-type silicon region 342
- the implanted portion of the germanium-containing well 30 comprises a second-conductivity-type germanium-containing region 302 .
- the second-conductivity-type silicon region 342 and the second-conductivity-type germanium-containing region 302 may be heavily doped.
- each of the second-conductivity-type silicon region 342 and the second-conductivity-type germanium-containing region 302 may include electrical dopants of the second conductivity type at an atomic concentration in a range from 1.0 ⁇ 10 19 /cm 3 to 2.0 ⁇ 10 21 /cm 3 .
- the remaining portion of the passivation silicon region 340 may provide lateral isolation between the first-conductivity-type silicon region 341 and the second-conductivity-type silicon region 342 .
- the combination of the passivation silicon region 340 , the first-conductivity-type silicon region 341 , and the second-conductivity-type silicon region 342 comprises a silicon capping structure 34 , which is a silicon-containing capping structure.
- the unimplanted portion of the germanium-containing well 30 is herein referred to as an intermediate germanium-containing region 308 .
- the intermediate germanium-containing region 308 may be intrinsic or may have a doping with an atomic concentration of dopants in a range from 1.0 ⁇ 10 13 /cm 3 to 1.0 ⁇ 10 18 /cm 3 .
- the intermediate germanium-containing region 308 provides lateral spacing between the first-conductivity-type germanium-containing region 301 and the second-conductivity-type germanium-containing region 302 .
- the combination of the intermediate germanium-containing region 308 , the first-conductivity-type germanium-containing region 301 , and the second-conductivity-type germanium-containing region 302 comprises the germanium-containing well 30 .
- the dielectric mask layer 12 may be removed, for example, by performing an isotropic etch process such as a wet etch process.
- First dielectric material layers 190 , through-substrate via structures 104 , insulating spacers 102 that laterally surrounds the through-substrate via structures 104 , metal interconnect structures 80 , and first bonding pads 188 may be formed over the first semiconductor substrate 110 .
- sensing circuits for photodetectors provided on the first semiconductor substrate 110 of FIG. 5G may be formed on a second semiconductor substrate 210 .
- An array of sensing circuits may be formed for an array of photodetectors provided on the first semiconductor substrate 110 of FIG. 5G .
- each sensing circuit for a photodetector may include a transfer transistor 610 including a source region 48 and a floating drain region 46 , and additional field effect transistors that may include p-type field effect transistors 630 and n-type field effect transistors.
- the sensing circuit of FIG. 5F as provided on the second semiconductor substrate 210 may be the same as the sensing circuit of FIG. 2K as provided on the single crystalline silicon substrate 10 .
- Metal interconnect structures 80 formed within second dielectric material layers 290 may be formed over the second semiconductor substrate 210 to provide electrical wiring to and from the various semiconductor devices on the second semiconductor substrate 210 .
- Second bonding pads 288 may be formed on the second dielectric material layers 290 .
- a first wafer including the first semiconductor substrate 110 and the first dielectric material layers 190 may be bonded to a second wafer including the second semiconductor substrate 210 and the second dielectric material layers 290 by wafer-to-wafer bonding.
- the first bonding pads 188 and be aligned to, and disposed upon, the second bonding pads 288 , and metal-to-metal bonding may be induced on each mating pair of a first bonding pad 188 and a second bonding pad 288 .
- the backside of the first semiconductor substrate 110 may be thinned to physically expose top surfaces of the through-substrate via structures 104 .
- a backside dielectric layer 106 may be formed on the backside of the first semiconductor substrate 110 , and external bonding pads 198 may be formed through the backside dielectric layer 106 on a backside surface of a respective one of the through-substrate via structures 104 .
- the bonded assembly of the first wafer and the second wafer may be diced to provide bonded semiconductor dies.
- Each bonded semiconductor die may include a first semiconductor die 710 including diced portions of the first semiconductor substrate 110 and the first dielectric material layers 190 , and a second semiconductor die 720 including diced portions of the second semiconductor substrate 210 and the second dielectric material layers 290 .
- FIGS. 6A-6F are vertical cross-sectional views of alternative configurations of the fourth exemplary structure according to the fourth embodiment of the present disclosure.
- a first alternative configuration of the fourth exemplary structure may be derived from the fourth exemplary structure of FIG. 5F by omitting formation of the silicon liner 32 .
- the germanium-containing well 30 may be formed directly on sidewalls and a horizontal surface of the trench 69 . Thus, the germanium-containing well 30 may directly contact the single crystalline silicon substrate comprising the first semiconductor substrate 110 .
- a second alternative configuration of the fourth exemplary structure may be derived from the first alternative configuration of the fourth exemplary structure of FIG. 6A by forming a silicon nitride capping structure 41 in lieu of a silicon capping structure 34 .
- each of the first-conductivity-type germanium-containing region 301 and the second-conductivity-type germanium-containing region 302 may be directly contacted by a respective one of the metal interconnect structures 80 , such as a respective metal via structure 82 .
- a third alternative configuration of the fourth exemplary structure may be derived from the fourth exemplary structure of FIG. 5F by forming a plurality of first-conductivity-type germanium-containing regions 301 and/or a plurality of second-conductivity-type germanium-containing region 302 .
- a plurality of first-conductivity-type silicon regions 341 and/or a plurality of second-conductivity-type silicon regions 342 may be formed.
- a fourth alternative configuration of the fourth exemplary structure may be derived from the first alternative configuration of the fourth exemplary structure of FIG. 6A by forming a plurality of first-conductivity-type germanium-containing regions 301 and/or a plurality of second-conductivity-type germanium-containing region 302 .
- a plurality of first-conductivity-type silicon regions 341 and/or a plurality of second-conductivity-type silicon regions 342 may be formed.
- a fifth alternative configuration of the fourth exemplary structure may be derived from the fourth exemplary structure of FIG. 5F or from the third alternative configuration of the fourth exemplary structure of FIG. 6C by doping the intermediate germanium-containing region 308 with dopants of the first conductivity type to form an additional first-conductivity-type germanium-containing region 305 .
- the atomic concentration of dopants of the first conductivity type within the additional first-conductivity-type germanium-containing region 305 may be in a range from 1.0 ⁇ 10 17 /cm 3 to 1.0 ⁇ 10 19 /cm 3 , although lesser and greater atomic concentrations may also be used.
- the photovoltaic junction may be a p-n junction.
- a sixth alternative configuration of the fourth exemplary structure may be derived from the fifth alternative configuration of the fourth exemplary structure of FIG. 6E by doping the intermediate germanium-containing region 308 with dopants of the first conductivity type at an atomic concentration on par with the atomic concentration of dopants of the first conductivity type in the first-conductivity-type germanium-containing regions 301 .
- the first-conductivity-type germanium-containing region 301 replaces the intermediate germanium-containing region 308 .
- a p-n junction may be formed between the first-conductivity-type germanium-containing regions 301 and the second-conductivity-type germanium-containing region 302 .
- the germanium-containing well 30 includes, and/or consists of, the first-conductivity-type germanium-containing regions 301 and the second-conductivity-type germanium-containing region 302 .
- FIG. 7A-7G are sequential vertical cross-sectional views of a fifth exemplary structure during formation of a pixel of an image sensor according to a fifth embodiment of the present disclosure.
- a fifth exemplary structure according to a fifth embodiment of the present disclosure may be formed by providing a semiconductor substrate 500 , which may include a single crystalline silicon substrate 10 .
- the single crystalline silicon substrate 10 may be the same as in the first exemplary structure.
- Semiconductor devices for forming a sensing circuit may be formed on, and/or in, an upper portion of the single crystalline silicon substrate 10 .
- the semiconductor devices may include a transfer transistor 610 , p-type field effect transistors 630 , and n-type field effect transistors 640 .
- the transfer transistor 610 may be formed in the photodetector region 510 , and the p-type field effect transistors 630 and the n-type field effect transistors 640 may be formed in the sensing circuit region 520 .
- the various field effect transistors ( 610 , 630 , 640 ) may be the same as in the first exemplary structure.
- a dielectric material such as silicon oxide may be deposited over the semiconductor devices on the proximal horizontal surface of the single crystalline silicon substrate 10 , and may be planarized to provide a dielectric mask layer 92 having a horizontal top surface.
- the thickness of the dielectric mask layer 92 may be greater than the height of the gate electrodes 52 , and the dielectric mask layer 92 may cover the gate electrodes 52 .
- a photoresist layer 67 may be applied over the dielectric mask layer 12 , and may be lithographically patterned to form an opening within the photodetector region 510 .
- An anisotropic etch process may be performed to transfer the pattern of the opening in the photoresist layer 67 through the dielectric mask layer 92 and into an upper portion of the single crystalline silicon substrate 10 .
- a trench 69 may be formed in the upper portion of the single crystalline silicon substrate 10 . The depth of the trench 69 may be greater than, the same as, or less than, the depth of the second-conductivity-type doped well 60 .
- the depth of the trench 69 may be in a range from 0.5 micron to 10 microns, such as from 1 micron to 6 microns, although lesser and greater depths may also be used.
- the lateral dimension of the trench 69 may be in a range from 0.5 micron to 30 microns, such as from 1 micron to 15 microns.
- the lateral dimension of the trench 69 may be the diameter or the major axis of the horizontal cross-sectional shape of the trench 69 in embodiments in which the trench 69 has a circular or an elliptical horizonal cross-sectional shape, or may be the length of a side of a rectangular shape in embodiments in which the horizontal cross-sectional shape of the trench 69 is the rectangular shape.
- the photoresist layer 67 may be subsequently removed, for example, by ashing.
- the processing steps of FIGS. 2D and 2E may be performed to form a silicon liner 32 and a germanium-containing material layer 30 L.
- the silicon liner 32 may have the same thickness, the same crystallinity, and/or the same material composition as in the first exemplary structure.
- the germanium-containing material layer 30 L may have the same crystallinity and the same material composition as in the first exemplary structure.
- FIGS. 2F and 2G may be performed to form a germanium-containing well 30 .
- the processing steps of FIG. 2H may be performed to form a passivation silicon region 340 .
- the passivation silicon region 340 may have a top surface within a horizontal plane including the top surface of the dielectric mask layer 92 .
- the processing steps of FIG. 5D may be performed to form a first-conductivity-type silicon region 341 , a first-conductivity-type germanium-containing region 301 , a second-conductivity-type silicon region 342 , and a second-conductivity-type germanium-containing region 302 .
- the remaining portion of the passivation silicon region 340 may provide lateral isolation between the first-conductivity-type silicon region 341 and the second-conductivity-type silicon region 342 .
- the combination of the passivation silicon region 340 , the first-conductivity-type silicon region 341 , and the second-conductivity-type silicon region 342 comprises a silicon capping structure 34 , which is a silicon-containing capping structure.
- the combination of the intermediate germanium-containing region 308 , the first-conductivity-type germanium-containing region 301 , and the second-conductivity-type germanium-containing region 302 comprises the germanium-containing well 30 .
- any of the p-i-n junction structures illustrated in FIGS. 6A-6D or the p-n junction structures illustrated in FIGS. 6E and 6F may be formed instead of the p-i-n junction illustrated in FIG. 6F .
- any p-i-n junction or any p-n junction described above may be formed in the trench 69 .
- additional dielectric material layers 94 and metal interconnect structures 80 may be formed to provide electrical connection to and from the various nodes of the semiconductor devices and the photodetector.
- the second-conductivity-type germanium-containing region 302 may be connected to the source region 48 of the transfer transistor 610 through a subset of the metal interconnect structures and the second-conductivity-type silicon region 342 .
- the first-conductivity-type germanium-containing region 301 may be suitably biased by a biasing circuit through another subset of metal interconnect structures 80 .
- FIG. 7H is a vertical cross-sectional view of an alternative configuration of the fifth exemplary structure according to the fifth embodiment of the present disclosure.
- an alternative configuration of the fifth exemplary structure may be derived from the fifth exemplary structure of FIG. 7G by forming a silicon nitride capping structure 41 in lieu of a silicon capping structure 34 .
- each of the first-conductivity-type germanium-containing region 301 and the second-conductivity-type germanium-containing region 302 may be directly contacted by a respective one of the metal interconnect structures 80 , such as a respective metal via structure 82 .
- any type of photovoltaic junction may be formed within the germanium-containing well 30 .
- the photovoltaic junction may be a vertical p-i-n junction, a lateral p-i-n junction, a vertical p-n junction, or a lateral p-n junction.
- the configuration of a pinned diode using an pinning layer or the configuration of a single-photon avalanche diode (SPAD) may also be used.
- photovoltaic junction formed within a germanium-containing well 30 While specific embodiments of the photovoltaic junction formed within a germanium-containing well 30 are described herein, it is to be understood that the scope of the present disclosure is not limited by any particular configuration of a photovoltaic junction provided that a germanium-containing well 30 is used as a component of a photovoltaic junction.
- the germanium-containing material of the germanium-containing well 30 may be doped germanium or a doped silicon-germanium alloy including germanium at an atomic percentage greater than 50%.
- the germanium-containing well 30 may be completely encapsulated by a combination of the first-conductivity-type silicon region 21 and the silicon-containing capping structure ( 34 or 41 ), or by a combination of the silicon liner 32 and the silicon-containing capping structure ( 34 or 41 ).
- physical contact between the germanium-containing well 30 and the dielectric material layers 90 or any other oxygen-containing component within the fourth or fifth exemplary structure may be avoided, and the germanium-containing well 30 may remain free of oxidation.
- a semiconductor structure including a photodetector comprises: a germanium-containing well 30 embedded in a single crystalline silicon substrate ( 10 , 110 ) and extending to a proximal horizontal surface 7 of the single crystalline silicon substrate ( 10 , 110 ), wherein the germanium-containing well 30 includes germanium at an atomic percentage greater than 50%; and a silicon-containing capping structure ( 34 or 41 ) located on a top surface of the germanium-containing well 30 and including silicon atoms at an atomic percentage greater than 42%.
- the silicon-containing capping structure ( 34 or 41 ) may comprise a silicon capping structure 34 consisting essentially of doped silicon, or as a silicon nitride capping structure 41 consisting essentially of silicon nitride.
- the germanium-containing well 30 comprises a photovoltaic junction including a first-conductivity-type germanium-containing region 301 and a second-conductivity-type germanium-containing region 302 .
- the photovoltaic junction comprises a p-i-n junction
- the germanium-containing well 30 comprises an intermediate germanium-containing region 308 having an atomic concentration of dopants in a range from 1.0 ⁇ 10 13 /cm 3 to 1.0 ⁇ 10 17 /cm 3 and contacting the first-conductivity-type germanium-containing region 301 and the second-conductivity-type germanium-containing region 302 .
- the silicon-containing capping structure 34 comprises: a first-conductivity-type silicon region 341 contacting the first-conductivity-type germanium-containing region 301 ; and a second-conductivity-type silicon region 342 contacting the second conductivity type germanium-containing region 302 .
- the silicon-containing capping structure 34 comprises an passivation silicon region 340 having an atomic concentration of dopants in a range from 1.0 ⁇ 10 13 /cm 3 to 1.0 ⁇ 10 17 /cm 3 and located between the first-conductivity-type silicon region 341 and the second-conductivity-type silicon region 342 .
- the germanium-containing well 30 comprises a single crystalline germanium-containing semiconductor material in epitaxial alignment with the single crystalline silicon substrate ( 10 , 110 ).
- a proximal surface of the silicon-containing capping structure ( 34 or 41 ) is in contact with the germanium-containing well 30 ; and a distal surface of the silicon-containing capping structure ( 34 or 41 ) is vertically offset away from a horizontal plane including a proximal horizontal surface 7 of the single crystalline silicon substrate ( 10 , 110 ).
- the photovoltaic junction comprises a p-n junction; and the first-conductivity-type germanium-containing region 301 contacts the second-conductivity-type germanium-containing region 302 .
- the semiconductor structure may comprise a sensing circuit comprising field effect transistors located on the single crystalline silicon substrate ( 10 , 110 ); and dielectric material layers ⁇ 90 , 190 , ( 92 , 94 ) ⁇ located on the proximal horizontal surface 7 of the single crystalline silicon substrate ( 10 , 110 ) and containing metal interconnect structures 80 .
- a subset of the metal interconnect structures 80 may provide an electrically conductive path between the second-conductivity-type germanium-containing region 302 and a source/drain region of one of the field effect transistors (such as a source region 48 of a transfer transistor 610 ).
- the semiconductor structure may comprise: first dielectric material layers 190 located on the proximal horizontal surface 7 of the single crystalline silicon substrate 110 and containing first metal interconnect structures 80 and first bonding pads 188 ; a semiconductor die 720 comprising a semiconductor substrate 210 , a sensing circuit comprising field effect transistors that are located on the semiconductor substrate 210 , and second dielectric material layers 290 located on the semiconductor substrate 210 and containing second metal interconnect structures 80 and second bonding pads 288 therein.
- the second bonding pads 288 may be bonded to a respective one of the first bonding pads 188 , and a subset of the first metal interconnect structures 80 and the second metal interconnect structures 80 provides an electrically conductive path between the second-conductivity-type germanium-containing region 302 and a source/drain region of one of the field effect transistors in the sensing circuit (such as a source region 48 of a transfer transistor 610 ).
- a first process flow diagram 800 illustrates an exemplary process sequence for forming an image sensor according to an embodiment of the present disclosure.
- a dielectric mask layer 12 , 92
- a trench 69 may be etched in the single crystalline silicon substrate ( 10 , 110 ) through an opening in the dielectric mask layer ( 12 , 92 ).
- a germanium-containing well 30 may be formed within the trench 69 .
- the germanium-containing well 30 includes germanium at an atomic percentage greater than 50%.
- the germanium-containing well 30 may be single crystalline, and may be epitaxially aligned to the single crystalline silicon substrate ( 10 , 110 ). Referring to step 840 and FIGS.
- a silicon-containing capping structure ( 34 or 41 ) may be formed on the top surface of the germanium-containing well 30 .
- a photovoltaic junction may be formed within, or across, the trench 69 by implanting dopants of a first conductivity type and dopants of a second conductivity type.
- a second process flow diagram 900 illustrates an exemplary process sequence for forming an image sensor illustrated in FIG. 2K or in FIG. 2L .
- a single crystalline silicon substrate 10 may be provided.
- a patterned dielectric mask layer 12 may be formed on a top surface of the single crystalline silicon substrate 10 , and a trench 69 may be formed in the upper portion of the single crystalline silicon substrate 10 employing the patterned dielectric mask layer 12 as an etch mask.
- a first-conductivity-type silicon region 21 may be formed around the trench 69 within the single crystalline silicon substrate 10 , for example, by ion implantation of dopants of a first conductivity type.
- a silicon liner 32 may be optionally grown from physically exposed surfaces of the first-conductivity-type silicon region 21 .
- a germanium-containing material layer 30 L may be formed in the trench 69 and over the single-crystalline silicon substrate ( 9 , 10 ).
- an epitaxial deposition process may be performed to grow a single crystalline germanium-containing material inside the trench 69 to form the germanium-containing material layer 30 L.
- a germanium-containing well 30 may be formed by performing a planarization process on the germanium-containing material layer 30 L. Referring to step 927 and FIG. 2G , the germanium-containing well 30 may be optionally vertically recessed. Referring to step 928 and FIGS. 2H and 2L , a silicon-containing capping structure (such as a passivation silicon region 340 illustrated in FIG. 2H or a silicon nitride capping structure 41 illustrated in FIG. 2L ) may be formed on a top surface of the germanium-containing well 30 . Referring to step 929 and FIGS.
- a second-conductivity-type germanium-containing region 302 may be formed by doping an upper portion of the germanium-containing well 30 with dopants of a second conductivity type.
- field effect transistors ( 610 , 630 , 640 ) may be formed in a photodetector region 510 and in a sensing circuit region 520 on the single crystalline silicon substrate 10 .
- dielectric material layers 90 and metal interconnect structures 80 may be formed over the field effect transistors ( 610 , 630 , 640 ).
- a third process flow diagram 1000 illustrates an exemplary process sequence for forming an image sensor illustrated in FIG. 3A or in FIG. 3B .
- a photovoltaic junction of a subpixel may be formed in a first semiconductor substrate 110 by performing the processing steps of FIGS. 2A-2I, 2K, and 2L , which correspond to the processing steps 921 - 929 and 930 in the second process flow diagram of FIG. 9 .
- field effect transistors ( 610 , 630 , 640 ) are not present on the first semiconductor substrate 110 as illustrated in FIGS. 3A and 3B .
- the sensing circuit of the subpixel may be formed on a second semiconductor substrate 210 , which may be a silicon substrate.
- the transfer transistor 610 for each photodetector may be formed on the second semiconductor substrate 210 .
- a first wafer including the first semiconductor substrate 110 and the first dielectric material layers 190 may be bonded to a second wafer including the second semiconductor substrate 210 and the second dielectric material layers 290 by wafer-to-wafer bonding. Subsequently, the first semiconductor substrate 110 may be thinned, and the bonded assembly can be subsequently diced.
- FIG. 3A illustrates an embodiment in which a silicon-containing capping structure comprises a passivation silicon region 340
- FIG. 3B illustrates an embodiment in which the silicon-containing capping structure comprises a silicon nitride capping structure 41 .
- a fourth process flow diagram 1100 illustrates an exemplary process sequence for forming an image sensor illustrated in FIG. 4A or in FIG. 4B .
- a photovoltaic junction of a subpixel may be formed in a first semiconductor substrate 110 by performing the processing steps of FIGS. 2A-2L .
- field effect transistors are formed on the first semiconductor substrate 110 as illustrated in FIGS. 4A and 4B .
- additional field effect transistors ( 630 , 640 ) may be formed on a second semiconductor substrate 210 , which may be a silicon substrate.
- the transfer transistor 610 for photodetector may be formed on the first semiconductor substrate 110 , and field effect transistors for the sensing circuit can be formed on the first semiconductor substrate 110 and/or on the second semiconductor substrate 210 .
- a first wafer including the first semiconductor substrate 110 and the first dielectric material layers 190 may be bonded to a second wafer including the second semiconductor substrate 210 and the second dielectric material layers 290 by wafer-to-wafer bonding.
- the first semiconductor substrate 110 may be thinned, and the bonded assembly can be subsequently diced.
- FIG. 4A illustrates an embodiment in which a silicon-containing capping structure comprises a passivation silicon region 340
- FIG. 4B illustrates an embodiment in which the silicon-containing capping structure comprises a silicon nitride capping structure 41 .
- a fifth process flow diagram 1200 illustrates an exemplary process sequence for forming an image sensor illustrated in in FIGS. 5F and 6A-6F .
- a trench 69 may be formed in an upper portion of a first semiconductor substrate 110 through an opening in a dielectric mask layer 12 .
- a silicon liner 32 may be formed as illustrated in FIGS. 5F, 6C, 6E , or may be omitted as illustrated in FIGS. 6A, 6B, 6D, and 6F .
- an optional silicon liner 32 and a germanium-containing well 30 can be formed.
- a passivation silicon region 340 can be formed on a top surface of the germanium-containing well 30 within an opening in the dielectric mask layer 12 .
- electrical dopants can be implanted into upper portions of the germanium-containing well 30 and into the passivation silicon region 340 to form a p-i-n junction as illustrated in FIGS. 5D and 6A-6D , or to form a p-n junction as illustrated in FIGS.
- the dielectric mask layer 12 may be removed, and first dielectric material layers 190 , metal interconnect structures 80 , and first bonding pads 188 may be formed over the first semiconductor substrate 110 .
- a first wafer including the first semiconductor substrate 110 and the first dielectric material layers 190 can be bonded to a second wafer including the second semiconductor substrate 210 and the second dielectric material layers 290 by wafer-to-wafer bonding. Subsequently, the first semiconductor substrate 110 may be thinned, and the bonded assembly can be subsequently diced.
- a sixth process flow diagram 1300 illustrates an exemplary process sequence for forming an image sensor illustrated in FIGS. 7G and 7H .
- semiconductor devices of a sensing circuit may be formed on, and/or in, an upper portion of a single crystalline silicon substrate 10 .
- a trench 69 may be formed through a dielectric mask layer 92 into an upper portion of the single crystalline silicon substrate 10 .
- an optional silicon liner 32 and a germanium-containing material layer 30 L can be formed in the trench 69 .
- a germanium-containing well 30 may be formed in the trench 60 by patterning the germanium-containing material layer 30 L.
- a silicon-containing capping structure comprising a passivation silicon region 34 or a silicon nitride capping structure 41 can be formed on top of the germanium-containing well 30 .
- ion implantation processes may be performed to form a p-i-n junction or a p-n junction in the trench 69 .
- additional dielectric material layers 94 and metal interconnect structures 80 may be formed over the single crystalline silicon substrate 10 to provide electrical connection to and from the various nodes of the semiconductor devices and the photodetector.
- the germanium-based photodetector of the present disclosure may provide high quantum efficiency in the infrared wavelength range. Further, the germanium-based photodetector of the present disclosure may provide higher operation speed and fast response for high-speed motion applications such as high-speed distance measurement compared to silicon-based photodetectors.
- the germanium-based photodetector of the present disclosure is integrated with standard CMOS logic devices (such as CMOS field effect transistors) to provide incorporation into a semiconductor die.
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Abstract
Description
- This application claims priority to U.S. Provisional Patent Application No. 63/031,933 entitled “Germanium-Containing Photodetector and Method of Forming the Same” filed on May 29, 2020, the entire contents of which are hereby incorporated by reference for all purposes.
- Semiconductor image sensors may be used to sense electromagnetic radiation such as visible range light, infrared radiation, and/or ultraviolet light. Complementary metal-oxide-semiconductor (CMOS) image sensors (CIS) and charge-coupled device (CCD) sensors may be used in various applications such as digital cameras or cameras integrated in mobile devices. These devices utilize an array of pixels (which may include photodiodes and transistors) to detect radiation using photogeneration of electron-hole pairs.
- Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
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FIG. 1A is a plan view of a first configuration for an array of pixels of an image sensor according to an embodiment of the present disclosure. -
FIG. 1B is a plan view of a second configuration for an array of pixels of an image sensor according to another embodiment of the present disclosure. -
FIG. 2A-2K are sequential vertical cross-sectional views of a first exemplary structure during formation of a pixel of an image sensor according to a first embodiment of the present disclosure. -
FIG. 2L is a vertical cross-sectional view of an alternative configuration of the first exemplary structure according to the first embodiment of the present disclosure. -
FIGS. 3A and 3B are vertical cross-sectional views of configurations of a second exemplary structure including a pixel of an image sensor according to a second embodiment of the present disclosure. -
FIGS. 4A and 4B are vertical cross-sectional views of configurations of a third exemplary structure including a pixel of an image sensor according to a second embodiment of the present disclosure. -
FIG. 5A-5F are sequential vertical cross-sectional views of a fourth exemplary structure during formation of a pixel of an image sensor according to a fourth embodiment of the present disclosure. -
FIGS. 6A-6F are vertical cross-sectional views of alternative configurations of the fourth exemplary structure according to the fourth embodiment of the present disclosure. -
FIG. 7A-7G are sequential vertical cross-sectional views of a fifth exemplary structure during formation of a pixel of an image sensor according to a fifth embodiment of the present disclosure. -
FIG. 7H is a vertical cross-sectional view of an alternative configuration of the fifth exemplary structure according to the fifth embodiment of the present disclosure. -
FIG. 8 is a first process flow diagram illustrating an exemplary process sequence for forming an image sensor according to an embodiment of the present disclosure. -
FIG. 9 is a second process flow diagram illustrating an exemplary process sequence for forming an image sensor shown inFIG. 2K or inFIG. 2L . -
FIG. 10 is a third process flow diagram illustrating an exemplary process sequence for forming an image sensor shown inFIG. 3A or inFIG. 3B . -
FIG. 11 is a fourth process flow diagram illustrating an exemplary process sequence for forming an image sensor shown inFIG. 4A or inFIG. 4B . -
FIG. 12 is a fifth process flow diagram illustrating an exemplary process sequence for forming an image sensor shown in inFIGS. 5F and 6A-6F . -
FIG. 13 is a sixth process flow diagram illustrating an exemplary process sequence for forming an image sensor shown inFIGS. 7G and 7H . - The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It is presumed that elements having the same reference numeral have a same material composition.
- Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- Generally, the structures and methods of the present disclosure may be used to manufacture a germanium-based photodetector and/or an image sensor incorporating array of germanium-based photodetectors. Specifically, the structures and methods of the present disclosure may be used to manufacture a germanium-based photodetector formed on a silicon substrate, i.e., a germanium-in-silicon (GiS) photodetector and/or an image sensor including an array of GiS photodetectors. Such a photodetector or an image sensor may provide high quantum efficiency at near-infrared (NIR) spectrum for various sensing applications.
- Generally, silicon-based photodetectors display low sensitivity in the infrared range due to low quantum efficiency. Silicon-based photodetector provides poor optical performance in wavelength ranges greater than 1,000 nm due to low absorption of photons. Germanium provides higher absorption of photons in infrared wavelength ranges, but manufacture of complementary metal oxide semiconductor (CMOS) devices on a germanium substrate pose many challenges.
- According to an aspect of the present disclosure, a germanium-based photodetector may be formed within a silicon substrate to provide use of standard CMOS manufacturing processes on the silicon substrate. According to an aspect of the present disclosure, a germanium-containing material portion including germanium or a silicon-germanium alloy may be passivated by enclosing walls of a silicon substrate around a trench, and by an overlying silicon-containing capping structure, which may include silicon nitride or crystalline silicon.
- Embodiments of the present disclosure provide a controlled height for the germanium-containing material portion relative to a top surface of silicon substrate. For example, a dielectric material layer may be formed with a controlled thickness, and a chemical mechanical planarization may be used to form the germanium-containing material portion with a top surface at the height of the top surface of the dielectric mask layer. The germanium-containing material portion may be formed in a crystalline phase. The germanium-containing material portion may be single crystalline with epitaxial alignment with the single crystalline silicon material in the silicon substrate. In some embodiments, selective epitaxial growth process may be used to maintain epitaxial alignment between the germanium-containing material portion and the single crystalline silicon material of the silicon substrate.
- The silicon-containing capping structure may include silicon. In one embodiment, the silicon material of the silicon-containing capping structure may be formed as a single crystalline silicon material to enhance effectiveness as a passivation structure, i.e., as a diffusion barrier structure. Alternatively, the silicon-containing capping structure may include silicon nitride.
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FIG. 1A is a plan view of a first configuration for an array of pixels of an image sensor according to an embodiment of the present disclosure.FIG. 1B is a plan view of a second configuration for an array of pixels of an image sensor according to another embodiment of the present disclosure. Referring toFIGS. 1A and 1B , a first configuration for anarray 1000 ofpixels 900 of an image sensor and a second configuration of anarray 1000 ofpixels 900 of an image sensor are illustrated in a respective plan view. The image sensor may be a backside illuminated (BSI) image sensor device. However, for simplicity, embodiments of the disclosure are discussed as used in a front-side illuminated (FSI) image sensor. - Each
pixel 900 represents a smallest unit area for the purpose of generating an image from the image sensor. The region including thearray 1000 ofpixels 900 is herein referred to as a pixel array region. Thepixels 900 in the pixel array region may be arranged in rows and columns. For example, the pixel array region may include M rows and N columns, in which M and N are integers in a range from 1 to 216, such as from 28 to 214. The rows ofpixels 900 may be consecutively numbered with integers that range from 1 to M, and the columns ofpixels 900 may be consecutively numbered with integers that range from 1 to N. A pixel Pij refers to apixel 900 in the i-th row and in the j-th column. - Each
pixel 900 includes at least one photodetector that is configured to detect radiation of a given wavelength range. Eachpixel 900 may include a plurality of photodetectors configured to detect radiation of a respective wavelength range, which may be different from each of the plurality of photodetectors. In one embodiment, eachpixel 900 may include a plurality of subpixels, each of which including a respective combination of a photodetector and an electronic circuit configured to detect radiation that impinged into the photodetector. For example, apixel 900 may include a subpixel configured to detect radiation in a red wavelength range (such as a range from 635 nm to 700 nm), a subpixel configured to detect radiation in a green wavelength range (such as a range from 520 nm to 560 nm), and a subpixel configured to detect radiation in a blue wavelength range (such as a range from 450 nm to 490 nm). Such subpixels are referred to as a red subpixel, green subpixel, and a blue subpixel, respectively. - Generally, a
pixel 900 generates information regarding the impinging radiation for a unit detection area. A subpixel generates information regarding the intensity of the impinging radiation within a specific wavelength range as detected within a region of the unit detection area. Amonochromatic pixel 900 may include only a single subpixel. Apixel 900 configured to detect spectral distribution of impinging radiation includes multiple subpixels having at least two different detection wavelength ranges. Photodetectors in a pixel array region may include photodiodes, complimentary metal-oxide-semiconductor (CMOS) image sensors, charged coupling device (CCD) sensors, active sensors, passive sensors, other applicable sensors, or a combination thereof. - A subpixel within an image sensor may be formed using a germanium-containing well formed within a single crystalline silicon substrate as will be described below. While various exemplary structures described below describe only a single subpixel region including a photodetector region including a single germanium-based photodetector and a sensing circuit region containing a sensing circuit for the germanium-based photodetector, it is understood that multiple instances of the subpixel region may be arranged to provide a two-dimensional array of subpixels for an image sensor. Further, it is understood that additional subpixels, such as subpixels that include silicon-based photodetectors, may be optionally incorporated into the image sensor. Thus, embodiments in which instances of the various exemplary structures are multiplied to provide an image sensor including an array of pixels are expressly contemplated for each exemplary structure described below.
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FIG. 2A-2K are sequential vertical cross-sectional views of a first exemplary structure during formation of a pixel of an image sensor according to a first embodiment of the present disclosure. Referring toFIG. 2A , a first exemplary structure according to a first embodiment of the present disclosure is illustrated. The first exemplary structure includes asemiconductor substrate 500 that includes a singlecrystalline silicon substrate 10. The singlecrystalline silicon substrate 10 may have a pair of major horizontal surfaces. The major horizontal surface located on the top side is herein referred to as a proximalhorizontal surface 7. The major horizontal surface located on the backside is herein referred to as a distalhorizontal surface 17. The singlecrystalline silicon substrate 10 may be single crystalline, and may have a doping of a suitable conductivity type, which may be p-type or n-type. In one embodiment, the singlecrystalline silicon substrate 10 may have a doping of a first conductivity type, and may include dopants of the first conductivity type at an atomic concentration in a range from 1.0×1013/cm3 to 1.0×1017/cm3, although lesser and greater dopant concentrations may also be used. - The first exemplary structure includes a
photodetector region 510 in which a germanium-base photodetector is to be subsequently formed, and asensing circuit region 520 in which a sensing circuit for the germanium-based photodetector is to be subsequently formed. In one embodiment, a masked ion implantation processes may be performed to form various doped regions having various depths. For example, a second-conductivity-type doped well 60 having a doping of the second conductivity type may be formed by ion implantation. The second-conductivity-type doped well 60 may be formed to laterally surround an enclosed region of the singlecrystalline silicon substrate 10. The second conductivity type is the opposite of the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The depth of the second-conductivity-type doped well 60 may be in a range from 1 micron to 2 microns, although lesser and greater depths may also be used. The second-conductivity-type doped well 60 may include dopants of the second conductivity type at an atomic concentration in a range from 1.0×1015/cm3 to 1.0×1018/cm3, although lesser and greater dopant concentrations may also be used. - Doped well contact
regions 68 having a doping of the second conductivity type may be formed in an upper portion of the second-conductivity-type doped well 60 by performing a masked ion implantation process. The dopedwell contact regions 68 may be heavily doped to reduce contact resistance. The dopedwell contact regions 68 may include dopants of the second conductivity type at an atomic concentration in a range from 1.0×1019/cm3 to 1.0×1022/cm3, although lesser and greater dopant concentrations may also be used. - A first doped
photodiode contact region 28 having a doping of the first conductivity type may be formed under the proximalhorizontal surface 7 of the singlecrystalline silicon substrate 10 within the area enclosed by the second-conductivity-type doped well 60. The first dopedphotodiode contact region 28 may be heavily doped to reduce contact resistance. The first dopedphotodiode contact region 28 may include dopants of the first conductivity type at an atomic concentration in a range from 1.0×1019/cm3 to 1.0×1022/cm3, although lesser and greater dopant concentrations may also be used. - Referring to
FIG. 2B , adielectric mask layer 12 may be formed on the proximalhorizontal surface 7 of the singlecrystalline silicon substrate 10. Thedielectric mask layer 12 includes a dielectric material such as silicon oxide. Other suitable materials are within the contemplated scope of disclosure. Thedielectric mask layer 12 may be formed by deposition of a silicon oxide layer or by thermal oxidation of a surface of portion of the singlecrystalline silicon substrate 10. The thickness of thedielectric mask layer 12 may be in a range from 50 nm to 300 nm, such as from 80 nm to 150 nm, although lesser and greater thicknesses may also be used. - A
photoresist layer 67 may be applied over thedielectric mask layer 12. Thephotoresist layer 67 may be lithographically patterned to form an opening within the area laterally enclosed by the second-conductivity-type doped well 60. An anisotropic etch process may be performed to transfer the pattern of the opening in thephotoresist layer 67 through thedielectric mask layer 12 and into an upper portion of the singlecrystalline silicon substrate 10. Atrench 69 may be formed in the upper portion of the singlecrystalline silicon substrate 10. Thetrench 69 is laterally enclosed by, and is laterally spaced inward from, the second-conductivity-type doped well 60. The depth of thetrench 69 may be greater than, the same as, or less than, the depth of the second-conductivity-type doped well 60. In one embodiment, the depth of thetrench 69 may be in a range from 0.5 micron to 10 microns, such as from 1 micron to 6 microns, although lesser and greater depths may also be used. The lateral dimension of thetrench 69 may be be in a range from 0.5 micron to 30 microns, such as from 1 micron to 15 microns, although lesser and greater lateral dimensions may also be used. The lateral dimension of thetrench 69 may be the diameter or the major axis of the horizontal cross-sectional shape of thetrench 69 in embodiments in which thetrench 69 has a circular or an elliptical horizonal cross-sectional shape, or may be the length of a side of a rectangular shape in embodiments in which the horizontal cross-sectional shape of thetrench 69 is the rectangular shape. Thephotoresist layer 67 may be subsequently removed, for example, by ashing. - Referring to
FIG. 2C , dopants of the first conductivity type may be implanted around the region of thetrench 69. The dopants of the first conductivity type are implanted at least within the area laterally enclosed by the second-conductivity-type doped well 60. A multiple angled ion implantation processes may be performed to implant the dopants of the first conductivity type through sidewalls of thetrench 69. Further, the dopants of the first conductivity type may be implanted into surface portion of the singlecrystalline silicon substrate 10 that underlies the proximalhorizontal surface 7 of the singlecrystalline silicon substrate 10. In addition, the dopants of the first conductivity type may be implanted into a horizontal portion of the singlecrystalline silicon substrate 10 that underlies the bottom surface of thetrench 69. A first-conductivity-type silicon region 21 may be formed within the singlecrystalline silicon substrate 10. The first-conductivity-type silicon region 21 is connected to the first dopedphotodiode contact region 28, which is the contact region for the first-conductivity-type silicon region 21. The lateral width of the first-conductivity-type silicon region 21 around each sidewall of thetrench 69 may be in a range from 100 nm to 1,000 nm, although lesser and greater lateral dimensions may also be used. The thickness of the horizontal portion of the first-conductivity-type silicon region 21 underneath the bottom surface of thetrench 69 may be in a range from 100 nm to 1,000 nm, although lesser and greater thicknesses may also be used. - Referring to
FIG. 2D , in some embodiments asilicon liner 32 may be optionally grown from physically exposed surfaces of the first-conductivity-type silicon region 21, which are surfaces of thetrench 69. Thesilicon liner 32 may be grown by a selective silicon epitaxy process that grows epitaxial silicon only from physically exposed semiconductor surfaces and does not grow silicon from dielectric surfaces. Thesilicon liner 32 may include epitaxially grown silicon, i.e., single crystalline silicon in epitaxial alignment with the single crystalline silicon material of the singlecrystalline silicon substrate 10. Thesilicon liner 32 may be intrinsic, or may have a low level of doping. For example, the atomic concentration of dopants within thesilicon liner 32 may be in a range from 1.0×1013/cm3 to 1.0×1016/cm3, although lesser and greater dopant concentrations may also be used. The conductivity type of thesilicon liner 32, in embodiments in which thesilicon liner 32 is not intrinsic, may be the first conductivity type or the second conductivity type. The thickness of thesilicon liner 32 may be in a range from 5 nm to 200 nm, such as from 10 nm to 100 nm, although lesser and greater thicknesses may also be used. Thesilicon liner 32, if present, may function as a buffer between a germanium-containing material to be subsequently deposited and the first-conductivity-type silicon region 21. - Referring to
FIG. 2E , a germanium-containing material may be grown from the physically exposed surfaces of thesilicon liner 32 in embodiments that include thesilicon liner 32 or from the physically exposed surfaces of the first-conductivity-type silicon region 21 in embodiments that do not include thesilicon liner 32. The germanium-containing material includes germanium at an atomic percentage greater than 50%. In one embodiment, the germanium-containing material may include doped or undoped germanium such that the atomic percentage of germanium is at least 99%, and is essentially free of silicon. In another embodiment, the germanium-containing material may include a silicon-germanium alloy in which the atomic percentage of germanium is greater than 50%, and the atomic percentage of silicon is less than 50%, such as from 5% to 30%. A germanium-containingmaterial layer 30L may be formed by the deposited germanium-containing material. - The germanium-containing
material layer 30L may be formed by a selective deposition process or a non-selective deposition process. A selective deposition process is a process in which the germanium-containing material is grown from physically exposed semiconductor surfaces such as the physically exposed surfaces of thesilicon liner 32 or the physically exposed surfaces of the first-conductivity-type silicon region 21. In this embodiment, a germanium-containing reactant (such as germane or digermane) may be flowed into a process chamber containing the first exemplary structure concurrently with, or alternately with, flow of an etchant gas such as hydrogen chloride. Generally, a semiconductor material (such as a germanium-containing material) has a higher growth rate on semiconductor surfaces than on dielectric surfaces. The flow rates and the deposition temperature may be controlled such that the net deposition rate (i.e., the deposition rate less the etch rate) is positive on semiconductor surfaces, and is negative on dielectric surfaces during the selective deposition process. In this embodiment, growth of the germanium-containing material occurs only on semiconductor surfaces. A non-selective deposition process is a deposition process in which the germanium-containing material grows from all physically exposed surfaces. In this embodiment, the deposition process may use a germanium-containing reactant without use of an etchant gas. - In one embodiment, the selective deposition process or the non-selective deposition process that is used to deposit the germanium-containing
material layer 30L may be an epitaxial deposition process, i.e., a deposition process that provides alignment of crystallographic structure of the deposited germanium-containing material to the crystalline structure at the physically exposed surfaces of the underlying material portions. Thus, the portion of the germanium-containingmaterial layer 30L that is deposited in thetrench 69 may be epitaxially aligned to the crystalline structure of the silicon liner 32 (in embodiments in which thesilicon liner 32 is included) and/or the crystalline structure of the first-conductivity-type silicon region 21. In embodiments in which a selective epitaxial deposition process is used to deposit the germanium-containingmaterial layer 30L, the material of the germanium-containingmaterial layer 30L grows from the physically exposed surfaces of thesilicon liner 32 or the first-conductivity-type silicon region 21. In such embodiments, the entirety of the germanium-containingmaterial layer 30L may be single crystalline and may be in epitaxial alignment with the single crystalline silicon material of the single crystalline silicon substrate 8. In embodiments in which a non-selective epitaxial deposition process is used to deposit the germanium-containingmaterial layer 30L, the material of the germanium-containingmaterial layer 30L grows from the physically exposed surfaces of the silicon liner 32 (in embodiments in which thesilicon liner 32 is included) or the first-conductivity-type silicon region 21, and from the physically exposed surfaces of thedielectric mask layer 12. In this embodiment, only the portion of the germanium-containingmaterial layer 30L that grows from the physically exposed surfaces of the silicon liner 32 (in embodiments in which thesilicon liner 32 is included) or the first-conductivity-type silicon region 21 may be single crystalline, and the portions of the germanium-containingmaterial layer 30L that grows from the physically exposed surfaces of thedielectric mask layer 12 may be polycrystalline. - Generally, an epitaxial deposition process may be performed to grow a single crystalline germanium-containing material inside the
trench 69. At least the portion of the germanium-containingmaterial layer 30L that grows within thetrench 69 may be single crystalline, and may be formed with epitaxial alignment with the single crystalline silicon material of the singlecrystalline silicon substrate 10,. In this embodiment, the entirety of the portion of the germanium-containingmaterial layer 30L located within thetrench 69 may be single crystalline. - The germanium-containing
material layer 30L may be intrinsic, or may have a low level of doping. For example, the atomic concentration of dopants within the germanium-containingmaterial layer 30L may be in a range from 1.0×1013/cm3 to 1.0×1018/cm3, although lesser and greater dopant concentrations may also be used. - Referring to
FIG. 2F , excess portions of the germanium-containing material may be removed from above the horizontal plane including the top surface of thedielectric mask layer 12. In one embodiment, a chemical mechanical planarization (CMP) process may be performed to remove portions of the germanium-containingmaterial layer 30L located above the horizontal plane including the top surface of thedielectric mask layer 12. A remaining portion of the germanium-containingmaterial layer 30L located within thetrench 69 comprises a germanium-containing material portion, which is herein referred to as a germanium-containingwell 30. The germanium-containing well 30 may have a top surface within the same horizontal plane as the top surface of thedielectric mask layer 12. - While the present disclosure is described using an embodiment in which the germanium-containing well 30 is formed as a single crystalline germanium-containing material portion, the germanium-containing well 30 may be formed as a polycrystalline material portion or as an amorphous material portion albeit at a reduced efficiency. Such variations are expressly contemplated herein.
- Referring to
FIG. 2G , a remaining portion of the germanium-containing material may be vertically recessed within an opening in thedielectric mask layer 12. Specifically, the germanium-containing well 30 and optionally an upper portion of theoptional silicon liner 32 may be vertically recessed, for example, by performing a recess etch process. In such embodiments, the vertical recess distance may be greater than, the same as, or less than, the thickness of thedielectric mask layer 12. Regardless of the vertical recess distance, the germanium-containing well 30 does not contact thedielectric mask layer 12, and the material of the germanium-containing well 30 does not contact any oxygen-containing material (such as silicon oxide) of thedielectric mask layer 12. In embodiments in which asilicon liner 32 is not used, the vertical recess distance may be greater than the thickness of thedielectric mask layer 12 to prevent direct contact between the germanium-containing well 30 and thedielectric mask layer 12. - Referring to
FIG. 2H , a silicon-containing capping material may be deposited on the physically exposed top surface of the germanium-containingwell 30. In embodiments in which asilicon liner 32 is present, the silicon-containing capping material may be deposited on the top surface of thesilicon liner 32. The silicon-containing capping material may include, and/or may consist essentially of, a silicon-containing material that may prevent diffusion of oxygen. For example, the silicon-containing capping material may include, and/or may consist essentially of, silicon or silicon nitride. - In one embodiment, a selective epitaxy process may be performed to grow silicon from the top surface of the germanium-containing
well 30. In this embodiment, apassivation silicon region 340 including single crystalline silicon may be formed over the germanium-containingwell 30. Alternatively, a selective or non-selective silicon deposition process may be performed under conditions that forms polycrystalline silicon. In this embodiment, thepassivation silicon region 340 may include, and/or may consist essentially of, polysilicon. - If a selective silicon deposition process (which may, or may not, be an epitaxial deposition process) is used, the
passivation silicon region 340 may be formed only inside the opening in thedielectric mask layer 12. In this embodiment, a planarization process is not necessary, and the top surface of thepassivation silicon region 340 may be located at, below, or above, the horizontal plane including the top surface of thedielectric mask layer 12. If a non-selective silicon deposition process is used, a planarization process such as a chemical mechanical planarization process may be performed to remove portions of the deposited silicon material from above the horizontal plane including the top surface of thedielectric mask layer 12. In this embodiment, the top surface of thepassivation silicon region 340 may be located within the same horizontal plane as the top surface of thedielectric mask layer 12. - In one embodiment, the
passivation silicon region 340 as formed may include intrinsic silicon or lightly doped silicon, i.e., silicon including electrical dopants at an atomic concentration in a range from 1.0×1013/cm3 to 1.0×1017/cm3. The conductivity type of doping in thepassivation silicon region 340 may be the first conductivity type or the second conductivity type. Generally, thepassivation silicon region 340 may be formed as a single crystalline silicon portion, a polysilicon portion, a microcrystalline silicon portion, or an amorphous silicon portion depending on the deposition conditions. - Referring to
FIG. 2I , dopants of the second conductivity type may be implanted into thepassivation silicon region 340 and an upper portion of the germanium-containingwell 30. The implanted portion of the germanium-containing well 30 may be converted into a second-conductivity-type germanium-containingregion 302, and thepassivation silicon region 340 may be converted into a second-conductivity-type silicon region 342. The atomic concentration of electrical dopants of the second conductivity type in the second-conductivity-type germanium-containingregion 302 and the second-conductivity-type silicon region 342 may be in a range from 1.0×1018/cm3 to 1.0×1021/cm3, although lesser and greater atomic concentrations may also be used. The thickness of the second-conductivity-type germanium-containingregion 302 may be in a range from 50 nm to 500 nm, although lesser and greater thicknesses may also be used. The thickness of the second-conductivity-type germanium-containingregion 302 may be in a range from 50 nm to 300 nm, although lesser and greater thicknesses may also be used. - The unimplanted portion of the germanium-containing well 30 is herein referred to as an intermediate germanium-containing
region 308. The intermediate germanium-containingregion 308 may be intrinsic or may have a doping with an atomic concentration of dopants in a range from 1.0×1013/cm3 to 1.0×1018/cm3. The intermediate germanium-containingregion 308 contacts the second-conductivity-type germanium-containingregion 302, and is laterally surrounded by the first-conductivity-type silicon region 21. The combination of the intermediate germanium-containingregion 308 and the intermediate germanium-containingregion 308 constitutes a germanium-containingwell 30. - The first-conductivity-
type silicon region 21, the intermediate germanium-containingregion 308, and the second-conductivity-type germanium-containingregion 302 collectively form a p-i-n type photovoltaic junction, i.e., a photovoltaic junction including a p-doped region, an n-doped region, and an intermediate semiconductor region located between the p-doped region and the n-doped region and including an intrinsic semiconductor material or a lightly-doped semiconductor material. In one embodiment, the first conductivity type may be p-type and the second conductivity type may be n-type. In another embodiment, the first conductivity type may be n-type and the first conductivity type may be p-type. The photovoltaic junction may be formed across thetrench 69, i.e., may spatially extend across the boundary of thetrench 69 due to the presence of the first-conductivity-type silicon region 21 outside thetrench 69. The intermediate germanium-containingregion 308 is located within thetrench 69, and functions as the intermediate semiconductor region including an intrinsic semiconductor material or a lightly-doped semiconductor material. - In an alternative embodiment, the intermediate germanium-containing
region 308 may have a doping of the second conductivity type, and the photovoltaic junction may include a p-n junction formed between the intermediate germanium-containingregion 308 and the first-conductivity-type silicon region 21. In this embodiment, the intermediate germanium-containingregion 308 may include dopants of the second conductivity type at an atomic concentration in arrange from 1.0×1017/cm3 to 1.0×1020/cm3, although lesser and greater atomic concentrations may also be used. In embodiments in which thesilicon liner 32 is not included, the p-n junction may be formed at the sidewall and the bottom surface of thetrench 69. In embodiments in which thesilicon liner 32 is included, thesilicon liner 32 may be intrinsic, may be p-doped, or may be n-doped. Generally, the photovoltaic junction may comprise a p-i-n junction or a p-n junction formed across the germanium-containing well 30 and the singlecrystalline silicon substrate 10 that contains the first-conductivity-type silicon region 21. - Referring to
FIG. 2J , thedielectric mask layer 12 may be removed, for example, by performing a wet etch process. In embodiments in which thedielectric mask layer 12 includes silicon oxide, a wet etch process using dilute hydrofluoric acid may be performed to remove thedielectric mask layer 12. - Shallow
trench isolation structures 20 may be formed in an upper portion of the singlecrystalline silicon substrate 10. The shallowtrench isolation structures 20 may include a dielectric fill material such as silicon oxide, and provide electrical isolation from semiconductor devices to be subsequently formed. Various field effect transistors (610, 630, 640) may be formed in thephotodetector region 510 and in thesensing circuit region 520. For example, atransfer transistor 610 may be formed in thephotodetector region 510, and p-typefield effect transistors 630 and n-typefield effect transistors 640 may be formed in thesensing circuit region 520. Each of the field effect transistors (610, 630, 640) may include arespective gate dielectric 50, arespective gate electrode 52, and a respective pair of a source region and a drain region. The source regions and the drain regions are collectively referred to as source/drain regions. For example, the p-typefield effect transistors 630 may include p-doped source/drain regions 42, and the n-typefield effect transistors 640 may include n-doped source/drain regions 44. Thetransfer transistor 610 may include asource region 48 to be electrically connected to the second-conductivity-type germanium-containingregion 302, and a floatingdrain region 46. The second-conductivity-type germanium-containingregion 302 and the floatingdrain region 46 may have a doping of the second conductivity type. Various doped wells may be formed in thesensing circuit region 520 as needed. While the present disclosure illustrates only two field effect transistors in thesensing circuit region 520, it is understood that a full set of field effect transistors for providing a sensing circuit for a subpixel may be formed in thesensing circuit region 520. The field effect transistors in thesensing circuit region 520 may include transistors such as a reset transistor, a source follower transistor, and a select transistor. Any sensing circuit for sensing stored electrical charges in the second-conductivity-type germanium-containingregion 302 may be formed. - Referring to
FIG. 2K , dielectric material layers 90 andmetal interconnect structures 80 may be formed over the field effect transistors (610, 630, 640) and the second-conductivity-type silicon region 342. Each of the dielectric material layers 90 includes a respective interlayer dielectric (ILD) material such as undoped silicate glass, a doped silicate glass, organosilicate glass, and/or a porous dielectric material. The dielectric material layers 90 may include dielectric liners such as silicon nitride dielectric liners, dielectric metal oxide dielectric liners, silicon carbide dielectric liners, and/or silicon oxynitride dielectric liners. Themetal interconnect structures 80 may include metal viastructures 82 andmetal line structures 84. The second-conductivity-type silicon region 342 may be electrically connected to thesource region 48 of thetransfer transistor 610 by a subset of themetal interconnect structures 80. -
FIG. 2L is a vertical cross-sectional view of an alternative configuration of the first exemplary structure according to the first embodiment of the present disclosure. Referring toFIG. 2L , an alternative configuration of the first exemplary structure may be derived from the first exemplary structure ofFIG. 2H by using silicon nitride as the material for a silicon-containing capping structure. A siliconnitride capping structure 41 including, and/or consisting essentially of, silicon nitride may be formed on the top surface of the germanium-containingwell 30. - Subsequently, the processing steps of
FIG. 2I may be performed to convert an upper portion of the germanium-containing well 30 into a second-conductivity-type germanium-containingregion 302. The processing steps ofFIGS. 2J and 2K may be subsequently performed. A metal viastructure 82 may be formed through the silicon nitride capping structure 41 (that includes silicon nitride) to contact the second-conductivity-type germanium-containingregion 302. - Generally, a silicon-containing capping structure (342 or 41) may be located on a top surface of the germanium-containing
well 30. The silicon-containing capping structure (342 or 41) includes a silicon-containing diffusion barrier material, which may be silicon or silicon nitride. If the silicon-containing capping structure (342 or 41) include silicon (comprising the second-conductivity-type silicon region 342), the atomic percentage of silicon in the silicon-containing capping structure (comprising a second-conductivity-type silicon region 342) may be greater than 98%, and may be greater than 99%, the balance being electrical dopants of the second conductivity type. If the silicon-containing capping structure (comprising a silicon nitride capping structure 41) includes silicon nitride, the atomic percentage of silicon may be about 3/7×100%, which is about 42.8%. Generally, the silicon-containing capping structure (342 or 41) of the embodiments of the present disclosure may include silicon at an atomic percentage greater than 42%. -
FIGS. 3A and 3B are vertical cross-sectional views of configurations of a second exemplary structure including a pixel of an image sensor according to a second embodiment of the present disclosure.FIG. 3A illustrates a configuration in which the silicon-containing capping structure comprises a second-conductivity-type silicon region 342, andFIG. 3B illustrates a configuration in which the silicon-containing capping structure comprises a siliconnitride capping structure 41. - In the second exemplary structures, the photovoltaic junction of each subpixel may be formed in a
first semiconductor substrate 110. Thefirst semiconductor substrate 110 may be a single crystalline silicon substrate that may be the same as the singlecrystalline silicon substrate 10 as described above. First dielectric material layers 190 containing a first subset of themetal interconnect structures 80 may be formed over thefirst semiconductor substrate 110.First bonding pads 188 may be formed on the first dielectric material layers 190. Through-substrate viastructures 104 laterally surrounded by a respective insulatingspacer 102 may be formed in thefirst semiconductor substrate 110. - The sensing circuit of each subpixel may be formed on a
second semiconductor substrate 210, which may be a silicon substrate. In this embodiment, thetransfer transistor 610 for the photodetector may be formed on thesecond semiconductor substrate 210. Second dielectric material layers 290 containing a second subset of themetal interconnect structures 80 may be formed over thesecond semiconductor substrate 210.Second bonding pads 288 may be formed on the second dielectric material layers 290. - A first wafer including the
first semiconductor substrate 110 and the first dielectric material layers 190 may be bonded to a second wafer including thesecond semiconductor substrate 210 and the second dielectric material layers 290 by wafer-to-wafer bonding. For example, thefirst bonding pads 188 and be aligned to, and disposed upon, thesecond bonding pads 288, and metal-to-metal bonding may be induced on each mating pair of afirst bonding pad 188 and asecond bonding pad 288. Subsequently, the backside of thefirst semiconductor substrate 110 may be thinned to physically expose top surfaces of the through-substrate viastructures 104. Abackside dielectric layer 106 may be formed on the backside of thefirst semiconductor substrate 110, andexternal bonding pads 198 may be formed through thebackside dielectric layer 106 on a backside surface of a respective one of the through-substrate viastructures 104. The bonded assembly of the first wafer and the second wafer may be diced to provide bonded semiconductor dies. Each bonded semiconductor die may include a first semiconductor die 710 including diced portions of thefirst semiconductor substrate 110 and the first dielectric material layers 190, and a second semiconductor die 720 including diced portions of thesecond semiconductor substrate 210 and the second dielectric material layers 290. -
FIGS. 4A and 4B are vertical cross-sectional views of configurations of a third exemplary structure including a pixel of an image sensor according to a second embodiment of the present disclosure.FIG. 4A illustrates a configuration in which the silicon-containing capping comprises a second-conductivity-type silicon region 342, andFIG. 4B illustrates a configuration in which the silicon-containing capping structure comprises a siliconnitride capping structure 41. - In the third exemplary structures, the photovoltaic junction of each subpixel and at least a subset of the sensing circuit of each subpixel may be formed in a
first semiconductor substrate 110, which is a single crystalline silicon substrate that may be the same as the singlecrystalline silicon substrate 10 as described above. First dielectric material layers 190 containing a first subset of themetal interconnect structures 80 may be formed over thefirst semiconductor substrate 110. Through-substrate viastructures 104 laterally surrounded by a respective insulatingspacer 102 may be formed in thefirst semiconductor substrate 110. - Additional semiconductor devices such as p-type
field effect transistors 630 and n-type field effect transistors may be formed on asecond semiconductor substrate 210, which may be a silicon substrate. The additional semiconductor devices may, or may not, include components of a sensing circuit for a photovoltaic junction in thefirst semiconductor substrate 110. The additional semiconductor devices may include additional semiconductor devices that may be used in conjunction with the subpixels of an image sensor. For example, the additional semiconductor devices may include memory devices or logic devices that may support operation of the image sensor. - The devices on the
first semiconductor substrate 110 and the devices on thesecond semiconductor substrate 210 may be connected to each other front-to-front, back-to-back, or front-to-back. The illustrated configurations include embodiments in which the backside of thefirst semiconductor substrate 110 is thinned, abackside dielectric layer 106 is deposited on the backside of thefirst semiconductor substrate 110, andfirst bonding pads 188 are formed through thebackside dielectric layer 106 on bottom surfaces of the through-substrate viastructures 104. Thefirst bonding pads 188 are bonded tosecond bonding pads 288 provided in the second dielectric material layers 290 overlying thesecond semiconductor substrate 210. - Generally, any type of photovoltaic junction may be formed within, or around, the germanium-containing
well 30. The photovoltaic junction may be a vertical p-i-n junction, a lateral p-i-n junction, a vertical p-n junction, or a lateral p-n junction. Further, the configuration of a pinned diode using an pinning layer or the configuration of a single-photon avalanche diode (SPAD) may also be used. While specific embodiments of the photovoltaic junction formed within, or around, a germanium-containing well 30 are described herein, it is to be understood that the scope of the present disclosure is not limited by any particular configuration of a photovoltaic junction provided that a germanium-containing well 30 is used as a component of a photovoltaic junction. - The germanium-containing material of the germanium-containing well 30 may be doped germanium or a doped silicon-germanium alloy including germanium at an atomic percentage greater than 50%. The germanium-containing well 30 may be completely encapsulated by a combination of the first-conductivity-
type silicon region 21 and the silicon-containing capping structure (342 or 41), or by a combination of thesilicon liner 32 and the silicon-containing capping structure (342 or 41). Thus, physical contact between the germanium-containing well 30 and the dielectric material layers 90 or any other oxygen-containing component within the first, second, and third exemplary structures may be avoided, and the germanium-containing well 30 may remain free of oxidation. - Referring to
FIGS. 2A-4B and according to various embodiments of the present disclosure, a semiconductor structure including a photodetector is provided. The photodetector comprises: germanium-containing well 30 embedded within a single crystalline silicon substrate (10, 110) and extending to a proximalhorizontal surface 7 of the single crystalline silicon substrate (9, 10), wherein the germanium-containing well 30 includes germanium at an atomic percentage greater than 50% (such as from 50% to 100%); and a silicon-containing capping structure (342 or 41) located on a top surface of the germanium-containing well 30 and including silicon atoms at an atomic percentage greater than 42%. A portion of the single crystalline silicon substrate (10, 110) that surrounds thetrench 69 comprises a first-conductivity-type silicon region 21. The germanium-containing well 30 comprises a second-conductivity-type germanium-containingregion 302. - In one embodiment, the photovoltaic junction may comprise a p-i-n junction (21, 308, 302); and the germanium-containing well 30 comprises an intermediate germanium-containing
region 308 having an atomic concentration of dopants in a range from 1.0×1013/cm3 to 1.0×1018/cm3, contacting the second-conductivity-type germanium-containingregion 302, and laterally surrounded by the first-conductivity-type silicon region 21. - In one embodiment, the semiconductor structure may comprise a single
crystalline silicon liner 32 contacting an inner sidewall of the first-conductivity-type silicon region 302, laterally surrounding the germanium-containing well 30, and epitaxially aligned to the single crystalline silicon substrate (9, 10). In one embodiment, the germanium-containing well 30 comprises a single crystalline germanium-containing semiconductor material in epitaxial alignment with the singlecrystalline silicon liner 32 and the single crystalline silicon substrate (9, 10). - In one embodiment, the first-conductivity-
type silicon region 21 continuously surrounds the germanium-containing well 30 and comprises a first horizontally-extending portion that contacts a bottom surface of the germanium-containing well 30 and a second horizontally-extending portion that extends outward from the germanium-containing well 30 under the proximalhorizontal surface 7 of the single crystalline silicon substrate (9, 10). - The semiconductor structure may comprise: a sensing circuit located on the single crystalline silicon substrate (10, 110) or on a
semiconductor substrate 210 bonded to the single crystalline silicon substrate (10, 110) through dielectric material layers (190, 290) and bonding pads located (188, 288) within the dielectric material layers (190, 290); andmetal interconnect structures 80 that provide electrical connection between the second-conductivity-type germanium-containingregion 302 and the sensing circuit. -
FIG. 5A-5F are sequential vertical cross-sectional views of a fourth exemplary structure during formation of a pixel of an image sensor according to a fourth embodiment of the present disclosure. The fourth exemplary structure illustrated inFIG. 5A includes afirst semiconductor substrate 110, which may be a single crystalline silicon substrate. Thefirst semiconductor substrate 110 may be the same as the singlecrystalline silicon substrate 10 in the first exemplary structure. A proximalhorizontal surface 7 may be located on the top side of thefirst semiconductor substrate 110. Adielectric mask layer 12 may be formed on the proximal horizontal surface, and the atrench 69 may be formed in an upper portion of thefirst semiconductor substrate 110 through an opening in thedielectric mask layer 12. The fourth exemplary structure ofFIG. 5A may be derived from the first exemplary structure ofFIG. 2B by omitting formation of the first dopedphotodiode contact region 28, the second-conductivity-type doped well 60, and the dopedwell contact regions 68. - Referring to
FIG. 5B , the processing steps ofFIGS. 2D, 2E, 2F, and 2G may be sequentially performed to form asilicon liner 32 and a germanium-containingwell 30. Thesilicon liner 32 may have the same thickness and the same material composition as in the first embodiment. The germanium-containing well 30 may have the same material composition and the same crystallinity as in the first embodiment. The germanium-containing well 30 may be single crystalline and epitaxially aligned to the single crystalline semiconductor substrate of thefirst semiconductor substrate 110, or may be polycrystalline or amorphous. - Referring to
FIG. 5C , silicon may be deposited on the top surface of the germanium-containingwell 30. In one embodiment, deposited silicon may include undoped silicon. As used herein, undoped silicon refers to silicon without intentionally introduced dopants during a deposition process. Thus, the level of electrical dopants in undoped silicon may at a residual level. For example, undoped silicon may be intrinsic, or may include electrical dopants at a dopant concentration less than 1.0×1016/cm3, such as from 1.0×1012/cm3 to 1.0×1015/cm3. Undoped silicon provides relatively high resistivity, and is effective in suppressing leakage current. Undoped silicon may be grown by a selective deposition process or a non-selective deposition process. In embodiments in which a non-selective deposition process is used, excess portions of the deposited undoped silicon material may be removed from above the horizontal plane including the top surface of thedielectric mask layer 12. Remaining portions of the deposited undoped silicon comprises apassivation silicon region 340. The top surface of thepassivation silicon region 340 may be within the horizontal plane including the top surface of thedielectric mask layer 12. In embodiments in which undoped silicon is deposited using a selective deposition process, a planarization process may not be necessary. Thepassivation silicon region 340 functions as a silicon-containing capping structure for the germanium-containingwell 30. - Referring to
FIG. 5D , dopants of the first conductivity type may be implanted into a portion of thepassivation silicon region 340 and an upper portion of the germanium-containing well 30 using a first masked ion implantation process. The implanted portion of thepassivation silicon region 340 comprises a first-conductivity-type silicon region 341, and the implanted portion of the germanium-containing well 30 comprises a first-conductivity-type germanium-containingregion 301. The first-conductivity-type silicon region 341 and the first-conductivity-type germanium-containingregion 301 may be heavily doped. For example, each of the first-conductivity-type silicon region 341 and the first-conductivity-type germanium-containingregion 301 may include electrical dopants of the first conductivity type at an atomic concentration in a range from 1.0×1019/cm3 to 2.0×1021/cm3. - Dopants of the second conductivity type may be implanted into another portion of the
passivation silicon region 340 and another upper portion of the germanium-containing well 30 using a second masked ion implantation process. The implanted portion of thepassivation silicon region 340 comprises a second-conductivity-type silicon region 342, and the implanted portion of the germanium-containing well 30 comprises a second-conductivity-type germanium-containingregion 302. The second-conductivity-type silicon region 342 and the second-conductivity-type germanium-containingregion 302 may be heavily doped. For example, each of the second-conductivity-type silicon region 342 and the second-conductivity-type germanium-containingregion 302 may include electrical dopants of the second conductivity type at an atomic concentration in a range from 1.0×1019/cm3 to 2.0×1021/cm3. - The remaining portion of the
passivation silicon region 340 may provide lateral isolation between the first-conductivity-type silicon region 341 and the second-conductivity-type silicon region 342. The combination of thepassivation silicon region 340, the first-conductivity-type silicon region 341, and the second-conductivity-type silicon region 342 comprises asilicon capping structure 34, which is a silicon-containing capping structure. - The unimplanted portion of the germanium-containing well 30 is herein referred to as an intermediate germanium-containing
region 308. The intermediate germanium-containingregion 308 may be intrinsic or may have a doping with an atomic concentration of dopants in a range from 1.0×1013/cm3 to 1.0×1018/cm3. The intermediate germanium-containingregion 308 provides lateral spacing between the first-conductivity-type germanium-containingregion 301 and the second-conductivity-type germanium-containingregion 302. The combination of the intermediate germanium-containingregion 308, the first-conductivity-type germanium-containingregion 301, and the second-conductivity-type germanium-containingregion 302 comprises the germanium-containingwell 30. - Referring to
FIG. 5E , thedielectric mask layer 12 may be removed, for example, by performing an isotropic etch process such as a wet etch process. First dielectric material layers 190, through-substrate viastructures 104, insulatingspacers 102 that laterally surrounds the through-substrate viastructures 104,metal interconnect structures 80, andfirst bonding pads 188 may be formed over thefirst semiconductor substrate 110. - Referring to
FIG. 5F , sensing circuits for photodetectors provided on thefirst semiconductor substrate 110 ofFIG. 5G may be formed on asecond semiconductor substrate 210. An array of sensing circuits may be formed for an array of photodetectors provided on thefirst semiconductor substrate 110 ofFIG. 5G . For example, each sensing circuit for a photodetector may include atransfer transistor 610 including asource region 48 and a floatingdrain region 46, and additional field effect transistors that may include p-typefield effect transistors 630 and n-type field effect transistors. The sensing circuit ofFIG. 5F as provided on thesecond semiconductor substrate 210 may be the same as the sensing circuit ofFIG. 2K as provided on the singlecrystalline silicon substrate 10.Metal interconnect structures 80 formed within second dielectric material layers 290 may be formed over thesecond semiconductor substrate 210 to provide electrical wiring to and from the various semiconductor devices on thesecond semiconductor substrate 210.Second bonding pads 288 may be formed on the second dielectric material layers 290. - A first wafer including the
first semiconductor substrate 110 and the first dielectric material layers 190 may be bonded to a second wafer including thesecond semiconductor substrate 210 and the second dielectric material layers 290 by wafer-to-wafer bonding. For example, thefirst bonding pads 188 and be aligned to, and disposed upon, thesecond bonding pads 288, and metal-to-metal bonding may be induced on each mating pair of afirst bonding pad 188 and asecond bonding pad 288. Subsequently, the backside of thefirst semiconductor substrate 110 may be thinned to physically expose top surfaces of the through-substrate viastructures 104. Abackside dielectric layer 106 may be formed on the backside of thefirst semiconductor substrate 110, andexternal bonding pads 198 may be formed through thebackside dielectric layer 106 on a backside surface of a respective one of the through-substrate viastructures 104. The bonded assembly of the first wafer and the second wafer may be diced to provide bonded semiconductor dies. Each bonded semiconductor die may include a first semiconductor die 710 including diced portions of thefirst semiconductor substrate 110 and the first dielectric material layers 190, and a second semiconductor die 720 including diced portions of thesecond semiconductor substrate 210 and the second dielectric material layers 290. -
FIGS. 6A-6F are vertical cross-sectional views of alternative configurations of the fourth exemplary structure according to the fourth embodiment of the present disclosure. Referring toFIG. 6A , a first alternative configuration of the fourth exemplary structure may be derived from the fourth exemplary structure ofFIG. 5F by omitting formation of thesilicon liner 32. In this embodiment, the germanium-containing well 30 may be formed directly on sidewalls and a horizontal surface of thetrench 69. Thus, the germanium-containing well 30 may directly contact the single crystalline silicon substrate comprising thefirst semiconductor substrate 110. - Referring to
FIG. 6B , a second alternative configuration of the fourth exemplary structure may be derived from the first alternative configuration of the fourth exemplary structure ofFIG. 6A by forming a siliconnitride capping structure 41 in lieu of asilicon capping structure 34. In this embodiment, each of the first-conductivity-type germanium-containingregion 301 and the second-conductivity-type germanium-containingregion 302 may be directly contacted by a respective one of themetal interconnect structures 80, such as a respective metal viastructure 82. - Referring to
FIG. 6C , a third alternative configuration of the fourth exemplary structure may be derived from the fourth exemplary structure ofFIG. 5F by forming a plurality of first-conductivity-type germanium-containingregions 301 and/or a plurality of second-conductivity-type germanium-containingregion 302. In this embodiment, a plurality of first-conductivity-type silicon regions 341 and/or a plurality of second-conductivity-type silicon regions 342 may be formed. - Referring to
FIG. 6D , a fourth alternative configuration of the fourth exemplary structure may be derived from the first alternative configuration of the fourth exemplary structure ofFIG. 6A by forming a plurality of first-conductivity-type germanium-containingregions 301 and/or a plurality of second-conductivity-type germanium-containingregion 302. In this embodiment, a plurality of first-conductivity-type silicon regions 341 and/or a plurality of second-conductivity-type silicon regions 342 may be formed. - Referring to
FIG. 6E , a fifth alternative configuration of the fourth exemplary structure may be derived from the fourth exemplary structure ofFIG. 5F or from the third alternative configuration of the fourth exemplary structure ofFIG. 6C by doping the intermediate germanium-containingregion 308 with dopants of the first conductivity type to form an additional first-conductivity-type germanium-containingregion 305. In this embodiment, the atomic concentration of dopants of the first conductivity type within the additional first-conductivity-type germanium-containingregion 305 may be in a range from 1.0×1017/cm3 to 1.0×1019/cm3, although lesser and greater atomic concentrations may also be used. In this embodiment, the photovoltaic junction may be a p-n junction. - Referring to
FIG. 6F , a sixth alternative configuration of the fourth exemplary structure may be derived from the fifth alternative configuration of the fourth exemplary structure ofFIG. 6E by doping the intermediate germanium-containingregion 308 with dopants of the first conductivity type at an atomic concentration on par with the atomic concentration of dopants of the first conductivity type in the first-conductivity-type germanium-containingregions 301. In this embodiment, the first-conductivity-type germanium-containingregion 301 replaces the intermediate germanium-containingregion 308. A p-n junction may be formed between the first-conductivity-type germanium-containingregions 301 and the second-conductivity-type germanium-containingregion 302. The germanium-containing well 30 includes, and/or consists of, the first-conductivity-type germanium-containingregions 301 and the second-conductivity-type germanium-containingregion 302. -
FIG. 7A-7G are sequential vertical cross-sectional views of a fifth exemplary structure during formation of a pixel of an image sensor according to a fifth embodiment of the present disclosure. Referring toFIG. 7A , a fifth exemplary structure according to a fifth embodiment of the present disclosure may be formed by providing asemiconductor substrate 500, which may include a singlecrystalline silicon substrate 10. The singlecrystalline silicon substrate 10 may be the same as in the first exemplary structure. Semiconductor devices for forming a sensing circuit may be formed on, and/or in, an upper portion of the singlecrystalline silicon substrate 10. For example, the semiconductor devices may include atransfer transistor 610, p-typefield effect transistors 630, and n-typefield effect transistors 640. Thetransfer transistor 610 may be formed in thephotodetector region 510, and the p-typefield effect transistors 630 and the n-typefield effect transistors 640 may be formed in thesensing circuit region 520. The various field effect transistors (610, 630, 640) may be the same as in the first exemplary structure. - A dielectric material such as silicon oxide may be deposited over the semiconductor devices on the proximal horizontal surface of the single
crystalline silicon substrate 10, and may be planarized to provide adielectric mask layer 92 having a horizontal top surface. The thickness of thedielectric mask layer 92 may be greater than the height of thegate electrodes 52, and thedielectric mask layer 92 may cover thegate electrodes 52. - Referring to
FIG. 7B , aphotoresist layer 67 may be applied over thedielectric mask layer 12, and may be lithographically patterned to form an opening within thephotodetector region 510. An anisotropic etch process may be performed to transfer the pattern of the opening in thephotoresist layer 67 through thedielectric mask layer 92 and into an upper portion of the singlecrystalline silicon substrate 10. Atrench 69 may be formed in the upper portion of the singlecrystalline silicon substrate 10. The depth of thetrench 69 may be greater than, the same as, or less than, the depth of the second-conductivity-type doped well 60. In one embodiment, the depth of thetrench 69 may be in a range from 0.5 micron to 10 microns, such as from 1 micron to 6 microns, although lesser and greater depths may also be used. The lateral dimension of thetrench 69 may be in a range from 0.5 micron to 30 microns, such as from 1 micron to 15 microns. The lateral dimension of thetrench 69 may be the diameter or the major axis of the horizontal cross-sectional shape of thetrench 69 in embodiments in which thetrench 69 has a circular or an elliptical horizonal cross-sectional shape, or may be the length of a side of a rectangular shape in embodiments in which the horizontal cross-sectional shape of thetrench 69 is the rectangular shape. Thephotoresist layer 67 may be subsequently removed, for example, by ashing. - Referring to
FIG. 7C , the processing steps ofFIGS. 2D and 2E may be performed to form asilicon liner 32 and a germanium-containingmaterial layer 30L. Thesilicon liner 32 may have the same thickness, the same crystallinity, and/or the same material composition as in the first exemplary structure. The germanium-containingmaterial layer 30L may have the same crystallinity and the same material composition as in the first exemplary structure. - Referring to
FIG. 7D , the processing steps ofFIGS. 2F and 2G may be performed to form a germanium-containingwell 30. - Referring to
FIG. 7E , the processing steps ofFIG. 2H may be performed to form apassivation silicon region 340. In one embodiment, thepassivation silicon region 340 may have a top surface within a horizontal plane including the top surface of thedielectric mask layer 92. - Referring to
FIG. 7F , the processing steps ofFIG. 5D may be performed to form a first-conductivity-type silicon region 341, a first-conductivity-type germanium-containingregion 301, a second-conductivity-type silicon region 342, and a second-conductivity-type germanium-containingregion 302. The remaining portion of thepassivation silicon region 340 may provide lateral isolation between the first-conductivity-type silicon region 341 and the second-conductivity-type silicon region 342. The combination of thepassivation silicon region 340, the first-conductivity-type silicon region 341, and the second-conductivity-type silicon region 342 comprises asilicon capping structure 34, which is a silicon-containing capping structure. The combination of the intermediate germanium-containingregion 308, the first-conductivity-type germanium-containingregion 301, and the second-conductivity-type germanium-containingregion 302 comprises the germanium-containingwell 30. Alternatively, any of the p-i-n junction structures illustrated inFIGS. 6A-6D or the p-n junction structures illustrated inFIGS. 6E and 6F may be formed instead of the p-i-n junction illustrated inFIG. 6F . Generally, any p-i-n junction or any p-n junction described above may be formed in thetrench 69. - Referring to
FIG. 7G , additional dielectric material layers 94 andmetal interconnect structures 80 may be formed to provide electrical connection to and from the various nodes of the semiconductor devices and the photodetector. For example, the second-conductivity-type germanium-containingregion 302 may be connected to thesource region 48 of thetransfer transistor 610 through a subset of the metal interconnect structures and the second-conductivity-type silicon region 342. The first-conductivity-type germanium-containingregion 301 may be suitably biased by a biasing circuit through another subset ofmetal interconnect structures 80. -
FIG. 7H is a vertical cross-sectional view of an alternative configuration of the fifth exemplary structure according to the fifth embodiment of the present disclosure. Referring toFIG. 7H , an alternative configuration of the fifth exemplary structure may be derived from the fifth exemplary structure ofFIG. 7G by forming a siliconnitride capping structure 41 in lieu of asilicon capping structure 34. In this embodiment, each of the first-conductivity-type germanium-containingregion 301 and the second-conductivity-type germanium-containingregion 302 may be directly contacted by a respective one of themetal interconnect structures 80, such as a respective metal viastructure 82. - Generally, any type of photovoltaic junction may be formed within the germanium-containing
well 30. The photovoltaic junction may be a vertical p-i-n junction, a lateral p-i-n junction, a vertical p-n junction, or a lateral p-n junction. Further, the configuration of a pinned diode using an pinning layer or the configuration of a single-photon avalanche diode (SPAD) may also be used. While specific embodiments of the photovoltaic junction formed within a germanium-containing well 30 are described herein, it is to be understood that the scope of the present disclosure is not limited by any particular configuration of a photovoltaic junction provided that a germanium-containing well 30 is used as a component of a photovoltaic junction. - The germanium-containing material of the germanium-containing well 30 may be doped germanium or a doped silicon-germanium alloy including germanium at an atomic percentage greater than 50%. The germanium-containing well 30 may be completely encapsulated by a combination of the first-conductivity-
type silicon region 21 and the silicon-containing capping structure (34 or 41), or by a combination of thesilicon liner 32 and the silicon-containing capping structure (34 or 41). Thus, physical contact between the germanium-containing well 30 and the dielectric material layers 90 or any other oxygen-containing component within the fourth or fifth exemplary structure may be avoided, and the germanium-containing well 30 may remain free of oxidation. - Referring to
FIGS. 5A-7H and according to various embodiments of the present disclosure, a semiconductor structure including a photodetector is provided. The photodetector comprises: a germanium-containing well 30 embedded in a single crystalline silicon substrate (10, 110) and extending to a proximalhorizontal surface 7 of the single crystalline silicon substrate (10, 110), wherein the germanium-containing well 30 includes germanium at an atomic percentage greater than 50%; and a silicon-containing capping structure (34 or 41) located on a top surface of the germanium-containing well 30 and including silicon atoms at an atomic percentage greater than 42%. The silicon-containing capping structure (34 or 41) may comprise asilicon capping structure 34 consisting essentially of doped silicon, or as a siliconnitride capping structure 41 consisting essentially of silicon nitride. The germanium-containing well 30 comprises a photovoltaic junction including a first-conductivity-type germanium-containingregion 301 and a second-conductivity-type germanium-containingregion 302. - In one embodiment, the photovoltaic junction comprises a p-i-n junction; and the germanium-containing well 30 comprises an intermediate germanium-containing
region 308 having an atomic concentration of dopants in a range from 1.0×1013/cm3 to 1.0×1017/cm3 and contacting the first-conductivity-type germanium-containingregion 301 and the second-conductivity-type germanium-containingregion 302. - In one embodiment, the silicon-containing
capping structure 34 comprises: a first-conductivity-type silicon region 341 contacting the first-conductivity-type germanium-containingregion 301; and a second-conductivity-type silicon region 342 contacting the second conductivity type germanium-containingregion 302. - In one embodiment, the silicon-containing
capping structure 34 comprises anpassivation silicon region 340 having an atomic concentration of dopants in a range from 1.0×1013/cm3 to 1.0×1017/cm3 and located between the first-conductivity-type silicon region 341 and the second-conductivity-type silicon region 342. - In one embodiment, the germanium-containing well 30 comprises a single crystalline germanium-containing semiconductor material in epitaxial alignment with the single crystalline silicon substrate (10, 110). In one embodiment, a proximal surface of the silicon-containing capping structure (34 or 41) is in contact with the germanium-containing well 30; and a distal surface of the silicon-containing capping structure (34 or 41) is vertically offset away from a horizontal plane including a proximal
horizontal surface 7 of the single crystalline silicon substrate (10, 110). - In one embodiment, the photovoltaic junction comprises a p-n junction; and the first-conductivity-type germanium-containing
region 301 contacts the second-conductivity-type germanium-containingregion 302. - In one embodiment, the semiconductor structure may comprise a sensing circuit comprising field effect transistors located on the single crystalline silicon substrate (10, 110); and dielectric material layers {90, 190, (92, 94)} located on the proximal
horizontal surface 7 of the single crystalline silicon substrate (10, 110) and containingmetal interconnect structures 80. A subset of themetal interconnect structures 80 may provide an electrically conductive path between the second-conductivity-type germanium-containingregion 302 and a source/drain region of one of the field effect transistors (such as asource region 48 of a transfer transistor 610). - In one embodiment, the semiconductor structure may comprise: first dielectric material layers 190 located on the proximal
horizontal surface 7 of the singlecrystalline silicon substrate 110 and containing firstmetal interconnect structures 80 andfirst bonding pads 188; asemiconductor die 720 comprising asemiconductor substrate 210, a sensing circuit comprising field effect transistors that are located on thesemiconductor substrate 210, and second dielectric material layers 290 located on thesemiconductor substrate 210 and containing secondmetal interconnect structures 80 andsecond bonding pads 288 therein. Thesecond bonding pads 288 may be bonded to a respective one of thefirst bonding pads 188, and a subset of the firstmetal interconnect structures 80 and the secondmetal interconnect structures 80 provides an electrically conductive path between the second-conductivity-type germanium-containingregion 302 and a source/drain region of one of the field effect transistors in the sensing circuit (such as asource region 48 of a transfer transistor 610). - Referring to
FIG. 8 , a first process flow diagram 800 illustrates an exemplary process sequence for forming an image sensor according to an embodiment of the present disclosure. Referring to step 810 andFIGS. 2B, 5A, and 7A , a dielectric mask layer (12, 92) may be deposited and patterned over a single crystalline silicon substrate (10, 110). Referring to step 820 andFIGS. 2B, 5A, and 7B , atrench 69 may be etched in the single crystalline silicon substrate (10, 110) through an opening in the dielectric mask layer (12, 92). Referring to step 830 andFIGS. 2C-2G, 3A, 3B, 4A, 4B, 5B, 5F, 6A-6F, 7C and 7D, and 7H , a germanium-containing well 30 may be formed within thetrench 69. The germanium-containing well 30 includes germanium at an atomic percentage greater than 50%. In one embodiment, the germanium-containing well 30 may be single crystalline, and may be epitaxially aligned to the single crystalline silicon substrate (10, 110). Referring to step 840 andFIGS. 2H, 2L, 3A, 3B, 4A, 4B, 5C, 5F, 6A-6F, 7E, and 7H , a silicon-containing capping structure (34 or 41) may be formed on the top surface of the germanium-containingwell 30. Referring to step 850 andFIGS. 2I-2L, 3A, 3B, 4A, 4B, 5D-5F, 6A-6F, and 7F-7H , a photovoltaic junction may be formed within, or across, thetrench 69 by implanting dopants of a first conductivity type and dopants of a second conductivity type. - Referring to
FIG. 9 , a second process flow diagram 900 illustrates an exemplary process sequence for forming an image sensor illustrated inFIG. 2K or inFIG. 2L . Referring to step 921 andFIG. 2A , a singlecrystalline silicon substrate 10 may be provided. Referring to step 922 andFIG. 2B , a patterneddielectric mask layer 12 may be formed on a top surface of the singlecrystalline silicon substrate 10, and atrench 69 may be formed in the upper portion of the singlecrystalline silicon substrate 10 employing the patterneddielectric mask layer 12 as an etch mask. Referring to step 923 andFIG. 2C , a first-conductivity-type silicon region 21 may be formed around thetrench 69 within the singlecrystalline silicon substrate 10, for example, by ion implantation of dopants of a first conductivity type. Referring to step 924 andFIG. 2D , asilicon liner 32 may be optionally grown from physically exposed surfaces of the first-conductivity-type silicon region 21. Referring to step 925 andFIG. 2E , a germanium-containingmaterial layer 30L may be formed in thetrench 69 and over the single-crystalline silicon substrate (9, 10). In one embodiment, an epitaxial deposition process may be performed to grow a single crystalline germanium-containing material inside thetrench 69 to form the germanium-containingmaterial layer 30L. Referring to step 926 andFIG. 2F , a germanium-containing well 30 may be formed by performing a planarization process on the germanium-containingmaterial layer 30L. Referring to step 927 andFIG. 2G , the germanium-containing well 30 may be optionally vertically recessed. Referring to step 928 andFIGS. 2H and 2L , a silicon-containing capping structure (such as apassivation silicon region 340 illustrated inFIG. 2H or a siliconnitride capping structure 41 illustrated inFIG. 2L ) may be formed on a top surface of the germanium-containingwell 30. Referring to step 929 andFIGS. 2I and 2L , a second-conductivity-type germanium-containingregion 302 may be formed by doping an upper portion of the germanium-containing well 30 with dopants of a second conductivity type. Referring to step 930 andFIGS. 2J and 2L , field effect transistors (610, 630, 640) may be formed in aphotodetector region 510 and in asensing circuit region 520 on the singlecrystalline silicon substrate 10. Referring to step 931 andFIGS. 2K and 2L , dielectric material layers 90 andmetal interconnect structures 80 may be formed over the field effect transistors (610, 630, 640). - Referring to
FIG. 10 , a third process flow diagram 1000 illustrates an exemplary process sequence for forming an image sensor illustrated inFIG. 3A or inFIG. 3B . Referring to step 1010, a photovoltaic junction of a subpixel may be formed in afirst semiconductor substrate 110 by performing the processing steps ofFIGS. 2A-2I, 2K, and 2L , which correspond to the processing steps 921-929 and 930 in the second process flow diagram ofFIG. 9 . In this embodiment, field effect transistors (610, 630, 640) are not present on thefirst semiconductor substrate 110 as illustrated inFIGS. 3A and 3B . Referring to step 1020 andFIGS. 3A and 3B , the sensing circuit of the subpixel may be formed on asecond semiconductor substrate 210, which may be a silicon substrate. Thetransfer transistor 610 for each photodetector may be formed on thesecond semiconductor substrate 210. Referring to step 1030 andFIGS. 3A and 3B , a first wafer including thefirst semiconductor substrate 110 and the first dielectric material layers 190 may be bonded to a second wafer including thesecond semiconductor substrate 210 and the second dielectric material layers 290 by wafer-to-wafer bonding. Subsequently, thefirst semiconductor substrate 110 may be thinned, and the bonded assembly can be subsequently diced.FIG. 3A illustrates an embodiment in which a silicon-containing capping structure comprises apassivation silicon region 340, andFIG. 3B illustrates an embodiment in which the silicon-containing capping structure comprises a siliconnitride capping structure 41. - Referring to
FIG. 11 , a fourth process flow diagram 1100 illustrates an exemplary process sequence for forming an image sensor illustrated inFIG. 4A or inFIG. 4B . Referring to step 1110, a photovoltaic junction of a subpixel may be formed in afirst semiconductor substrate 110 by performing the processing steps ofFIGS. 2A-2L . In this case, field effect transistors are formed on thefirst semiconductor substrate 110 as illustrated inFIGS. 4A and 4B . Referring to step 1120 andFIGS. 4A and 4B , additional field effect transistors (630, 640) may be formed on asecond semiconductor substrate 210, which may be a silicon substrate. Thetransfer transistor 610 for photodetector may be formed on thefirst semiconductor substrate 110, and field effect transistors for the sensing circuit can be formed on thefirst semiconductor substrate 110 and/or on thesecond semiconductor substrate 210. Referring to step 1130 andFIGS. 4A and 4B , a first wafer including thefirst semiconductor substrate 110 and the first dielectric material layers 190 may be bonded to a second wafer including thesecond semiconductor substrate 210 and the second dielectric material layers 290 by wafer-to-wafer bonding. Subsequently, thefirst semiconductor substrate 110 may be thinned, and the bonded assembly can be subsequently diced.FIG. 4A illustrates an embodiment in which a silicon-containing capping structure comprises apassivation silicon region 340, andFIG. 4B illustrates an embodiment in which the silicon-containing capping structure comprises a siliconnitride capping structure 41. - Referring to
FIG. 12 , a fifth process flow diagram 1200 illustrates an exemplary process sequence for forming an image sensor illustrated in inFIGS. 5F and 6A-6F . Referring to step 1210 andFIG. 2A-2C, 5A, and 6A-6F , atrench 69 may be formed in an upper portion of afirst semiconductor substrate 110 through an opening in adielectric mask layer 12. Asilicon liner 32 may be formed as illustrated inFIGS. 5F, 6C, 6E , or may be omitted as illustrated inFIGS. 6A, 6B, 6D, and 6F . Referring to step 1220 andFIGS. 2D, 2E, 2F, 2G, 5B, and 6A-6F , anoptional silicon liner 32 and a germanium-containing well 30 can be formed. Referring to step 1230 andFIGS. 5C and 6A-6F , apassivation silicon region 340 can be formed on a top surface of the germanium-containing well 30 within an opening in thedielectric mask layer 12. Referring to step 1240 andFIGS. 5D and 6A-6F , electrical dopants can be implanted into upper portions of the germanium-containing well 30 and into thepassivation silicon region 340 to form a p-i-n junction as illustrated inFIGS. 5D and 6A-6D , or to form a p-n junction as illustrated inFIGS. 6E and 6F . Referring to step 1250 andFIGS. 5E and 6A-6F , thedielectric mask layer 12 may be removed, and first dielectric material layers 190,metal interconnect structures 80, andfirst bonding pads 188 may be formed over thefirst semiconductor substrate 110. Referring to step 1260 andFIGS. 5F and 6A-6F , a first wafer including thefirst semiconductor substrate 110 and the first dielectric material layers 190 can be bonded to a second wafer including thesecond semiconductor substrate 210 and the second dielectric material layers 290 by wafer-to-wafer bonding. Subsequently, thefirst semiconductor substrate 110 may be thinned, and the bonded assembly can be subsequently diced. - Referring to
FIG. 13 , a sixth process flow diagram 1300 illustrates an exemplary process sequence for forming an image sensor illustrated inFIGS. 7G and 7H . Referring to step 1310 andFIG. 7A , semiconductor devices of a sensing circuit may be formed on, and/or in, an upper portion of a singlecrystalline silicon substrate 10. Referring to step 1320 andFIG. 7B , atrench 69 may be formed through adielectric mask layer 92 into an upper portion of the singlecrystalline silicon substrate 10. Referring to step 1330 andFIG. 7C , anoptional silicon liner 32 and a germanium-containingmaterial layer 30L can be formed in thetrench 69. Referring to step 1340 andFIG. 7D , a germanium-containing well 30 may be formed in thetrench 60 by patterning the germanium-containingmaterial layer 30L. Referring to step 1350 andFIGS. 7E and 7H , a silicon-containing capping structure comprising apassivation silicon region 34 or a siliconnitride capping structure 41 can be formed on top of the germanium-containingwell 30. Referring to step 1360 andFIGS. 7F and 7H , ion implantation processes may be performed to form a p-i-n junction or a p-n junction in thetrench 69. Referring to step 1370 andFIGS. 7G and 7H , additional dielectric material layers 94 andmetal interconnect structures 80 may be formed over the singlecrystalline silicon substrate 10 to provide electrical connection to and from the various nodes of the semiconductor devices and the photodetector. - The germanium-based photodetector of the present disclosure may provide high quantum efficiency in the infrared wavelength range. Further, the germanium-based photodetector of the present disclosure may provide higher operation speed and fast response for high-speed motion applications such as high-speed distance measurement compared to silicon-based photodetectors. The germanium-based photodetector of the present disclosure is integrated with standard CMOS logic devices (such as CMOS field effect transistors) to provide incorporation into a semiconductor die.
- The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
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US17/227,432 US11837613B2 (en) | 2020-05-29 | 2021-04-12 | Germanium-containing photodetector and methods of forming the same |
DE102021109737.1A DE102021109737A1 (en) | 2020-05-29 | 2021-04-19 | GERMANIUM CONTAINING PHOTODETECTOR AND PROCESS FOR ITS MANUFACTURING |
TW110118880A TWI789767B (en) | 2020-05-29 | 2021-05-25 | Semiconductor structure and method of forming photodetector |
KR1020210069444A KR102579596B1 (en) | 2020-05-29 | 2021-05-28 | Germanium-containing photodetector and methods of forming the same |
CN202110601878.0A CN113380845A (en) | 2020-05-29 | 2021-05-31 | Semiconductor structure including a photodetector and method of forming a photodetector |
US18/358,257 US12051763B2 (en) | 2020-05-29 | 2023-07-25 | Germanium-containing photodetector and methods of forming the same |
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