US20200364138A1

US20200364138A1 - Apparatuses and methods for write address tracking

Info

Publication number: US20200364138A1
Application number: US16/983,779
Authority: US
Inventors: Gary L. Howe; Timothy P. Finkbeiner
Original assignee: Micron Technology Inc
Current assignee: Lodestar Licensing Group LLC
Priority date: 2016-07-20
Filing date: 2020-08-03
Publication date: 2020-11-19
Also published as: US10733089B2; US20180024769A1

Abstract

Apparatuses and methods are provided for write address tracking. An example apparatus can include an array of memory cells and a cache coupled to the array. The example apparatus can include tracking circuitry coupled to the cache. The tracking circuitry can be configured to track write addresses of data written to the cache.

Description

PRIORITY INFORMATION

This application is a Continuation of U.S. application Ser. No. 15/215,296, filed Jul. 20, 2016, which issues as U.S. Pat. No. 10,733,089 on Aug. 4, 2020, the contents of which are incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates generally to semiconductor memory and methods, and more particularly, to apparatuses and methods for write address tracking.

BACKGROUND

Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other computing systems. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its data (e.g., host data, error data, etc.) and includes random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), and thyristor random access memory (TRAM), among others. Non-volatile memory can provide persistent data by retaining stored data when not powered and can include NAND flash memory, NOR flash memory, and resistance variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), such as spin torque transfer random access memory (STT RAM), among others.
Computing systems often include a number of processing resources (e.g., one or more processors), which may retrieve and execute instructions and store the results of the executed instructions to a suitable location. A processing resource (e.g., CPU) can comprise a number of functional units such as arithmetic logic unit (ALU) circuitry, floating point unit (FPU) circuitry, and/or a combinatorial logic block, for example, which can be used to execute instructions by performing logical operations such as AND, OR, NOT, NAND, NOR, and XOR, and invert (e.g., inversion) logical operations on data (e.g., one or more operands). For example, functional unit circuitry may be used to perform arithmetic operations such as addition, subtraction, multiplication, and/or division on operands via a number of logical operations.
A number of components in a computing system may be involved in providing instructions to the functional unit circuitry for execution. The instructions may be executed, for instance, by a processing resource such as a controller and/or host processor. Data (e.g., the operands on which the instructions will be executed) may be stored in a memory array that is accessible by the functional unit circuitry. The instructions and/or data may be retrieved from the memory array and sequenced and/or buffered before the functional unit circuitry begins to execute instructions on the data. Furthermore, as different types of operations may be executed in one or multiple clock cycles through the functional unit circuitry, intermediate results of the instructions and/or data may also be sequenced and/or buffered. Data stored in the memory array and/or intermediate results of the instructions may be stored in a memory cache. The memory cache can be used to transfer and/or operate on the stored data. When data located in the cache is operated on, changed, and/or updated, the data may conflict with corresponding data stored in the memory array. In order to update the memory array, an entire cache of data may be written to the memory array in order to correlate the data in the cache to the data in the memory array.
In many instances, the processing resources (e.g., processor and/or associated functional unit circuitry) may be external to the memory array, and data is accessed via a bus between the processing resources and the memory array to execute a set of instructions. Processing performance may be improved in a processor-in-memory (PIM) device, in which a processor may be implemented internal and/or near to a memory (e.g., directly on a same chip as the memory array). A PIM device may save time by reducing and/or eliminating external communications and may also conserve power.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an apparatus in the form of a computing system including one example of a processing in memory (PIM) capable device coupled to a host in accordance with the present disclosure.

FIG. 2 is a schematic diagram illustrating a system for tracking write addresses in accordance with the present disclosure.

FIG. 3 is a block diagram illustrating a portion of one example of a PIM capable device in greater detail in accordance with the present disclosure.

FIG. 4 is a schematic diagram illustrating sensing circuitry of a memory device in accordance with a number of embodiments of the present disclosure.

FIG. 5 is a schematic diagram illustrating circuitry for data transfer in a memory device in accordance with a number of embodiments of the present disclosure.

DETAILED DESCRIPTION

An example apparatus includes an array of memory cells and a cache coupled to the array. The example apparatus can include tracking circuitry coupled to the cache. The tracking circuitry can be configured to track write addresses of data written to the cache.
According to various embodiments of the present disclosure, tracking circuitry is configured to track write addresses. For example, data can be written from a memory array to a cache. At least a portion of the data written to the cache can be updated and the data in the cache can be written to the memory array to maintain consistency between the memory array and the cache. Further, a write address associated with the data can be tracked when the write address corresponds to data in a cache that has been updated. For example, when data in a cache associated with a first write address is updated to include a change in that data in the cache, the first write address is tracked as being updated (e.g., a latch corresponding to the first write address may set an indicator bit). In addition, when data in a cache associated with a second write address is not updated, the second write address is indicated as not being updated (e.g., a latch corresponding to the second write address may not have one or more indicator bits set). In previous approaches, in response to a command to transfer data from a cache to a memory array the entire cache may be written to the memory array to maintain consistency of data between them. However, this can involve significant power and/or transfer time to write data (including non-updated data) from the cache to the memory array. Thus, in some embodiments where data in the memory array is written into the cache but not updated, duplicative power and/or additional transfer time may be involved as data that is already consistent will be transferred (e.g., the non-updated data will be written even though the non-updated data has not changed).
In accordance with embodiments of the present disclosure, data may be written to a cache. The data written to the cache can be updated and written back to the memory array. In response to a command to write the data in the cache to the memory array, the data that has been updated and is associated with the first write address can be written to the memory array and data that has not been updated and is associated with the second write address will not be written to the memory array. In this way, power and/or transfer time will be saved by transferring updated data from the cache to the memory array without transferring data that has not been updated.
In the following detailed description of the present disclosure, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration how one or more embodiments of the disclosure may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the embodiments of this disclosure, and it is to be understood that other embodiments may be utilized and that process, electrical, and/or structural changes may be made without departing from the scope of the present disclosure. As used herein, “a number of” a particular thing can refer to one or more of such things (e.g., a number of memory arrays can refer to one or more memory arrays). A “plurality of” is intended to refer to more than one of such things.
The figures herein follow a numbering convention in which the first digit or digits correspond to the drawing figure number and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by the use of similar digits. For example, 130 may reference element “30” in FIG. 1, and a similar element may be referenced as 230 in FIG. 2. As will be appreciated, elements shown in the various embodiments herein can be added, exchanged, and/or eliminated so as to provide a number of additional embodiments of the present disclosure. In addition, as will be appreciated, the proportion and the relative scale of the elements provided in the figures are intended to illustrate certain embodiments of the present invention, and should not be taken in a limiting sense.
FIG. 1 is a block diagram of an apparatus in the form of a computing system 100 including one example of a processing in memory (PIM) capable device 101 coupled to a host 110. The PIM capable device 101 (also referred to as “memory device 101”) may include a controller 140. FIG. 1 is provided as an example of a system including a current PIM capable device 101 architecture.
As shown in the example of FIG. 1, the memory device 101 may include a memory array 130, a command interface 136, sensing circuitry 150, and additional logic circuitry 170. The system 100 can include separate integrated circuits or both the logic and memory can be on the same integrated device as with a system on a chip (SoC). The system 100 can be, for instance, a server system and/or a high performance computing (HPC) system and/or a portion thereof.
For clarity, the system 100 has been simplified to focus on features with relevance to the present disclosure. The memory array 130 can be a DRAM array, SRAM array, STT RAM array, PCRAM array, TRAM array, RRAM array, NAND flash array, and/or NOR flash array, for instance. The array 130 can comprise memory cells arranged in rows coupled by access lines (which may be referred to herein as word lines or select lines) and columns coupled by sense lines, which may be referred to herein as data lines or digit lines. Although a single array 130 is shown in FIG. 1, embodiments are not so limited. For instance, memory device 101 may include a number of arrays 130 (e.g., a number of banks of DRAM cells, NAND flash cells, etc.).
The memory device 101 includes address circuitry 142 to latch address signals provided over a data bus 156 (e.g., an I/O bus) through I/O circuitry 144. Status and/or exception information can be provided from the controller 140 on the memory device 101 to a host 102 and/or logic resource through an out-of-band bus 157. Address signals are received through address circuitry 142 and decoded by a row decoder 146 and a column decoder 152 to access the memory array 130. Data can be read from memory array 130 by sensing voltage and/or current changes on the data lines using sensing circuitry 150. The sensing circuitry 150 can read and latch a page (e.g., row) of data from the memory array 130. The I/O circuitry 144 can be used for bi-directional data communication with host 110 over the data bus 156. The write circuitry 148 is used to write data to the memory array 130. Address, control and/or commands, e.g., processing in memory (PIM) commands, may be received to the controller 140 via bus 154.
Command interface 136 may include control registers, e.g., double data rate (DDR) control registers in a DRAM, to control the operation of the array 130, e.g., DRAM array, and/or controller 140. As such, the command interface 136 may be coupled to the I/O circuitry 144 and/or controller 140. In various embodiments the command interface 136 may be memory mapped I/O registers. The memory mapped I/O registers can be mapped to a plurality of locations in memory where microcode instructions are stored. However, embodiments are not so limited. For example, any number of memory arrays with a cache between the main array and a host interface can use the command interface 136.
In various embodiments, controller 140 may decode signals received via bus 154 from the host 110. These signals can include chip enable signals, write enable signals, and address latch signals that are used to control operations performed on the memory array 130, including data read, data write, and data erase operations. In one or more embodiments, portions of the controller 140 can be a reduced instruction set computer (RISC) type controller operating on 32 and/or 64 bit length instructions. In various embodiments, the controller 140 is responsible for executing instructions from the host 110 and/or logic components in association with the sensing circuitry 150 to perform logical Boolean operations such as AND, OR, XOR, etc. Further, the controller 140 can control shifting data (e.g., right or left) in an array, e.g., memory array 130. Additionally, portions of the controller 140 can include control logic, a sequencer, timing circuitry and/or some other type of controller, described further in connection with FIG. 2.
Examples of the sensing circuitry 150 and its operations are described further below in connection with FIG. 4. In various embodiments the sensing circuitry 150 can comprise a plurality of sense amplifiers and a plurality of compute components, which may serve as and be referred to herein as an accumulator, and can be used to perform logical operations (e.g., on data associated with complementary data lines).
In various embodiments, the sensing circuitry 150 can be used to perform logical operations using data stored in array 130 as inputs and store the results of the logical operations back to the array 130 without transferring data via a sense line address access (e.g., without firing a column decode signal). As such, various compute functions can be performed using, and within, sensing circuitry 150 rather than (or in association with) being performed by processing resources external to the sensing circuitry (e.g., by a processing resource associated with host 110 and/or other processing circuitry, such as ALU circuitry, located on memory device 101 (e.g., on controller 140 or elsewhere)).
In various previous approaches, data associated with an operand, for instance, would be read from memory via sensing circuitry and provided to external ALU circuitry via I/O lines (e.g., via local I/O lines and/or global I/O lines). The external ALU circuitry could include a number of registers and would perform compute functions using the operands, and the result would be transferred back to the array via the I/O lines. In contrast, in a number of embodiments of the present disclosure, sensing circuitry 150 is configured to perform logical operations on data stored in memory array 130 and store the result back to the memory array 130 without enabling an I/O line (e.g., a local I/O line) coupled to the sensing circuitry 150. The sensing circuitry 150 can be formed on pitch with the memory cells of the array 130. Additional peripheral sense amplifiers, extended row address (XRA) registers, cache and/or data buffering, e.g., additional logic circuitry 170, can be coupled to the sensing circuitry 150 and can be used to store, e.g., cache and/or buffer, results of operations described herein.
Thus, in various embodiments, circuitry external to array 130 and sensing circuitry 150 is not needed to perform compute functions as the sensing circuitry 150 can perform the appropriate logical operations to perform such compute functions without the use of an external processing resource. Therefore, the sensing circuitry 150 may be used to compliment and/or to replace, at least to some extent, such an external processing resource (or at least the bandwidth consumption of such an external processing resource).
However, in a number of embodiments, the sensing circuitry 150 may be used to perform logical operations (e.g., to execute instructions) in addition to logical operations performed by an external processing resource (e.g., on host 110). For instance, processing resources on host 110 and/or sensing circuitry 150 on memory device 101 may be limited to performing only certain logical operations and/or a certain number of logical operations.
Enabling an I/O line can include enabling (e.g., turning on) a transistor having a gate coupled to a decode signal (e.g., a column decode signal) and a source/drain coupled to the I/O line. However, embodiments are not limited to not enabling an I/O line. For instance, in a number of embodiments, the sensing circuitry (e.g., 150) can be used to perform logical operations without enabling column decode lines of the array; however, the local I/O line(s) may be enabled in order to transfer a result to a suitable location other than back to the array 130 (e.g., to an external register).
FIG. 2 is a schematic diagram illustrating a system for tracking write addresses in accordance with the present disclosure. The system illustrated in FIG. 2 can include a memory array 230 coupled to a cache 270. The memory array 230 can store data to be processed by the controller 240 and/or additional controllers (not illustrated). The data stored in the memory array 230 can be stored to the cache 270 in a number of memory cells and/or registers. The data stored to the cache 270 can be requested by additional components and/or memory locations (such as memory bank 321-7 in FIG. 3). For example, a memory location (e.g., memory bank 321-7) may request data stored in the memory array 230 that is also stored in the cache 270 for processing. The data can be transferred from the cache 270 to the memory location using a number of I/O lines (e.g., shared I/O line 555 in FIG. 5).
A controller 240 can be coupled to the cache 270. The controller 240 can send a number of indications to the cache 270. A first indication 274 can indicate to copy data in the cache 270 to the memory array 230. A second indication 276 can indicate column addresses 276 associated with data to the cache 270, indicating where the data is stored in the cache 270 and/or in the memory array 230.
A command interface 236 can be coupled to the cache 270. The command interface 236 can be a Double Data Rate (DDR) Synchronous Dynamic Random-Access Memory (SDRAM) command interface. The command interface 236 can send a write command 266 to the cache 270. The write command 266 can be transferred through latch circuitry 260 of the cache 270 and indicate to the latch circuitry that data 272 associated with the write command 266 will be updated. While the tracking circuitry including logic 264 and latch circuitry 260 is illustrated as being a portion of the cache 270, embodiments are not so limited. For example, the logic 264 and/or the latch circuitry 260 can be located outside the cache 270 and can be coupled to and/or in communication with the cache 270.
The latch circuitry 260 can include a latch 262 that corresponds to a particular write address. For example, the command interface 236 can send a write command 266 to write a particular portion of data 272 associated with a particular column address 268. In response to the write command 266 being sent to the latch circuitry 260, the latch 262 can store a particular data value. The latch 262 storing the particular data value can be a set flag that indicates that the portion of data 272 (corresponding to the column address 268) has been updated.
As described herein, in response to a controller sending an indication 274 to copy data in the cache 270 to the memory array 230, portions of the data of the cache 270 that include a set flag in the latch circuitry 260 are written to the memory array. For example, data (e.g., data 272) associated with a latch (e.g., latch 262) that stores a data value indicating the data has been updated and/or written to is written to the memory array 230. Additional portions of the data of the cache 270 that do not include a set flag (e.g., a latch corresponding to each column address of the additional portions includes a data value that indicates the additional portions have not been updated) are not written to the memory array 230. For example, a column address 276 associated with data to be written from the cache 270 to the memory array 230 can be compared, using logic circuitry 264, to a column address 268 associated with data indicated by the command interface 236 to be updated in the cache.
Put another way, the command interface can send write commands 266 to the cache to update a first set of data 272 associated with column addresses 268. In response to the controller 240 indicating, at 274, to write data from the cache 270 associated with indicated column addresses, at 276, to the memory array 230, the first set of data 272 is written to the memory array 230 and a second set of data (not illustrated) is not written to the memory array 230. For example, the controller indicates, at 274, to copy a first set of column addresses (indicated at 276). The first set of column addresses are received by logic circuitry 264 and compared to the column addresses 268 that have entered the latch circuitry 260. In response to a column address at 274 matching a column address 268 that includes a set flag in a corresponding latch 262, the data associated with set flag is written to the memory array. Each of the column addresses indicated at 276 are compared to a corresponding latch 262 and written to the memory array 230 when a corresponding latch 262 includes a set flag and not written to the memory array 230 when the corresponding latch 262 does not include a set flag. This can avoid having to transfer a full cache to the memory array 230 in response to at least a portion of the data in the cache being updated and/or altered.
In some embodiments, the controller 240 can indicate to copy column addresses 276 associated with all data stored in the cache 270. The latch circuitry 260 can track column addresses that correspond to updated data 272. The unwritten and/or non-updated column addresses can be masked such that in response to all column addresses of the cache 270 being selected to be written to the memory array 230, only the column addresses of data that have been updated are written to the memory array 230. Masking can include blocking column select activation lines of the unwritten data of the column addresses and/or disabling write data drivers associated with the unwritten data of the column addresses. For example, array write paths (from the cache 270 to the memory array 230) are enabled for addresses associated with data written (updated) to the cache 270. Array write paths (from the cache 270 to the memory array 230) are masked for addresses associated with data not written (non-updated) to the cache 270. The write address latch circuitry 260 can be cleared in response to a write from the cache 270 to the memory array 230. In this way, transferring of updated data is not duplicated and tracking of write addresses is restarted after each write to the memory array 230 from the cache 270.
In some embodiments, a number of I/O data lines can determine a configuration of the system. For example, a system with 64 I/O lines can use a minimum data size of 512 bits such that eight cycles can be correlated to a 4 k data transfer at a time. In this example, 32 enable bits would be used to store data in a 16 k wide data register. Further, 32 enable bits each corresponding to 512 bits equals 16 k wide data. In an example including a system with 32 I/O lines, a minimum data size of 256 bits can be used with 64 enable bits for a 16 k wide data register. In an example including a system with 16 I/O lines, a minimum data size of 128 bits can be used with 128 enable bits for a 16 k wide data register.
In a number of embodiments, a cache control mode can be used to control reads and writes. For example, a particular word line and a particular column address of the cache 270 can be activated such that an entire cache 270 of data is not transferred.
FIG. 3 is another block diagram in greater detail of a portion of one example of a PIM capable device 320 such as memory device 101 in FIG. 1. In the example of FIG. 3, a controller 340-1, . . . , 340-7 (referred to generally as controller 340) may be associated with each bank 321-1, . . . , 321-7 (referred to generally as 321) to the PIM capable device 320. Eight banks are shown in the example of FIG. 3. However, embodiments are not limited to this example number. Controller 340 may represent controller 140 shown in FIG. 1. Each bank may include one or more arrays of memory cells (not shown). For example each bank may include one or more arrays such as array 130 in FIG. 1 and can include decoders, other circuitry and registers shown in FIG. 1. In the example PIM capable device 320 shown in FIG. 3, controllers 340-1, . . . , 340-7 are shown having control logic 331-1, . . . , 331-7, sequencers 332-1, . . . , 332-7, and timing circuitry 333-1, . . . , 333-7 as part of a controller 340 on one or more memory banks 321 of a memory device 320. The PIM capable device 320 may represent part of memory device 101 shown in FIG. 1.
As shown in the example of FIG. 3, the PIM capable device 320 may include a high speed interface (HSI) 341 to receive data, addresses, control signals, and/or commands at the PIM capable device 320. In various embodiments, the HSI 341 may be coupled to a bank arbiter 345 associated with the PIM capable device 320. The HSI 341 may be configured to receive commands and/or data from a host, e.g., 110 as in FIG. 1. As shown in the example of FIG. 3, the bank arbiter 345 may be coupled to the plurality of banks 321-1, . . . , 321-7.
In the example shown in FIG. 3, the control logic 331-1, . . . , 331-7 may be in the form of a microcoded engine responsible for fetching and executing machine instructions, e.g., microcode instructions, from an array of memory cells, e.g., an array as array 130 in FIG. 1, that is part of each bank 321-1, . . . , 321-7 (not detailed in FIG. 3). The sequencers 332-1, . . . , 332-7 may also be in the form of microcoded engines. Alternatively, the control logic 331-1, . . . , 331-7 may be in the form of a very large instruction word (VLIW) type processing resource and the sequencers 332-1, . . . , 332-7, and the timing circuitry 333-1, . . . , 333-7 may be in the form of state machines and transistor circuitry.
The control logic 331-1, . . . , 331-7 may decode microcode instructions into function calls, e.g., microcode function calls (uCODE), implemented by the sequencers 332-1, . . . , 332-7. The microcode function calls can be the operations that the sequencers 332-1, . . . , 332-7 receive and execute to cause the PIM device 320 to perform particular logical operations using the sensing circuitry such as sensing circuitry 150 in FIG. 1. The timing circuitry 333-1, . . . , 333-7 may provide timing to coordinate performance of the logical operations and be responsible for providing conflict free access to the arrays such as array 130 in FIG. 1.
As described in connection with FIG. 1, the controllers 340-1, . . . , 340-7 may be coupled to sensing circuitry 150 and/or additional logic circuitry 170, including cache, buffers, sense amplifiers, extended row address (XRA) latches, and/or registers 350/370-1, associated with arrays of memory cells via control lines and data paths shown in FIG. 3 as 355-1, 355-7. As such, sensing circuitry 150 and logic 170 shown in FIG. 1 can be associated to the arrays of memory cells 130 using data I/Os shown as 355-1, . . . , 355-7 in FIG. 3. The controllers 340-1, . . . , 340-7 may control regular DRAM operations for the arrays such as a read, write, copy, and/or erase operations, etc. Additionally, however, microcode instructions retrieved and executed by the control logic 331-1, . . . , 331-7 and the microcode function calls received and executed by the sequencers 332-1, . . . , 332-7 cause sensing circuitry 150 shown in FIG. 1 to perform additional logical operations such as addition, multiplication, or, as a more specific example, Boolean operations such as an AND, OR, XOR, etc., which are more complex than regular DRAM read and write operations. Hence, in this PIM capable device 320 example, microcode instruction execution and logic operations are performed on the banks 321-1, . . . , 321-7 to the PIM device 320.
As such, the control logic 331-1, . . . , 331-7, sequencers 332-1, . . . , 332-7, and timing circuitry 333-1, . . . , 333-7 may operate to generate sequences of operation cycles for a DRAM array. In the PIM capable device 320 example, each sequence may be designed to perform operations, such as a Boolean logic operations AND, OR, XOR, etc., which together achieve a specific function. For example, the sequences of operations may repetitively perform a logical operation for a one (1) bit add in order to calculate a multiple bit sum. Each sequence of operations may be fed into a first in/first out (FIFO) buffer coupled to the timing circuitry 333-1, . . . , 333-7 to provide timing coordination with the sensing circuitry 150 and/or additional logic circuitry 170 associated with the array of memory cells 130, e.g., DRAM arrays, shown in FIG. 1.
In the example PIM capable device 320 shown in FIG. 3, the timing circuitry 333-1, . . . , 333-7 provides timing and provides conflict free access to the arrays from four (4) FIFO queues. In this example, one FIFO queue may support array computation, one may be for Instruction fetch, one for microcode (e.g., Ucode) instruction fetch, and one for DRAM I/O. Both the control logic 331-1, . . . , 331-7 and the sequencers 332-1, . . . , 332-7 can generate status information, which is routed back to the bank arbiter 345 via a FIFO interface. The bank arbiter 345 may aggregate this status data and report it back to a host 110 via the HSI 341.
FIG. 4 is a schematic diagram illustrating sensing circuitry 450 in accordance with a number of embodiments of the present disclosure. The sensing circuitry 450 can correspond to sensing circuitry 150 shown in FIG. 1.
A memory cell can include a storage element (e.g., capacitor) and an access device (e.g., transistor). For instance, a first memory cell can include transistor 402-1 and capacitor 403-1, and a second memory cell can include transistor 402-2 and capacitor 403-2, etc. In this embodiment, the memory array 430 is a DRAM array of 1T1C (one transistor one capacitor) memory cells, although other embodiments of configurations can be used (e.g., 2T2C with two transistors and two capacitors per memory cell). In a number of embodiments, the memory cells may be destructive read memory cells (e.g., reading the data stored in the cell destroys the data such that the data originally stored in the cell is refreshed after being read).
The cells of the memory array 430 can be arranged in rows coupled by access (word) lines 404-X (Row X), 404-Y (Row Y), etc., and columns coupled by pairs of complementary sense lines (e.g., digit lines DIGIT(D) and DIGIT(D)_ shown in FIG. 4 and DIGIT_0 and DIGIT_0* shown in FIG. 5). The individual sense lines corresponding to each pair of complementary sense lines can also be referred to as digit lines 405-1 for DIGIT (D) and 405-2 for DIGIT (D)_, respectively, or corresponding reference numbers in FIG. 5. Although only one pair of complementary digit lines are shown in FIG. 4, embodiments of the present disclosure are not so limited, and an array of memory cells can include additional columns of memory cells and digit lines (e.g., 4,096, 8,192, 16,384, etc.).
Although rows and columns are illustrated as orthogonally oriented in a plane, embodiments are not so limited. For example, the rows and columns may be oriented relative to each other in any feasible three-dimensional configuration. For example, the rows and columns may be oriented at any angle relative to each other, may be oriented in a substantially horizontal plane or a substantially vertical plane, and/or may be oriented in a folded topology, among other possible three-dimensional configurations.
Memory cells can be coupled to different digit lines and word lines. For example, a first source/drain region of a transistor 402-1 can be coupled to digit line 405-1 (D), a second source/drain region of transistor 402-1 can be coupled to capacitor 403-1, and a gate of a transistor 402-1 can be coupled to word line 404-Y. A first source/drain region of a transistor 402-2 can be coupled to digit line 405-2 (D)_, a second source/drain region of transistor 402-2 can be coupled to capacitor 403-2, and a gate of a transistor 402-2 can be coupled to word line 404-X. A cell plate, as shown in FIG. 4, can be coupled to each of capacitors 403-1 and 403-2. The cell plate can be a common node to which a reference voltage (e.g., ground) can be applied in various memory array configurations.
The memory array 430 is configured to couple to sensing circuitry 450 in accordance with a number of embodiments of the present disclosure. In this embodiment, the sensing circuitry 450 comprises a sense amplifier 406 and a compute component 431 corresponding to respective columns of memory cells (e.g., coupled to respective pairs of complementary digit lines). The sense amplifier 406 can be coupled to the pair of complementary digit lines 405-1 and 405-2. The compute component 431 can be coupled to the sense amplifier 406 via pass gates 407-1 and 407-2. The gates of the pass gates 407-1 and 407-2 can be coupled to operation selection logic 413.
The operation selection logic 413 can be configured to include pass gate logic for controlling pass gates that couple the pair of complementary digit lines un-transposed between the sense amplifier 406 and the compute component 431 and swap gate logic for controlling swap gates that couple the pair of complementary digit lines transposed between the sense amplifier 406 and the compute component 431. The operation selection logic 413 can also be coupled to the pair of complementary digit lines 405-1 and 405-2. The operation selection logic 413 can be configured to control continuity of pass gates 407-1 and 407-2 based on a selected operation.
The sense amplifier 406 can be operated to determine a data value (e.g., logic state) stored in a selected memory cell. The sense amplifier 406 can comprise a cross coupled latch, which can be referred to herein as a primary latch. In the example illustrated in FIG. 4, the circuitry corresponding to sense amplifier 406 comprises a latch 415 including four transistors coupled to a pair of complementary digit lines D 405-1 and (D)_ 405-2. However, embodiments are not limited to this example. The latch 415 can be a cross coupled latch (e.g., gates of a pair of transistors) such as n-channel transistors (e.g., NMOS transistors) 427-1 and 427-2 are cross coupled with the gates of another pair of transistors, such as p-channel transistors (e.g., PMOS transistors) 429-1 and 429-2).
In operation, when a memory cell is being sensed (e.g., read), the voltage on one of the digit lines 405-1 (D) or 405-2 (D)_ will be slightly greater than the voltage on the other one of digit lines 405-1 (D) or 405-2 (D)_. An ACT signal and an RNL* signal can be driven low to enable (e.g., fire) the sense amplifier 406. The digit lines 405-1 (D) or 405-2 (D)_ having the lower voltage will turn on one of the PMOS transistor 429-1 or 429-2 to a greater extent than the other of PMOS transistor 429-1 or 429-2, thereby driving high the digit line 405-1 (D) or 405-2 (D)_ having the higher voltage to a greater extent than the other digit line 405-1 (D) or 405-2 (D)_ is driven high.
Similarly, the digit line 405-1 (D) or 405-2 (D)_ having the higher voltage will turn on one of the NMOS transistor 427-1 or 427-2 to a greater extent than the other of the NMOS transistor 427-1 or 427-2, thereby driving low the digit line 405-1 (D) or 405-2 (D)_ having the lower voltage to a greater extent than the other digit line 405-1 (D) or 405-2 (D)_ is driven low. As a result, after a short delay, the digit line 405-1 (D) or 405-2 (D)_ having the slightly greater voltage is driven to the voltage of the supply voltage V_CCthrough a source transistor, and the other digit line 405-1 (D) or 405-2 (D)_ is driven to the voltage of the reference voltage (e.g., ground) through a sink transistor. Therefore, the cross coupled NMOS transistors 427-1 and 427-2 and PMOS transistors 429-1 and 429-2 serve as a sense amplifier pair, which amplify the differential voltage on the digit lines 405-1 (D) and 405-2 (D)_ and operate to latch a data value sensed from the selected memory cell.
Embodiments are not limited to the sense amplifier 406 configuration illustrated in FIG. 4. As an example, the sense amplifier 406 can be a current-mode sense amplifier and a single-ended sense amplifier (e.g., sense amplifier coupled to one digit line). Also, embodiments of the present disclosure are not limited to a folded digit line architecture such as that shown in FIG. 4.
The sense amplifier 406 can, in conjunction with the compute component 431, be operated to perform various operations using data from an array as input. In a number of embodiments, the result of an operation can be stored back to the array without transferring the data via a digit line address access and/or moved between banks without using an external data bus (e.g., without firing a column decode signal such that data is transferred to circuitry external from the array and sensing circuitry via local I/O lines). As such, a number of embodiments of the present disclosure can enable performing operations and compute functions associated therewith using less power than various previous approaches. Additionally, since a number of embodiments eliminate the need to transfer data across local and global I/O lines and/or external data buses in order to perform compute functions (e.g., between memory and discrete processor), a number of embodiments can enable an increased (e.g., faster) processing capability as compared to previous approaches.
The sense amplifier 406 can further include equilibration circuitry 414, which can be configured to equilibrate the digit lines 405-1 (D) and 405-2 (D)_. In this example, the equilibration circuitry 414 comprises a transistor 424 coupled between digit lines 405-1 (D) and 405-2 (D)_. The equilibration circuitry 414 also comprises transistors 425-1 and 425-2 each having a first source/drain region coupled to an equilibration voltage (e.g., V_DD/2), where V_DDis a supply voltage associated with the array. A second source/drain region of transistor 425-1 can be coupled digit line 405-1 (D), and a second source/drain region of transistor 425-2 can be coupled digit line 405-2 (D)_. Gates of transistors 424, 425-1, and 425-2 can be coupled together, and to an equilibration (EQ) control signal line 426. As such, activating EQ enables the transistors 424, 425-1, and 425-2, which effectively shorts digit lines 405-1 (D) and 405-2 (D)_ together and to the equilibration voltage (e.g., V_DD/2).
Although FIG. 4 shows sense amplifier 406 comprising the equilibration circuitry 414, embodiments are not so limited, and the equilibration circuitry 414 may be implemented discretely from the sense amplifier 406, implemented in a different configuration than that shown in FIG. 4, or not implemented at all.
As described further below, in a number of embodiments, the sensing circuitry 450 (e.g., sense amplifier 406 and compute component 431) can be operated to perform a selected operation and initially store the result in one of the sense amplifier 406 or the compute component 431 without transferring data from the sensing circuitry via a local or global I/O line and/or moved between banks without using an external data bus (e.g., without performing a sense line address access via activation of a column decode signal, for instance).
Performance of operations (e.g., Boolean logical operations involving data values) is fundamental and commonly used. Boolean logical operations are used in many higher level operations. Consequently, speed and/or power efficiencies that can be realized with improved operations, can translate into speed and/or power efficiencies of higher order functionalities.
As shown in FIG. 4, the compute component 431 can also comprise a latch, which can be referred to herein as a secondary latch 464. The secondary latch 464 can be configured and operated in a manner similar to that described above with respect to the primary latch 415, with the exception that the pair of cross coupled p-channel transistors (e.g., PMOS transistors) included in the secondary latch can have their respective sources coupled to a supply voltage (e.g., V_DD), and the pair of cross coupled n-channel transistors (e.g., NMOS transistors) of the secondary latch can have their respective sources selectively coupled to a reference voltage (e.g., ground), such that the secondary latch is continuously enabled. The configuration of the compute component 431 is not limited to that shown in FIG. 4, and various other embodiments are feasible.
As described herein, a memory device (e.g., 101 in FIG. 1) can be configured to couple to a host (e.g., 110) via a data bus (e.g., 156) and a control bus (e.g., 154). A bank (e.g., bank 321-1 in FIG. 3) in the memory device can include a plurality of subarrays of memory cells. The bank can include sensing circuitry (e.g., 150 in FIG. 1 and corresponding reference numbers 450 in FIGS. 4 and 550 in FIG. 5) coupled to the plurality of subarrays via a plurality of columns (e.g., 522 in FIG. 5) of the memory cells. The sensing circuitry can include a sense amplifier and a compute component (e.g., 406 and 431, respectively, in FIG. 4) coupled to each of the columns.
The bank can include a plurality of sensing stripes (e.g., 350/370 in FIG. 3) each with sensing circuitry coupled to a respective subarray of the plurality of the subarrays. A controller (e.g., 140 in FIG. 1) coupled to the bank can be configured to direct, as described herein, movement of data values stored in a first subarray (e.g., from data values in a row of the subarray sensed (cached) by the coupled sensing stripe) to be stored in latches of a latch stripe and/or a latch component. Moving (e.g., copying, transferring, and/or transporting) data values between sense amplifiers and/or compute components (e.g., 406 and 431, respectively, in FIG. 4) in a sensing stripe and corresponding sense amplifiers and/or compute components that form latches in a latch stripe can be enabled by a number of selectably coupled shared I/O lines (e.g., 355 in FIG. 3) shared by the sensing component stripe and the latch stripe, as described herein.
The memory device can include a sensing stripe configured to include a number of a plurality of sense amplifiers and compute components (e.g., 506-0, 506-1, . . . , 506-7 and 531-0, 531-1, . . . , 331-7, respectively, as shown in FIG. 5) that can correspond to a number of the plurality of columns (e.g., 522 in FIGS. 5 and 405-1 and 405-2 in FIG. 4) of the memory cells, where the number of sense amplifiers and/or compute components can be selectably coupled to the plurality of shared I/O lines (e.g., via column select circuitry 558-1 and 558-2). The column select circuitry can be configured to selectably sense data in a particular column of memory cells of a subarray by being selectably coupled to a plurality of (e.g., four, eight, and sixteen, among other possibilities) sense amplifiers and/or compute components.
In some embodiments, a number of a plurality of sensing stripes (e.g., 350/370 in FIG. 3) in the bank can correspond to a number of the plurality of subarrays in the bank. A sensing stripe can include a number of sense amplifiers and/or compute components configured to move (e.g., copy, transfer, and/or transport) an amount of data sensed from a row of the first subarray in parallel to a plurality of shared I/O lines. In some embodiments, the amount of data can correspond to at least a thousand bit width of the plurality of shared I/O lines.
As described herein, the array of memory cells can include an implementation of DRAM memory cells where the controller is configured, in response to a command, to move (e.g., copy, transfer, and/or transport) data from the source location to the destination location via a shared I/O line. In various embodiments, the source location can be in a first bank and the destination location can be in a second bank in the memory device and/or the source location can be in a first subarray of one bank in the memory device and the destination location can be in a second subarray of a different bank. According to embodiments, the data can be moved as described in connection with FIG. 1. The first subarray and the second subarray can be in the same section of the bank or the subarrays can be in different sections of the bank.
As described herein, the apparatus can be configured to move (e.g., copy, transfer, and/or transport) data from a source location, including a particular row (e.g., 519 in FIG. 5) and column address associated with a first number of sense amplifiers and compute components) to a shared I/O line. In addition, the apparatus can be configured to move the data to a destination location, including a particular row and column address associated with a second number of sense amplifiers and compute components. As the reader will appreciate, each shared I/O line (e.g., 555) can actually include a complementary pair of shared I/O lines (e.g., shared I/O line and shared I/O line* as shown in the example configuration of FIG. 4). In some embodiments described herein, 2048 shared I/O lines (e.g., complementary pairs of shared I/O lines) can be configured as a 2048 bit wide shared I/O line.
FIG. 5 is a schematic diagram illustrating circuitry for data transfer in a memory device in accordance with a number of embodiments of the present disclosure. FIG. 5 shows eight sense amplifiers (e.g., sense amplifiers 0, 1, . . . , 7 shown at 506-0, 506-1, . . . , 506-7, respectively) each coupled to a respective pair of complementary sense lines (e.g., digit lines 505-1 and 505-2). FIG. 5 also shows eight compute components (e.g., compute components 0, 1, . . . , 7 shown at 531-0, 531-1, . . . , 531-7) each coupled to a respective sense amplifier (e.g., as shown for sense amplifier 0 at 506-0) via respective pass gates 507-1 and 507-2 and digit lines 505-1 and 505-2. For example, the pass gates can be connected as shown in FIG. 4 and can be controlled by an operation selection signal, Pass. For example, an output of the selection logic can be coupled to the gates of the pass gates 507-1 and 507-2 and digit lines 505-1 and 505-2. Corresponding pairs of the sense amplifiers and compute components can contribute to formation of the sensing circuitry indicated at 550-0, 550-1, . . . , 550-7.
Data values present on the pair of complementary digit lines 505-1 and 505-2 can be loaded into the compute component 531-0 as described in connection with FIG. 4. For example, when the pass gates 507-1 and 507-2 are enabled, data values on the pair of complementary digit lines 505-1 and 505-2 can be passed from the sense amplifiers to the compute component (e.g., 506-0 to 531-0). The data values on the pair of complementary digit lines 505-1 and 505-2 can be the data value stored in the sense amplifier 506-0 when the sense amplifier is fired.
The sense amplifiers 506-0, 506-1, . . . , 506-7 in FIG. 5 can each correspond to sense amplifier 406 shown in FIG. 4. The compute components 531-0, 531-1, . . . , 531-7 shown in FIG. 5 can each correspond to compute component 431 shown in FIG. 4. A combination of one sense amplifier with one compute component can contribute to the sensing circuitry (e.g., 550-0, 550-1, . . . , 550-7) of a portion of a DRAM memory subarray 525 configured to an I/O line 555 shared by a number of sensing component stripes for subarrays and/or latch components, as described herein. The paired combinations of the sense amplifiers 506-0, 506-1, . . . , 506-7 and the compute components 531-0, 531-1, . . . , 531-7, shown in FIG. 5, can be included in the sensing stripes, as shown at 350/370-1 in FIG. 3.
The configurations of embodiments illustrated in FIG. 5 are shown for purposes of clarity and are not limited to these configurations. For instance, the configuration illustrated in FIG. 5 for the sense amplifiers 506-0, 506-1, . . . , 506-7 in combination with the compute components 531-0, 531-1, . . . , 531-7 and the shared I/O line 555 is not limited to half the combination of the sense amplifiers 506-0, 506-1, . . . , 506-7 with the compute components 531-0, 531-1, . . . , 531-7 of the sensing circuitry being formed above the columns 522 of memory cells (not shown) and half being formed below the columns 522 of memory cells. Nor are the number of such combinations of the sense amplifiers with the compute components forming the sensing circuitry configured to couple to a shared I/O line limited to eight. In addition, the configuration of the shared I/O line 555 is not limited to being split into two for separately coupling each of the two sets of complementary digit lines 505-1 and 505-2, nor is the positioning of the shared I/O line 555 limited to being in the middle of the combination of the sense amplifiers and the compute components forming the sensing circuitry (e.g., rather than being at either end of the combination of the sense amplifiers and the compute components).
The circuitry illustrated in FIG. 5 also shows column select circuitry 558-1 and 558-2 that is configured to implement data movement operations with respect to particular columns 522 of a subarray 525, the complementary digit lines 505-1 and 505-2 associated therewith, and the shared I/O line 555 (e.g., as directed by the controller 140 shown in FIG. 1). For example, column select circuitry 558-1 has select lines 0, 2, 4, and 6 that are configured to couple with corresponding columns, such as column 0 (532-0), column 2, column 4, and column 6. Column select circuitry 558-2 has select lines 1, 3, 5, and 7 that are configured to couple with corresponding columns, such as column 1, column 3, column 5, and column 7.
Controller 140 can be coupled to column select circuitry 558 to control select lines (e.g., select line 0) to access data values stored in the sense amplifiers, compute components, and/or present on the pair of complementary digit lines (e.g., 505-1 and 505-2 when selection transistors 559-1 and 559-2 are activated via signals from select line 0). Activating the selection transistors 559-1 and 559-2 (e.g., as directed by the controller 140) enables coupling of sense amplifier 506-0, compute component 531-0, and/or complementary digit lines 505-1 and 505-2 of column 0 (522-0) to move data values on digit line 0 and digit line 0* to shared I/O line 555. For example, the moved data values may be data values from a particular row 519 stored (cached) in sense amplifier 506-0 and/or compute component 531-0. Data values from each of columns 0 through 7 can similarly be selected by controller 140 activating the appropriate selection transistors.
Moreover, enabling (e.g., activating) the selection transistors (e.g., selection transistors 559-1 and 559-2) can enable a particular sense amplifier and/or compute component (e.g., 506-0 and/or 531-0, respectively) to be coupled with a shared I/O line 555 such that data values stored by an amplifier and/or compute component can be moved to (e.g., placed on and/or transferred to) the shared I/O line 555. In some embodiments, one column at a time is selected (e.g., column 522-0) to be coupled to a particular shared I/O line 555 to move (e.g., copy, transfer, and/or transport) the stored data values. In the example configuration of FIG. 5, the shared I/O line 355 is illustrated as a shared, differential I/O line pair (e.g., shared I/O line and shared I/O line*). Hence, selection of column 0 (522-0) could yield two data values (e.g., two bits with values of 0 and/or 1) from a row (e.g., row 519) and/or as stored in the sense amplifier and/or compute component associated with complementary digit lines 505-1 and 505-2. These data values could be input in parallel to each shared, differential I/O pair (e.g., shared I/O and shared I/O*) of the shared differential I/O line 555.
While example embodiments including various combinations and configurations of sensing circuitry, sense amplifiers, compute component, dynamic latches, isolation devices, and/or shift circuitry have been illustrated and described herein, embodiments of the present disclosure are not limited to those combinations explicitly recited herein. Other combinations and configurations of the sensing circuitry, sense amplifiers, compute component, dynamic latches, isolation devices, and/or shift circuitry disclosed herein are expressly included within the scope of this disclosure.
Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will appreciate that an arrangement calculated to achieve the same results can be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of one or more embodiments of the present disclosure. It is to be understood that the above description has been made in an illustrative fashion, and not a restrictive one. Combination of the above embodiments, and other embodiments not specifically described herein will be apparent to those of skill in the art upon reviewing the above description. The scope of the one or more embodiments of the present disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of one or more embodiments of the present disclosure should be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled.
In the foregoing Detailed Description, some features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the disclosed embodiments of the present disclosure have to use more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.

Claims

1-20. (canceled)

21. An apparatus, comprising:

an array of memory cells;

a cache coupled to the array;

sensing circuitry comprising a plurality of sense amplifiers each coupled to the array; and

a shared input/output (I/O) line shared by each of the plurality of sense amplifiers;

a command interface coupled to the cache and configured to provide commands to the cache along with corresponding column addresses and updated data received through the shared I/O line and to be written to the cache; and

tracking circuitry coupled to the cache, wherein the tracking circuitry is configured to track write addresses of data written to the cache from the shared I/O line.

22. The apparatus of claim 21, further comprising a controller coupled to the cache and configured to:

send a command for copying cache data from the cache to the array, the command having an associated column address.

23. The apparatus of claim 22, wherein the controller is further configured to transfer data from the shared I/O line to the sensing circuitry and selectably transfer data from the plurality of sense amplifiers to a portion of the array corresponding to a number of columns of memory cells;

24. The apparatus of claim 21, wherein the tracking circuitry comprises latch circuitry and the column addresses are latched in the latch circuitry.

25. The apparatus of claim 24, wherein the tracking circuitry is further configured to track each of the column addresses associated with the updated data received to the cache via the command interface.

26. The apparatus of claim 21, wherein the tracking circuitry is configured to set a flag associated with a first column address in response to updated data associated with the first column address being written to the cache.

27. The apparatus of claim 26, wherein the tracking circuitry further comprises a latch to store a data value that indicates the flag is set.

28. The apparatus of claim 26, wherein the tracking circuitry is configured to not set a flag associated with a second column address in response to data associated with the second column address not being written to the cache.

29. The apparatus of claim 21, wherein the tracking circuitry is configured to latch a data value that corresponds to a column address associated with at least one of the write commands.

30. A method, comprising:

writing data stored in an array of memory cells to a cache;

updating a portion of the data stored in the cache, wherein the updated data is transferred via a shared input/output (I/O) line coupled to each of a plurality of sense amplifiers coupled to the array and via a compute component coupled to at least one of the plurality of sense amplifiers;

tracking column addresses associated with the updated portion of the data; and

in response to receiving a write command, from a controller, to copy at least the updated portion of data from the cache to the array, comparing the column addresses associated with the write command with the tracked column addresses.

31. The method of claim 30, further comprising, in response to the column addresses matching the tracked column addresses, writing the updated portion of the data associated with each of the matched column addresses to the array.

32. The method of claim 31, further comprising not writing portions of the data associated with column addresses that do not match.

33. The method of claim 30, further comprising, in response to a command being sent via a command interface to update a portion of the data associated with column addresses and stored in the cache with data received across the shared I/O line, modifying the portion of the data associated with the command.

34. An apparatus, comprising:

an array of memory cells;

a controller coupled to a cache and configured to transfer data from the shared I/O line to the sensing circuitry and selectably transfer data from the plurality of sense amplifiers to a portion of the array corresponding to a number of columns of memory cells;

tracking circuitry configured to compare the column address of one of the commands for copying cache data from the cache to the array to tracked addresses associated with the updated data received to the cache via the command interface.

35. The apparatus of claim 34, wherein the controller is a DDR4 SDRAM controller.

36. The apparatus of claim 34, wherein the controller is further configured to, in response to the tracking circuitry matching the column address and one of the tracked addresses, write data associated with the each of the matched column addresses from the cache to the array.

37. The apparatus of claim 36, wherein the controller is further configured to not write data associated with a column address that does not match a tracked address of the tracked addresses.

38. The apparatus of claim 34, wherein the command interface is a DRAM command interface.

39. The apparatus of claim 34, wherein the controller is further configured to cause latching of a value in a latch in response to receiving a write command associated with a column address.

40. The apparatus of claim 39, wherein the controller is further configured to cause:

writing data associated with the latched value to the array; and

clearing of the latched value in response to the writing of the data associated with the tracked column addresses to the array.