US20200035601A1 - Semiconductor device having symmetric conductive interconnection patterns - Google Patents

Semiconductor device having symmetric conductive interconnection patterns Download PDF

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Publication number
US20200035601A1
US20200035601A1 US16/358,661 US201916358661A US2020035601A1 US 20200035601 A1 US20200035601 A1 US 20200035601A1 US 201916358661 A US201916358661 A US 201916358661A US 2020035601 A1 US2020035601 A1 US 2020035601A1
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Prior art keywords
patterns
pattern
conductive interconnection
preliminary
filling
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US16/358,661
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Inventor
Tae-Jung HA
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SK Hynix Inc
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SK Hynix Inc
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Assigned to SK Hynix Inc. reassignment SK Hynix Inc. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HA, TAE-JUNG
Publication of US20200035601A1 publication Critical patent/US20200035601A1/en
Priority to US17/189,839 priority Critical patent/US11456252B2/en
Abandoned legal-status Critical Current

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    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H01L23/53266—Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068—Formation and after-treatment of conductors

Definitions

  • the technology and implementations disclosed in this patent document relate to symmetric conductive interconnection patterns having smaller widths and/or spaces than widths and/or spaces of mask patterns formed in a photolithography process, and a method of forming the same.
  • Exemplary embodiments provide a method of forming conductive interconnection patterns having finer widths and spaces than line widths and intervals of mask patterns formed in a photolithography process.
  • Exemplary embodiments provide a method of forming conductive interconnection patterns having finer widths and spaces than a line width and an interval of a pattern primarily formed by using a single spacer forming technique.
  • a semiconductor device may include a lower interlayer dielectric layer; conductive interconnection pattern structure and filling pattern over the lower interlayer dielectric layer; and an upper interlayer dielectric layer over the conductive interconnection pattern structure and the filling pattern.
  • Each of the conductive interconnection pattern structure may include an intermediate pattern in the center thereof; a first conductive interconnection pattern on a first side surface of the intermediate pattern; and a second conductive interconnection pattern on a second side surface of the intermediate pattern.
  • the first conductive interconnection pattern and the second conductive interconnection pattern may have a symmetrical structure to each other.
  • a method for fabricating a semiconductor device may include forming a stopper layer; forming an intermediate pattern material layer over the stopper layer; forming a plurality of first preliminary intermediate patterns by patterning the intermediate pattern material layer; forming a plurality of second preliminary intermediate patterns by shrinking the first preliminary intermediate patterns; forming a conductive material layer to cover the second preliminary intermediate patterns; forming a plurality of preliminary conductive interconnection patterns by patterning the conductive material layer; forming a filling layer between the preliminary conductive interconnection patterns; and forming a plurality of intermediate patterns, a plurality of conductive interconnection patterns and a plurality of filling patterns by removing top portions of the filling layer, the preliminary conductive interconnection patterns and the second preliminary intermediate patterns.
  • a method for fabricating a semiconductor device may include forming a lower interlayer dielectric layer over a substrate; forming a stopper layer over the lower interlayer dielectric layer; forming first preliminary intermediate patterns over the stopper layer; forming second preliminary intermediate patterns by shrinking the first preliminary intermediate patterns; forming preliminary conductive interconnection patterns to cover top surfaces and both side surfaces of the second preliminary intermediate patterns; forming a filling layer between the preliminary conductive interconnection patterns; forming intermediate patterns with side surfaces, conductive interconnection patterns on side surfaces of the intermediate patterns and filling patterns between the conductive interconnection patterns by removing a top portion of each of the filling layer, the preliminary conductive interconnection patterns and the second preliminary intermediate patterns; forming a capping layer over the intermediate patterns, the conductive interconnection patterns and the filling patterns; and forming an upper interlayer dielectric layer over the capping layer.
  • FIGS. 1 to 9 are cross-sectional views illustrating a method of forming conductive interconnection patterns of a semiconductor memory device in accordance with an embodiment of the disclosure.
  • FIGS. 10 to 15 are cross-sectional views illustrating a method of forming conductive interconnection patterns of a semiconductor memory device in accordance with an embodiment of the disclosure.
  • FIGS. 1 to 9 are cross-sectional views illustrating a method of forming conductive interconnection patterns of a semiconductor device in accordance with an embodiment.
  • a method of forming the conductive interconnection patterns of a semiconductor device may include forming a lower interlayer dielectric layer 20 on a substrate 10 by performing a first deposition process; forming a stopper layer 30 on the lower interlayer dielectric layer 20 by performing a second deposition process; forming an intermediate pattern material layer 40 on the stopper layer 30 by performing a third deposition process; and forming mask patterns M on the intermediate pattern material layer 40 by performing a photolithography process.
  • the substrate 10 may include at least one of a mono-crystalline silicon wafer, an epitaxially grown mono-crystalline silicon layer, or a Silicon-On-Insulator (SOI) layer.
  • the substrate 10 may be a dielectric material covering various electrical circuits.
  • the lower interlayer dielectric layer 20 may include a dielectric material covering various electrical circuits (not illustrated) formed on the substrate 10 .
  • the lower interlayer dielectric layer 20 may include at least one of silicon oxide (SiO 2 ); silicon nitride (SiN); silicon oxynitride (SiON); silicon hydride oxide (SiOH); or silicon carbide oxide (SiCO), or any combination thereof.
  • the first deposition process may include a chemical vapor deposition (CVD) process.
  • the stopper layer 30 may include a dielectric material, denser and harder than both the lower interlayer dielectric layer 20 and the intermediate pattern material layer 40 .
  • the stopper layer 30 may include a material different from, or not included in, the lower interlayer dielectric layer 20 , so that stopper layer 30 has a different etch selectivity from both the lower interlayer dielectric layer 20 and the intermediate pattern material layer 40 .
  • the stopper layer 30 may include at least one of silicon nitride (SiN); silicon oxynitride (SiON); hydrogen (H)-containing material such as silicon hydride oxide (SiOH); carbon (C)-containing material such as silicon carbide oxide (SiCO); silicon carbide nitride (SiCN); or silicon carbide oxynitride (SiCON), or any combination thereof.
  • the second deposition process may include a CVD process to form a silicon nitride layer.
  • the intermediate pattern material layer 40 may include at least one of silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON), hydrogen (H)-containing material such as silicon hydride oxide (SiOH), carbon (C)-containing material such as silicon carbide oxide (SiCO), silicon carbide nitride (SiCN), or silicon carbide oxynitride (SiCON), or any combination thereof.
  • the third deposition process may include a CVD process to form a silicon oxide layer.
  • the mask patterns M may include organic patterns containing an organic polymeric material such as photoresist, and/or other inorganic patterns such as silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or silicon carbide oxynitride (SiCON).
  • organic patterns containing an organic polymeric material such as photoresist
  • other inorganic patterns such as silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or silicon carbide oxynitride (SiCON).
  • Horizontal widths W 1 of the mask patterns M may be substantially equal or similar to horizontal intervals W 2 between the mask patterns M.
  • the horizontal widths W 1 of the mask patterns M and the horizontal intervals W 2 between the mask patterns M may be dimensions that are at or close to the minimum resolution of photolithography processes.
  • the minimum resolution may represent or refer to the minimum widths and/or minimum intervals within patterns that may be formed in any given photolithography apparatus.
  • the method may include patterning the intermediate pattern material layer 40 by performing a first etch process using the mask patterns M as etch masks.
  • the intermediate pattern material layer 40 may be patterned into first preliminary intermediate patterns 41 .
  • Each of the first preliminary intermediate patterns 41 may have a line or bar-like shape extending horizontally.
  • First trench spaces TS 1 may be present between the first preliminary intermediate patterns 41 .
  • the stopper layer 30 may be exposed between the first preliminary intermediate patterns 41 .
  • vertical heights and horizontal widths, illustrated in FIG. 2 of the mask patterns M may be reduced.
  • the method may include removing the mask patterns M by performing an ashing process or a stripping process, for example.
  • the ashing process may include an oxygen (O 2 ) plasma process.
  • the stripping process may include a sulfuric acid boiling process and a wet removing process using hydrofluoric acid or phosphoric acid.
  • the first horizontal widths Wp 1 of the first preliminary intermediate patterns 41 may be substantially equal or similar to or smaller than the horizontal widths W 1 of the mask patterns M.
  • the first horizontal widths Ws 1 of the first trench spaces TS 1 may be substantially equal or similar to or greater than the horizontal intervals W 2 between the mask patterns M.
  • the method may include forming second preliminary intermediate patterns 42 by shrinking the first preliminary intermediate patterns 41 by performing a shrinking process.
  • the shrinking process may include a soft etch process using a diluted etchant or a strong cleaning process using concentrated cleaning fluid.
  • the forming of the second preliminary intermediate patterns 42 may include partially removing the upper and all side portions or parts of the first preliminary intermediate patterns 41 by performing an isotropic etch process or the like.
  • the first preliminary intermediate patterns 41 are reduced in size to the second preliminary intermediate patterns 42 .
  • the first trench spaces TS 1 may be transformed into widened second trench spaces TS 2 as material is removed from side areas or regions of first preliminary intermediate patterns 41 .
  • the shrinking process may include widening the first trench spaces TS 1 to form the second trench spaces TS 2 .
  • Horizontal widths Ws 2 of the second trench spaces TS 2 may be approximately three times greater than horizontal widths Wp 2 of the second preliminary intermediate patterns 42 .
  • the ratio of the dimensions of horizontal widths Wp 2 to horizontal widths Ws 2 may be 3:1.
  • Vertical heights, i.e., thicknesses may shrink in a half proportion of the first preliminary intermediate patterns 41 .
  • the method may further include entirely forming a conductive material layer 60 to cover the exposed surfaces of second preliminary intermediate patterns 42 by performing a deposition process.
  • This may be the fourth deposition process in the method.
  • the conductive material layer 60 may include a conductor such as a metal.
  • the conductive material layer 60 may completely cover the second preliminary intermediate patterns 42 .
  • the conductive material layer 60 may be formed on, for example in a semi-conformal manner, along the profiles of the second preliminary intermediate patterns 42 .
  • the deposition process may include a sputtering process, a Physical Vapor Deposition (PVD) process or a CVD process to form a metal layer.
  • PVD Physical Vapor Deposition
  • the method may further include forming first preliminary conductive interconnection patterns 61 by blanket-etching the conductive material layer 60 in a second etch process.
  • the second etch process may include an anisotropic etch-back process.
  • the second etch process may include a physical sputtering etch process.
  • the first preliminary conductive interconnection patterns 61 may be formed in a mound or sheath-like shapes covering or surrounding the second preliminary intermediate patterns 42 using the etch-back process to form a spacer shape.
  • the first preliminary conductive interconnection patterns 61 may completely cover the top and side surfaces of the second preliminary intermediate patterns 42 .
  • the surface of the stopper layer 30 may be exposed between the first preliminary conductive interconnection patterns 61 .
  • the first preliminary conductive interconnection patterns 61 may be converted into or configured for use as individual patterns that are physically and electrically separated from one another.
  • the method may further include wholly or entirely forming a filling layer 70 covering the first preliminary conductive interconnection patterns 61 by performing a deposition process. This may be a fifth deposition process.
  • the filling layer 70 may fill spaces between the first preliminary conductive interconnection patterns 61 .
  • the filling layer 70 may include at least one of silicon oxide (SiO 2 ); silicon nitride (SiN); or silicon oxynitride (SiON), or any combination thereof.
  • the deposition process may include a CVD process to form a silicon oxide layer.
  • the method may further include forming conductive pattern structures 100 A and filling patterns 71 by partially removing upper portions or regions of the filling layer 70 ; the first preliminary conductive interconnection patterns 61 ; and the second preliminary intermediate patterns 42 by performing a Chemical Mechanical Polishing (CMP) process.
  • Each resulting conductive pattern structure 100 A may include intermediate patterns 43 between or sandwiched by conductive interconnection patterns 62 L and 62 R.
  • the conductive pattern structure 100 A includes an intermediate pattern 43 positioned in the center, left conductive interconnection patterns 62 L positioned on the left side of the intermediate pattern 43 , and right conductive interconnection pattern 62 R positioned on the right side of the intermediate pattern 43 .
  • Two or more conductive pattern structures 100 A may be formed spaced apart on stopper layer 30 .
  • the filling patterns 71 may be formed between the conductive pattern structures 100 A and on stopper layer 30 .
  • the left conductive interconnection patterns 62 L may be formed on left side surfaces of the intermediate patterns 43
  • right conductive interconnection patterns 62 R may be formed on the right side surfaces of the intermediate patterns 43 .
  • Each of the left conductive interconnection patterns 62 L may have a right side surface, closer to in contact with the intermediate pattern 43 , that is substantially vertical and flat, and a left side surface that is non-planar and tapered in a vertical direction, from a wider base (wider lower portion) closer to or in contact with the surface of the stopper layer 30 to a narrower upper portion.
  • a cross-section of the left side surface of the conductive interconnection pattern 62 L may be rounded and inclined, for example by following a circular or elliptical arc, so that the upper portion is narrower, and the lower portion is wider.
  • Each of the right conductive interconnection patterns 62 R may have a left side surface, closer to or in contact with the intermediate pattern 43 , that is substantially vertical and flat, and a right side surface that is non-planar and tapered in a vertical direction, from a wider base (wider lower portion) closer to or in contact with the surface of the stopper layer 30 to a narrower upper portion.
  • a cross-section of the right side surface of the conductive interconnection pattern 62 R may be rounded and inclined so that the upper portion is narrower, and the lower portion is wider, for example along a circular or elliptical arc.
  • the left conductive interconnection patterns 62 L and the right conductive interconnection patterns 62 R may form a bilaterally symmetrical structure with an intermediate pattern 43 at the center of the structure.
  • the left conductive interconnection patterns 62 L and the right conductive interconnection patterns 62 R may be alternately disposed on either side of, to face or opposite to each other, an intermediate pattern 43 .
  • the left conductive interconnection patterns 62 L and the right conductive interconnection patterns 62 R may have substantially flat or planar bottom, or lower, surfaces and top, or upper, surfaces.
  • the horizontal widths of the top surfaces of the left conductive interconnection patterns 62 L and the right conductive interconnection patterns 62 R may be smaller than Wa, the horizontal widths of the bottom surfaces, closer to or in contact with the stopper layer 30 , of the left conductive interconnection patterns 62 L and the right conductive interconnection patterns 62 R.
  • the filling pattern 71 may be disposed between the conductive pattern structures 100 A.
  • the filling pattern 71 can be formed on the stopper layer 30 in spaces or gaps between the left conductive patterns 62 L of one conductive pattern structure 100 A and the right conductive pattern 62 R of an adjacent conductive pattern structure 100 A.
  • the filling pattern 71 may also be disposed between the right conductive pattern 62 R of one conductive pattern structure 100 A and the left conductive pattern 62 L of another adjacent conductive pattern structure 100 A.
  • Each of the intermediate patterns 43 may have both side surfaces that are substantially vertical and flat closer to or in contact with the left conductive interconnection patterns 62 L and the right conductive interconnection patterns 62 R.
  • Each of the filling patterns 71 may have side surfaces that are non-planar and tapered in a vertical direction, from a narrower base (narrower lower portion) closer to or in contact with the stopper layer 30 to a wider upper surface.
  • both side surfaces of the filling pattern 71 may be negatively rounded so that the upper portion is wider and the lower portion is narrower.
  • the rounded sides may have a cross-section shape that follows a circular or an elliptical arc.
  • the CMP process may include a first CMP process, a second CMP process, and a third CMP process.
  • the first CMP process may mainly remove the filling layer 70 .
  • the second CMP process may remove the filling layer 70 and the preliminary conductive interconnection patterns 61 .
  • the third CMP process may remove the filling layer 70 , the preliminary conductive interconnection patterns 61 , and the second preliminary intermediate patterns 42 .
  • the intermediate patterns 43 , the conductive interconnection patterns 62 L and 62 R, and the filling patterns 71 may be substantially coplanar with one another.
  • the intermediate patterns 43 may be used as a CMP stopper layer.
  • the left conductive interconnection patterns 62 L and the right conductive interconnection patterns 62 R may have horizontal widths Wa and/or horizontal intervals Wb closer to or in contact with the stopper layer 30 that are smaller than the minimum horizontal widths W 1 and/or the minimum horizontal intervals W 2 of the limit (marginal) resolution of the photolithography process.
  • a horizontal interval Wb between a left conductive interconnection pattern 62 L and a right conductive interconnection pattern 62 R may be equal or similar to the horizontal width of an intermediate pattern 43 and/or a filling pattern 71 , each of which are less than W 1 and/or W 2 .
  • the sum of the horizontal width Wa of the left or right conductive interconnection pattern 62 L or 62 R and the horizontal interval Wb between the left conductive interconnection pattern 62 L and the right conductive interconnection pattern 62 R may be equal or substantially equal to the minimum horizontal width W 1 and/or the minimum horizontal interval W 2 of the limit resolution.
  • the method may include forming a capping layer 80 on the conductive pattern structures 100 A and the filling patterns 71 by performing a deposition process. This may be the sixth deposition process.
  • the method may further include forming an upper interlayer dielectric layer 90 on the capping layer 80 by performing another deposition process, which can be a seventh deposition process.
  • the capping layer 80 may include a material denser and harder than the material used to form intermediate patterns 43 and the filling patterns 71 .
  • the capping layer 80 may include at least one of silicon nitride (SiN), silicon oxynitride (SiON) or a combination thereof.
  • the sixth deposition process may include a CVD process for depositing silicon nitride (SiN).
  • the upper interlayer dielectric layer 90 may include at least one of silicon oxide (SiO 2 ); silicon nitride (SiN); silicon oxynitride (SiON); silicon hydride oxide (SiOH); or silicon carbide oxide (SiCO), or any combination thereof.
  • the seventh deposition process may include a CVD process to form silicon oxide (SiO 2 ).
  • patterns having finer resolution than the limit (marginal) resolution may be formed using a mask patterns only in a photolithography process.
  • FIGS. 10 to 15 are cross-sectional views illustrating a method of forming conductive interconnection patterns of a semiconductor device in accordance with an embodiment.
  • a method of forming the conductive interconnection patterns of a semiconductor device may include sequentially forming a lower interlayer dielectric layer 20 , a stopper layer 30 , an intermediate pattern material layer 40 and mask patterns M over a substrate 10 , forming first preliminary intermediate patterns 41 by patterning the intermediate pattern material layer 40 , removing the mask patterns M, and forming second preliminary intermediate patterns 42 by shrinking the first preliminary intermediate patterns 41 , by performing the series of processes described above and with reference to FIGS. 1 to 4 , and forming a barrier material layer 50 to cover or surround exposed areas of the second preliminary intermediate patterns 42 and the exposed portions of stopper layer 30 .
  • the barrier material layer 50 may be conformally formed on the top and side surfaces of the second preliminary intermediate patterns 42 and the exposed surfaces of the stopper layer 30 .
  • the barrier material layer 50 may include at least one of conductive barrier materials such as titanium nitride (TiN); tantalum nitride (TaN); or tungsten nitride (WN), or dielectric barrier materials such as silicon nitride (SiN) or silicon oxynitride (SiON).
  • the barrier material layer 50 may be formed by performing a PVD process or a CVD process.
  • the method may further include forming a conductive material layer 60 wholly or entirely covering the exposed surface of barrier material layer 50 by performing the process described above and with reference to FIG. 5 .
  • the barrier material layer 50 may enhance the adhesion between the second preliminary intermediate patterns 42 and the conductive material layer 60 .
  • the method may further include forming preliminary conductive interconnection patterns 61 by blanket-etching the conductive material layer 60 by performing the process described above and with reference to FIG. 6 , and forming preliminary barrier patterns 51 by sequentially etching the barrier material layer 50 to create gaps or spaces in the conductive material layer 60 and the barrier material layer 50 closer to or in contact with the stopper layer 30 . As a result, portions of the upper surface of the stopper layer 30 may be exposed between the preliminary conductive interconnection patterns 61 and the preliminary barrier patterns 51 .
  • the method may further include forming a filling layer 70 across the resultant structure by performing the process described above and with reference to FIG. 7 .
  • the method may further include forming a conductive pattern structure 100 B and filling patterns 71 by partially removing upper regions of the filling layer 70 , the preliminary conductive interconnection patterns 61 , the preliminary barrier patterns 51 , and the second preliminary intermediate patterns 42 by performing CMP processes.
  • the conductive pattern structure 100 B may include an intermediate pattern 43 , a left barrier pattern 52 L, a right barrier pattern 52 R, a left conductive interconnection pattern 62 L, and a right conductive interconnection pattern 62 R.
  • the filling patterns 71 may be disposed between the conductive pattern structures 100 B.
  • Each of the intermediate patterns 43 may have both side surfaces that are substantially vertical and flat closer to or in contact with the left conductive interconnection patterns 62 L and the right conductive interconnection patterns 62 R.
  • Each of the filling patterns 71 may have both side surfaces that are non-planar and tapered in a vertical direction, from a narrower base closer to or in contact with the stopper layer 30 to a wider upper surface.
  • both side surfaces of the filling pattern 71 may be rounded negatively so that the upper portion is wider, and the lower portion is narrower.
  • the rounded sides may have a cross-section shape that that follows a circular or an elliptical arc.
  • Each of the left barrier patterns 52 L may include a vertical portion between the left side surface of an intermediate pattern 43 and the right side surface of a left conductive interconnection pattern 62 L, and a horizontal portion between the bottom, or lower, surface of the left conductive interconnection pattern 62 L and the top surface of the stopper layer 30 .
  • Each of the right barrier patterns 52 R may include a vertical portion between the right side surface of an intermediate pattern 43 and the left side surface of a right conductive interconnection pattern 62 R, and a horizontal portion between the bottom surface of the right conductive interconnection pattern 62 R and the top surface of the stopper layer 30 .
  • each of the left barrier patterns 52 L may have an inverted-L shaped cross-section
  • each of the right barrier patterns 52 R may have an L-shaped cross-section. Accordingly, the left barrier patterns 52 L and the right barrier patterns 52 R may form a bilaterally symmetrical structure centered on an intermediate pattern 43 .
  • Each of the left conductive interconnection patterns 62 L may have a right side surface, closer to or in contact with a left barrier pattern 52 L, that is substantially vertical and flat and a left side surface that is non-planar and tapered in a vertical direction, from a wider base closer to or in contact with the stopper layer 30 to a narrower upper portion.
  • a cross-section of the left side surface of a conductive interconnection pattern 62 L may be rounded and inclined, for example by following a circular or elliptical arc, so that the upper portion is narrower and the lower portion is wider.
  • Each of the right conductive interconnection patterns 62 R may have a left side surface, close to or in contact with a right barrier pattern 52 R, that is substantially vertical and flat and a right side surface that is non-planar and tapered in a vertical direction, from a wider base closer to or in contact with the stopper layer 30 to a narrower upper portion.
  • a cross-section of the right side surface of a conductive interconnection pattern 62 R may be rounded and inclined so that the upper portion is narrower and the lower portion is wider, for example along a circular or elliptical arc.
  • the left conductive interconnection patterns 62 L and the right conductive interconnection patterns 62 R may form a bilaterally symmetrical structure with an intermediate pattern 43 at the center of the structure.
  • Each of the filling patterns 71 may have tapered side surfaces with negative slopes.
  • both side surfaces of the filling pattern 71 may be rounded negatively so that the upper portion is wider and the lower portion is narrower.
  • the rounded sides may have a cross-section shape that that follows a circular or an elliptical arc.
  • the intermediate patterns 43 , the left and right barrier patterns 52 L and 52 R, the left and right conductive interconnection patterns 62 L and 62 R and the filling patterns 71 may be substantially coplanar with one another as a result of a CMP process.
  • the intermediate patterns 43 may be used as a CMP stopper layer.
  • the method may further include forming a capping layer 80 on the conductive pattern structures 100 B and forming a top interlayer dielectric layer 90 on the capping layer 80 , by performing the series of processes described above and with reference to FIG. 9 .
  • the conductive interconnection patterns having smaller widths and intervals than the widths and intervals of the mask patterns in a photolithography process.
  • the conductive interconnection patterns having smaller widths and intervals than the widths and intervals of the mask patterns formed in the photolithography process by performing one photolithography process and one etch-back process to form a mound or sheath-like shapes.

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CN110783257A (zh) 2020-02-11
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US20210183769A1 (en) 2021-06-17

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