US20200021305A1 - Common mode rejection in reservoir capacitor analog-to-digital converter - Google Patents
Common mode rejection in reservoir capacitor analog-to-digital converter Download PDFInfo
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- H—ELECTRICITY
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0602—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic
- H03M1/0604—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic at one point, i.e. by adjusting a single reference value, e.g. bias or gain error
- H03M1/0607—Offset or drift compensation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0602—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic
- H03M1/0612—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic over the full range of the converter, e.g. for correcting differential non-linearity
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/462—Details of the control circuitry, e.g. of the successive approximation register
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/68—Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
- G11C27/02—Sample-and-hold arrangements
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
- G11C27/02—Sample-and-hold arrangements
- G11C27/024—Sample-and-hold arrangements using a capacitive memory element
- G11C27/026—Sample-and-hold arrangements using a capacitive memory element associated with an amplifier
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
- H03M1/468—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors in which the input S/H circuit is merged with the feedback DAC array
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
- H03M1/80—Simultaneous conversion using weighted impedances
- H03M1/802—Simultaneous conversion using weighted impedances using capacitors, e.g. neuron-mos transistors, charge coupled devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
- H03M1/80—Simultaneous conversion using weighted impedances
- H03M1/802—Simultaneous conversion using weighted impedances using capacitors, e.g. neuron-mos transistors, charge coupled devices
- H03M1/804—Simultaneous conversion using weighted impedances using capacitors, e.g. neuron-mos transistors, charge coupled devices with charge redistribution
Definitions
- This document pertains generally, but not by way of limitation, to integrated circuits, and more particularly, to analog-to-digital converter circuits and systems.
- Successive approximation routine (SAR) analog-to-digital converters convert an analog input to a digital value.
- the analog input is held while the SAR ADC circuit converges to a solution after a number of bit trials.
- Some SAR ADC circuits convert a differential analog input to a digital value.
- a differential SAR ADC may require that the common mode of the input signal to be at a fixed value; e.g., Vref/2. This can be accomplished by additional circuitry to translate the input common mode to the common mode required by the SAR ADC, However; this additional circuitry can result in additional space needed for an SAR ADC circuit, additional power consumption, and can introduce additional sources of noise in the signal chain.
- a differential digital-to-analog (DAC) circuit can include a reservoir capacitor and various switches to couple the bottom plates of the input capacitors; e.g., bit-trial capacitors, to reference voltages, e.g., REF+ or REF ⁇ .
- the reservoir capacitor can be used to provide any differential charge to the input capacitors, e.g., bit-trial capacitors, and the reference voltages, e.g., REF+ and REF ⁇ , can be used to provide any common mode charge to the input capacitors.
- this disclosure is directed to a differential digital-to-analog (DAC) circuit comprising a capacitor array including a number of DAC units, each DAC unit including: a pair of input capacitors configured to couple to a comparator; a dedicated reference capacitor associated with the pair of input capacitors; and a control circuit configured to: control operation of a first set of switches to transfer a differential residue charge from the reservoir capacitor to the pair of input capacitors when setting the pair of input capacitors in a differential configuration based on a decision of the comparator; and control operation of a second set of switches to transfer a common-mode residue charge from a reference voltage to set the pair of input capacitors when setting the pair of input capacitors in a common-mode configuration based on a decision of the comparator.
- DAC digital-to-analog
- this disclosure is directed to a method of operating a differential analog-to-digital converter (ADC) circuit to convert an analog input to a digital output.
- the method comprises coupling the analog input onto a capacitor array of a first ADC circuit, the capacitor array including a number of DAC units, each DAC unit including: a pair of input capacitors; and a dedicated reference capacitor associated with the pair of input capacitors.
- the method further comprises transferring a differential residue charge from the reservoir capacitor to the pair of input capacitors when setting the pair of input capacitors in a differential configuration based on a decision of a comparator; and transferring a common-mode residue charge from a reference voltage to set the pair of bit-trial capacitors when setting the pair of bit-trial capacitors in a common-mode configuration based on a decision of the comparator.
- this disclosure is directed to a differential digital-to-analog (DAC) circuit
- DAC digital-to-analog circuit
- the capacitor array including a number of DAC units, each DAC unit including: a pair of input capacitors; and a dedicated reference capacitor associated with the pair of input capacitors; and means for transferring a differential residue charge from the reservoir capacitor to the pair of input capacitors when setting the pair of input capacitors in a differential configuration based on a decision of a comparator; and means for transferring a common-mode residue charge from a reference voltage to set the pair of bit-trial capacitors when setting the pair of bit-trial capacitors in a common-mode configuration based on a decision of the comparator.
- DAC digital-to-analog
- FIG. 1 is a functional block diagram of an example of a differential SAR ADC.
- FIG. 2 is a functional block diagram of portions of an example of a reservoir-capacitor SAR ADC.
- FIG. 3 is circuit diagram showing an example of a portion of a SAR ADC circuit including the circuit block of FIG. 2 , in accordance with this disclosure.
- FIG. 4 is an example of a comparator circuit that can implement various techniques of this disclosure.
- FIG. 5 is circuit diagram showing an example of a circuit that can include the main ADC circuit of FIG. 3 in combination with an auxiliary ADC circuit.
- FIG. 6 is a schematic diagram of the circuit block of FIG. 5 in a sampling phase.
- FIG. 7 is a schematic diagram of the circuit block of FIG. 5 in a positive differential residue charge phase.
- FIG. 8 is a schematic diagram of the circuit block of FIG. 5 in a negative differential residue charge phase.
- FIG. 9 is a schematic diagram of the circuit block of FIG. 5 in a positive common mode residue charge phase.
- FIG. 10 is a schematic diagram of the circuit block of FIG. 5 in a negative common mode residue charge phase.
- Successive approximation routine (SAR) analog-to-digital converters convert an analog input to a digital value.
- the analog input is held while the SAR ADC circuit converges to a solution after a number of bit trials.
- SAR. ADC circuits convert a differential analog input to a digital value.
- a differential SAR ADC may require that the common mode of the input signal to be at a fixed value, e.g., Vref/2.
- the common mode voltage of the differential digital-to-analog (DAC) top plates can vary during the hit trials and the comparator in the ADC will have to manage this varying common mode voltage.
- the final common mode voltage during a conversion differs from conversion to conversion, nonlinear errors can be introduced. Therefore, it is desirable for a SAR ADC structure that accommodates variation of the input common mode voltage.
- a differential digital-to-analog (DAC) circuit can include a reservoir capacitor and various switches to couple the bottom plates of the input capacitors, e.g., bit-trial capacitors, to reference voltages, e.g., REF+ or REF ⁇ .
- the reservoir capacitor can be used to provide any differential charge to the input capacitors, e.g., bit-trial capacitors, and the reference voltages, e.g., REF+ and REF ⁇ , can be used to provide any common mode charge to the input capacitors.
- FIG. 1 is a functional block diagram of an example of a differential SAR ADC.
- the SAR ADC 100 includes a positive digital-to-analog converter (DAC) circuit 105 , a negative DAC circuit 110 , and a comparator circuit 115 .
- Each DAC circuit (or “DAC” in this disclosure) can include weighted bit-trial capacitors 120 .
- the capacitors are weighted as C/2, C/4 . . . C/(2 N ), where N is the number of bits in the DACs and C is the total capacitance of the bit-trial capacitors added together.
- a differential analog input voltage (IN+, IN ⁇ ) can be sampled onto the bit-trial capacitors with respect to the common mode of the comparator (CompCM) by closing switches 125 and 130 .
- the input voltage can be held on the capacitors by opening switches 130 , then opening switches 125 .
- the top plates of the capacitors can be at the CompCM voltage.
- the positive DAC 105 and the negative DAC 110 can also be connected to positive and negative reference voltage (REF+, REF ⁇ ).
- REF+, REF ⁇ positive and negative reference voltage
- bit trials for each of the bit-trial capacitors can be performed iteratively.
- the output of the positive DAC 105 and the output of the negative DAC 110 can be applied to the inputs of the comparator circuit 115 .
- a bit capacitor can be connected to either REF+ or REF ⁇ using switches 135 .
- bit capacitor is connected to REF+ the bit of the digital value corresponding to the bit-trial capacitors is assigned a logic value ‘1’, and if the bit capacitor is connected to REF+ the bit of the digital value corresponding to the bit-trial capacitors is assigned a logic value ‘0’. Conversion can then proceed to the next bit capacitor until all bits of the digital value are determined.
- FIG. 2 is a functional block diagram of portions of an example of a reservoir-capacitor based SAR ADC 200 .
- the reservoir-capacitor based SAR ADC 200 includes two DAC circuits, a positive DAC circuit 205 and a negative circuit DAC circuit 210 , and a comparator circuit 215 .
- Each DAC circuit 205 , 210 can form a capacitor array and can include weighted bit-trial capacitors 220 shown attached to circuit blocks 222 to simplify the figure.
- Some examples of the DACs include 8, 12, or 16-bit DACs.
- Each circuit block 222 can be a unit element or “DAC unit” of a respective DAC capacitor array.
- the reservoir-capacitor SAR ADC 200 can include logic circuitry 250 (also referred to as a “control circuit”).
- the logic circuitry 250 can be included in an SAR ADC controller.
- the logic circuitry 250 can include a sequencer to advance the SAR ADC 200 through multiple circuit states to perform the SAR.
- FIG. 3 is circuit diagram showing an example of a portion of a SAR ADC circuit 300 including the circuit block 222 of FIG. 2 , in accordance with this disclosure.
- the circuit block 222 can be a unit element or “DAC unit” of a capacitor array of a DAC circuit such that a DAC circuit, e.g., DAC circuit 205 of FIG. 2 , can include a number of circuit blocks 222 . For purposes of clarity, only one DAC unit is depicted in FIG. 3 .
- Each circuit block 222 can be coupled to the differential analog input voltage (IN+, IN ⁇ ), differential reference voltage (REF+, REF ⁇ ), and comparator circuit 215 .
- the circuit block 222 can include a reservoir capacitor 301 .
- the reservoir capacitor 301 can be a dedicated reference capacitor associated with the pair of input capacitors 220 A, 220 B of a DAC unit element 222 .
- the value of capacitance of a reservoir capacitor can be larger than the capacitance value of its corresponding bit capacitor.
- the value of capacitance of a reservoir capacitor can be five to twenty times the capacitance of the bit-trial capacitors.
- the differential analog input voltage (IN+, IN ⁇ ) can sampled and stored onto input capacitors 220 A, 220 B, e.g., bit-trial capacitors, with respect to the comparator common mode (CompCM) using switches 302 A, 302 B (collectively “switches 302 ”) and 304 A, 304 B (collectively “switches 304 ”).
- the reference voltage can be sampled on the reservoir capacitor 301 when the input voltage is sampled on the bit-trial capacitors 220 using switches 306 A, 306 B (collectively “switches 306 ”).
- Switches 308 A- 308 D (collectively “switches 308 ”) can isolate the reservoir capacitor 301 from the input capacitors 220 A, 220 B, e.g., bit-trial capacitors, during the sampling.
- Logic circuitry e.g., logic circuitry 250 of FIG. 2
- the voltage of the reservoir capacitor 301 can be added or subtracted from the voltage of the input capacitors 220 A, 220 B, e.g., bit-trial capacitors.
- the bit of the digital value corresponding to the trial can be set to a logical ‘1’ or ‘0’ depending on the comparator result and therefore whether the voltage of the reservoir capacitor 301 is added or subtracted from the bit-trial capacitors using switches 308 .
- Logic circuitry can progress the conversion of the differential analog input signal through all of the bit-trial capacitors until all bits of the digital value are determined.
- the logic circuitry can include a SAR controller (e.g., a processor) that progresses the SAR ADC through a conversion according to outcomes determined at the comparator circuit 215 .
- the logic circuitry can include a logic sequencer that progresses the conversion through a series of logic states that correspond to steps of the bit trials. Using reservoir capacitors can speed up the bit trials from the embodiment of FIG. 1 because resampling does not need to take place during every bit trial.
- the differential SAR ADCs of FIG. 1 and FIG. 2 can require that the common mode of the input signal be at Vref/2, for example. If the common mode of input signal is maintained at a fixed value, e.g., Vref/2, the common mode of the DAC top plates during the bit trials can be a fixed value V CM, COMP .
- the bits of the negative DAC are complementary to the bits of the positive DAC, e.g., if a bit of the positive DAC is a “1”, a bit of the negative DAC can be a “0”.
- the common mode of the DAC top plates can vary during the bit trials and the comparator in the ADC will have to manage this varying common mode voltage. Moreover, if the final common mode voltage during a conversion differs from conversion to conversion, nonlinear errors can be introduced. As explained above, additional circuit components may be needed to provide an input to the ADC with a fixed common mode voltage. Therefore, it is desirable for a SAR ADC structure that accommodates variation of the input common mode voltage.
- switches 312 A, 312 B can couple the bottom plates of the input capacitors, e.g., bit-trial capacitors 220 A, 220 B, to REF+ and switches 314 A, 314 B (collectively “switches 314 ”) can couple the bottom plates of the input capacitors, e.g., bit-trial capacitors 220 A, 220 B, to REF ⁇ .
- the reservoir capacitor 301 can be used to provide any differential charge to the capacitors 220 A, 220 B, and the reference voltages REF+ and REF ⁇ can be used to provide any common mode charge to the bit-trial capacitors 220 A, 220 B.
- top plate and “bottom plate” are used for convenience to describe the capacitors and are not meant to imply that there is any, required spatial orientation for the capacitors.
- switches referred to in this disclosure can include transistors and, in particular, complementary metal-oxide-semiconductor (CMOS) transistors due to their high performance and yield.
- CMOS complementary metal-oxide-semiconductor
- N-bit SAR ADC circuit without an auxiliary ADC circuit, e.g., flash ADC or SAR ADC circuit, there can be ‘N’ circuit blocks 222 of FIG. 3 , e.g., unit elements or “units” of a capacitor array of a DAC circuit, connected in parallel and coupled to the comparator 215 .
- all of the bit-trial capacitors 220 can be associated with a respective circuit block 222 similar to the example shown in FIG. 3 .
- only some of the bit-trial capacitors 220 e.g., at least some of the most significant bits (MSBs), can be associated with a respective circuit block 222 similar to the example shown in FIG. 3 .
- the least significant bit (LSB) bit-trial capacitors do not need to couple to reference voltages REF+ or REF ⁇ because they only resolve the differential signal information and, as such, switches 312 and 314 are not needed for the circuit blocks 222 associated with the LSBs.
- the circuit 300 associated with the LSBs can exclude switches 312 and 314 .
- FIG. 4 is an example of a comparator circuit that can implement various techniques of this disclosure.
- the comparator circuit 215 of FIG. 4 is an example of the comparator circuit 215 of FIG. 3 .
- the comparator circuit 215 can include a non-inverting input (+) and an inverting input ( ⁇ ) coupled to the top plate nodes “TOP-P” and “TOP-N” that are coupled to the top plates of the bit-trial capacitors, e.g., top plates 212 A and 212 B of FIG. 2 .
- the comparator 215 can include an additional input 420 that can be the intended DAC common mode output reference voltage for the comparator's differential inputs.
- the input 420 can be connected to a bias voltage (which could be any suitable voltage, including ground), although it could also be connected to other sources, for example a variable voltage that asymptotes to the bias voltage.
- the comparator circuit 415 can include an additional output OUT 2 , such that the outputs OUT 1 and OUT 2 are responsive to both the differential and common mode components of its inputs.
- the logic circuitry e.g., the logic circuitry 250 of FIG. 2 , can accommodate the additional comparator outputs and produce independent bus outputs to control the positive DAC and negative DAC circuits.
- the comparator circuit 215 of FIG. 4 is shown and described in commonly assigned U.S. Pat. No. 7,432,844 to Mueck et al., titled “Differential Input Successive Approximation Analog to Digital Converter with Common Mode Rejection,” the entire contents of which being incorporated herein by reference, including FIGS. 7A-7E and the associated description of those figures.
- the circuit 300 of FIG. 3 can form part of a main SAR ADC circuit.
- a main SAR ADC and an auxiliary ADC e.g., a flash or SAR.
- ADC can be used in conjunction with the techniques described above with respect to FIG. 3 .
- the auxiliary ADC can have a resolution less than the main ADC circuit.
- FIG. 5 is circuit diagram showing an example of a circuit 500 that can include the main ADC circuit of FIG. 3 in combination with an auxiliary ADC circuit.
- the circuit block 222 can be a unit element or “DAC unit” of a capacitor array of a DAC circuit such that a DAC circuit, e.g., DAC circuit 205 of FIG. 2 , can include a number of circuit blocks 222 .
- DAC circuit e.g., DAC circuit 205 of FIG. 2
- FIG. 3 only one DAC unit is depicted in FIG. 3 .
- the circuit 500 can include a first auxiliary ADC circuit 502 A to convert a voltage referenced from the input of the positive DAC circuit to the comparator common mode, and a second auxiliary ADC circuit 502 B to convert a voltage referenced from the input of the negative DAC circuit to the comparator common mode.
- the auxiliary ADC circuits 502 A, 502 B can provide low resolution using a smaller sampling capacitor and a low power, relatively noisy comparator, and a main ADC, e.g., main ADC circuit 200 of FIG. 2 , can provide for high resolution.
- An auxiliary ADC circuit can help convert higher input voltage ranges using a low voltage supply and can allow the main ADC to power down its comparator during the acquisition phase.
- An auxiliary ADC can convert the input voltage to, for example, 2-bit accuracy using a binary search algorithm.
- An auxiliary ADC can perform this conversion before the main ADC takes any action. Then, the auxiliary ADC circuit can transfer the results of the low-resolution conversion to the main ADC circuit, including to bit-trial capacitors 220 , which can then resolve the remaining bits.
- auxiliary ADC circuits can be used in the comparison of the output of the positive DAC, the output of the negative DAC, and the common mode voltage of the comparator circuit.
- the auxiliary ADC circuit is a flash ADC circuit (also referred to as “a direct-conversion ADC”).
- the result of the flash ADC circuit can be available after one conversion cycle.
- the flash ADC circuit 502 A can convert a voltage referenced from the input of the positive DAC circuit to the comparator common mode and flash ADC circuit 502 B can convert a voltage referenced from the input of the negative DAC circuit to the comparator common mode.
- the logic circuit 250 can control couple the analog input signal onto the flash ADC circuits 502 A, 502 B, perform at least one bit-trial using the flash ADC circuits 502 A, 502 B, and load an output of the flash ADC circuits 502 A, 502 B onto at least one of the bit-trial capacitors of the first ADC circuit.
- the states can be determined by the comparators of auxiliary ADC circuits, e.g., flash ADC circuits 502 A, 502 B of FIG. 5 .
- the states can be determined by a comparator such as comparator 215 in FIG. 4 .
- both the input at the positive side and the input at the negative side are greater than the comparator common mode.
- the input voltage has a common mode different from the comparator common mode and the bit-trial capacitors 220 A and 220 B can resolve positive common mode voltage.
- both the input at the positive side and the input at the negative side are less than the comparator common mode.
- capacitors 220 A and 220 B can resolve a negative common mode voltage.
- the logic circuitry 250 can apply a correction voltage to one or more of the bit-trial capacitors 220 A, 220 B.
- the logic circuitry 250 can couple the reference voltages REF+ and REF ⁇ to the bit-trial capacitors 220 A, 220 B to provide any common mode residue charge. This can cause the common mode voltage of top plates to converge to a desired value.
- the reservoir capacitor 301 can be used to provide any differential residue charge to the bit-trial capacitors 220 A, 220 B, as described below with respect to FIGS. 7 and 8
- the reference voltages REF+ and REF ⁇ can be used to provide any common mode residue charge to the bit-trial capacitors 220 A, 220 B, as described below with FIGS. 9 and 10 .
- the techniques of this disclosure are applicable to circuits without auxiliary ADC circuits, such as shown in FIG. 3 .
- the comparator 215 e.g., as shown in FIG. 4
- the techniques will be described with respect to the circuit of FIG. 5 , which can include auxiliary ADC circuits in combination with a main ADC circuit.
- the circuit block 222 of FIGS. 3 and 5 can be a unit element or “DAC unit” of a capacitor array of a DAC circuit such that a DAC circuit, e.g., DAC circuit 205 and/or DAC circuit 210 of FIG. 2 , can include a number of circuit blocks 222 .
- the DAC units can include most significant bit (MSB) DAC units and least significant bit (LSB) DAC units.
- all of the DAC units can be similar such that the MSB and LSB units include the set of switches 312 A, 312 B, 314 A, 314 E to transfer a common-mode residue charge from a reference voltage to set the pair of input capacitors when setting the pair of input capacitors in a common-mode configuration based on a decision of the comparator.
- only some of the DAC units include the set of switches 312 A, 312 B, 314 A, 314 B.
- the LSB DAC units in some configurations do not include the switches 312 A, 312 B, 314 A, 314 B.
- either some or all of the MSB DAC units the switches 312 A, 312 B, 314 A, 314 B.
- FIG. 6 is a schematic diagram of the circuit block 222 of FIG. 5 in a sampling phase.
- the top plate switches 304 A, 304 B can be closed to couple the top plates of bit-trial capacitors 220 A, 220 B to the bias voltage, e.g., shown as common mode voltage CompCM.
- switches 302 A, 302 B can be closed to couple the bottom plates of bit-trial capacitors 220 A, 220 B to analog input signal IN+, IN ⁇ , respectively.
- the reservoir capacitor 301 can be charged by coupling to the main reference voltage sources REF+ and REF ⁇ using switches 306 A, 306 B.
- the bit-trial capacitors of the DAC circuits can store the input signal as sampled charge and deliver a differential input voltage to the inputs of the comparator 215 .
- the comparator differential input voltage can represent the imperfection between the original input signal and an estimate of the input signal developed by the DAC circuits.
- the comparator differential input voltage can include an input common mode offset, and the comparator circuit 215 can include a comparator common mode offset.
- the logic circuitry 250 of FIG. 2 can be coupled to positive and negative DAC circuits, the switches, and the comparator circuit, such as shown in FIG. 1 .
- the logic circuitry 250 can initiate successive bit trials using the weighted bit-trial capacitors to convert the input voltage to a digital value by comparing the outputs of the positive DAC circuit and the negative DAC circuit using the comparator circuit and updating the DAC values.
- the comparator differential input voltage can be reduced towards zero by transferring charge from the reference reservoir capacitor 301 to the bit-trial capacitors 220 A, 220 B. This can converge the estimate of the input signal on the DAC circuits to the original input signal.
- FIG. 7 is a schematic diagram of the circuit block 222 of FIG. 5 in a positive differential residue charge phase.
- the logic circuitry 250 of FIG. 2 determined that to converge the estimate of the input signal on the DAC circuits to the original input signal, a positive differential residue charge can be applied, e.g., based on flash ADC results such as Case No. 1 in Table 1.
- the logic circuit 250 can close switches 308 A, 308 D to transfer charge from the reference reservoir capacitor 301 to set the input capacitors 220 A, 220 B, e.g., bit-trial capacitors, in a “10” state.
- the control circuit can control operation of a first set of switches to transfer a differential residue charge from the reservoir capacitor 301 to the pair of input capacitors 220 A, 220 B when setting the pair of input capacitors in a differential configuration based on a decision of the comparator.
- Setting the pair of input capacitors in a differential configuration based on a decision of the comparator can include setting the first plates of the input capacitors to a state “10”, which is a first of two states in a first set of states: 01 and 10.
- the control circuit 250 can control operation of a first set of switches 308 A, 308 D to directly couple plates of the reference capacitor 301 to a first plate of the bit-trial capacitor 220 A and a first plate of bit-trial capacitor 220 B, where a second plate of the bit-trial capacitor 220 A and a second plate the bit-trial capacitor 220 Bs are configured to couple to inputs of the comparator 215 .
- FIG. 8 is a schematic diagram of the circuit block 222 of FIG. 5 in a negative differential residue charge phase.
- the logic circuitry 250 of FIG. 2 determined that to converge the estimate of the input signal on the DAC circuits to the original input signal, a negative differential residue charge can be applied, e.g., based on flash ADC results such as Case No. 2 in Table 1.
- the logic circuit 250 can close switches 308 B, 308 C to transfer charge by cross-coupling from the reference reservoir capacitor 301 to the input capacitors 220 A, 220 B, e.g., bit-trial capacitors, to set to a “01” state.
- the control circuit can control operation of a first set of switches to transfer a differential residue charge from the reservoir capacitor 301 to the pair of input capacitors 220 A, 220 B when setting the pair of input capacitors in a differential configuration based on a decision of the comparator.
- Setting the pair of input capacitors in a differential configuration based on a decision of the comparator can include setting the first plates of the input capacitors to a state “01”, which is a second of two states in a first set of states: 01 and 10.
- the control circuit 250 can control operation of a first set of switches 308 B, 308 C to cross-couple plates of the reference capacitor 301 to a first plate of the bit-trial capacitor 220 A and a first plate of bit-trial capacitor 220 B, where a second plate of the bit-trial capacitor 220 A and a second plate the bit-trial capacitor 220 Bs are configured to couple to inputs of the comparator 215 .
- the control circuit can couple a reference voltage, e.g., REF+ or REF ⁇ , to the previously set input capacitor, e.g., bit-trial capacitor, to transfer a second charge.
- a reference voltage e.g., REF+ or REF ⁇
- the control circuit e.g., logic circuit 250 of FIG. 2
- control circuit can couple a reference voltage, e.g., REF+ or REF ⁇ , to the at least one previously set bit-trial capacitors to transfer a second charge, where the reference voltage is more accurate than the voltage of the reservoir, or reference, capacitor.
- a reference voltage e.g., REF+ or REF ⁇
- the reservoir capacitor 301 can supply most of the charge to the bit-trial capacitors 220 A, 220 B as the bit-trials are performed.
- the accurate reference voltage source e.g., an “external” reference buffer circuit, only needs to supply the difference, e.g., an inaccuracy, in the charge supplied by the reservoir capacitors. Instead of having to resettle for each bit-trial, the accurate reference voltage source has only to deliver the initial charge to the reservoir capacitors during acquisition and once more when the ADC circuit is ready to sample onto the residue amplifier.
- FIG. 9 is a schematic diagram of the circuit block 222 of FIG. 5 in a positive common mode residue charge phase.
- the logic circuitry 250 can apply a correction voltage to the input capacitors 220 A, 220 B, e.g., bit-trial capacitors, based upon the bit trial.
- the logic circuitry 250 (or “control circuit”) can close switches 3112 A, 3112 B to couple the bit-trial capacitors 220 A, 220 B to the positive reference voltage REF+ to transfer positive charge to the bit-trial capacitors 220 A, 220 B.
- control circuit can control operation of a second set of switches to transfer a common-mode residue charge from a positive reference voltage REF+ to set the pair of input capacitors 220 A, 220 B when setting the pair of input capacitors in a common-mode configuration based on a decision of the comparator.
- Setting the pair of input capacitors in a common-mode configuration based on a decision of the comparator includes setting the first plates of the input capacitors to a state “11”, which a first of two states in a second set of two states: 11 and 00.
- the control circuit 250 can control operation of a second set of switches 312 A, 312 B to directly couple the positive reference voltage REF+ to a first plate of the bit-trial capacitor 220 A and a first plate of bit-trial capacitor 220 B, where a second plate of the bit-trial capacitor 220 A and a second plate the bit-trial capacitor 220 Bs are configured to couple to inputs of the comparator 215 .
- the logic circuitry can correct the difference in the common mode voltages such that the common mode of the input signal matches the comparator common mode CompCM.
- FIG. 10 is a schematic diagram of the circuit block 222 of FIG. 6 in a negative common mode residue charge phase.
- the logic circuitry 250 can apply a correction voltage to the input capacitors 220 A, 220 B, e.g., bit-trial capacitors, based upon the bit trial.
- the logic circuitry 250 can close switches 314 A, 314 B to couple the bit-trial capacitors 220 A, 220 B to the negative reference voltage REF ⁇ to transfer negative charge to the bit-trial capacitors 220 A, 220 B.
- control circuit can control operation of a second set of switches to transfer a common-mode residue charge from a negative reference voltage REF- to set the pair of input capacitors 220 A, 220 B when setting the pair of input capacitors in a common-mode configuration based on a decision of the comparator.
- Setting the pair of input capacitors in a common-mode configuration based on a decision of the comparator includes setting the first plates of the input capacitors to a state “00”, which a second of two states in a second set of two states: 11 and 00.
- the logic circuitry can correct the difference in the common mode voltages such that the common mode of the input signal matches the comparator common mode CompCM.
- the common mode estimation may be performed for several bits of the DAC circuit at the same time.
- the correction could be applied to several bits at the same time.
- the correction may be applied to a bit capacitor array of the first DAC circuit and a bit capacitor array of the second DAC circuit, where a capacitor array includes one or more bit-trial capacitors.
- the terms “a” or “an” are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of “at least one” or “one or more.”
- the term “or” is used to refer to a nonexclusive or, such that “A or B” includes “A but not B,” “B but not A,” and “A and B,” unless otherwise indicated.
- Method examples described herein may be machine or computer-implemented at least in part. Some examples may include a computer-readable medium or machine-readable medium encoded with instructions operable to configure an electronic device to perform methods as described in the above examples.
- An implementation of such methods may include code, such as microcode, assembly language code, a higher-level language code, or the like. Such code may include computer readable instructions for performing various methods. The code may form portions of computer program products. Further, in an example, the code may be tangibly stored on one or more volatile, non-transitory, or non-volatile tangible computer-readable media, such as during execution or at other times.
- tangible computer-readable media may include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact discs and digital video discs), magnetic cassettes, memory cards or sticks, random access memories (RAMs), read only memories (ROMs), and the like.
Abstract
Description
- This document pertains generally, but not by way of limitation, to integrated circuits, and more particularly, to analog-to-digital converter circuits and systems.
- Successive approximation routine (SAR) analog-to-digital converters (ADCs) convert an analog input to a digital value. Typically, the analog input is held while the SAR ADC circuit converges to a solution after a number of bit trials. Some SAR ADC circuits convert a differential analog input to a digital value. A differential SAR ADC may require that the common mode of the input signal to be at a fixed value; e.g., Vref/2. This can be accomplished by additional circuitry to translate the input common mode to the common mode required by the SAR ADC, However; this additional circuitry can result in additional space needed for an SAR ADC circuit, additional power consumption, and can introduce additional sources of noise in the signal chain.
- This disclosure describes, among other things, a differential digital-to-analog (DAC) circuit that can include a reservoir capacitor and various switches to couple the bottom plates of the input capacitors; e.g., bit-trial capacitors, to reference voltages, e.g., REF+ or REF−. In this manner, the reservoir capacitor can be used to provide any differential charge to the input capacitors, e.g., bit-trial capacitors, and the reference voltages, e.g., REF+ and REF−, can be used to provide any common mode charge to the input capacitors.
- In some aspects, this disclosure is directed to a differential digital-to-analog (DAC) circuit comprising a capacitor array including a number of DAC units, each DAC unit including: a pair of input capacitors configured to couple to a comparator; a dedicated reference capacitor associated with the pair of input capacitors; and a control circuit configured to: control operation of a first set of switches to transfer a differential residue charge from the reservoir capacitor to the pair of input capacitors when setting the pair of input capacitors in a differential configuration based on a decision of the comparator; and control operation of a second set of switches to transfer a common-mode residue charge from a reference voltage to set the pair of input capacitors when setting the pair of input capacitors in a common-mode configuration based on a decision of the comparator.
- In some aspects, this disclosure is directed to a method of operating a differential analog-to-digital converter (ADC) circuit to convert an analog input to a digital output. The method comprises coupling the analog input onto a capacitor array of a first ADC circuit, the capacitor array including a number of DAC units, each DAC unit including: a pair of input capacitors; and a dedicated reference capacitor associated with the pair of input capacitors. The method further comprises transferring a differential residue charge from the reservoir capacitor to the pair of input capacitors when setting the pair of input capacitors in a differential configuration based on a decision of a comparator; and transferring a common-mode residue charge from a reference voltage to set the pair of bit-trial capacitors when setting the pair of bit-trial capacitors in a common-mode configuration based on a decision of the comparator.
- In some aspects, this disclosure is directed to a differential digital-to-analog (DAC) circuit comprising means for coupling the analog input onto a capacitor array of a first ADC circuit, the capacitor array including a number of DAC units, each DAC unit including: a pair of input capacitors; and a dedicated reference capacitor associated with the pair of input capacitors; and means for transferring a differential residue charge from the reservoir capacitor to the pair of input capacitors when setting the pair of input capacitors in a differential configuration based on a decision of a comparator; and means for transferring a common-mode residue charge from a reference voltage to set the pair of bit-trial capacitors when setting the pair of bit-trial capacitors in a common-mode configuration based on a decision of the comparator.
- This overview is intended to provide an overview of subject matter of the present patent application. It is not intended to provide an exclusive or exhaustive explanation of the invention. The detailed description is included to provide further information about the present patent application.
- In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. Like numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed in the present document.
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FIG. 1 is a functional block diagram of an example of a differential SAR ADC. -
FIG. 2 is a functional block diagram of portions of an example of a reservoir-capacitor SAR ADC. -
FIG. 3 is circuit diagram showing an example of a portion of a SAR ADC circuit including the circuit block ofFIG. 2 , in accordance with this disclosure. -
FIG. 4 is an example of a comparator circuit that can implement various techniques of this disclosure. -
FIG. 5 is circuit diagram showing an example of a circuit that can include the main ADC circuit ofFIG. 3 in combination with an auxiliary ADC circuit. -
FIG. 6 is a schematic diagram of the circuit block ofFIG. 5 in a sampling phase. -
FIG. 7 is a schematic diagram of the circuit block ofFIG. 5 in a positive differential residue charge phase. -
FIG. 8 is a schematic diagram of the circuit block ofFIG. 5 in a negative differential residue charge phase. -
FIG. 9 is a schematic diagram of the circuit block ofFIG. 5 in a positive common mode residue charge phase. -
FIG. 10 is a schematic diagram of the circuit block ofFIG. 5 in a negative common mode residue charge phase. - Successive approximation routine (SAR) analog-to-digital converters (ADCs) convert an analog input to a digital value. Typically, the analog input is held while the SAR ADC circuit converges to a solution after a number of bit trials. Some SAR. ADC circuits convert a differential analog input to a digital value. A differential SAR ADC may require that the common mode of the input signal to be at a fixed value, e.g., Vref/2.
- If the input common mode voltage varies from the fixed value, e.g., Vref/2, the common mode voltage of the differential digital-to-analog (DAC) top plates can vary during the hit trials and the comparator in the ADC will have to manage this varying common mode voltage. Moreover, if the final common mode voltage during a conversion differs from conversion to conversion, nonlinear errors can be introduced. Therefore, it is desirable for a SAR ADC structure that accommodates variation of the input common mode voltage.
- This disclosure describes, among other things, a differential digital-to-analog (DAC) circuit that can include a reservoir capacitor and various switches to couple the bottom plates of the input capacitors, e.g., bit-trial capacitors, to reference voltages, e.g., REF+ or REF−. In this manner, the reservoir capacitor can be used to provide any differential charge to the input capacitors, e.g., bit-trial capacitors, and the reference voltages, e.g., REF+ and REF−, can be used to provide any common mode charge to the input capacitors.
-
FIG. 1 is a functional block diagram of an example of a differential SAR ADC. The SAR ADC 100 includes a positive digital-to-analog converter (DAC)circuit 105, anegative DAC circuit 110, and acomparator circuit 115. Each DAC circuit (or “DAC” in this disclosure) can include weighted bit-trial capacitors 120. In the example, the capacitors are weighted as C/2, C/4 . . . C/(2N), where N is the number of bits in the DACs and C is the total capacitance of the bit-trial capacitors added together. A differential analog input voltage (IN+, IN−) can be sampled onto the bit-trial capacitors with respect to the common mode of the comparator (CompCM) byclosing switches opening switches 130, thenopening switches 125. The top plates of the capacitors can be at the CompCM voltage. - The
positive DAC 105 and thenegative DAC 110 can also be connected to positive and negative reference voltage (REF+, REF−). As part of the successive approximation routine, bit trials for each of the bit-trial capacitors can be performed iteratively. In a bit trial, the output of thepositive DAC 105 and the output of thenegative DAC 110 can be applied to the inputs of thecomparator circuit 115. Based on the output of the comparator circuit, a bit capacitor can be connected to either REF+ or REF− usingswitches 135. If the bit capacitor is connected to REF+ the bit of the digital value corresponding to the bit-trial capacitors is assigned a logic value ‘1’, and if the bit capacitor is connected to REF+ the bit of the digital value corresponding to the bit-trial capacitors is assigned a logic value ‘0’. Conversion can then proceed to the next bit capacitor until all bits of the digital value are determined. -
FIG. 2 is a functional block diagram of portions of an example of a reservoir-capacitor based SAR ADC 200. Similar to the SAR ADC ofFIG. 1 , the reservoir-capacitor based SAR ADC 200 includes two DAC circuits, apositive DAC circuit 205 and a negativecircuit DAC circuit 210, and acomparator circuit 215. EachDAC circuit trial capacitors 220 shown attached tocircuit blocks 222 to simplify the figure. Some examples of the DACs include 8, 12, or 16-bit DACs. There can be a circuit block for each bit weight (C/2, C/4 . . . C/(2N)) and a circuit block can include an arrangement of electronic switches and a reservoir capacitor. Eachcircuit block 222 can be a unit element or “DAC unit” of a respective DAC capacitor array. - The reservoir-capacitor SAR ADC 200 can include logic circuitry 250 (also referred to as a “control circuit”). In certain examples, the
logic circuitry 250 can be included in an SAR ADC controller. In certain examples, thelogic circuitry 250 can include a sequencer to advance theSAR ADC 200 through multiple circuit states to perform the SAR. -
FIG. 3 is circuit diagram showing an example of a portion of aSAR ADC circuit 300 including thecircuit block 222 ofFIG. 2 , in accordance with this disclosure. Thecircuit block 222 can be a unit element or “DAC unit” of a capacitor array of a DAC circuit such that a DAC circuit, e.g.,DAC circuit 205 ofFIG. 2 , can include a number of circuit blocks 222. For purposes of clarity, only one DAC unit is depicted inFIG. 3 . Eachcircuit block 222 can be coupled to the differential analog input voltage (IN+, IN−), differential reference voltage (REF+, REF−), andcomparator circuit 215. - The
circuit block 222 can include areservoir capacitor 301. In some example configurations, thereservoir capacitor 301 can be a dedicated reference capacitor associated with the pair ofinput capacitors DAC unit element 222. The value of capacitance of a reservoir capacitor can be larger than the capacitance value of its corresponding bit capacitor. For example, the value of capacitance of a reservoir capacitor can be five to twenty times the capacitance of the bit-trial capacitors. - The differential analog input voltage (IN+, IN−) can sampled and stored onto
input capacitors switches reservoir capacitor 301 when the input voltage is sampled on the bit-trial capacitors 220 usingswitches reservoir capacitor 301 from theinput capacitors - Logic circuitry, e.g.,
logic circuitry 250 ofFIG. 2 , can open switches 302, 304 and 306, andclose switch 310 for a bit trial. Depending on the result of the hit trial at the comparator output, the voltage of thereservoir capacitor 301 can be added or subtracted from the voltage of theinput capacitors reservoir capacitor 301 is added or subtracted from the bit-trial capacitors using switches 308. - Logic circuitry, e.g.,
logic circuitry 250 ofFIG. 2 , can progress the conversion of the differential analog input signal through all of the bit-trial capacitors until all bits of the digital value are determined. In certain examples, the logic circuitry can include a SAR controller (e.g., a processor) that progresses the SAR ADC through a conversion according to outcomes determined at thecomparator circuit 215. In certain examples, the logic circuitry can include a logic sequencer that progresses the conversion through a series of logic states that correspond to steps of the bit trials. Using reservoir capacitors can speed up the bit trials from the embodiment ofFIG. 1 because resampling does not need to take place during every bit trial. - The differential SAR ADCs of
FIG. 1 andFIG. 2 can require that the common mode of the input signal be at Vref/2, for example. If the common mode of input signal is maintained at a fixed value, e.g., Vref/2, the common mode of the DAC top plates during the bit trials can be a fixed value VCM, COMP. At the end of the conversion, the bits of the negative DAC are complementary to the bits of the positive DAC, e.g., if a bit of the positive DAC is a “1”, a bit of the negative DAC can be a “0”. - If the input common mode varies from the fixed value, e.g., Vref/2, the common mode of the DAC top plates can vary during the bit trials and the comparator in the ADC will have to manage this varying common mode voltage. Moreover, if the final common mode voltage during a conversion differs from conversion to conversion, nonlinear errors can be introduced. As explained above, additional circuit components may be needed to provide an input to the ADC with a fixed common mode voltage. Therefore, it is desirable for a SAR ADC structure that accommodates variation of the input common mode voltage.
- Using the techniques of this disclosure, additional switches can be included in the
circuit block 222 to couple the bottom plates of the input capacitors, e.g., bit-trial capacitors 220, to reference voltages REF+ or REF−. As seen inFIG. 3 , switches 312A, 312B (collectively “switches 312”) can couple the bottom plates of the input capacitors, e.g., bit-trial capacitors trial capacitors reservoir capacitor 301 can be used to provide any differential charge to thecapacitors trial capacitors - In this disclosure, the terms “top plate” and “bottom plate” are used for convenience to describe the capacitors and are not meant to imply that there is any, required spatial orientation for the capacitors. Further, the switches referred to in this disclosure can include transistors and, in particular, complementary metal-oxide-semiconductor (CMOS) transistors due to their high performance and yield.
- For an N-bit SAR ADC circuit, without an auxiliary ADC circuit, e.g., flash ADC or SAR ADC circuit, there can be ‘N’ circuit blocks 222 of
FIG. 3 , e.g., unit elements or “units” of a capacitor array of a DAC circuit, connected in parallel and coupled to thecomparator 215. In some example configurations, all of the bit-trial capacitors 220 can be associated with a respective circuit block 222 similar to the example shown inFIG. 3 . In other example configurations, only some of the bit-trial capacitors 220, e.g., at least some of the most significant bits (MSBs), can be associated with a respective circuit block 222 similar to the example shown inFIG. 3 . For example, in some implementations, the least significant bit (LSB) bit-trial capacitors do not need to couple to reference voltages REF+ or REF− because they only resolve the differential signal information and, as such, switches 312 and 314 are not needed for the circuit blocks 222 associated with the LSBs. As such, in some examples, thecircuit 300 associated with the LSBs can exclude switches 312 and 314. -
FIG. 4 is an example of a comparator circuit that can implement various techniques of this disclosure. Thecomparator circuit 215 ofFIG. 4 is an example of thecomparator circuit 215 ofFIG. 3 . - The
comparator circuit 215 can include a non-inverting input (+) and an inverting input (−) coupled to the top plate nodes “TOP-P” and “TOP-N” that are coupled to the top plates of the bit-trial capacitors, e.g.,top plates FIG. 2 . Thecomparator 215 can include anadditional input 420 that can be the intended DAC common mode output reference voltage for the comparator's differential inputs. Theinput 420 can be connected to a bias voltage (which could be any suitable voltage, including ground), although it could also be connected to other sources, for example a variable voltage that asymptotes to the bias voltage. The comparator circuit 415 can include an additional output OUT2, such that the outputs OUT1 and OUT2 are responsive to both the differential and common mode components of its inputs. - The logic circuitry, e.g., the
logic circuitry 250 ofFIG. 2 , can accommodate the additional comparator outputs and produce independent bus outputs to control the positive DAC and negative DAC circuits. - The
comparator circuit 215 ofFIG. 4 is shown and described in commonly assigned U.S. Pat. No. 7,432,844 to Mueck et al., titled “Differential Input Successive Approximation Analog to Digital Converter with Common Mode Rejection,” the entire contents of which being incorporated herein by reference, includingFIGS. 7A-7E and the associated description of those figures. - The
circuit 300 ofFIG. 3 can form part of a main SAR ADC circuit. In some example configurations, both a main SAR ADC and an auxiliary ADC, e.g., a flash or SAR. ADC, can be used in conjunction with the techniques described above with respect toFIG. 3 . The auxiliary ADC can have a resolution less than the main ADC circuit. -
FIG. 5 is circuit diagram showing an example of acircuit 500 that can include the main ADC circuit ofFIG. 3 in combination with an auxiliary ADC circuit. Thecircuit block 222 can be a unit element or “DAC unit” of a capacitor array of a DAC circuit such that a DAC circuit, e.g.,DAC circuit 205 ofFIG. 2 , can include a number of circuit blocks 222. For purposes of clarity, only one DAC unit is depicted inFIG. 3 . Thecircuit 500 can include a firstauxiliary ADC circuit 502A to convert a voltage referenced from the input of the positive DAC circuit to the comparator common mode, and a secondauxiliary ADC circuit 502B to convert a voltage referenced from the input of the negative DAC circuit to the comparator common mode. - The
auxiliary ADC circuits main ADC circuit 200 ofFIG. 2 , can provide for high resolution. An auxiliary ADC circuit can help convert higher input voltage ranges using a low voltage supply and can allow the main ADC to power down its comparator during the acquisition phase. An auxiliary ADC can convert the input voltage to, for example, 2-bit accuracy using a binary search algorithm. An auxiliary ADC can perform this conversion before the main ADC takes any action. Then, the auxiliary ADC circuit can transfer the results of the low-resolution conversion to the main ADC circuit, including to bit-trial capacitors 220, which can then resolve the remaining bits. - In some examples, auxiliary ADC circuits can be used in the comparison of the output of the positive DAC, the output of the negative DAC, and the common mode voltage of the comparator circuit. In the non-limiting example of
FIG. 5 , the auxiliary ADC circuit is a flash ADC circuit (also referred to as “a direct-conversion ADC”). - In contrast to a SAR ADC circuit, the result of the flash ADC circuit can be available after one conversion cycle. In the example of
FIG. 9 , theflash ADC circuit 502A can convert a voltage referenced from the input of the positive DAC circuit to the comparator common mode andflash ADC circuit 502B can convert a voltage referenced from the input of the negative DAC circuit to the comparator common mode. Before a conversion phase using the first ADC circuit, thelogic circuit 250 can control couple the analog input signal onto theflash ADC circuits flash ADC circuits flash ADC circuits - There are four possible outcomes or “states” (states “10”, “01”, “11”, and “00”) to the conversion of the input are shown in Table 1 below:
-
TABLE 1 Case No. FlashP FlashN 1 1 0 2 0 1 3 1 1 4 0 0 - The states can be determined by the comparators of auxiliary ADC circuits, e.g.,
flash ADC circuits FIG. 5 . In configurations that do not include auxiliary ADC circuits, such as shown inFIG. 3 , the states can be determined by a comparator such ascomparator 215 inFIG. 4 . - In Case Nos. 1 and 2, the auxiliary ADC circuits for the bit position have different outcomes. For example, in Case No. 1, FlashP is 1 and FlashN is 0. For Case Nos. 1 and 2, there is no input common mode issue because the input voltage is intermediate the output voltage of the positive DAC circuit and the negative DAC circuit. For Case No. 1
capacitors capacitors - For case No. 3, both the input at the positive side and the input at the negative side are greater than the comparator common mode. Thus, the input voltage has a common mode different from the comparator common mode and the bit-
trial capacitors capacitors - To reduce a difference between the input common mode voltage and Vref/2, for example, the
logic circuitry 250 can apply a correction voltage to one or more of the bit-trial capacitors logic circuitry 250 can couple the reference voltages REF+ and REF− to the bit-trial capacitors reservoir capacitor 301 can be used to provide any differential residue charge to the bit-trial capacitors FIGS. 7 and 8 , and the reference voltages REF+ and REF− can be used to provide any common mode residue charge to the bit-trial capacitors FIGS. 9 and 10 . - The techniques of this disclosure are applicable to circuits without auxiliary ADC circuits, such as shown in
FIG. 3 . In such configurations, thecomparator 215, e.g., as shown inFIG. 4 , can determine the states as shown in Table 1. However, for purposes of conciseness, the techniques will be described with respect to the circuit ofFIG. 5 , which can include auxiliary ADC circuits in combination with a main ADC circuit. - As mentioned above, the
circuit block 222 ofFIGS. 3 and 5 can be a unit element or “DAC unit” of a capacitor array of a DAC circuit such that a DAC circuit, e.g.,DAC circuit 205 and/orDAC circuit 210 ofFIG. 2 , can include a number of circuit blocks 222. The DAC units can include most significant bit (MSB) DAC units and least significant bit (LSB) DAC units. In some example configurations, all of the DAC units can be similar such that the MSB and LSB units include the set ofswitches - In other example configurations, only some of the DAC units include the set of
switches switches switches switches -
FIG. 6 is a schematic diagram of thecircuit block 222 ofFIG. 5 in a sampling phase. During a sampling phase, thetop plate switches trial capacitors trial capacitors reservoir capacitor 301 can be charged by coupling to the main reference voltage sources REF+ and REF− usingswitches - The bit-trial capacitors of the DAC circuits can store the input signal as sampled charge and deliver a differential input voltage to the inputs of the
comparator 215. The comparator differential input voltage can represent the imperfection between the original input signal and an estimate of the input signal developed by the DAC circuits. The comparator differential input voltage can include an input common mode offset, and thecomparator circuit 215 can include a comparator common mode offset. - The
logic circuitry 250 ofFIG. 2 can be coupled to positive and negative DAC circuits, the switches, and the comparator circuit, such as shown inFIG. 1 . As part of a SAR operation, thelogic circuitry 250 can initiate successive bit trials using the weighted bit-trial capacitors to convert the input voltage to a digital value by comparing the outputs of the positive DAC circuit and the negative DAC circuit using the comparator circuit and updating the DAC values. As the conversion progresses, the comparator differential input voltage can be reduced towards zero by transferring charge from thereference reservoir capacitor 301 to the bit-trial capacitors -
FIG. 7 is a schematic diagram of thecircuit block 222 ofFIG. 5 in a positive differential residue charge phase. In the example configuration shown inFIG. 7 , thelogic circuitry 250 ofFIG. 2 determined that to converge the estimate of the input signal on the DAC circuits to the original input signal, a positive differential residue charge can be applied, e.g., based on flash ADC results such as Case No. 1 in Table 1. - To reduce the comparator differential input voltage towards zero, the logic circuit 250 (or “control circuit”) can close
switches reference reservoir capacitor 301 to set theinput capacitors reservoir capacitor 301 to the pair ofinput capacitors - For example, when setting the pair of bit-trial capacitors in a differential configuration based on a bit-trial result to transfer the differential residue charge during the conversion phase, the
control circuit 250 can control operation of a first set ofswitches reference capacitor 301 to a first plate of the bit-trial capacitor 220A and a first plate of bit-trial capacitor 220B, where a second plate of the bit-trial capacitor 220A and a second plate the bit-trial capacitor 220Bs are configured to couple to inputs of thecomparator 215. -
FIG. 8 is a schematic diagram of thecircuit block 222 ofFIG. 5 in a negative differential residue charge phase. In the example configuration shown inFIG. 8 , thelogic circuitry 250 ofFIG. 2 determined that to converge the estimate of the input signal on the DAC circuits to the original input signal, a negative differential residue charge can be applied, e.g., based on flash ADC results such as Case No. 2 in Table 1. - To reduce the comparator differential input voltage towards zero, the
logic circuit 250 can closeswitches reference reservoir capacitor 301 to theinput capacitors reservoir capacitor 301 to the pair ofinput capacitors - For example, when setting the pair of bit-trial capacitors in a differential configuration based on a bit-trial result to transfer the differential residue charge during the conversion phase, the
control circuit 250 can control operation of a first set ofswitches reference capacitor 301 to a first plate of the bit-trial capacitor 220A and a first plate of bit-trial capacitor 220B, where a second plate of the bit-trial capacitor 220A and a second plate the bit-trial capacitor 220Bs are configured to couple to inputs of thecomparator 215. - In some example implementations, after coupling the
reservoir capacitor 301 to the input capacitors, e.g., bit-trial capacitors, to transfer a first change such as described with respect toFIGS. 7 and 8 , the control circuit can couple a reference voltage, e.g., REF+ or REF−, to the previously set input capacitor, e.g., bit-trial capacitor, to transfer a second charge. For example, during a conversion phase, the control circuit, e.g.,logic circuit 250 ofFIG. 2 , can control transfer of a first charge from thereservoir capacitor 301 to set at least one of the bit-trial capacitors - In this manner, the
reservoir capacitor 301 can supply most of the charge to the bit-trial capacitors -
FIG. 9 is a schematic diagram of thecircuit block 222 ofFIG. 5 in a positive common mode residue charge phase. As explained above, when the outputs of the auxiliary ADC circuits are both ‘1s’, such as in Case No. 3 in Table 1, both the input at the positive side and the input at the negative side are more than the comparator common mode CompCM because of the positive common mode residue. Thelogic circuitry 250 can apply a correction voltage to theinput capacitors trial capacitors trial capacitors - In other words, the control circuit can control operation of a second set of switches to transfer a common-mode residue charge from a positive reference voltage REF+ to set the pair of
input capacitors - For example, when setting the pair of bit-trial capacitors in a common-mode configuration based on a bit-trial result to transfer the common-mode residue charge during a conversion phase, the
control circuit 250 can control operation of a second set ofswitches trial capacitor 220A and a first plate of bit-trial capacitor 220B, where a second plate of the bit-trial capacitor 220A and a second plate the bit-trial capacitor 220Bs are configured to couple to inputs of thecomparator 215. In this manner, the logic circuitry can correct the difference in the common mode voltages such that the common mode of the input signal matches the comparator common mode CompCM. -
FIG. 10 is a schematic diagram of thecircuit block 222 ofFIG. 6 in a negative common mode residue charge phase. As explained above, when the outputs of the auxiliary ADC circuits are both ‘0s’, such as in Case No. 3 in Table 1, both the input at the positive side and the input at the negative side are less than the comparator common mode CompCM because of the negative common mode residue. Thelogic circuitry 250 can apply a correction voltage to theinput capacitors logic circuitry 250 can closeswitches trial capacitors trial capacitors - In other words, the control circuit can control operation of a second set of switches to transfer a common-mode residue charge from a negative reference voltage REF- to set the pair of
input capacitors - Although the process of correcting for common mode mismatch has been described in terms of one bit of a DAC circuit at a time with respect to
FIGS. 9 and 10 , the common mode estimation may be performed for several bits of the DAC circuit at the same time. In addition, the correction could be applied to several bits at the same time. Thus, the correction may be applied to a bit capacitor array of the first DAC circuit and a bit capacitor array of the second DAC circuit, where a capacitor array includes one or more bit-trial capacitors. - Various Notes
- Each of the non-limiting aspects or examples described herein may stand on its own, or may be combined in various permutations or combinations with one or more of the other examples.
- The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as “examples.” Such examples may include elements in addition to those shown or described. However, the present inventors also contemplate examples in which only those elements shown or described are provided. Moreover, the present inventors also contemplate examples using any combination or permutation of those elements shown or described (or one or more aspects thereof), either with respect to a particular example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein.
- In the event of inconsistent usages between this document and any documents so incorporated by reference, the usage in this document controls.
- In this document, the terms “a” or “an” are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of “at least one” or “one or more.” In this document, the term “or” is used to refer to a nonexclusive or, such that “A or B” includes “A but not B,” “B but not A,” and “A and B,” unless otherwise indicated. In this document, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein.” Also, in the following claims, the terms “including” and “comprising” are open-ended, that is, a system, device, article, composition, formulation, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms “first,” “second,” and “third,” etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.
- Method examples described herein may be machine or computer-implemented at least in part. Some examples may include a computer-readable medium or machine-readable medium encoded with instructions operable to configure an electronic device to perform methods as described in the above examples. An implementation of such methods may include code, such as microcode, assembly language code, a higher-level language code, or the like. Such code may include computer readable instructions for performing various methods. The code may form portions of computer program products. Further, in an example, the code may be tangibly stored on one or more volatile, non-transitory, or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media may include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact discs and digital video discs), magnetic cassettes, memory cards or sticks, random access memories (RAMs), read only memories (ROMs), and the like.
- The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be used, such as by one of ordinary skill in the art upon reviewing the above description. The Abstract is provided to comply with 37 C.F.R. § 1.72(b), to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. This should not be interpreted as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may lie in less than all features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description as examples or embodiments, with each claim standing on its own as a separate embodiment, and it is contemplated that such embodiments may be combined with each other in various combinations or permutations. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.
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US16/032,752 US10516411B1 (en) | 2018-07-11 | 2018-07-11 | Common mode rejection in reservoir capacitor analog-to-digital converter |
DE102019118670.6A DE102019118670A1 (en) | 2018-07-11 | 2019-07-10 | EVALUATION OF REACTIVITY IN AN ANALOG-DIGITAL CONVERTER WITH RESERVOIR CAPACITOR |
CN201910622244.6A CN110719104B (en) | 2018-07-11 | 2019-07-11 | Common mode rejection in storage capacitor analog-to-digital converter |
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