US20170323989A1 - Solar module structures and assembly methods for three-dimensional thin-film solar cells - Google Patents

Solar module structures and assembly methods for three-dimensional thin-film solar cells Download PDF

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US20170323989A1
US20170323989A1 US15/602,906 US201715602906A US2017323989A1 US 20170323989 A1 US20170323989 A1 US 20170323989A1 US 201715602906 A US201715602906 A US 201715602906A US 2017323989 A1 US2017323989 A1 US 2017323989A1
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layer
prism
silicon
hexagonal
step
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Mehrdad M. Moslehi
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Ob Realty LLC
Beamreach Solar Inc
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Ob Realty LLC
Beamreach Solar Inc
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Priority to US82867806P priority Critical
Priority to US88630307P priority
Priority to US11/868,491 priority patent/US7999174B2/en
Priority to US13/187,291 priority patent/US8742249B2/en
Priority to US14/293,676 priority patent/US20150068583A1/en
Application filed by Ob Realty LLC, Beamreach Solar Inc filed Critical Ob Realty LLC
Priority to US15/602,906 priority patent/US20170323989A1/en
Assigned to SOLEXEL, INC. reassignment SOLEXEL, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MOSLEHI, MEHRDAD M.
Assigned to OB REALTY, LLC . reassignment OB REALTY, LLC . RECORDATION OF FORECLOSURE OF PATENT PROPERTIES Assignors: OB REALTY, LLC
Assigned to BEAMREACH SOLAR, INC. reassignment BEAMREACH SOLAR, INC. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: SOLEXEL, INC.
Publication of US20170323989A1 publication Critical patent/US20170323989A1/en
Application status is Abandoned legal-status Critical

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    • Y10T117/1092Shape defined by a solid member other than seed or product [e.g., Bridgman-Stockbarger]

Abstract

A method for assembling a solar module structure comprises patterning a frontside and a backside of a double-sided printed circuit board coated with metallic foils according to desired frontside and backside interconnect layouts; applying a first coating layer to the rear side of a plurality of three-dimensional thin-film solar cells, each three-dimensional thin-film solar cell comprising: a three-dimensional thin-film solar cell substrate comprising emitter junction regions and doped base regions; emitter metallization and base metallization regions; the three-dimensional thin-film solar cell substrate comprising a plurality of single-aperture unit cells; placing the three-dimensional thin-film solar cells on the frontside of the double-sided printed circuit board; preparing a solar module assembly, comprising: a glass layer; a top encapsulant layer; the plurality of three-dimensional thin-film solar cells on the frontside of the double-sided printed circuit board; a rear encapsulant layer; a protective back plate; and sealing and packaging the solar module assembly.

Description

    RELATED APPLICATIONS
  • This U.S. patent application is a continuation of U.S. patent application Ser. No. 13/187,291 filed Jul. 20, 2011 which is a continuation of U.S. patent application Ser. No. 11/868,491 filed Oct. 6, 2007 application which claims the benefit of provisional patent applications 60/828,678 filed on Oct. 9, 2006 and 60/886,303 filed on Jan. 24, 2007, and which are all hereby incorporated by reference in their entirety.
  • FIELD
  • This disclosure relates in general to the field of photovoltaics and solar cells, and more particularly to solar module structures and assembly methods. Even more particularly, the presently disclosed subject matter relates to solar module structures and assembly methods for three-dimensional (3-D) thin-film solar cells (TFSCs).
  • DESCRIPTION OF THE RELATED ART
  • Renewable, high-efficiency, and cost-effective sources of energy are becoming a growing need on a global scale. Increasingly expensive, unreliable, and environmentally-risky fossil fuels and a rising global demand for energy, including electricity, have created the need for alternate, secure, clean, widely available, cost-effective, environmentally-friendly, and renewable forms of energy. Solar photovoltaic (PV) electricity generation using solar cells is uniquely suited to meet the needs of residential, commercial, industrial, and centralized utility applications. Key attributes that make solar energy attractive are the abundant, worldwide, point-of-use supply of sunlight, environmental friendliness, scalability (from milliwatts to megawatts), secure point-of-use generation of solar electricity, and excellent distributed energy economics. The sun provides more energy to the earth in one hour than the annual energy consumption of the entire world. Much of the earth's surface receives a significant amount of annual sun-hours which may be effectively harnessed for clean and secure electricity generation. A key driver for this market pull is a rising public awareness of environmentally-benign technologies. However, due to relatively low solar cell efficiencies (e.g., less than 12% for most thin-film technologies and roughly 12% to 18% for most crystalline silicon solar cell technologies), high costs of raw materials (e.g., silicon for crystalline silicon wafer solar cells) and manufacturing processes, limitations on cost-effective and efficient electrical storage, and a general lack of infrastructure to support solar cell proliferation, to date there has been limited use of this energy solution (currently, electricity generation by solar photovoltaics accounts for less than 0.1% of total worldwide electricity generation).
  • For commercial applications, cost of energy to the end-user (e.g., in cents/kWh for electricity) should be sufficiently low and comparable to or even better than that from utility grids using conventional electricity generation sources. The solar photovoltaic electricity generation, which currently accounts for less than 0.1% of the global electricity generation, may be substantially expanded if it achieves cost parity with conventional grid electricity. As the costs of solar cells and modules (typically expressed as $/Wp) are reduced, grid-tied solar photovoltaic applications are gaining acceptance at an accelerated pace, making them an attractive option for significant proliferation in electricity generation.
  • In the price-sensitive solar cell market, two principal technology options exist. On the one hand, crystalline silicon (c-Si) wafers may serve as the basis for solar cell formation (currently accounting for more than 90% of the solar PV market). On the other hand, thin-film (amorphous and polycrystalline) technologies using silicon and other semiconductor absorber materials (such as amorphous silicon, CdTe, or CIGS) may offer significant cost advantages compared to crystalline silicon wafer-based solar cells. These different approaches are at opposite ends of the price-performance scale. Crystalline silicon wafers offer higher performance, but at higher costs (due to the relatively high cost of starting monocrystalline and multicrystalline silicon wafers). Thin-film technologies may offer lower manufacturing costs, but typically at lower performance levels (i.e., lower efficiencies). For both approaches, the price-per-watt typically increases as cell efficiencies rise (due to higher material and/or manufacturing costs).
  • Due to a rapid annual growth rate of more than 40% during the past ten years and the concurrent demands for silicon material by both semiconductor microelectronics and solar PV industries, the solar PV industry has been experiencing a shortage of polysilicon feedstock supply. The polysilicon feedstock shortage has significantly constrained the solar PV industry growth, particularly during the past several years. In fact, the solar cell industry currently consumes over half of the worldwide production of high-purity polysilicon feedstock. Within the last few years, the contract price of polysilicon has increased from roughly $30/kg to roughly $85/kg, with spot prices exceeding $250/kg. This has led to large increases in the price of monocrystalline and multicrystalline silicon wafers, which now account for roughly half of the total solar module manufacturing cost.
  • The trend in the mainstream crystalline silicon (c-Si) wafer solar cell industry has been to scale down wafer thicknesses to below 200 microns (in order to reduce the amount of silicon material in grams used per watt of solar cell rated peak power). For example, monocrystalline silicon wafer solar cells are projected to scale down to a thickness of roughly 120 microns by 2012, from a current wafer thickness of roughly 200 microns. Multicrystalline silicon wafer solar cells are projected to scale down to a thickness of roughly 180 microns by 2012, from a current average wafer thickness of roughly 260 microns. This wafer thickness reduction, however, presents additional challenges related to mechanical rigidity, manufacturing yield, and solar cell efficiency. Despite its high cost, crystalline silicon (c-Si) technology still dominates the solar cell market, mainly due to higher efficiencies and synergies with the established microelectronics industry and supply chain. Currently, c-Si accounts for slightly over 90% of the solar cell market (95% when ribbon silicon is included).
  • Historically, crystalline silicon solar cells have achieved a 20% cost reduction for each doubling of cumulative global cell production (measured in megawatts or MWp and gigawatts or GWp). It is projected that through innovative cost reduction and efficiency enhancement methods, the cost of electricity derived from grid-connected rooftop solar photovoltaic modules may become comparable to the cost of electricity purchased from the utility grid in five to ten years. A 2005 survey of the commercially available monocrystalline silicon and multicrystalline silicon solar modules reports the solar module efficiencies then in the range of 9.1% to 16.1%, with a median efficiency value of about 12.5%. Commercial crystalline silicon modules usually show a rapid initial efficiency degradation of 1% to 3% (relative) due to various effects, including photodegradation effects in wafered solar cells (e.g., wafer minority carrier lifetime degradation). Monocrystalline silicon wafer solar cell efficiencies are projected to increase to roughly 20.5% by 2012, from a current efficiency of roughly 16.5% (leading-edge commercially available monocrystalline silicon solar cell and solar module efficiencies are currently about 21.5% and 18%, respectively). Multicrystalline silicon wafer solar cell efficiencies are projected to increase to roughly 18% by 2012, from a current efficiency level of roughly 15.5%.
  • State-of-the-art crystalline silicon solar cell manufacturing currently uses about 10 grams of high-purity polysilicon feedstock per peak watt (g/Wp), resulting in a polysilicon feedstock material cost of about $0.85/Wp (assuming a polysilicon price of $85/kg). Over the next five years, the projected trends of solar cell wafer thickness reduction (e.g., to less than 200 micron wafers) and a long-term assumed price of about $20/kg for solar-grade polysilicon may reduce the polysilicon feedstock cost (in g/Wp) by about a factor of four to eight to about $0.10/Wp to $0.20/Wp. Thus, any competing solar cell technologies should benchmark their manufacturing cost goals against this reduced raw material cost number. For a given cell efficiency, silicon wafer thickness reduction presents a prime opportunity for solar cell cost reduction by reducing the amount of polysilicon feedstock consumed per watt of peak solar power.
  • The cost associated with wire saws, amounting to about $0.25/Wp for current silicon solar cells provides another wafer-related cost component for silicon wafer solar cells. Innovative and cost-effective technologies that eliminate the kerf losses associated with sawing and slicing should further facilitate silicon solar cell cost reductions. It is projected that the wafer-based crystalline silicon solar module manufacturing cost (which is currently on the order of $2.10 per watt to more than $2.70 per watt) may be reduced to the range of roughly $1.50/Wp to $1.80/Wp by the year 2012, in part due to wafer sawing kerf loss reduction to roughly 130 microns by 2012 from the current value of roughly 200 microns. The overall cost reductions for wafer-based crystalline silicon solar cells may come from various sources including: lower cost polysilicon feedstock, thinner wafers, higher cell-level efficiencies, reduced wafer sawing kerf losses, and increased economy of scale or manufacturing volume.
  • State-of-the-art silicon wafer solar cell fabrication facilities (“solar fabs”) typically produce 125 mm×125 mm up to 156 mm×156 mm solar cells today. The trend in crystalline silicon wafer solar cells is toward thinner and larger wafers. The monocrystalline and cast (as well as ribbon) multicrystalline silicon solar cell wafer thicknesses in leading-edge solar cells used for power generation modules are projected to be reduced to around 150 and 200 microns, respectively, by around 2009-2010. Any cost-effective, high-efficiency, innovative silicon solar cell technology which enables a substantial reduction of the silicon material consumption (e.g., wafer or film thickness) per Wp of cell power compared to the above-mentioned current and projected 2009-2010 numbers may offer significant promise as a viable commercial solar cell technology for solar photovoltaic applications (e.g., residential, commercial, and industrial rooftop as well as large-scale centralized utilities electrical power generation applications).
  • Higher solar cell efficiencies have favorable effects on the entire solar cell value chain and levelized cost of energy (LCOE in $/kWh) due to reduced material consumption and cost as well as reduced balance-of-system (BOS) costs (e.g., area-related solar module installation and inverter costs). The current mainstream commercial crystalline solar cells provide efficiencies on the order of 14% to 17%. It is expected that the projected crystalline silicon solar cell efficiencies in commercial solar cells may approach around 19% and 17% for monocrystalline and multicrystalline silicon solar cells, respectively, by the year 2009. A key area for new solar cell business opportunities is development of innovative cell structures and simplified process flows which may drive efficiencies up while lowering overall solar cell and module manufacturing costs. For alternative (e.g., thin-film PV) approaches to succeed over the mainstream wafer-based crystalline silicon solar cell technologies, they should provide higher efficiencies at even lower manufacturing costs compared to the projected efficiency and cost numbers for the mainstream wafer-based crystalline silicon solar cells when the new technology is fully commercialized.
  • Economy-of-scale fab cost reduction associated with high-volume solar fab capacities is a key factor impacting LCOE. The state-of-the-art high-volume solar photovoltaic fabs have annual production capacities on the order of or in excess of 50 MWp to 100 MWp (MWp=1 million Wp). High-volume solar photovoltaic fab capacities are expected to increase substantially to annual production rates of several hundred MWp or even approaching 1 GWp (GWp=1 billion Wp) in the coming decade. While very-high-volume solar fabs in the range of 100 MWp to 1 GWp should facilitate longer term cost reductions (including LCOE) through high-volume manufacturing economies of scale, the relatively high initial fab investment costs, which may easily exceed $100M, may impose certain limits on solar photovoltaic fab construction options. Ideally, the preference may be to develop innovative crystalline silicon solar cell designs and simplified manufacturing processes which facilitate substantial manufacturing cost reductions in solar cells and modules even in smaller-scale (and less capital intensive) fabs with modest production volumes (e.g., annual production volumes in the range of 5 MWp to 50 MWp). This type of technology would allow for modest-volume solar photovoltaic fabs with modest fab setup and operation costs. Reduced fab setup and operation costs would further facilitate global proliferation of cost-effective solar modules, enabling construction of a multitude of very affordable modest-volume fabs (in contrast to having to set up very expensive high-volume fabs in order to achieve sufficient economy of scale for manufacturing cost reduction). Of course, an innovative solar cell technology that meets the above-mentioned criteria for cost-effective, modest-volume fabs (i.e., meeting the LCOE roadmap requirements even at modest production volumes in low-cost fabs set up for simplified solar cell processing), may also be applicable to very-high-volume (e.g., greater than 100 MWp) solar fabs. Such solar photovoltaic fabs can take further advantage of the economies of scale associated with increased volume.
  • Thin-film solar cell (TFSC) technologies (e.g., amorphous silicon, CdTe, and CIGS) require little absorber material (usually much less than 10 microns in thickness) to absorb typical standard “Air Mass 1.5” (AM-1.5) solar illumination due to absorption bands that are well matched to the solar spectrum. The TFSC absorber material may be deposited on inexpensive substrates such as glass or flexible metallic or non-metallic substrates. TFSCs typically offer low cost, reduced module weight, reduced materials consumption, and a capability for using flexible substrates, but are usually much lower in efficiency (e.g., usually 5% to 12%). In the case of prior art thin crystalline silicon films, there are a number of major problems and challenges with the use of flat silicon films (such as epitaxially growth silicon films with thicknesses below 50 microns) for low-cost, high-performance solar cells. These include: relatively low solar module efficiencies (typically 7% to 12%), field degradation of module efficiencies, scarce and expensive absorber materials (e.g., In and Se for CIGS and Te for CdTe), limited validation of system field reliability, and adverse environmental impact of non-silicon technologies such as CIS/CIGS and CdTe.
  • Prior art FIG. 1 shows process flow 10 for fabricating c-Si TFSCs using planar silicon thin-film absorber layers produced by epitaxial silicon. This prior art TFSC fabrication process flow uses several shadow mask process steps to form the cell structure. The cell absorber is simply a thin planar film of c-Si formed by silicon epitaxial growth processing. The cell uses frontside silicon texturing to improve light trapping and a detached rear aluminum mirror to improve the cell efficiency. Step 12 starts with single-crystal p+ CZ silicon. Step 14 involves electrochemical HF etching of silicon to form 2-layer porous silicon comprising a 1 micron top layer with 20% porosity and a 200 nanometer rear layer with greater than 50% porosity. Step 16 involves a hydrogen (H2) anneal at 1100° C. for 30 minutes. Step 18 involves epitaxial silicon growth at 1100° C. using trichlorosilane or SiHCl3 (deposition rate of 1 micron per minute), forming 2 microns of p+− Si and 30 microns of p-Si. Step 20 involves frontside surface texturing by wet KOH etching to form upright surface pyramids. Step 22 involves the first shadow mask process, with LPCVD silicon nitride (SiNx) deposition through a shadow mask to define emitter diffusion windows. Step 24 involves solid source phosphorus diffusion at 830° C. (to achieve 80 Ω/square for the n+ doped junction). Step 26 involves the second shadow mask process, with frontside metallization (titanium/Pd/silver grid) by evaporation through shadow mask. Step 28 involves emitter surface passivation by hydrogenated PVD or PECVD SiNx. Step 30 involves contact frontside busbar by a conductive adhesive. Step 32 involves gluing the cell frontside to MgF2-coated glass using clear glue. Step 34 involves separating the cell from silicon wafer by mechanical stress. Step 36 involves the third shadow mask process, with backside aluminum metallization using evaporation through shadow mask. Finally, step 38 involves attaching an aluminum reflector at 200 micron spacing from the cell backside.
  • Prior art FIG. 2 shows another process flow method 40 for fabrication of solar cells on silicon wafers with self-aligned selective emitter and metallization. This prior art process uses laser processing to pattern the top cell dielectric layer while melting the underlying silicon to form the heavily-doped n++ emitter contact diffusion regions (after formation of the lightly diffused selective emitter regions by rapid thermal annealing). Step 42 starts with single-crystal p-type silicon. Step 44 involves saw damage removal etch and anisotropic texturing etch in dilute NaOH at 90° C. Step 46 involves spin-on application and drying of phosphorus diffusion source. Step 48 involves rapid thermal annealing to form lightly diffused emitter (80 to 200 Ω/square). Step 50 involves application of backside metal contact by vacuum evaporation or screen printing of aluminum or silver/aluminum alloy, followed by drying. Step 52 involves backside metal sintering/firing (e.g., at 820° C. in oxygen/nitrogen) for a screen-printed contact (fires the metal paste while oxidizing the dielectric to raise its resistance to the metal plating solution). Step 54 involves laser processing to pattern the top dielectric layer while melting the underlying silicon to form the n++ contact diffusion region. Step 56 involves dilute HF etch to prepare metal plating surface. Step 58 involves electroless nickel plating at 90° C. for five minutes. Step 60 involves nickel sintering at 350° C. to 450° C. (in nitrogen, argon, or forming gas). Step 62 involves an additional 2 minutes of nickel plating followed by long electroless copper plating to form thick high-conductivity copper film. Step 64 involves flash immersion silver (silver) deposition on copper surface. Finally, step 66 involves edged junction isolation (e.g., using laser grooving, edge cleavage, or plasma etching).
  • With regard to the prior art crystalline silicon (c-Si) thin-film solar cell (TFSC) technology, there are difficulties associated with sufficient surface texturing of the thin silicon film to reduce surface reflectance losses, while reducing the crystalline silicon film thickness. This places a limit on the minimum flat (co-planar) monocrystalline silicon thickness due to production yield and cell performance (efficiency) considerations. In the case of a flat or co-planar film, it is essential to use surface texturing since the reflectance of an untextured crystalline silicon film is quite excessive (can be greater than 30%) and results in substantial optical reflection losses and degradation of the external quantum efficiency. Thus, reduction of reflectance-induced photon losses in co-planar epitaxial silicon films requires effective surface texturing which itself places a limit on the minimum epitaxial silicon layer thickness. Depending on the film surface texturing requirements and processes, the minimum crystalline silicon layer thickness may be on the order of at least 10 microns (so that the texturing process does not break through any portions of the crystalline silicon layer).
  • In addition, substantially reduced mean optical path lengths in thin planar crystalline silicon films result in reduced photon absorption, particularly for photons with energies near the infrared bandgap of silicon (800 to 1100 nanometers), resulting in reduced solar cell quantum efficiency (reduced short-circuit current or Jsc). This results in serious degradation of the solar cell efficiency due to reduced cell quantum efficiency and reduced Jsc. For instance, in a co-planar (flat) crystalline silicon absorber layer with thickness of 20 microns, a solar light beam impacting the cell at a near-normal angle would have an effective path length equal to the film thickness, far too short for the solar radiation photons with energies near the infrared bandgap of silicon (i.e., with wavelengths of roughly 800 to 1100 nanometers) to be absorbed effectively in the silicon thin film. In fact, a reduction of the active cell silicon thickness to below roughly 50 microns results in appreciable reduction of Jsc and the resulting solar cell efficiency, with this degradation effect rapidly accelerating when the silicon film thickness is reduced below roughly 20 microns. Thus, a co-planar thin crystalline silicon film may also require effective light trapping using both top surface texturing and rear surface back reflection of the light exiting the back surface of the crystalline silicon film in order to create effective optical path lengths equal to a large multiple of the crystalline silicon film thickness.
  • The prior art technologies using this approach mostly use either back reflection through internal reflection of the light at the crystalline silicon film/silicon substrate, or reflection from a blanket backside contact (such as a back surface field aluminum contact/mirror). The back reflectance provided by these techniques may not be great (e.g., roughly 70% effective near-IR rear reflectance), constraining the performance gain that would have otherwise been achieved by an optimal back reflector. The problem with this approach is that the primary incident beam always passes the crystalline silicon film only once. Any subsequent second passes of the primary incident beam photons are dependent on the back surface reflection.
  • There is also the problem of lack of rigidity and mechanical support of the thin film during cell and module processing steps. This problem relates to the mechanical strength of a large-area (e.g., 200 mm×200 mm) thin silicon film. It is well known that reducing the large-area crystalline silicon wafer thickness to below 100 microns results in a substantial loss of TFSC substrate mechanical strength/rigidity, and such thin wafers tend to be flexible and very difficult to handle without breakage during cell fabrication process flow.
  • Large-area, co-planar (flat) crystalline silicon films thinner than, for instance, 50 microns must be properly mounted and supported on a cost-effective support or handle substrate in order to achieve acceptable yield for solar cell and module manufacturing. One approach is to grow and retain the thin epitaxial film on a relatively low-cost (e.g., metallurgical-grade) silicon substrate (over which the epitaxial layer is grown); however, this approach suffers from some inherent problems constraining the ultimate solar cell efficiency. Another approach is to release or lift off the epitaxial silicon film from its (reusable) parent silicon substrate and subsequently place it on a cheaper non-silicon support or handle substrate to provide mechanical strength through the solar cell process flow. This approach may suffer from any thermal coefficient of expansion (TCE) mismatch between the support/handle substrate and silicon film during any high-temperature oxidation and anneal processes, as well as potential contamination of the thin epitaxial silicon film from the non-silicon support substrate (both creating possible manufacturing yield and performance/efficiency degradation problems).
  • The cost of the monocrystalline silicon film growth process using silicon epitaxy, particularly for thicker epitaxial films with thicknesses in excess of 30 microns is an additional issue which should be addressed. Using a relatively small epitaxial film thickness (in one embodiment, much below 30 microns) may lower the cost of epitaxy to an attractive range. However, this would present various challenges for fabrication of planar silicon thin-film solar cells. As stated, thinner co-planar (flat) epitaxial films (e.g., in the range of much less than 30 microns) produce a number of problems and challenges, including a lack of film mechanical strength, constraints limiting effective surface texturing of thin silicon films for low surface reflectance and reduced optical reflectance losses, relatively short optical path lengths, and reduced cell quantum efficiencies. Effective light trapping is essential for enhanced thin-film c-Si solar cell efficiencies. The requirement for effective light trapping is based on a combination of front surface texturing and back surface mirror, while achieving sufficiently low surface recombination velocities (for high cell efficiencies). This is very difficult to achieve in the co-planar (flat) c-Si thin film solar cells.
  • High-performance c-Si thin-film solar cells require some patterning steps or patterned processing steps (e.g., for formation of selective emitter, frontside emitter or backside emitter wrap-through metallization contacts, backside base metallization contacts, etc.). These patterning steps are usually achieved using photolithography, screen printing, and/or shadow-mask deposition (e.g., shadow-mask sputtering or evaporation) processes. The use of photolithography and/or screen printing and/or shadow-mask deposition patterning steps usually increases the manufacturing process flow complexity and cost, and may also detrimentally impact the fabrication yield as well as the ultimate achievable solar cell efficiency.
  • Therefore a need has arisen for a thin-film solar cell (TFSC) which corrects the problems identified above.
  • Yet a further need exists to address shortcomings of existing mainstream c-Si solar cell technology. This includes reducing the amount of polysilicon feedstock consumed per peak watt of solar power, and eliminating the kerf losses associated with sawing and slicing; thus, substantially reducing the overall solar cell manufacturing cost.
  • A further need exists for innovative solar cell structures and simplified process flows, increasing cell and module efficiencies while significantly lowering the overall solar cell and module manufacturing costs. A still further need exists for innovative c-Si solar cell designs and simplified self-aligned manufacturing processes which facilitate substantial solar cell and module cost reduction even in fabs with modest production volumes, enabling low to mid-volume solar cell fabs with modest fab setup and operation costs (thus, achieving economies of scale for manufacturing cost reduction at substantially lower fab volumes than the prior art fabs).
  • A still further need exists to address shortcomings of existing TFSC technology. This includes addressing difficulties associated with sufficient surface texturing of the thin planar silicon films to reduce surface reflectance losses, which currently places a limit on the minimum flat (co-planar) crystalline silicon thickness due to production yield and cell performance considerations. A still further need exists for effective light trapping based on a combination of front surface texturing and back surface mirror, while achieving low surface recombination velocities (for high cell efficiencies).
  • A still further need exists to address additional shortcomings of existing TFSC technologies. This includes the problem of lack of rigidity and mechanical support of the thin film substrate during cell and module processing steps, thus, necessitating the use of support or handle substrates (made of silicon or another material) for the thin-film TFSC substrates.
  • This further includes the cost of the epitaxial silicon film growth process, particularly for thicker epitaxial films required for planar crystalline silicon TFSCs. This further includes the requirement of multiple photolithography and/or screen printing and/or shadow-mask processing/patterning steps which usually increase the manufacturing process flow complexity and cost, and may also detrimentally impact the fabrication yield as well as the ultimate achievable solar cell efficiency.
  • SUMMARY
  • In accordance with the present disclosure, solar module structures utilizing three-dimensional thin-film solar cells (3-D TFSCs) and methods of assembling such solar module structures are provided. The solar module structures of the disclosed subject matter utilizing 3-D TFSCs substantially eliminate or reduce disadvantages and problems associated with previously developed TFSCs, both in terms of efficiency and manufacturing cost.
  • According to one aspect of the disclosed subject matter, there is provided a solar module structure comprising a top protective layer, a plurality of 3-D TFSCs, a printed circuit boar, and a protective back plate. Each 3-D TFSC comprises a 3-D TFSC substrate comprising emitter and base regions, and where the 3-D TFSC substrate comprises a plurality of unit cells.
  • According to another aspect of the disclosed subject matter, there is provided a solar module structure comprising a top glass plate, a plurality of 3-D TFSCs, and a bottom glass plate. Each 3-D TFSC comprises a 3-D TFSC substrate comprising emitter and base regions, and where the 3-D TFSC substrate comprises a plurality of unit cells.
  • According to still another aspect of the disclosed subject matter, there is provided a solar module structure comprising a top protective layer, a plurality of 3-D TFSCs, and a bottom protective layer. Each 3-D TFSC comprises a 3-D TFSC substrate comprising emitter and base regions, and where the 3-D TFSC substrate comprises a plurality of unit cells.
  • According to still another aspect of the disclosed subject matter, there is a provided a solar module structure. The solar module structure comprises a top encapsulant layer, a plurality of 3-D TFSCs, a printed circuit board (PCB), a rear encapsulant layer and a protective back plate. The 3-D TFSC comprises a 3-D TFSC substrate with emitter junction regions doped base regions. The 3-D TFSC further includes emitter metallization regions and base metallization regions. The 3-D TFSC substrate comprises a plurality of single-aperture unit cells.
  • According to still another aspect of the disclosed subject matter, there is a provided a method for assembling a solar module structure. The method includes a first step of patterning a frontside and a backside of a double-sided printed circuit board coated with metallic foils according to desired frontside and backside interconnect layouts. The method includes a next step of applying a first coating layer to the rear side of a plurality of 3-D TFSCs. The 3-D TFSC comprises a 3-D TFSC substrate with emitter junction regions doped base regions. The 3-D TFSC further includes emitter metallization regions and base metallization regions. The 3-D TFSC substrate comprises a plurality of single-aperture unit cells. The method includes a next step of placing the plurality of 3-D TFSCs on the frontside of the double-sided printed circuit board. The method includes a next step of preparing a solar module assembly. The solar module assembly includes a glass layer, a top encapsulant layer, the plurality of 3-D TFSCs on the frontside of the double-sided printed circuit board, a rear encapsulant layer, and a protective back plate. Finally, the method includes sealing and packaging the solar module assembly.
  • According to still another aspect of the disclosed subject matter, there is a provided a solar module structure. The solar module structure comprises a top glass plate, a plurality of 3-D TFSCs, a rear patterned cell interconnect layer, and a bottom glass plate. The 3-D TFSC comprises a 3-D TFSC substrate with emitter junction regions doped base regions. The 3-D TFSC further includes emitter metallization regions and base metallization regions. The 3-D TFSC substrate comprises a plurality of dual-aperture unit cells.
  • According to still another aspect of the disclosed subject matter, there is a provided a method for assembling a solar module structure. The method includes a first step of applying a rear patterned cell interconnect layer to the rear side of a 3-D TFSC. The 3-D TFSC comprises a 3-D TFSC substrate with emitter junction regions doped base regions. The 3-D TFSC further includes emitter metallization regions and base metallization regions. The 3-D TFSC substrate comprises a plurality of dual-aperture unit cells. The method includes a next step of preparing a solar module assembly. The solar module assembly includes a top glass plate, the plurality of 3-D TFSCs with the rear patterned cell interconnect layer applied to the rear side, and a bottom glass plate. Finally, the method includes sealing and packaging the solar module assembly.
  • These and other advantages of the disclosed subject matter, as well as additional novel features, will be apparent from the description provided herein. The intent of this summary is not to be a comprehensive description of the claimed subject matter, but rather to provide a short overview of some of the subject matter's functionality. Other systems, methods, features and advantages here provided will become apparent to one with skill in the art upon examination of the following FIGURES and detailed description. It is intended that all such additional systems, methods, features and advantages be included within this description, be within the scope of the accompanying claims.
  • BRIEF DESCRIPTIONS OF THE DRAWINGS
  • The features, nature, and advantages of the disclosed subject matter may become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout and wherein:
  • FIG. 1 (PRIOR ART) shows a prior art process flow for fabricating crystalline silicon (c-Si) thin-film solar cells (TFSCs) using planar silicon thin-film absorber layers produced by silicon epitaxy;
  • FIG. 2 (PRIOR ART) shows a prior art process flow for fabrication of solar cells on silicon wafers including self-aligned selective emitter and metallization;
  • FIG. 3 (PRIOR ART) summarizes the key process steps eliminated by the current disclosure, compared to the prior art;
  • FIG. 4 summarizes the high-level process flow and the competitive advantages of the current disclosure, compared to the prior art;
  • FIG. 5 provides another summary of the key features and benefits of the current disclosure;
  • FIG. 6 shows a view of series connections of TFSCs in a solar module assembly;
  • FIG. 7 shows a top view of an embodiment of a hexagonal-prism TFSC including a square-shaped hexagonal-prism 3-D TFSC substrate with a planar peripheral silicon frame;
  • FIGS. 8A and 8B show scanning electron microscopic views of two embodiments of a hexagonal-prism 3-D TFSC, without and with a rear base layer, respectively (FIGS. 8A and 8B show the dual-aperture and single-aperture 3-D TFSC substrates, respectively);
  • FIG. 9 provides an overview of the 3-D TFSC substrate and solar cell fabrication process flow;
  • FIG. 10 shows a view of an embodiment of a template including hexagonal prism posts;
  • FIGS. 11A and 11B show magnified scanning views (with two different magnifications) of one embodiment of a template including hexagonal prism posts;
  • FIG. 12 shows a view of an embodiment of a template including staggered (shifted) square prism posts;
  • FIG. 13 shows a view of the frontside metallization pattern of a printed-circuit board (PCB) used for solar module assembly using the TFSCs of the current disclosure;
  • FIGS. 14 and 15 show views of the backside metallization pattern of a PCB used for solar module assembly using the TFSCs of the current disclosure;
  • FIG. 16A shows an enlarged top view of the frontside of a solar module PCB, showing one of the PCB patterned metallization sites for placement of one of the solar cells of the current disclosure;
  • FIG. 16B shows an enlarged top view of the backside of a solar module PCB, showing the series connections of the adjacent cells on the PCB;
  • FIG. 17 shows a cross-sectional view of an embodiment of a solar module structure comprising the TFSCs of the current disclosure and a tempered glass cover;
  • FIG. 18 shows an embodiment of a process flow for fabrication of solar modules using a tempered glass cover;
  • FIG. 19 shows a cross-sectional view of an embodiment of a solar module structure comprising the TFSCs of the current disclosure and a coated layer cover;
  • FIG. 20 shows an embodiment of a process flow for fabrication of solar modules without a tempered glass cover;
  • FIGS. 21 and 22 show cross-sectional views of a solar glass assembly for building façade applications;
  • FIG. 23 shows a view of an electrically conductive layer formed on a glass plate to interconnect cells in series for solar glass applications;
  • FIG. 24 shows an embodiment of a process flow for fabrication of solar modules for solar glass applications;
  • FIG. 25 serves as a reference FIGURE for calculation of TFSC interconnect ohmic losses;
  • FIGS. 26 through 31 show graphs of interconnect (emitter contact metallization) ohmic losses at maximum cell power versus the ratio of emitter contact metal coverage height for various emitter metal sheet resistance values.
  • FIG. 32 outlines an embodiment of a process flow for fabrication of a template using photolithography patterning;
  • FIG. 33 shows a top view of an embodiment of a lithography mask design to produce a hexagonal array (honeycomb) pattern;
  • FIGS. 34 through 37 outline various embodiments of process flows for fabrication of a template using either direct laser micromachining or photolithography patterning;
  • FIG. 38 shows the Y-Y and Z-Z cross-sectional axes on an embodiment of a hexagonal-prism (honeycomb) 3-D TFSC substrate;
  • FIGS. 39 and 40 show Y-Y cross-sectional views of an embodiment of a template including through-wafer and within-wafer trenches, respectively;
  • FIGS. 41 through 47 show Y-Y cross-sectional views of a silicon substrate during the fabrication process flow for making an embodiment of a template based on the process flows of FIG. 36 or FIG. 37;
  • FIGS. 48 through 52 show Y-Y cross-sectional views of alternative embodiments of templates;
  • FIGS. 53 and 54 show embodiments of mask designs for patterning a semiconductor (silicon) wafer rear to produce backside openings on a template;
  • FIG. 55 shows an alternative frontside lithography mask with an array of hexagonal array openings for formation of template trenches and an array of holes for formation of an array of release channels from the template backside to the template frontside;
  • FIG. 56 shows the frontside patterning mask in FIG. 55 with a backside square array pattern (to be used for backside patterning with relative alignment as shown to the frontside pattern) superimposed for reference;
  • FIG. 57 shows the backside lithography mask pattern (square array) in FIG. 56 with the frontside mask hexagonal array pattern from FIG. 55 superimposed for reference;
  • FIGS. 58 through 66 show Y-Y cross-sectional views of a semiconductor (silicon) substrate during the fabrication process flow for making an embodiment of a template based on the process flows of FIG. 36 or FIG. 37;
  • FIGS. 67 through 75 show Y-Y cross-sectional views of a silicon substrate during the fabrication process flow for making an embodiment of a template based on the process flows of FIG. 36 or FIG. 37;
  • FIG. 76 and FIGS. 79 through 86 show Y-Y cross-sectional views of a semiconductor (e.g., silicon) substrate during the fabrication process flow for making an embodiment of a template based on the process flows of FIG. 36 or FIG. 37;
  • FIGS. 77 and 78 show backside lithography mask designs; FIG. 78 shows the relative alignment of the backside square array pattern with respect to the frontside hexagonal array pattern whereas FIG. 77 shows the backside square array pattern used for formation of chemical release channels on the template.
  • FIGS. 87 and 88 show cross-sectional views of stacked template structures for concurrently fabricating and releasing two hexagonal-prism 3-D TFSC substrates per process pass (FIGS. 87 and 88 show the stacked templates with within-wafer trenches and through-wafer trenches, respectively);
  • FIGS. 89A through 95C show examples of several embodiments of 3-D polygon-prism TFSC substrates including various prism unit cell geometrical designs and arrangements;
  • FIG. 96 shows an embodiment of a process flow for fabrication of self-supporting hexagonal prism 3-D TFSC substrates using layer release processing;
  • FIGS. 97 through 102 show alternative embodiments of process flows for fabrication of self-supporting hexagonal-prism (as well as other prism array patterns) 3-D TFSC substrates without rear base layers (to form dual-aperture 3-D TFSC substrates; i.e., 3-D TFSC substrates with top and bottom unit cell openings);
  • FIGS. 103 through 107 show Y-Y cross-sectional views of the evolution of one prism unit cell of a template with through-wafer trenches, as it goes through several key process steps for fabricating a hexagonal-prism 3-D TFSC substrate (dual-aperture 3-D TFSC substrate) without a rear base layer;
  • FIGS. 108 through 111 illustrate Y-Y cross-sectional views of an embodiment of a template with within-wafer trenches and no dielectric layers on the template frontside or template backside, as it goes through several key process steps for fabricating a hexagonal-prism 3-D TFSC substrate (dual-aperture 3-D TFSC substrate) without a rear base layer;
  • FIGS. 112 through 115 illustrate Y-Y cross-sectional views of an embodiment of a template with through-wafer trenches and no dielectrics on the template frontside, as it goes through several key process steps for fabricating a hexagonal-prism 3-D TFSC substrate (dual-aperture 3-D TFSC substrate) without a rear base layer;
  • FIGS. 116 and 117 show alternative embodiments of a process flows for fabrication of self-supporting hexagonal prism 3-D TFSC substrates including rear base layers (single-aperture 3-D TFSC substrates with single-aperture unit cells);
  • FIGS. 118 through 122 illustrate Y-Y cross-sectional views of a template with within-wafer trenches and no dielectrics on the template frontside, as it goes through the key process steps to fabricate a hexagonal prism 3-D TFSC substrate (single-aperture 3-D TFSC substrate) with a rear base layer; FIGS. 121 and 122 show the released 3-D TFSC substrate with a base layer and the reusable template after the 3-D TFSC substrate release, respectively.
  • FIGS. 123 through 125 illustrate Y-Y cross-sectional views of the template in FIG. 66 with the rear-to-front release channels, as it goes through the key process steps to fabricate a hexagonal-prism 3-D TFSC substrate (single-aperture 3-D TFSC substrate) with a rear base layer (template is made on <100> silicon substrate);
  • FIGS. 126 through 128 illustrate Y-Y cross-sectional views of the template in FIG. 75 with the rear-to-front release channels, as it goes through the key process steps to fabricate a hexagonal-prism 3-D TFSC substrate (single-aperture TFSC substrate) with a rear base layer (template is made on <110> silicon substrate);
  • FIGS. 129 through 131 illustrate Y-Y cross-sectional views of the template in FIG. 86 with backside release channels aligned to the bottom of hexagonal-prism trenches, as it goes through the key process steps to fabricate a hexagonal-prism 3-D TFSC substrate with a rear base layer (single-aperture 3-D TFSC substrate);
  • FIG. 132 shows a 3-D cross-sectional view of an embodiment of a single-aperture hexagonal-prism 3-D TFSC substrate (i.e., 3-D TFSC substrate with an integral base layer), including the substrate rear monolithically (integrally) connected to a substantially flat planar thin semiconductor film;
  • FIG. 133 shows a top view of an embodiment of a regular (equilateral) hexagonal-prism 3-D TFSC substrate;
  • FIG. 134A shows a Y-Y cross-sectional view of an embodiment of a single aperture hexagonal prism 3-D TFSC substrate, while FIG. 134B shows a Z-Z cross-sectional view;
  • FIGS. 135 through 140 show alternative process flow embodiments for fabricating hexagonal-prism 3-D TFSCs using single-aperture 3-D TFSC substrates including rear base layers;
  • FIG. 141 shows multiple adjacent hexagonal-prism unit cells, after completion of the TFSC fabrication process and after mounting the cell rear base side onto a rear mirror;
  • FIGS. 142A through 144A show Y-Y cross-sectional views of a unit cell within an embodiment of a single-aperture hexagonal-prism 3-D TFSC substrate including a rear base layer;
  • FIGS. 144B through 148 show Y-Y cross-sectional views of an embodiment of a single-aperture hexagonal-prism 3-D TFSC substrate including a rear base layer, and including either a detached or an integrated rear mirror;
  • FIG. 149 shows a schematic view of a double-sided coater setup for self-aligned application (coating) of dopant liquid or paste layers on 3-D TFSC substrate hexagonal-prism top ridges and hexagonal-prism rear surface or ridges by roller coating and in-line curing of the applied liquid/paste layers (shown in conjunction with an integrated belt-driven process equipment);
  • FIG. 150 shows a view of an alternative spray coater and curing setup to perform the same processes as the roller coater and curing setup of FIG. 149;
  • FIG. 151 shows a view of another alternative setup design using liquid-dip coating or liquid-transfer coating to perform the same processes as the roller coater and curing setup of FIG. 149 and the spray coater and curing setup of FIG. 150;
  • FIG. 152 shows a 3-D view of an embodiment of a hexagonal-prism 3-D thin-film semiconductor substrate after release and removal from a template;
  • FIG. 153A shows a schematic Y-Y cross-sectional view of an embodiment of a dual-aperture hexagonal-prism 3-D TFSC substrate, while FIG. 153B shows a Z-Z cross-sectional view of the same substrate;
  • FIGS. 154 through 159 show alternative process flow embodiments for fabricating hexagonal-prism 3-D TFSCs using dual-aperture 3-D TFSC substrates without rear base layers;
  • FIG. 160A shows a schematic Y-Y cross-sectional view of an embodiment of a self-supporting (free-standing) hexagonal-prism dual-aperture 3-D TFSC substrate (without a base layer) including a thin peripheral semiconductor (silicon) frame, before 3-D TFSC fabrication;
  • FIG. 160B shows a schematic Y-Y cross-sectional view of the 3-D TFSC substrate of FIG. 160A after TFSC fabrication;
  • FIG. 161A shows a schematic Y-Y cross-sectional view of an embodiment of a self-supporting (free-standing) hexagonal-prism dual-aperture 3-D TFSC substrate including a thick peripheral semiconductor (silicon) frame, before TFSC fabrication;
  • FIG. 161B shows a schematic Y-Y cross-sectional view of the 3-D TFSC substrate of FIG. 161A after cell fabrication;
  • FIGS. 162A through 163B show schematic Y-Y cross-sectional views of a single unit cell from a dual-aperture 3-D TFSC substrate within an embodiment of a hexagonal-prism 3-D TFSC fabricated using a 3-D TFSC substrate without a rear base layer;
  • FIGS. 164A and 164B show Y-Y cross-sectional views of a single unit cell from a dual-aperture 3-D TFSC substrate after mounting the cell onto a rear mirror;
  • FIGS. 165A through 166 show Y-Y cross-sectional views of multiple unit cells from a dual-aperture 3-D TFSC substrate, after mounting onto a rear mirror (with and without a spacing between the mirror and the rear cell);
  • FIGS. 167A through 171 show schematic Y-Y cross-sectional views of an embodiment of a hexagonal-prism 3-D TFSC formed on a dual-aperture 3-D TFSC substrate without a rear base layer, with substantially vertical hexagonal-prism sidewalls;
  • FIGS. 172A and 172B show 3-D views of a single unit cell in a dual-aperture hexagonal-prism 3-D TFSC substrate, before and after self-aligned base and emitter contact metallization, respectively;
  • FIG. 173 shows multiple adjacent hexagonal-prism unit cells, after completion of the TFSC fabrication process and after mounting the cell rear base side onto a rear mirror;
  • FIG. 174 shows a schematic view of a single unit cell from an embodiment of a hexagonal-prism 3-D TFSC substrate for reference including certain 3-D TFSC substrate calculations;
  • FIG. 175 shows a graph of the computed 3-D TFSC substrate hexagonal-prism area ratio (ratio of 3-D cell surface area to the flat cell base area) versus hexagonal-prism aspect ratio (unit cell height to aperture diameter ratio);
  • FIG. 176 shows a graph of the ratio of the hexagonal-prism 3-D TFSC substrate mass to a reference flat semiconductor wafer mass for both types of 3-D honeycomb-prism TFSC substrates (single and dual aperture substrates), versus various ratio of the honeycomb-prism sidewall silicon thickness to the reference flat silicon wafer thickness;
  • FIG. 177 shows a schematic diagram of ray tracing for solar rays incident on a dual-aperture hexagonal-prism unit cell employing reflective emitter metallization contact;
  • FIGS. 178 through 181 show various numbers of solar light rays incident at various angles of incidence, demonstrating efficient light trapping characteristics of the current disclosure;
  • FIG. 182 shows simulated light trapping in a unit cell and short circuit current density versus angle of incidence for various emitter contact metallization embodiments of the solar cell designs of the current disclosure;
  • FIG. 183 shows Standard Test Condition (STC) cell efficiency and short-circuit current density for the solar cell of the current disclosure versus unit cell prism height;
  • FIG. 184 shows maximum photocurrent density versus incident angle, also indicating the effect of emitter contact metallization (assuming 100% optical reflectance for emitter contact metal);
  • FIG. 185 shows a graph of the representative selective emitter phosphorus and 3-D TFSC substrate boron doping profiles in hexagonal-prism 3-D TFSCs of this disclosure, shown with graded boron doping profile to create a built-in electric field;
  • FIG. 186 serves as a reference FIGURE for calculation of the hexagonal-prism TFSC internal ohmic losses due to the base current along the hexagonal-prism vertical sidewalls;
  • FIG. 187 shows maximum base resistivity and approximate p-type base doping concentration values for various 3-D honeycomb-prism sidewall film thicknesses in order to limit the base current ohmic losses to less than 0.1%; and
  • FIG. 188 shows various views of silicon frames and silicon frame slivers for the hexagonal-prism TFSCs of the current invention.
  • DETAILED DESCRIPTION OF THE SPECIFIC EMBODIMENTS
  • Preferred embodiments of the present disclosure are illustrated in the drawings, like numbers being used to refer to like and corresponding parts of the various drawings. The innovative solar cell designs and technologies of the current disclosure are based on the use of a three-dimensional (3-D), self-supporting, doped (in one embodiment, in-situ-doped) semiconductor thin film, deposited on and released from a reusable crystalline (embodiments include monocrystalline or multicrystalline silicon) semiconductor template.
  • A preferred semiconductor material for the 3-D TFSC substrate is crystalline silicon (c-Si), although other semiconductor materials may also be used. One embodiment uses monocrystalline silicon as the thin film semiconductor material. Other embodiments use multicrystalline silicon, polycrystalline silicon, microcrystalline silicon, amorphous silicon, porous silicon, and/or a combination thereof. The designs here are also applicable to other semiconductor materials such as germanium, silicon germanium, silicon carbide, a crystalline compound semiconductor, or a combination thereof. Additional applications include copper indium gallium selenide (CIGS) and cadmium telluride semiconductor thin films.
  • The 3-D TFSC designs and production technologies as well as associated module structures and assembly approaches of this disclosure effectively overcome the above-mentioned problems and challenges and enable cost-reduced fabrication of very-high-efficiency solar cells and modules using self-aligned cell process flows without the use of any photolithography patterning or screen printing or shadow-mask deposition process steps during cell fabrication (i.e., during 3-D TFSC substrate and cell fabrication after fabrication of the reusable 3-D template). The 3-D TFSC technologies of this disclosure are based on the formation of a 3-D prism-array thin-film TFSC substrate structure on a low-cost reusable template and its subsequent release and lift-off from the template to form a free-standing, self-supporting 3-D thin-film semiconductor substrate structure.
  • The current disclosure combines the benefits of TFSC fabrication on a proven high-efficiency crystalline silicon (c-Si) platform. The 3-D c-Si TFSC designs and technologies of this disclosure enable significant advancements in the areas of c-Si solar cell and module efficiency enhancement as well as manufacturing cost reduction. Based on innovative thin-film process steps, dependence on an expensive and constrained silicon wafer supply-chain is eliminated. Some of the unique advantages of the cells designs and technologies of this disclosure which enable achieving ultra-high-efficiency at reduced manufacturing cost are substantial decoupling from the traditional solar PV silicon supply chain, performance enhancement, cost reduction, and reliability improvement.
  • The disclosed subject matter improves solar cell efficiency by using a 3-D c-Si film as an absorber layer in conjunction with highly efficient light trapping. Use of the crystalline silicon absorber layer leverages known solar cell manufacturing techniques and supply chain, while reducing absorber layer thickness (e.g., reduced by a factor of ten or more compared to silicon wafers used for wafer-based solar cells). The disclosed method and system eliminates or substantially reduces photo-degradation and enhances open-circuit voltage (Voc) of cells. In addition, the disclosed method and system provides efficient frontside and rear side light-trapping in conjunction with a highly reflective rear mirror for maximum absorption of incident solar flux. Also, the disclosed method and system provides a selective emitter to enhance blue response and external quantum efficiency, with minimal shadowing of the cell and reduced ohmic losses due to a unique folded emitter metallization contact design and improved module assembly.
  • Manufacturing cost is reduced by decreasing silicon usage (by a significant factor, e.g., 3× to over 10×), with thinner deposited c-Si films also reducing the finished solar module energy payback time to less than 1 to 2 years. Manufacturing cost is further reduced by eliminating wire sawing and related kerf losses associated with mainstream solar cell wafer manufacturing technology. Manufacturing cost is still further reduced by using self-aligned processing without any lithography or patterning steps used during the substrate and cell fabrication process flow, and a reduced number of fabrication process steps, with improved yield and cycle time. Production cost is still further reduced by using a simplified interconnection and cell-module assembly process and lightweight monolithic modules.
  • Operational reliability is improved by using thinner silicon films, eliminating photo-degradation and reducing temperature coefficients. Operational reliability is further improved by using a simple distributed high-conductance electrical interconnection, minimizing field failures. Operational reliability is still further improved by eliminating module glass cover (for glassless module assembly), thus reducing cost and facilitating field installation and operation. Operational reliability is still further improved by reducing the number of manufacturing process steps and process variations using in-line manufacturing process control.
  • The current disclosure reduces the solar module cost per watt for the user (by at least 30% to 50%) and cuts balance-of-system (BOS) and installation costs for the integrators and installers. This may offer major benefits to the global grid-tied end-users and solar system installers and integrators. The current disclosure reduces the module integration and installation cost and installed solar cell system cost per Wp for the user, thereby lowering finished system cost per Wp. The current disclosure increases module efficiency, with higher module efficiency resulting in lower BOS cost. The lower installed solar cell system cost results in reduction of the economic break-even time to a lower fraction of the system lifetime, from roughly ½ to ⅓ for current best-of-breed c-Si solar cell systems to less than ¼ to ⅛ for the embodiments of this disclosure. The current disclosure reduces energy payback time (EPBT) from 3 to 7 years for best-of-breed c-Si solar cell systems to less than 1 to 2 years for the embodiments of this disclosure. Reduced EPBT substantially increases the net lifetime energy output (in kWh) for field-installed modules. The cell designs and module assemblies of this disclosure also provide stable degradation-free field operation over an extended time (e.g., 30 to 40 year life of the module), further increasing the net lifetime electrical energy output. Module manufacturing costs are expected to be 30% to 65% lower than that of the leading high-performance c-Si solar cells/modules at the time of market entry. This may shorten the ROI break-even time for the users compared to the current industry roadmap and projections. Further benefits include increased field performance stability and reliability and reduced environmental impact (non-toxic materials and shortened EPBT). Further, the cell and module designs of this disclosure are ideal for grid-tied applications where it is advantageous to maximize electricity generation from a limited building rooftop or façade area.
  • The absorber silicon film thickness of the current disclosure may be a value in the range of roughly 1 to 30 microns, where a thinner silicon layer is preferred for less material consumption (in one embodiment, in the range of 1 to 10 microns). Even after taking into account the effective surface area increase due to the 3-D geometric structure of the 3-D TFSC substrates, the 3-D TFSC substrates of this disclosure consume substantially less silicon material than the state-of-the-art wafer-based c-Si solar cells. Moreover, there are no sawing or kerf losses. Similarly, there is no requirement for saw damage removal since the 3-D crystalline silicon film is process-ready upon release from the reusable template. This substantially reduces the solar cell cost associated with silicon consumption. The self-supporting 3-D epitaxial silicon thin film is deposited on and released from a low-cost reusable crystalline (monocrystalline or multicrystalline) silicon substrate (template). The template may be reused numerous times before being reconditioned or recycled. The template may even be chosen from the much lower cost metallurgical-grade c-Si since any metallic impurities are prevented from contaminating the 3-D crystalline silicon film.
  • FIG. 3 summarizes the overall crystalline solar cell fabrication process flow of prior art techniques and highlights the specific steps eliminated by the current disclosure, compared to the prior art. FIG. 4 summarizes the overall cell and module fabrication process flow and the competitive advantages of the current disclosure, compared to the prior art. As highlighted here, the current disclosure enables fabrication of 3-D thin-film solar TFSC substrates and cells, thus, substantially reducing consumption of semiconductor absorber material (e.g., silicon) and the cell and module manufacturing costs. FIG. 5 provides another summary of the benefits of the embodiments of the current disclosure.
  • In the next section, various embodiments of this disclosure for making solar modules suitable for building rooftops and façades, centralized power generation, and other applications are described. Usually solar modules are made by arranging a plurality of solar cells and connecting them in series (series electrical connections) within a solar module assembly protected by a top glass layer and a rear protective material layer such as Tedlar. The cells may be connected in series in order to step up the DC voltage (while maintaining the solar module current at the same level at the level of the cell current) to facilitate high-efficiency DC-to-AC power conversion.
  • FIG. 6 shows a view of a representative example of series connections of TFSCs of this disclosure in a solar module assembly 100. This example shows 24 squared-shaped cells 102 connected in series (in a 6×4 array). The electrical connections in series are shown by arrows between the adjacent cells connected in series. Module power input and output leads 104 are also shown. In actual module assemblies, the numbers of cells may be smaller or larger and the cells may be connected in series or in a combination of series and parallel. As mentioned earlier, series connection of the cells within the module assembly allows for stepping up the DC voltage for the DC-to-AC inverter (and also limiting the DC current of the solar modules for ease of module installation in the field and reliability of the module-to-module electrical connections). The printed-circuit-board (PCB) based module assembly of this disclosure supports any number of cells assembled in a module and any electrical connection configuration (series, series/parallel combination, or parallel). The TFSCs and modules of this disclosure may provide relatively lightweight solar modules with areas from less than 1 m2 to several m2 (e.g., 10 m2) for various applications. The cells connected in series within a module assembly are chosen based on sorting to be matched in terms of their photogenerated current (e.g., short-circuit current Isc and/or maximum-power current Im).
  • FIG. 7 shows a top view 110 of a hexagonal-prism 3-D TFSC with a peripheral planar silicon frame 112 for use in the above solar module assembly 100, shown in FIG. 6. The top surface of the frame 112 may also be used as the top 3-D TFSC interconnect and may be used to produce a wrap-through or wrap-around emitter metallization for making contacts to the cell emitter at the bottom of the cell (in module assembly). The frame 112 is metallized, along with the top hexagonal emitter contacts, and is electrically connected to the hexagonal emitter contacts. The frame 112 may have the same thickness as the 3-D TFSC substrate or may be much thicker. In one embodiment, frame width 114 is between 5 and 500 microns. The hexagonal prism 3-D TFSC substrate is composed of hexagonal-prism unit cells 116. In one embodiment, the width 118 of the silicon film forming the sidewalls of the hexagonal prism unit cell is preferably 2 to 30 microns, and more preferably 2 to 10 microns. Typically, there are thousands to millions of hexagonal-prism unit cells 116 on a large-area 3-D TFSC. In one embodiment, frame length (S) 120 ranges from 125 to over 200 millimeters (e.g., 210 mm×210 mm). The hexagonal-prism 3-D TFSC substrates of this disclosure may have a thin silicon frame, a thick silicon frame, or no peripheral frame at all.
  • FIGS. 8A and 8B show microscopic views of 3-D thin-film TFSC substrates of a 3-D TFSC as illustrated in FIG. 7. FIG. 8A shows a view of a dual-aperture TFSC substrate without a base layer whereas FIG. 8B shows a view of a single-aperture TFSC substrate with a base layer.
  • FIG. 9 provides an overview of the 3-D TFSC substrate and cell fabrication process flow. Focusing on the top of FIG. 9 illustrating the 3-D TFSC substrate fabrication, note that the first step in this process flow uses a pre-fabricated template. The template with a pre-fabricated 3-D trench or groove pattern may be used for formation of 3-D TFSC substrates, which are then used in the formation of 3-D TFSCs, substantially eliminating or reducing disadvantages and problems associated with previously developed TFSCs and the wafer-based crystalline silicon cell technologies. The template is capable of being used numerous times (e.g., tens to hundreds of times) to fabricate numerous 3-D TFSC substrates before being reconditioned or recycled. In one embodiment, the template may be used hundreds of times to fabricate 3-D TFSC substrates before being recycled. The template may be reused for as long as it remains relatively free of dislocations and/or for as long as it maintains an acceptable trench or groove pattern with widths and surface conditions within acceptable control limits (e.g., as gauged by in-line metrology).
  • FIG. 10 shows a view 130 of a template with hexagonal-prism posts (pillars) 132. A hexagonal-prism 3-D thin-film TFSC substrate (not shown) is fabricated by first forming a suitable relatively conformal thin sacrificial layer (in one embodiment, porous silicon) on the template, then filling in the relatively deep trenches 134 between hexagonal-prism posts 132, and subsequently releasing the hexagonal prism 3-D TFSC substrate by selectively etching the sacrificial layer (not shown) deposited between the hexagonal-prism 3-D TFSC substrate and the template. In one embodiment, the template has deep interconnected hexagonal-prism trenches with slightly tapered sidewalls (i.e., larger trench widths near the top of the trenched compared to near the bottom of the trenches. Moreover, the trench widths near the top of the trenches may be made about one to several microns larger than the trench widths near the bottom of the trenches. FIGS. 11A and 11B show magnified views of one embodiment of a template with hexagonal-prism posts 132 and trenches 134. This embodiment was prepared using photolithography and deep reactive-ion etching (DRIE).
  • Note that the terms “honeycomb” and “hexagonal” are used interchangeably throughout this disclosure. The term “honeycomb” refers to the fact that embodiments of the 3-D TFSC substrates resemble a natural honeycomb.
  • FIG. 12 shows a view 140 of an alternative embodiment of a template (or master stencil) with staggered square prism posts 142. A square-prism 3-D TFSC substrate (not shown) is formed by first depositing or forming a relatively conformal sacrificial layer (e.g., porous silicon), filling in the trenches 144 between square prism posts 142, and subsequently releasing the 3-D TFSC substrate by selectively etching the sacrificial layer formed between the 3-D TFSC substrate and the template.
  • In the next section, various embodiments of this disclosure for making solar modules suitable for building rooftops and façades, centralized power generation, and other applications are described. Usually solar modules are made by arranging a plurality of solar cells and connecting them in series (series electrical connections) within a solar module assembly protected by a top glass layer and a rear protective material layer such as Tedlar. The cells may be connected in series in order to step up the DC voltage (while maintaining the solar module current at the same level at the level of the cell current) to facilitate high-efficiency DC-to-AC power conversion.
  • The solar module structures and assembly methods of this disclosure are based on the use of a printed-circuit board (PCB) to assemble the hexagonal prism 3-D TFSCs in a closely packed array and to connect the cells (in one embodiment in series) using the PCB plate within a module assembly. The PCB plate may have a single patterned metal (in one embodiment, copper) interconnect layer on the top of the PCB or two patterned copper layers on the top and rear surfaces of the PCB plate. FIG. 13 shows a view 150 of the frontside silver-coated copper layout of the printed-circuit board (PCB) used for solar module assembly (the square islands serve both as rear mirrors (if no integrated mirror is used with single-aperture cells, or if the cells are dual-aperture cells without base layers) and base interconnects; the peripheral square-shaped copper bands connect to the wrap-around emitter contact at the TFSC peripheral frame rear side; copper-filled via plugs connecting select regions of the PCB frontside and backside are shown as small circles). This example is shown for an array of 24 TFSCs arranged in 4 rows of 6 cells in each row (the PCB may be designed for any number and various arrangements of TFSCs). The PCB conductor (copper or aluminum) thickness may be in the range of roughly 10 to over 100 microns to provide high electrical and thermal conductivities. The PCB also serves as an effective heat sink to minimize temperature cycling of the TFSCs in operation. The PCB material may be selected to be a lightweight, high-strength material (such as carbon composite materials used in aerospace industry), or even a relatively thin flexible material. The larger-area square-shaped silver-coated copper regions 152 are connected to the TFSC rear base regions (bottoms of the rear base layers for the single-aperture cells or the bottom ridges of the dual-aperture cells for the dual-aperture cells). The peripheral silver-coated copper lines 154 are electrically connected to the TFSC emitter contact metallization regions.
  • FIG. 14 shows a top view 160 of the backside (optionally silver-coated) copper layout of the printed-circuit board (PCB) used for solar module assembly, showing the series connection of the TFSCs. The PCB backside may also include thin-film shunt diodes for shade protection of the TFSCs (as shown in FIG. 15). The copper-filled via plugs (shown as circles) connect the PCB frontside and backside metallization patterns in the corresponding areas. While the example shown here is for connecting 24 TFSCs in series on a solar panel, similar PCB design methodology may be applied to configure and connect any number of cells in any desired arrangements on the module. The frontside view of this PCB is shown in FIG. 13. This example is shown for an array of 24 TFSCs arranged in 4 rows of 6 cells in each row (the PCB may be designed for any number and various arrangements of TFSCs), all connected in series. The PCB conductor (copper or aluminum) thickness may be in the range of roughly 10 to over 100 microns to provide high electrical and thermal conductivities. The PCB also serves as an effective heat sink to minimize temperature cycling of the TFSCs in operation. The PCB material may be selected to be a lightweight, high-strength material (such as suitable carbon composite materials used in aerospace industry). FIG. 14 also shows power Output Lead 162 (first cell's p-lead) and power output lead 164 (last cell's n-lead).
  • FIG. 15 shows a backside view 170 of the copper pattern on the PCB and is essentially similar to FIG. 14. This picture also shows the use of protective thin-film shunt diodes mounted on the PCB backside pattern (for cell shadow protection).
  • FIG. 16A shows an enlarged top view 180 of the silver-coated copper pattern (the pad for mounting one cell) on the frontside of the solar module printed-circuit board (PCB) used for rear mirror and also emitter and base interconnects for one of the TFSCs (relative dimensions are not shown to scale). FIG. 16A shows dimensions of L1 182 and L2 184 (in one embodiment, 150 millimeters to greater than 200 millimeters, where L2=L1+2(W+S)). S 186 may be on the order of 25 to 250 microns. The width of the peripheral copper conductor band (W) 188 may be on the order of 50 to 500 microns. The copper-filled via plugs 190 are shown as circles (connecting the interconnect patterns on the PCB frontside and backside in a pre-designed arrangement in order to connect the TFSCs in series or in any other desired arrangement such as series/parallel; the representative example shown here is for connecting all the cells in series in order to step up the module open-circuit voltage). The via plug 190 diameters may be on the order of roughly 50 to 500 microns (and may be smaller than W 188). The large central square pad serves both as the rear cell mirror (for dual-aperture cells or single-aperture cells without integrated rear mirrors) and also base interconnect plane (connecting to the hexagonal-prism base contact metallization). The number of vias in the center square (p-region contact) (N) 192 may be on the order of hundreds to thousands. The number of vias in the peripheral line (n-region contact) (M) 194 may be on the order of tens to hundreds (or even thousands). The vias on the peripheral line contacting the TFSC emitter (n) regions are placed on three sides. The PCB conductor (copper or aluminum) thickness may be in the range of roughly 10 to over 100 microns to provide high electrical and thermal conductivities. The PCB plate also serves as an effective heat sink to minimize temperature cycling of the TFSCs in field operation. This FIGURE shows one of the copper interconnect/mirror pads shown in the full module PCB array of FIG. 13.
  • FIG. 16B shows an enlarged top view 200 of the silver-coated copper interconnect pattern on the backside of the solar module printed-circuit board (PCB) used for emitter and base electrical interconnects for a couple of adjacent TFSCs of this disclosure (a portion of the PCB view). FIG. 16B shows the PCB backside silver-coated copper interconnect pattern for TFSCs 1 and 2 in the array. The copper pattern here is shown for connecting the TFSCs in series to step up the module open-circuit voltage. FIG. 16B shows dimensions of L1202; peripheral emitter (n-region) connector linewidth W′ 204 (in one embodiment, 2 to 10 millimeters); spacing between the center base (p-region) connector plate and the peripheral emitter (n-region) connector line S′ 206 (in one embodiment, 100 microns to 1 millimeter). Note that L1202 is less than L1 from FIG. 16A by roughly 2 to 10 millimeters. This enables larger peripheral emitter (n-region) connector linewidth and substantially reduced ohmic losses on the PCB backside.
  • The PCB assembly described above may be used to create the final solar module assembly in a number of ways (with or without a frame, with or without top tempered glass, etc.).
  • FIG. 17 shows a cross-sectional view 210 of a solar module (solar panel) structure with a protective back plate 212 made of a proven prior art material (e.g., Tedlar or polyvinyl fluoride film); a rear encapsulant layer 214 (EVA), a 2-sided printed-circuit board (PCB) 216 of this disclosure with rear patterned electrical interconnects 218 and top patterned electrical interconnects 220; cell rear mirrors (if applicable for instance, for single-aperture cells with integrated rear mirrors) and TFSCs 222 with rear base and wrap-around (or wrap-through) emitter contacts mounted on the frontside of the PCB, a top encapsulate layer (EVA) 224, and an anti-reflection-coated (ARC) tempered glass (in one embodiment, textured tempered glass) 226 (from rear to top), with greater than 98% transmission, with sputtered or sprayed or liquid-coated anti-reflection coating). This module structure may be assembled as a hermetically sealed package either as a frameless module or with a frame (e.g., made of aluminum). In one embodiment, the module assembly is a frameless assembly (also for reduced materials energy content and reduced energy payback time).
  • FIG. 18 illustrates a first embodiment of a process flow 230 for fabrication of solar modules with top protective glass plates and embedded PCBs of this disclosure (corresponding to the solar module structure of FIG. 17 with a PCB and a TFSC mounted on the PCB). This manufacturing flow is compatible with a fully automated module assembly line. This module assembly flow is based on the use of a double-sided printed-circuit board (PCB) with the cell rear mirrors/base interconnects on the PCB topside (silver-coated patterned copper on the PCB topside). For hexagonal-prism 3-D TFSCs with rear base layers and integrated/embedded (or attached) rear mirrors fabricated prior to module assembly (e.g., hexagonal-prism cells with rear base layers and thin-film rear mirrors deposited on the rear surfaces of the rear base layers using PVD or plating or roller coating/spray coating and curing), the patterned PCB copper layer does not have to be coated with a high-reflectivity mirror material (silver). In step 232, module assembly starts with a double-sided PCB coated with copper foils on both frontside and backside. The PCB area should support the desired number/layout of TFSCs (e.g., 1 m2, with a copper foil thickness on each side of roughly 10 to over 100 microns). Step 234 involves PCB interconnect patterning and silver flash coating (the latter if needed for PCB rear mirror). The PCB frontside and backside copper foils are patterned according to the desired frontside and backside interconnect layouts. Copper patterns are flash coated with a thin layer of highly reflective silver (and/or aluminum). A highly reflective diffuse mirror may be used, though a specular mirror may also be used. Step 236 involves cell preparation for automated TFSC placement and soldering. The rear hexagonal metallized side of the TFSCs is roller coated (or spray coated or dip coated) with lead-free solder or an electrically conductive and thermally-conductive epoxy paste. For cells fabricated using a honeycomb-prism TFSC substrate without a rear flat silicon base layer, the rear metallized hexagonal-prism ridges are coated to a vertical height of roughly 2 to 20 microns depending on the hexagonal prism unit cell dimensions. For single-aperture cells fabricated using honeycomb prism TFSC substrates with a rear flat silicon base layer, only the hexagonal base interconnect ridges are coated. For single-aperture cells fabricated using honeycomb prism TFSC substrates with a rear flat silicon base layer and an integrated rear base mirror, the coating may cover the entire rear base mirror bottom surface if desired. Step 238 involves automated TFSC placement and soldering (or curing of epoxy). TFSCs are automatically picked and placed in a closely-packed array on the frontside of the PCB. The rear side of each cell sits on its designated site on the frontside of the double-sided PCB with patterned copper interconnects. The TFSC rear hexagonal prism base interconnect is soldered to the PCB frontside silver-coated patterned copper islands using thermal or ultrasonic soldering. In case of using epoxy instead of solder, the epoxy layer is cured using thermal and/or IR/UV curing. The protective thin-film shunt diodes are mounted and soldered (or epoxied) on the PCB backside. An optional step is to flash coat the metal regions with a thin layer of highly reflective silver. Step 240 involves final solar module assembly and lamination. A stack of low-reflection tempered (in one embodiment, also textured) top glass, an encapsulant layer, the cell-mounted PCB, another encapsulant layer and a Tedlar or polyvinyl fluoride back sheet is prepared. Next, the module stack assembly is hermetically sealed and packaged, for instance, using vacuum-pressure lamination.
  • FIG. 19 shows a cross-sectional view 240 of another embodiment of a solar module structure. Instead of a top encapsulate layer (EVA) 224, and an anti-reflection-coated (ARC) tempered glass 226, as shown in FIG. 17, there is a single frontside protective layer and anti-reflective coating layer 242. The frontside protective layer and anti-reflective coating (ARC) layer 242 is formed by liquid spray coating/curing, liquid roller coating/curing, liquid-dip coating/curing, plasma spray coating, or another suitable low-temperature coating technique. This frontside protective coating and ARC layer 242 is effectively textured for the coating layer as deposited as a result of the 3-D structure of the TFSCs (thus, no separate texturing process is needed). This is due to the fact that the coating layer may have dips (low points) over the TFSC hexagonal-prism cavities and peaks (high points) over the hexagonal-prism emitter ridges. The frontside protective layer and anti-reflective coating layer 242 may have a combined thickness in the range of tens to hundreds of microns. In one embodiment, the thickness may be approximately 30 to 300 microns. In addition to providing an anti-reflection coating (ARC) function, the stacked frontside protective/ARC layer provides excellent protection against weather/elements and force impact (e.g., hail impact) in actual outdoor field operation. Since the frontside coating is effectively and automatically textured as a result of the 3-D structure of the TFSCs, the use of a separate ARC layer on the frontside coating is optional. The textured coating may provide effective light trapping in the frontside coating for effective coupling of a very high fraction (e.g., greater than 95%) of the incident solar light intensity to the TFSCs. The frontside protective layers may also provide an optical waveguiding function to eliminate or reduce any reflection losses associated with the top emitter contact metallization.
  • FIG. 20 outlines an alternative embodiment of an assembly process flow 250 for fabrication of reduced cost and reduced weight (lightweight) solar modules (corresponding to the solar module structure of FIG. 19). This flow is compatible with a fully automated module assembly. This process flow shows the assembly process without the use of a thick glass plate (thus, further reducing the weight, cost, and energy payback time of the solar modules of this disclosure) and without an EVA encapsulant layer on the top of the cells. The module topside (the frontside of assembled cells) is covered with a hard protective glass-type layer (if desired, also including a top ARC layer) with a combined thickness on the order of tens to hundreds of microns. As deposited, this frontside protective layer is effectively textured as a result of the 3-D structure of the TFSCs. The top layer may be formed by a liquid coating technique (e.g., spray coating, liquid-dip coating, or roller coating) following by a thermal or UV curing process. The thermal (or UV) cure for the liquid-spray-coated (or liquid-dip coated or roller coated) protective/AR layers may be performed as a single step together with the vacuum-pressure thermal lamination process. This embodiment results in a lightweight module assembly with reduced materials consumption, reduced cost, and reduced energy payback time. Step 252 (providing PCB) corresponds to step 232 in FIG. 18; step 254 (PCB patterning and silver flash coat) corresponds to step 234; step 256 (cell preparation) corresponds to step 236; and step 258 (automated TFSC placement) corresponds to step 238. Step 260 involves solar module lamination. A stack of the cell-mounted PCB, an encapsulant layer, and a back sheet is prepared. Next, a suitable hermetic sealing/packaging process such as vacuum-pressure lamination is performed. Step 262 involves deposition of the solar module frontside protective coating (which may be automatically textured as deposited and provides efficient light trapping for effective coupling to the TFSCs) layer and an optional ARC layer. The frontside of the solar panel is coated with a thin layer of protective material (e.g., a glass-type transparent material) and an optional top anti-reflection coating (ARC) layer using a suitable coating method. This coating (roughly tens to hundreds of microns) may be performed using liquid spray coating, liquid roller coating, liquid-dip coating, plasma spray coating or another suitable method. Next, a thermal/UV curing process is performed.
  • The hexagonal-prism 3-D TFSCs of this disclosure (both the single-aperture and dual-aperture cells with and without the rear base layers) are inherently bifacial. The hexagonal-prism 3-D TFSCs of this disclosure (particularly hexagonal-prism cells without rear base layers) are uniquely suited for aesthetically appealing solar glass modules with uniform controlled light transmissivity for building façade applications. The hexagonal-prism 3-D TFSCs of this disclosure (the designs without rear base layers and without rear mirrors) provide very uniform partial sunlight transmissivity through the cells. The average level of sunlight transmissivity may be set by adjusting the prism unit cell aspect ratio (higher prism aspect ratios reduce the average sunlight transmissivity through the cells).
  • FIG. 21 shows the schematic cross-sectional view 270 of a solar glass assembly using the hexagonal-prism TFSCs of this disclosure for building façade (architectural solar glass) applications. This is an embodiment of solar module assembly of this disclosure wherein the semi-transparent versions of the hexagonal-prism TFSCs of this disclosure (primarily the dual-aperture cells without rear base layers and without rear mirrors) are used for partially transparent solar glass modules for building façade applications. This example shows the semi-transparent hexagonal-prism cells 272 (the version without the rear base layer and without the rear mirror such that it provides some level of sunlight or diffuse daylight transparency through the cell from frontside or outdoors through the cell backside, to allow a portion of the incident sunlight/daylight through the cell) mounted within a dual-pane argon-filled (gas-filled) low-E glass assembly. The partially transparent TFSCs of this disclosure are closely packed and placed on the lower glass plate 274 (the glass plate facing the building indoors) which is coated with an optically transparent (or semi-transparent) patterned cell interconnect layer 276 to connect the cells in the solar glass in electrical series. The patterned cell interconnect layer 276 may be made of a transparent conductive oxide (TCO) such as Indium Tin Oxide (ITO), a thin semi-transparent layer of silver, or a combination thereof. The top glass plate 278 shown here may face the façade outdoors while the lower glass plate 274 (the one with the patterned transparent/semi-transparent interconnect 276 formed on its inner surface) may face the building indoors. There is a sealed argon-filled space 280 between the glass plates 274 and 2008. Further, there is a sealing/support window frame 282 shown. This design allows for a very uniform level of partial light transparency through the dual-pane solar glass module, thus, providing an aesthetically appealing solar glass design for architectural solar glass applications. The level of partial transparency may be set by the hexagonal-prism cell geometrical parameters such as the unit cell hexagonal aperture size and the unit cell aspect ratio H/d. The level of partial light transparency may be increased by reducing the unit cell aspect ratio H/d and/or by increasing the unit cell aperture diagonal dimension d (see FIGS. 132 and 190). Conversely, the level of partial light transparency may be lowered by increasing the unit cell aspect ratio H/d and/or by decreasing the unit cell aperture diagonal dimension d. Moreover, it is possible to use a partially transparent rear mirror layer (in one embodiment, a thin silver layer formed on the glass plate to form a diffuse partial rear mirror) as part of the patterned cell interconnect formed on the glass plate holding the attached cells. The partially reflecting/partially transparent rear mirror increases the effective cell conversion efficiency, while reducing the partial light transmissivity through the solar glass assembly.
  • FIG. 22 shows another view 290, which is an enlarged, alternative view of a portion of the solar glass module assembly shown in FIG. 21 for building façade applications. This FIGURE has a magnified view of a portion of the solar glass with the hexagonal-prism cells (thus, the relative dimensions of the hexagonal prism cell and the solar glass are not shown to scale). FIG. 22 shows frontside TFSC hexagonal emitter interconnects 292 and self-aligned backside hexagonal base contact 294. The distance 296 between the top glass plate 278 and bottom glass plate 274 may be between 1 and 12 millimeters. The hexagonal-prism cell parameters may be designed to allow for a desired level of light transmission through the cell (e.g., roughly 10% to 90%). The level of average light transmissivity can be controlled by the aspect ratio of the TFSCs.
  • FIG. 23 shows a view 300 of a representative patterned semi-transparent or transparent electrically conductive layer 276 used for connecting the honey-comb-prism TFSCs placed within the solar glass assembly in series (such as a transparent conductive oxide —TCO including indium-tin-oxide or ITO layer, or a thin semi-transparent layer of silver, or a combination thereof; which may also include a partially transparent cell rear mirror made of a suitable material such as an ultrathin semitransparent layer of silver) formed on a glass plate 302 such as the lower glass plate 274 of FIG. 21. This example shows connection of 6×4=24 TFSCs in series within a solar glass module assembly. Of course, a similar patterning methodology may be used for connecting any number of TFSCs in series, or in a combination of series/parallel configuration within the solar glass assembly. Series connection of all the cells within a solar glass module assembly is a preferred electrical connection method (in order to step up the solar glass output voltage, while maintaining the solar glass module current at the TFSC current level). This pattern also shows the output electrical leads 304 of the solar module (solar glass) assembly. The solar glass power electrical leads 304 may be fed through the solar glass frame assembly via a junction box for electrical connections to the adjacent solar glass modules. Patterned IR mirror and cell interconnects 306 are visible to transparent light. The pattern of deposited thin film layer (or multiple layer structure) is formed by sputtering and/or plating. Note that the clear spaces shown between island and lines are typically smaller than those shown (FIGURE not to scale).
  • FIG. 24 shows an alternative embodiment of a module assembly process flow 310 for solar glass applications. This embodiment outlines fabrication of semi-transparent solar glass modules for building façade applications (corresponding to the solar module structures of FIGS. 21, 22, and 23). This solar glass module assembly flow is compatible with a fully automated solar glass module assembly. This flow shows the assembly process using a dual-pane low-E glass structure (other glass structures may be employed as well). This embodiment results in a lightweight solar glass module assembly with reduced materials consumption, reduced cost, and reduced module energy payback time. In step 312, solar glass manufacturing starts with a first glass plate which may serve as the indoors side of a low-E architectural glass assembly for building façade. The glass area may be in a range from less than one m2 to several m2 depending on the application. Step 314 involves formation of (semi)-transparent cell interconnect pattern on first glass plate. The glass plate is cleaned, and a patterned layer of optically transparent or semi-transparent electrically conducting layer is deposited to serve as the cell electrical interconnect plane. The patterned interconnect layer may be made of a transparent conductive oxide (TCO) such as Indium-Tin-Oxide (ITO), a thin semi-transparent layer of silver, or a combination thereof. The patterned layer may be formed by physical-vapor deposition (PVD) through a shadow mask or another suitable technique. Step 316 involves cell preparation for automated TFSC placement and attachment. The rear hexagonal metallized side of the TFSCs is roller coated with lead-free solder or an electrically conductive and thermally-conductive epoxy paste/liquid. For cells fabricated using a honeycomb-prism TFSC substrate without a rear flat silicon base layer, the rear metallized hexagonal-prism ridges are coated to a vertical height of roughly 1 to 20 microns depending on the hexagonal prism unit cell and base metal contact coverage dimensions. This process coats the base hexagonal array interconnects and the emitter wrap-around/wrap-through interconnects in preparation for cell placement and attachment. Step 318 involves automated TFSC placement and soldering (or curing of epoxy). TFSCs are automatically picked and placed in a closely-packed array on the glass plate surface with the patterned (semi)-transparent interconnects. The rear base sides of honeycomb-prism cells are placed on the glass plate. The TFSC rear hexagonal prism base interconnect is soldered (attached) to the patterned cell interconnect layer on glass using thermal or ultrasonic soldering. In case of using epoxy instead of solder, the epoxy is cured using thermal or UV curing. Step 320 involves automated solar glass/module assembly. In one embodiment, the solar glass module assembly is prepared in an atmospheric argon-filled automated assembly ambient by: mounting the glass plate with the attached cells onto a solar glass frame (e.g., a metallic frame such as aluminum frame with a peripheral seal); and attaching a glass plate (in one embodiment with an AR coating (ARC) layer) in parallel to and spaced apart (e.g., by roughly 1 to 30 millimeters) from the other glass plate (comprising the cells), to the solar glass frame such that the cells are confined within an argon-filled cavity formed between the two glass plates sealed by the metallic frame. This forms the low-E solar glass assembly with the cells confined and protected within the argon-filled cavity. The solar glass module frame also provides the electrical lead feedthroughs which are attached to the leads from the patterned interconnect. Module frame peripheral seals maintain the argon-filled cavity and prevent gas leakage.
  • One important consideration in the TFSC and module interconnects is the total power loss associated with the electrical interconnects in the TFSCs and the solar module assembly. The hexagonal-prism 3-D c-Si TFSC and PCB-based module designs of this disclosure effectively address this issue, resulting in very low interconnect ohmic losses in the cells and within the module. This feature (in conjunction with the highly efficient packing of the TFSCs on the PCB-based solar module assembly) substantially narrows the efficiency gap between the TFSCs and the solar module assembly in the technology of this disclosure.
  • The next section relates to the basic calculations of the emitter contact metallization ohmic losses in the hexagonal-prism 3-D TFSCs of this disclosure. The calculations of ohmic losses for emitter contact metallization are also applicable to the hexagonal base contact metallization. However, since several embodiments of this disclosure mount the hexagonal prism 3-D TFSCs on patterned printed circuit boards (PCBs), the base contact metallization is electrically connected in a planar format to a very high conductivity copper pad; this substantially reduces the base interconnect ohmic losses (compared to the emitter interconnect ohmic losses). Therefore, in practical embodiments of this disclosure, the interconnect ohmic losses are dominated by the emitter contact metallization.
  • FIG. 25 may be used for reference with an approximate analytical calculation of the TFSC interconnect ohmic losses, assuming a circular substrate with hexagonal-prism array of unit cells base on the cell design embodiments of this disclosure. Since the overall cell interconnect ohmic losses are dominated by the top emitter contact metallization, the ohmic power loss due to the hexagonal emitter contact metallization is calculated as a function of cell current at maximum power and emitter contact metal vertical height coverage ratio L/d (ratio of the height of emitter contact metal coverage on the prism sidewall to the prism unit cell long hexagonal diagonal dimension). The analytical calculations shown here were used to produce the plots shown in the following FIGURES (FIGS. 26-31). The calculations performed and trends obtained for round substrates are also approximately applicable to square-shaped TFSC substrates.
  • For the following calculations: I0 is the total cell current at peak power; Rthm is the sheet resistance of top hexagonal-coverage emitter contact metal; C is the effective flat surface coverage of hexagonal emitter contact metal with vertical height L; Reff=Rthm/C, where Reff is the effective flat surface sheet resistance of top contact metal; A=(πa2)/4; and J0=(4I0)/(πa2).
  • Interconnect Ohmic Losses @ Max Cell Power:

  • P 1≅(R eff I 0 2)/(8π)

  • C=[(8√3)/3](L/d)

  • R eff=(√3/8)(d/L)R thm

  • P 1≅(R thm I 0 2)[√3/(64π)(d/L)≅8.62×10−3(R thm I 0 2)(d/L)
  • FIGS. 26 through 31 show plots of the calculated hexagonal-prism 3-D TFSC interconnect (due to the dominant emitter contact metallization) ohmic losses versus L/d (ratio of the vertical coverage height of the emitter contact metal coverage on the prism sidewall to the long diagonal dimension of the hexagonal aperture of the hexagonal-prism unit cell), for various values of emitter contact metal sheet resistance (Rthm). Assuming a cell efficiency of 20%, a 200 mm×200 mm square-shaped cell based on one of the embodiments of this disclosure produces roughly 8 W of photogenerated power (AM1.5) and a cell current of roughly 12 A. Thus, in order to limit the maximum emitter contact metallization ohmic losses to roughly 1% of the peak photogenerated power of roughly 8 W, the ohmic power losses should be limited to 0.08 W.
  • FIG. 26 shows the interconnect (emitter contact metallization) ohmic losses at maximum cell power (200 W/m2) versus the ratio of emitter contact metal coverage height (coverage height of emitter contact metal on the prism unit cell sidewall) to hexagonal aperture diagonal dimension (L/d) for an emitter contact metal sheet resistance of Rthm=0.002 Ω/square (assuming a silver bulk resistivity of roughly 1.6 μΩ/square, this corresponds to an 8 microns thick silver layer used as the emitter contact metallization layer). In this case, L/d of more than 0.03 may meet the requirement of less than 1% interconnect ohmic losses (power loss less than 0.08 W). Thus, for d=150 microns, L≧4.5 microns may meet the negligible (<1%) interconnect power loss requirement. Similarly for d=300 microns, L≧9 microns may meet the less than 1% interconnect loss requirement.
  • FIG. 27 shows interconnect (emitter contact metallization) ohmic losses at maximum cell power (200 W/m2) versus the ratio of emitter contact metal vertical coverage height (coverage height of emitter contact metal on the prism unit cell sidewall) to hexagonal aperture diagonal dimension (L/d) for an emitter contact metal sheet resistance of Rthm=0.005 Ω/square (assuming a silver bulk resistivity of roughly 1.6 μΩ/square, this corresponds to a 3.2 micron thick silver layer used as the emitter contact metallization layer). In this case, L/d of more than 0.07 may meet the requirement of less than 1% interconnect ohmic losses (power loss less than 0.08 W). Thus, for d=150 microns, L≧10.5 microns may meet the negligible (<1%) interconnect power loss requirement. Similarly for d=300 microns, L≧21 microns may meet the less than 1% interconnect loss requirement.
  • FIG. 28 shows interconnect (emitter contact metallization) ohmic losses at maximum cell power (200 W/m2) versus the ratio of emitter contact metal coverage height (coverage height of emitter contact metal on the prism unit cell sidewall) to hexagonal aperture diagonal dimension (L/d) for an emitter contact metal sheet resistance of Rthm=0.0075 Ω/square (assuming a silver bulk resistivity of roughly 1.6 μΩ/square, this corresponds to a 2.1 micron thick silver layer used as the emitter contact metallization layer). In this case, L/d of more than 0.12 may meet the requirement of less than 1% interconnect ohmic losses (power loss less than 0.08 W). Thus, for d=150 microns, L≧18 microns may meet the negligible (less than 1%) interconnect power loss requirement. Similarly for d=300 microns, L≧36 microns may meet the <1% interconnect loss requirement. If the interconnect ohmic loss limit is raised to roughly 2% of the photogenerated power (i.e., 0.02×8=0.16 W), L/d>0.06 may meet the requirement of less than 2% interconnect ohmic losses (power loss less than 0.16 W). Thus, for d=150 microns, L≧9 microns may meet this revised interconnect power loss requirement. Similarly for d=300 microns, L≧18 microns may meet the <2% interconnect loss requirement.
  • FIG. 29 shows the emitter contact metal ohmic losses at maximum cell power (200 W/m2) versus the ratio of emitter contact metal coverage height (coverage height of emitter contact metal on the prism unit cell sidewall) to hexagonal aperture diagonal dimension (L/d) for Rthm=0.010 Ω/square (corresponding to a 1.6 micron thick silver layer used as the emitter contact metallization layer).
  • FIG. 30 shows the emitter contact metal ohmic losses at maximum cell power (200 W/m2) versus the ratio of emitter contact metal coverage height (coverage height of emitter contact metal on the prism unit cell sidewall) to hexagonal aperture diagonal dimension (L/d) for Rthm=0.015 Ω/square (corresponding to a 1.07 micron thick silver layer used as the emitter contact metallization layer).
  • FIG. 31 shows the emitter contact metal ohmic losses at maximum cell power (200 W/m2) versus the ratio of emitter contact metal coverage height (coverage height of emitter contact metal on the prism unit cell sidewall) to hexagonal aperture diagonal dimension (L/d) for Rthm=0.020 Ω/square (corresponding to a 0.8 micron thick silver layer used as the emitter contact metallization layer).
  • As shown in FIGS. 26 through 31, as the emitter contact metal (e.g., silver) sheet resistance is increased (or the emitter contact metal thickness is reduced), the vertical coverage of the emitter contact metal over the prism sidewall should be increased (as a fraction of the hexagonal prism unit cell aperture diameter) in order to maintain the interconnect ohmic losses below a pre-specified threshold value (e.g., less than 1%). In practice, the desired emitter contact metallization may comprise silver with a thickness on the order of 3 to 12 microns thick and with a vertical height coverage on the order of 5 to 20 microns.
  • As noted in FIG. 9, the first step in manufacturing a solar module assembly is the fabrication of a template.
  • In the following section, alternative embodiments of process flows for fabricating templates using either lithography and etch techniques or laser micromachining (or laser drilling) are described. The templates are then used and reused numerous times to fabricate the 3-D TFSC substrates with single-aperture or dual-aperture configurations (either with or without rear base silicon layers) for 3-D TFSC fabrication, which are then used in the formation of 3-D TFSCs, which are used in thin-film solar module assemblies of the disclosed subject matter.
  • Templates may be fabricated using electronic-grade silicon wafers, solar-grade silicon wafers, or lower-cost metallurgical-grade silicon wafers. Moreover, templates made of silicon can be fabricated either using monocrystalline or multicrystalline silicon wafers. The starting template wafer may either be a standard polished wafer (after saw damage removal) or even a lower grade wafer immediately after wire sawing (without saw damage removal). The latter may further reduce the cost of the templates. The relatively low cost of each template is spread over numerous 3-D thin-film TFSC substrates, resulting in much lower TFSC substrate and finished module costs compared to the standard state-of-the-art (e.g., 200 microns thick) solar-grade monocrystalline and multicrystalline silicon wafers and associated modules.
  • For further explaining how a template is fabricated, FIG. 32 shows an embodiment of a process flow 330. The process begins with step 332, where an unpatterned monocrystalline silicon or multicrystalline silicon, either square-shaped or round substrate (e.g., 200 mm×200 mm square or 200-mm round) is provided. The starting template wafer may be a wafer prepared by wire saw either with or without saw damage removal (the latter may further reduce the cost of template). The starting template wafer may also be made of a lower purity (and lower cost) metallurgical-grade silicon. In one embodiment, the substrate is roughly 200 to 800 microns thick. Optionally, step 332 includes performing gettering on a low-cost metallurgical-grade silicon and/or performing a surface texturing etch (e.g., using isotropic acid texturing by a mixture of nitric acid and hydrofluoric acid, or using alkaline texturing in KOH/IPA) to create an optional textured template surface. Step 334 uses photolithography patterning (in one embodiment, using a lower cost contact or proximity aligner/patterning) to produce a prism-array mask pattern such as hexagonal-array pattern in photoresist (i.e., interconnected hexagonal openings in the photoresist layer). The process sequence includes the formation of an oxide and/or nitride (optional) layer, photoresist coating (e.g., spin-on or spray coating) and pre-bake, photolithography exposure through a hexagonal-array mask, and photoresist development and post-bake. One embodiment includes a hard mask layer (SiO2 and/or SiNx; for example, a thin thermally grown oxide layer can be used as an optional hard mask) below the photoresist (although the process may be performed without the use of any hard mask layer by placing the photoresist coating directly on silicon). When using a hard mask layer, the exposed portions of the hard mask layer are etched after photoresist patterning (thus, forming hexagonal openings). Such etching of the exposed hard mask layer may be simply performed using a wet etchant such as hydrofluoric acid for oxide hard mask. Step 336 involves formation of hexagonal prisms using anisotropic plasma etch; where a high-rate deep reactive ion etch (DRIE) process forms a closely-packed array of deep (e.g., 100 to 400 microns) hexagonal-shaped trenches in silicon. The photoresist and/or oxide and/or nitride hard mask layer(s) are used for pattern transfer from the patterned photoresist layer to silicon. In one embodiment, the deep RIE (DRIE) process parameters are set to produce near-vertical, slightly tapered hexagonal-prism trench sidewalls. In an alternative embodiment, the deep RIE (DRIE) process parameters are set to produce roughly or essentially vertical hexagonal-prism sidewalls. Note that the slightly tapered sidewalls are preferred over the essentially vertical sidewalls. Step 338 involves template surface preparation and cleaning. This process includes stripping the patterned photoresist layer from the substrate. The template substrate is then cleaned in a wet bench prior to subsequent thermal deposition processing to form the TFSC substrates. Such cleaning may involve DRIE-induced polymer removal (using a suitable wet etchant such as a mixture of sulfuric acid and hydrogen peroxide) followed by an isotropic silicon wet etch (such as in a mixture of nitric acid and hydrofluoric acid) in order to isotropically remove a thin layer (e.g., on the order of 10 to 500 nanometers) of silicon from the trench sidewalls and bottoms. This may remove any surface and buried contaminants, such as any surface and embedded metallic and/or polymeric/organic contaminants introduced by the deep RIE (DRIE) process, from the sidewalls and bottoms of the DRIE-produced template trenches. Template processing may complete after a deionized (DI) water rinse and drying. Optionally and if desired, the template wafer may also go through a standard pre-diffusion (or pre-thermal processing) wafer cleaning process such as a so-called RCA wet clean prior to the above-mentioned DI water rinsing and drying. Another optional surface preparation step (either performed instead of or after the wet isotropic silicon etch process) includes performing a short thermal oxidation (e.g., to grow 5 to 100 nanometers of sacrificial silicon dioxide), followed by wet hydrofluoric acid (HF) oxide strip (to remove any residual contaminants from the patterned template). If no optional oxide growth/HF strip is used, an optional dilute HF etch may performed to remove the native oxide layer and to passivate the surface with hydrogen (forming Si—H bonds) in preparation for subsequent 3-D TFSC substrate fabrication. After the completion of step 338, the resulting template may then be used and reused multiple times to fabricate 3-D (e.g. hexagonal-prism) thin-film TFSC substrates.
  • FIG. 33 shows a top view of a lithography exposure mask design 340 which may be used for fabrication of a template, as described in step 334 of process flow 330 above. Dark regions 342 are an opaque coating such as Cr on a transparent mask plate. Light regions 344 are areas where the opaque coating (e.g., Cr) has been etched to allow for exposure of a photoresist layer. In one embodiment, the width of the hexagonal line (LM) 346 on the mask plate is between 1 and 30 microns, and the diagonal distance between hexagonal prism points (d) 348 or the hexagonal-prism aperture diameter is between 50 and 500 microns.
  • An alternative embodiment of a process flow 350 for patterning of a template is outlined in FIG. 34, which uses direct laser micromachining instead of photolithography and reactive-ion etch. Step 354 (providing an unpatterned substrate) corresponds to step 332 of FIG. 32. Step 354 involves the use of programmable precision laser micromachining to form the desired periodic array of deep trenches. This process may be performed in a controlled atmospheric ambient based on either physical ablation or a combination of physical ablation and laser-assisted chemical etching. Step 356 (surface preparation and cleaning) corresponds to step 338 of FIG. 32. After the completion of step 356, the resulting template may then be used and reused to fabricate multiple 3-D TFSC substrates.
  • Another alternative embodiment of a process flow 360 for patterning of a template is outlined in FIG. 35, which uses photolithography and etch to produce through-wafer trenches. Step 362 (providing an unpatterned substrate) corresponds to step 352 in FIG. 34. Step 364 involves forming a silicon dioxide (SiO2) layer and/or a silicon nitride (SiNx) layer on both the frontside and backside of the substrate (this step is optional and may not be used). In one embodiment, the SiO2 layer thickness is between 100 and 1000 nanometers. The SiO2 layer is formed by steam oxidation or LPCVD and may be followed by a layer of SiNx formed by LPCVD or PECVD. In one embodiment, the SiNx layer thickness is between 100 and 1000 nanometers. These layers may be formed on both sides of the silicon substrate (as shown in FIG. 34), or only on the substrate frontside or backside. Alternatively, only one layer (either oxide or nitride) may be used. Step 366 (patterning) corresponds to step 334 in FIG. 32; and step 368 (etch) corresponds to step 336. Step 370 involves formation of backside oxide/nitride openings for 3-D TFSC substrate release etching. Photoresist lithography patterning and plasma etch (or wet etch) are used to form a regular array of openings (e.g., a square grid or a line pattern) in oxide/nitride on the substrate backside. These openings may be used during subsequent 3-D TFSC substrate fabrication (for wet etchant access to sacrificial layer from backside). Step 372 (surface preparation and cleaning) corresponds to step 338 in FIG. 32 and may be modified such that the surface preparation and cleaning process does not remove the dielectric layers from the substrate backside. After step 372, the resulting template may then be used to fabricate 3-D TFSC substrates.
  • Another alternative embodiment of a process flow 380 for fabrication of a template is outlined in FIG. 36, which uses photolithography and etch, enabling fabrication of TFSC substrates with a rear base layer and grooves for formation of self-aligned base contacts. Another alternative embodiment of a process flow 400 for patterning of a template is outlined in FIG. 37, which uses photolithography and etch, enabling fabrication of TFSC substrates with a rear base layer and grooves for formation of self-aligned base contacts. FIGS. 41 through 47 show the Y-Y cross-sectional views of a silicon substrate during the fabrication process flow for making a template based on the process flows of FIG. 36 or FIG. 37. It may be useful to refer to FIGS. 41 through 47 while reviewing the process flow steps of FIGS. 36 and 37.
  • Referring to FIG. 36, step 382 (providing an unpatterned substrate) corresponds to step 362 in FIG. 35; step 384 (forming oxide and/or nitride layers) corresponds to step 364; step 386 (patterning) corresponds to step 366; and step 388 (etch) corresponds to step 368. Step 390 involves formation of self-aligned shallow trenches which are wider than deep trenches. The self-aligned wider shallow surface trenches are formed by a timed selective isotropic dielectric (hard mask) etch to form hard mask undercuts with known lateral dimension under photoresist, stripping patterned photoresist, and a timed anisotropic silicon RIE to form shallower/wider tapered trenches near surface. Step 392 (formation of backside openings) corresponds to step 370 in FIG. 35; and step 394 (surface preparation and cleaning) corresponds to step 372. After step 394, the resulting template may then be used and reused to fabricate multiple 3-D TFSC substrates. It should be noted that the self-aligned wider shallow trenches (which are wider than the deep trenches) may also be formed as part of the same deep RIE process which forms the deep trenches (i.e., steps 388 and 390 can be merged into a single deep RIE process in a DRIE process equipment), thus, eliminating the need for the above-mentioned timed selective isotropic dielectric hard mask etch to form hard mask undercuts under photoresist (this modified approach may also eliminate the need for the frontside hard mask (i.e., the patterned photoresist layer can be formed directly on the substrate) and further simplify the template fabrication process). This simplified process can be performed by using a DRIE process recipe which first forms the deep hexagonal-prism trenches and subsequently forms the shallow wider trenches (or shoulders) over the deep trenches by performing a less anisotropic (or more isotropic) silicon etch process which primarily affects the upper (topmost) portion of the deep hexagonal-prism trenches. Using this modified approach the sidewall profile of the wider shallow trenches may be slightly or heavily tapered (both are acceptable).
  • Referring to FIG. 37, step 402 (providing an unpatterned substrate) corresponds to step 382 in FIG. 36. Step 404 involves forming a SiO2 layer and/or a SiNx layer on the frontside and optionally on the backside of the substrate. In one embodiment, SiO2 layer thickness is between 100 and 1000 nanometers. The SiO2 layer is formed by steam oxidation or LPCVD followed by a layer of SiNx formed by LPCVD or PECVD. In one embodiment, the SiNx layer thickness is between 100 and 1000 nanometers. The layers are formed either on front or both sides of the silicon substrate. Alternatively, only one layer (oxide or nitride) may be used. Alternatively, a SiO2 layer only on the frontside and a SiNx layer only on backside may be formed. Step 406 (patterning) corresponds to step 386 of FIG. 36; step 408 (etch) corresponds to step 388; and step 410 (formation of shallower wider trenches) corresponds to step 390. Again and essentially as described for FIG. 36, the self-aligned wider shallow trenches (which are wider than the deep trenches) may also be formed as part of the same deep RIE process which forms the deep trenches (i.e., steps 408 and 410 can be merged into a single deep RIE process in a DRIE process equipment). Step 412 involves formation of an array of openings on the wafer backside of sufficient depth to connect to at least some portions of the rears (bottoms) of the deep trenches. These openings provide access to at least a portion of each prism unit cell from the substrate backside. These holes are formed by laser drilling (or may be formed using backside lithography and wet or plasma etch) and may be used for 3-D thin-film TFSC substrate release etching (for etchant access to sacrificial layer such as for etching the sacrificial porous silicon layer). Step 414 (surface preparation and cleaning) corresponds to step 394 of FIG. 36. After step 414, the resulting template may then be used and reused to fabricate multiple 3-D TFSC substrates.
  • FIGS. 36 and 37 result in templates which enable subsequent fabrication of 3-D thin-film TFSC substrates with rear base layers (e.g., such as flat rear silicon base layers) and interconnected shallow grooves or trenches for formation of self-aligned high-conductivity base contact metallization. These 3-D thin-film TFSC substrates may be used for subsequent fabrication of high-efficiency TFSCs with self-aligned base and emitter contacts. The dual-width trenches (or deep trenches with shallower and wider trench shoulders stacked on their top) in the template enable fabrication of self-aligned base metallization contacts beside self-aligned emitter metallization contacts.
  • In order to better understand the following FIGURES, FIG. 38 is provided to show a top view of a hexagonal prism 3-D TFSC substrate. FIG. 38 shows the reference imaginary Y-Y and Z-Z cross-sectional axes on a hexagonal-prism 3-D TFSC substrate.
  • FIG. 39 shows a Y-Y cross-sectional view of a template 420 with through-wafer trenches 422 (i.e., trenches formed through the substrate and stopped on backside dielectric). This template 420 may be used to fabricate numerous hexagonal-prism 3-D TFSC substrates, including those without rear base layers (i.e., dual-aperture TFSC substrates).
  • The template 420 has dimensions of h (horizontal distance between trenches) 424, Tst (trench top width) 426, H (height of the trench) 428, Tsb (trench rear width) 430, and 2θ 432 (where θ is the average sidewall taper angle). Note that because these are through-wafer trenches 422, H 428 is essentially the same as the silicon thickness of the template substrate. Because the through-wafer trenches 422 produce isolated posts, backside dielectric layer 434 is used and should be sufficiently thick and strong to provide sufficient mechanical support. Backside dielectric layer 434 may be a single dielectric layer such as oxide (or nitride) or a stack of two or more dielectric layers such as oxide/nitride. In one embodiment, backside dielectric layer 434 is composed of a layer of LPCVD Si3N4 on top of a layer of thin thermal SiO2. The template 420 contains a frontside etch-stop layer 436 (top hard mask layer). In one embodiment, the top hard mask 436 is composed of a layer 436 of LPCVD Si3N4 on top of a layer 438 of thin thermal SiO2. Alternatively, the top hard mask layer 436 may include a single layer instead of a 2-layer stack (e.g., Si3N4, SiCx, etc.). Alternatively, there may be no top hard mask layer (patterned photoresist formed directly on silicon).
  • FIG. 40 shows a Y-Y cross-sectional view of a template 440 with within-wafer trenches 442. This template 440 may also be used to fabricate numerous hexagonal-prism 3-D thin-film TFSC substrates, including those without rear base layers (i.e., dual-aperture TFSC substrates). The trenches 442 are confined within the wafer (within the template substrate) and do not penetrate the entire wafer thickness, leaving remaining wafer thickness R 444; note that for a given template substrate thickness, H 446 is less than H 428 in FIG. 39. Thus, the wafer itself provides sufficient mechanical support without a need for mechanical support from backside dielectrics (thus, eliminating the need for backside dielectrics; backside dielectrics are optional here).
  • The trenches formed in the templates shown in FIGS. 39 and 40 may have vertical sidewalls or slightly tapered sidewalls (in one embodiment, producing deep trenches with gradually and slightly decreasing trench width moving from the trench top towards the trench bottom). In one embodiment, sidewall angles are in the range of 0° to 10° (preferably in the range of 0° to 1°). Trenches with negative or re-entrant sidewall angles (i.e., trenches with increasing trench width moving from the trench top towards the trench bottom) are not desirable and may cause difficulty with 3-D TFSC substrate release and, therefore, should be avoided.
  • Both template 420 (FIG. 39) and template 440 (FIG. 40) are made using one of the template process flows outlined in FIGS. 34-36. These flowcharts describe the preferred process steps used for fabricating the templates used for subsequent fabrication of numerous 3-D thin-film TFSC substrates.
  • FIGS. 41 through 47 show one embodiment of a process flow and evolution of a template structure for a template version with within-wafer trenches 442 and design to enable formation of self-aligned base contacts during various stages of the template process flows outlined in FIGS. 34-36.
  • FIG. 41 shows a Y-Y cross-sectional view 450 after formation of a photoresist frontside pattern 452 on dielectric (oxide) hard mask (backside dielectrics 434 are optional and may not be used). FIG. 42 shows a Y-Y cross-sectional view 460 after anisotropic plasma oxide etch (or isotropic wet oxide etch) through the photoresist frontside pattern 452. FIG. 43 shows a Y-Y cross-sectional view 470 after formation of deep hexagonal-prism trenches using deep RIE (DRIE). FIG. 43 further shows remaining wafer thickness R′ 472 and trench height H′ 474. FIG. 44 shows a Y-Y cross-sectional view 480 after timed selective isotropic hard mask etch (e.g., oxide etch using HF) to form controlled lateral undercuts 482 under patterned photoresist 452 with width Wox. FIG. 45 shows a Y-Y cross-sectional view 490 after photoresist strip. Note that the top hard mask layer 436 remains and the photoresist layer has been removed. FIG. 46 shows a Y-Y cross-sectional view 500 after anisotropic silicon etch to form wider shallow trenches with controlled height (L) 502 on the top of the narrower and deeper trenches 442. FIG. 47 shows a Y-Y cross-sectional view of a completed template 510 after isotropic oxide etch to strip the top hard mask layer 436 as shown in FIG. 46. While shown here, the backside dielectric layers may also be removed (or may not be used at all). This template 510 may also be used to fabricate numerous hexagonal prism 3-D TFSC substrates. As described before, the combination of deep trenches and wider shallow trenches (top shoulders) may be formed using a single DRIE process sequence (anisotropic deep trench RIE followed by a less anisotropic silicon etch to form the top shoulders), thus, eliminating the need for the top dielectric hard mask layer 436 and the associated process steps reflected in FIGS. 44 and 45.
  • The following FIGURES (FIGS. 48 to 51) illustrate several alternative embodiments of completed templates.
  • FIG. 48 shows a Y-Y cross-sectional view of a template 520 with within-wafer trenches 442 without a dielectric top mask layer or a dielectric rear mask layer. FIG. 49 shows a Y-Y cross-sectional view of a template 530 with within-wafer trenches 442 without a dielectric top mask layer or a dielectric rear mask layer, compared to the embodiment shown in FIG. 48. This view also shows template backside holes 532 used to allow for 3-D TFSC substrate release etching. These backside holes 532 may be fabricated using either lithography and etch, or laser micromachining or drilling. FIG. 50 shows a Y-Y cross-sectional view of a template 540 with through-wafer trenches 422 without a top hard mask layer 436 as shown in FIG. 39. FIG. 51 shows a Y-Y cross-sectional view of a template 550 with through-wafer trenches 422 without a top hard mask layer 436, compared to FIG. 46. Note further that the through-wafer trenches 422 in FIG. 51 have wider trenches (top shoulders) with controlled height (L) 502 on the top of the narrower and deeper hexagonal trenches, like the trenches in FIG. 47. However, note that FIG. 51 shows through-wafer trenches 422, whereas FIG. 47 shows within-wafer trenches 442.
  • For templates with through-wafer trenches, mechanical support may be provided by either using a backside dielectric stack of sufficient strength (such as oxide, nitride, polysilicon, or a combination thereof as described before), or using a backside-bonded silicon wafer. FIG. 52 shows a view of a template 560 with through-wafer trenches and without any frontside dielectrics, suitable for fabrication of hexagonal-prism single-aperture 3-D TFSC substrates with rear base layers. This template 560 includes a mechanical support rear silicon wafer 562 bonded at a bonded interface 564 (e.g., via a dielectric such as oxide or a dielectric stack 566 such as oxide/nitride between the wafers). The mechanical support rear silicon wafer 562 provides wet etchant access to the template trenches through holes 568, which may be created either by laser drilling or reactive ion etching. This template 560 enables fabrication of 3-D TFSC substrates with capability for formation of self-aligned base and emitter contacts during subsequent hexagonal prism 3-D TFSC substrate fabrication. In an alternative embodiment, mechanical support rear silicon wafer 562 may instead be formed by a layer of polysilicon deposited by LPCVD over the backside dielectric (or dielectric stack) 566, thus, eliminating the need for wafer bonding.
  • FIGS. 53 and 54 show views 570 and 580, respectively, of two examples of mask designs (out of many possible designs), the first one a square-array mask and the second one a line-array mask, which may be used to pattern the template backside to produce backside openings for 3-D TFSC substrate release etching. This patterning is performed only once on each template.
  • FIG. 53 shows a square-array mask 570, where each square-array unit cell 572 has a square-array unit cell width 574 and a square array unit cell spacing 576. In one embodiment, both of these are approximately 1 to 5 microns (may be smaller or larger as well). FIG. 54 shows a line-array mask 580, where the pattern shown is repeated over the entire mask as a periodic array. In one embodiment, the line widths and spaces are all 1 to 10 microns (may be smaller or larger as well). The pattern has a pattern width 582, which in one embodiment is approximately 50 to 500 microns. Other mask patterns (e.g., lines, circles, etc.) enabling etchant access to remove the sacrificial layer may be used instead of square array or orthogonal line array. Alternatively, it is possible to use laser drilling or laser micromachining instead of lithography/etch to create the backside holes/openings for etchant access.
  • An alternative to the backside patterning outlined in FIGS. 53 and 54 uses a frontside mask to enable release of single-aperture hexagonal-prism 3-D thin-film TFSC substrates with flat base layers by providing etchant access pathways from the template frontside.
  • FIG. 55 shows an alternative frontside hexagonal-prism mask design 590 with center holes 592, shown as white circles on the mask plate. In one embodiment, center holes 592 are roughly 1 to 5 microns in diameter. Note that the hexagonal-prism array design is the same as in FIG. 33. Dark regions 342 are opaque coating (e.g., Cr) on the mask plate. Light regions 344 and 592 are areas to be etched. In one embodiment, the width of the line mask (LM) 346 is between 1 and 30 microns, and the diagonal distance between hexagonal-prism points (d) 348 is between 50 and 500 microns.
  • FIG. 56 shows a view 600 of the template frontside mask design 590 shown in FIG. 55, also shown with dotted squares 572 indicating a superimposed image of one embodiment of the backside mask design (in order to see the relative alignment of the frontside mask and backside mask from the frontside mask perspective).
  • FIG. 57 shows a top view of a template backside mask design 610, with the superimposed image of the hexagonal array of the mask design 590 from FIGS. 55 and 56 shown as gray hexagonal-array pattern in order to see the relative alignment of the frontside mask and backside mask from the backside mask perspective).
  • FIGS. 58 through 66 show an alternative template version during various stages of the template process flows outlined in FIGS. 36 and 37.
  • FIG. 58 shows a Y-Y cross-sectional view of an n-type (e.g., phosphorus-doped) [100] silicon substrate 620 after formation of a top hard mask layer 436 and a backside hard mask layer 434 using thermal oxidation. Note that before oxidation, an optional surface texturing wet etch (such as using an acid texturing etch or an alkaline texturing etch) may be performed using a suitable etchant such as KOH in order to texture the silicon surface. FIG. 59 shows the substrate 620 in FIG. 58 after backside lithography to form a patterned photoresist layer 624 comprising an array of square-shaped openings 622 and after wet or anisotropic plasma etching of the backside hard mask layer 434 in the exposed areas. Note that in order to use anisotropic wet etch to form the backside channels, the backside mask square pattern for the substrate 620 backside is properly aligned to produce [111] sidewalls, [110] directed edges, and [211] directed ribs. FIG. 60 shows the substrate 620 in FIG. 59 after anisotropic etching of template from backside using an anisotropic wet etchant (e.g., KOH or TMAH) to form an array of pyramids 626 with square bases and after stripping photoresist layer 624 from template backside. Note the angle 628 of the pyramids 626. In one embodiment, this angle is 35.26°. The backside lithography mask square pattern is properly aligned to produce [111] plane sidewalls 630, [110] directed edges, and [211] directed ribs. FIG. 61 shows the substrate 620 in FIG. 60 after frontside patterning and anisotropic oxide plasma etch (or isotropic oxide wet etch) through patterned resist 452 in preparation for formation of honeycomb-prism trenches and concurrently forming frontside-etched small-diameter release trenches 632, and removing backside oxide layer 434. In one embodiment, the diameter (DR) of the release access trenches 632 is between 1 and 5 microns. FIG. 62 shows the substrate 620 in FIG. 61 after frontside deep silicon RIE. Note that frontside-etched small-diameter trenches 632 connect to the backside release channels 626 through shallower cone-shaped trenches 634 (in one embodiment, at the centers of the hexagonal-prism posts). FIG. 63 shows the substrate 620 in FIG. 62 after timed selective isotropic hard mask (SiO2) etch to form controlled lateral undercuts 482 under patterned photoresist. FIG. 64 shows the substrate 620 in FIG. 63 after photoresist 452 strip, with oxide hard mask 436 remaining. FIG. 65 shows the substrate 620 in FIG. 64 after anisotropic silicon reactive-ion etch to form wider trenches with controlled height (L) 502 on top of the narrower and deeper hexagonal-prism within-wafer trenches 442. FIG. 66 shows the substrate 620 in FIG. 65 after isotropic oxide etch to strip top oxide 436. After this step an optional timed silicon wet etch may be performed in HNA or TMAH to remove about 5 to 500 nanometers of silicon to remove any DRIE-induced trench sidewall damage and/or polymeric/metallic contamination. At this point, the substrate 620 may serve as a reusable template for formation of 3-D thin-film TFSC substrates. Again as described before, the combination of deep trenches and wider shallow trenches (top shoulders) may be formed using a single DRIE process sequence (anisotropic deep trench RIE followed by a less anisotropic silicon etch to form the top shoulders), thus, eliminating the need for the top dielectric hard mask layer 436 and the associated process steps reflected in FIGS. 64 and 65. This alternative process flow also eliminates the need for the oxide hard mask (thus, photoresist can be applied directly on silicon for frontside and backside patterning steps).
  • FIGS. 67 through 75 show a template version during various stages of the template fabrication process flow outlined in FIGS. 36 and 37. FIGS. 67 through 75 are substantially similar to FIGS. 58 through 66, except the initial silicon substrate is an n-type [110] substrate 640, which results in backside release channels 642 in the shape of rectangular trenches with vertical sidewalls, rather than pyramids. The resulting substrate 640 shown in FIG. 75 may serve as a reusable template for formation of 3-D thin-film TFSC substrates. Again as described before, the combination of deep trenches and wider shallow trenches (top shoulders) may be formed using a single DRIE process sequence (anisotropic deep trench RIE followed by a less anisotropic silicon etch to form the top shoulders), thus, eliminating the need for the top dielectric hard mask layer 436 and the associated process steps reflected in FIGS. 73 and 74. This alternative process flow also eliminates the need for the oxide hard mask (thus, photoresist can be applied directly on silicon for frontside and backside patterning steps).
  • Another approach to implement the template release channels is to place them on the template substrate backside such that they connect to the bottoms of the hexagonal-prism deep trenches (instead of tops of the posts or pillars as shown before). FIGS. 76 and 79 through 86 show a template version (with the release channels connected to the bottoms of the deep trenches) during various stages of the template process flows outlined in FIGS. 36 and 37. This embodiment uses a backside lithography mask design as shown in FIG. 77 (other types of backside mask patterns for backside release channels are also possible). FIG. 78 shows the backside lithography mask shown in FIG. 77, with the frontside hexagonal-prism array mask pattern shown as a superimposed gray pattern for reference (to show the relative alignment of the frontside and backside masks patterns).
  • FIG. 76 is substantially similar to FIG. 58 above, showing an initial n-type (e.g., phosphorus doped) [100] substrate 620. FIG. 79 is substantially similar to FIG. 59 above, except the mask design aligns backside release channels 644 with the bottoms of deep prism trenches 442 to be formed. FIG. 80 shows the substrate 620 shown in FIG. 79 after anisotropic wet etching (e.g., using anisotropic alkaline etching such as KOH-based etching) of the template backside to form an array of pyramids with square bases (note that the anisotropic etching may also be performed using anisotropic reactive ion etching and the backside openings may be circular or other shapes instead of square-shaped). FIG. 81 shows the substrate 620 in FIG. 80 after frontside patterning and after wet oxide etch through patterned resist in preparation for formation of deep trenches. This also removes the backside oxide layer 434. FIG. 82 shows the substrate 620 in FIG. 81 after formation of hexagonal-prism trenches 442 using deep RIE (DRIE). Note that the bottoms of prism trenches 442 essentially align with the backside release channel holes 644. FIG. 83 shows the substrate 620 in FIG. 82 after timed selective isotropic hard mask (in one embodiment SiO2) wet etch to form controlled lateral undercuts 482 under patterned photoresist. FIG. 84 shows the substrate 620 in FIG. 83 after top photoresist 452 strip using a photoresist stripper. FIG. 85 shows the substrate 620 in FIG. 84 after anisotropic silicon etch (using the oxide layer as a hard mask) to form wider trenches (top shoulders) with controlled height (L) 502 on top of the narrower and deeper hexagonal-prism within-wafer trenches 442. FIG. 86 shows the substrate 620 in FIG. 85 after isotropic oxide etch to strip top oxide 436. After this step an optional timed isotropic silicon wet etch may be performed in HNA or TMAH (or another suitable isotropic silicon wet etchant) to etch approximately 5 to 500 nanometers of silicon to remove any DRIE-induced trench sidewall contaminants (such as metallic and/or polymeric contaminants) and surface damage. At this point, the substrate 620 may serve as a template for formation of 3-D thin-film TFSC substrates. Again as described before, the combination of deep trenches and wider shallow trenches (top shoulders) may be formed using a single DRIE process sequence (anisotropic deep trench RIE followed by a less anisotropic or more isotropic silicon plasma etch to form the top shoulders), thus, eliminating the need for the top dielectric hard mask layer 436 and the associated process steps reflected in FIGS. 83 and 84. This alternative process flow also eliminates the need for the oxide hard mask (thus, photoresist can be applied directly on silicon for frontside and backside patterning steps).
  • Various embodiments of the templates shown earlier may be used to produce one hexagonal-prism (or other prism geometries) 3-D thin-film TFSC substrate per process pass. It is also possible to fabricate templates which are capable of producing two hexagonal-prism 3-D thin-film TFSC substrates concurrently per process pass (thus, doubling the 3-D TFSC substrate fabrication throughput). FIGS. 87 and 88 show cross-sectional views of two such templates capable of doubling the hexagonal-prism 3-D thin-film TFSC substrate production throughput.
  • FIG. 87 shows a Y-Y cross-sectional view of a stacked template structure 650 for fabricating two hexagonal prism 3-D thin-film TFSC substrates per process pass. FIG. 87 shows a template structure 650 with within-wafer trenches 442. Note the similarity to the template 440 in FIG. 40. Template structure 650 is made of two similar templates, a top template 652 and a rear template 654, which are first fabricated based on one of the embodiments outlined before and then bonded together backside to backside (e.g., using direct thermal bonding of the wafer backsides or thermal bonding of dielectric layers formed on the wafer backsides) at a backside interface 656. Note that the dielectric hard masks on the template frontsides may not be present (they are optional for subsequent use of the templates for TFSC substrate fabrication). FIG. 88 shows Y-Y cross-sectional view of an alternative stacked template structure 660 for concurrently fabricating two hexagonal-prism 3-D TFSC substrates per process pass. FIG. 88 shows a template structure 660 with through-wafer trenches 422. Note the similarity to the template 420 in FIG. 39. Template structure 660 is made of two similar templates, a top template 662 and a rear template 664, which are first fabricated based on one of the embodiments outlined before and then bonded together backside to backside (e.g., either through direct bonding of the substrate backsides or using thermal bonding of dielectric layers formed on the wafer backsides) at a backside interface 656. Note that the dielectric hard masks on the template frontsides may not be present (they are optional for subsequent use of the templates for TFSC substrate fabrication).
  • While FIGS. 87 and 88 show representative stacked template structures suitable for higher throughput fabrication of hexagonal-prism dual-aperture 3-D thin-film TFSC substrates without rear base layers, it is also possible to make stacked template structures for fabrication of hexagonal prism 3-D thin-film TFSC substrates with rear base layers. This may be done by first fabricating the suitable individual templates based on one of the process flow embodiments shown in FIGS. 36 and 37, corresponding to the template structure shown in FIG. 40 (this one shown with within-wafer trenches; it is also possible to fabricate templates with through-wafer trenches such as the structures shown in FIG. 51 or FIG. 52). Assuming we use a pair of templates with the structure shown in FIG. 40 (or a template structure with wider and shallow trenches or shoulders stacked on top of the deep trenches), these templates are then processed to create a series of large lateral/radial microchannels in conjunction with an array of holes/openings which communicate with the rears of trenches. The two templates are then bonded together backside-to-backside (e.g., by thermal bonding of the backside surfaces together). The radial/lateral microchannels sandwiched between the bonded wafers extend all the way to the periphery of the stacked/bonded templates and provide easy access for the wet etchant to reach the sacrificial layer (e.g., porous silicon formed by anodic etching of monocrystalline or microcrystalline silicon layer) in each template in order to selectively remove the sacrificial layer in each template and to release the embedded hexagonal-prism 3-D thin-film TFSC substrates from the top and rear templates in the stack (thus, concurrently forming two hexagonal-prism 3-D thin-film TFSC substrates per process pass). The microchannels on the template backsides may be formed before template bonding by laser ablation or a combination of lithography and etch. The microchannels are sufficiently large to allow for easy movement of wet etchant and etch byproducts between the inner portions of the wafers in the bonded stack and the peripheral openings of the microchannels in the middle of the bonded stack.
  • While one embodiment of the 3-D TFSC substrate unit cell structure of this disclosure is a regular hexagonal-prism unit cell (with equilateral hexagonal cross sections or ridges), this disclosure also covers a wide range of other 3-D prism unit cell geometrical designs with various polygon prism unit cell aperture designs. The prism array may be a uniform array of a single polygon prism unit cell or a hybrid (two or more) of multiple polygon-prism unit cell designs.
  • FIGS. 89A through 95C show examples of several 3-D polygon-prism thin-film TFSC substrates with various unit cell prism geometrical designs and arrangements. FIG. 89A shows a top view 670 of a prism design with hexagonal unit cell angles not equal to one another or 120°. FIG. 89B shows a top view 672 of a prism design with equilateral triangular prism unit cells. FIG. 90A shows a top view 674 of a prism design with non-equilateral triangular prism unit cells. FIG. 90B shows a top view 676 of a prism design with alternating equilateral triangular prism unit cells. FIG. 91A shows a top view 678 of a prism design with offset parallelogram prism unit cells. FIG. 91B shows a top view 680 of a prism design with parallelogram prism unit cells. FIG. 92A shows a top view 682 of a prism design with aligned square prism unit cells. FIG. 92B shows a top view 684 of a prism design with shifted square prism unit cells. FIG. 93A shows a top view 686 of a prism design with aligned rectangular prism unit cells. FIG. 93B shows a top view 688 of a prism design with shifted rectangular prism unit cells. FIG. 94A shows a top view 690 of a prism design with trapezoidal prism unit cells. FIG. 94B shows a top view 692 of a prism design with alternating trapezoidal prism unit cells. FIG. 95A shows a top view 694 of a prism design with hybrid pentagon-parallelogram prism unit cells.
  • FIG. 95B shows a top view 696 of a prism design with hybrid hexagon-triangle prism unit cells. FIG. 95C shows a top view 698 of a prism design with hybrid octagon-square prism unit cells.
  • In addition to these alternative TFSC designs, many other polygon-prism as well as other non-polygon prism unit cell designs (e.g., cylindrical-prism, elliptical-prism, etc.) are covered by this disclosure. In general, the 3-D TFSC substrates of this disclosure cover any arrays of one or more prism unit cells arranged to make a lightweight, enlarged-surface-area thin-film TFSC substrate for solar cell fabrication. Typically, there are millions (or as few as thousands) of these prism unit cells forming a large-area (e.g., 210 mm×210 mm) 3-D TFSC substrate. In one embodiment, the 3-D TFSC substrate film thickness is in the range of 1 to 30 microns, and preferably in the lower-end range of 2 to 10 microns. This is substantially less (by a factor of roughly 20× to 100×) than the current state-of-the-art silicon solar cell wafer thickness (roughly 200 microns).
  • As noted in FIG. 9, the templates described above may be used for formation of 3-D thin-film TFSC substrates, which are then used in the formation of 3-D TFSCs, which are used in thin-film solar module assemblies of the disclosed subject matter.
  • FIGS. 96 through 102 show various embodiments of hexagonal-prism 3-D thin-film TFSC substrate fabrication process flows for fabricating hexagonal-prism (or other prism-array shapes) dual-aperture 3-D thin-film TFSC substrates without rear base layers based on the use of templates described earlier. These 3-D thin-film TFSC substrates are then used in the formation of 3-D dual aperture TFSCs. The resulting hexagonal prism 3-D dual aperture TFSCs are uniquely suited for aesthetically appealing solar glass modules as shown in FIG. 21.
  • All of the embodiments shown in FIGS. 96 through 102 use sacrificial layer formation (e.g., porous silicon sacrificial layer) and trench-fill deposition processes (e.g., epitaxial silicon deposition) which may be highly conformal, for conformal formation of the sacrificial (porous silicon) layer and subsequent seamless void-free filling of the trenches with a semiconductor absorber layer such as in-situ-doped (e.g., in-situ boron doped) monocrystalline or multicrystalline silicon layer. One embodiment uses a patterned single-crystal (monocrystalline) silicon or multicrystalline silicon (mc-Si) square-shaped (or round) template, with dimensions of approximately 150 mm×150 mm to over 200 mm×200 mm. Alternative embodiments may use much lower cost metallurgical-grade or solar-grade silicon.
  • FIG. 96 shows an embodiment of a process flow 700 for fabrication of self-supporting (free standing) hexagonal-prism 3-D thin-film TFSC substrates using layer release processing. This process flow results in dual-aperture hexagonal-prism 3-D TFSC substrates with hexagonal prisms with open apertures formed on both the top and rear (there is no rear base layer). In step 702, a patterned hexagonal-prism (or another prism array) template is provided. This template has already been processed to form an embedded array of deep hexagonal-prism trenches. There is a patterned dielectric (oxide and/or nitride) hard mask on the template top and rear surfaces. Step 704 involves a multi-layer blanket epitaxial semiconductor deposition in an epitaxial growth reactor. Step 704 first involves an H2 or GeH4/H2 in-situ bake cleaning, which is performed after a standard pre-epitaxial wet clean (the latter if necessary). Next, a thin sacrificial epitaxial layer is deposited on the frontside only. In one embodiment, GexSi1-x is used for the sacrificial epitaxial layer and is between 10 and 2000 nanometers (in another embodiment a layer of porous silicon is directly deposited for the sacrificial layer). Next, a doped monocrystalline silicon epitaxial layer is deposited (in one embodiment, on the frontside only). In one embodiment, the layer is p-type, boron-doped and has a thickness between 1 and 30 microns. Step 706 involves selective silicon etch to selectively strip the top silicon layer, stopping on the sacrificial layer. First, the top silicon layer is removed using a selective (wet or dry) silicon etch process until the top GexSi1-x epitaxial layer (or porous silicon) or oxide/nitride hard mask is exposed. When using a plasma (dry) etch process, one embodiment uses optical end-point detection to ensure complete removal of the top silicon layer and exposure of the top sacrificial (GexSi1-x or porous silicon) layer. Step 708 involves 3-D thin-film TFSC substrate release using a selective etchant to etch the sacrificial layer. A highly selective isotropic (in one embodiment, wet) etch of GexSi1-x is performed, with very high selectivity with respect to silicon (in one embodiment, with etch selectivity much better than 100:1). In one embodiment, a mixture of hydrofluoric acid, nitric acid and acetic acid (HNA) is used to etch the sacrificial GexSi1-x layer (etchants such as H2O2+H2O or TMAH may be used to selectively etch porous silicon). Alternatively, a mixture of ammonia, peroxide, and water (NH4OH+H2O2+H2O) may be used. This process releases the crystalline silicon layer as a hexagonal-prism 3-D thin-film TFSC substrate, which may then be used for subsequent 3-D TFSC fabrication.
  • FIG. 97 shows a process flow 710 of an embodiment of a process flow for fabrication of self-supporting hexagonal-prism dual-aperture 3-D thin-film TFSC substrates using layer release processing. This process flow results in hexagonal-prism 3-D thin-film TFSC substrates comprising hexagonal-prisms with open apertures formed on both the 3-D thin-film TFSC substrate top and rear (there is no rear base layer). In step 712, a patterned hexagonal-prism template is provided. This template has already been processed to form an embedded array of deep trenches as described before. In this case, there are no dielectric hard mask layers on the template top and rear surfaces. Step 714 (multi-layer blanket epitaxial deposition) corresponds to step 704 in FIG. 96; step 716 (selective silicon etch) corresponds to step 706; step 718 (substrate release) corresponds to step 708. The resulting hexagonal-prism 3-D thin-film TFSC substrate may then be used for subsequent 3-D TFSC fabrication.
  • In the process flows described in FIGS. 96 and 97, while crystalline GexSi1-x is used as a sacrificial layer between the template and the in-situ-doped epitaxial silicon layer, other suitable sacrificial layers may be used. Alternative suitable materials include crystalline porous silicon (embodiments include microporous or mesoporous silicon), crystalline GeSiC, or SiC, among others. In the embodiments which use GexSi1-x as the sacrificial layer, the GexSi1-x layer is preferably between 50 nanometers and 3 microns thick, and more preferably between 0.1 and 1 micron. The germanium mole fraction (x) in the sacrificial layer is preferably between x=10% to x=45%, and more preferably between x=25% to x=40% in order o provide sufficient etch selectivity with respect to silicon. The germanium mole fraction should be high enough to achieve an acceptable high etch selectivity for removal of the GexSi1-x layer with minimal etching of silicon, while low enough to produce high-quality epitaxial silicon with sufficiently low defect density over the GexSi1-x sacrificial layer. The sacrificial layer may have a fixed germanium mole fraction throughout the sacrificial GexSi1-x layer or may also have graded mole fraction transition regions between the GexSi1-x layer and the template as well as between the GexSi1-x layer and the top in-situ-doped epitaxial silicon layer. Graded mole fraction transition regions result in a trapezoidal germanium mole fraction profile, first increasing from an x of 0% to an x of between 25% and 40% in the first transition region next to the template, then a GexSi1-x region with a fixed x between 25% and 40%, and a second transition region with x decreasing from an x of 40% to an x of 0% under the in-situ-doped epitaxial silicon layer. The transition regions with graded x and the middle layer with a fixed x may each be roughly between 10 nanometers and 1 micron thick.
  • Depending on the emitter doping type (n-type or p-type), the in-situ base doping type is chosen to be p-type (e.g., boron) or n-type (e.g., phosphorus). The embodiments shown in FIGS. 96 and 97 provide examples of boron-doped hexagonal prism 3-D thin-film TFSC substrates which may be used to fabricate TFSCs with n-type, phosphorus-doped selective emitters. In an alternative embodiment, all the doping polarities may be inverted, resulting in phosphorus-doped hexagonal-prism 3-D thin-film TFSC substrates which may be used for fabricating cells with boron-doped selective emitters.
  • FIGS. 96 through 98 show embodiments of process flows which utilize GexSi1-x as the sacrificial layer between the template and the epitaxial silicon TFSC substrate. FIGS. 96 and 97 depict embodiments of process flows which utilize blanket epitaxial silicon deposition as part of the process flow. On the other hand, FIG. 98 shows an alternative embodiment of a process flow 720 using selective epitaxial silicon deposition and layer release processing. The resulting 3-D dual-aperture thin-film TFSC substrates of FIG. 98 have open apertures on both substrate top and rear. In step 722, a patterned hexagonal-prism template is provided. This template has already been processed to form an embedded array of deep trenches. There is a patterned dielectric oxide and/or nitride (and/or another suitable dielectric such as diamond-like carbon or DLC, thin-film diamond, etc.) hard mask on the template top surfaces. Step 724 (multi-layer blanket epitaxy) corresponds to step 704 in FIG. 96. Note, however, that both the GexSi1-x sacrificial layer and the epitaxial silicon layer are selectively grown inside the trenches only. No layer is grown on the template top dielectric layer due to selective epitaxy (there is a patterned dielectric hard mask on top, such as oxide, nitride, DLC, etc.). Step 726 (substrate release) corresponds to step 718 in FIG. 97. The hexagonal-prism 3-D thin-film TFSC substrate may then be used for subsequent 3-D TFSC fabrication.
  • FIG. 99 depicts a process flow 730 of an embodiment of a process flow for fabrication of self-supporting hexagonal-prism 3-D dual-aperture thin-film TFSC substrates without rear base layers using layer release processing. Process flow 730 uses monocrystalline or quasi-monocrystalline porous (microporous or mesoporous) silicon (instead of GexSi1-x) as the sacrificial layer, and blanket epitaxial silicon fill. The dual-aperture hexagonal-prisms have open apertures on both top and rear. Step 732 (providing a substrate) corresponds to step 722 in FIG. 98. Step 734 involves forming a thin porous silicon sacrificial layer on template deep trenches (trench sidewalls and bottoms) using electrochemical HF etching (also known as electrochemical anodization of silicon). The porous silicon layer may be formed by one of two primary techniques as follows: (i) deposit a thin conformal crystalline silicon layer (in one embodiment, a p-type boron-doped silicon layer in the range of 0.2 to 2 microns) on an n-type template substrate, using silicon epitaxy, followed by conversion of the p-type epitaxial layer to porous silicon using electrochemical HF etching; or (ii) convert a thin layer of the template substrate (in one embodiment, a p-type template) to porous silicon (in one embodiment, in the thickness range of 0.01 to 1 micron). The sacrificial porous silicon formed by one of these two techniques also serves as a seed layer for subsequent epitaxial silicon deposition. Step 736 involves performing a hydrogen bake (at 950° to 1150° C.) to clean the surface and to form a continuous sealed monocrystalline surface layer on the surface of the porous silicon sacrificial layer, followed by depositing a blanket layer of doped silicon epitaxy (top only) in an epitaxial processing reactor. In one embodiment, the layer is p-type, boron-doped and has a thickness between 1 and 30 microns. Step 738 uses a selective (wet or dry) silicon etch process to strip the top silicon layer, until the top layer of porous silicon is exposed. When using a plasma (dry) etch process, one embodiment uses optical end-pointing to ensure complete removal of top silicon layer and exposure of the top porous silicon layer. Step 740 involves 3-D thin-film TFSC substrate release. A highly selective isotropic wet or dry etch of porous silicon is performed, with very high selectivity with respect to silicon. In one embodiment, a mixture of hydrofluoric acid, nitric acid and acetic acid (HNA) is used to etch the porous silicon layer. Alternatively, a mixture of ammonia, peroxide, and water (NH4OH+H2O2+H2O) or a mixture of hydrogen peroxide and hydrofluoric acid (H2O2+HF) or a suitable composition of tri-methyl-ammonium-hydroxide (TMAH) may be used. The etch composition and temperature may be adjusted to achieve maximum etch selectivity for porous silicon with respect to silicon. This process releases the embedded 3-D crystalline silicon structure as a hexagonal-prism 3-D thin-film TFSC substrate, which may then be used for subsequent 3-D TFSC fabrication.
  • FIG. 100 depicts a process flow 750 of an embodiment of a process flow for fabrication of self-supporting dual-aperture hexagonal-prism 3-D thin-film TFSC substrates without rear base layers using a porous silicon sacrificial layer and selective epitaxial silicon deposition. The main difference between FIGS. 99 and 100 is the epitaxial growth method. FIG. 100 uses selective epitaxy instead of blanket epitaxy as in FIG. 99. The use of selective epitaxy eliminates a process step to etch the top silicon layer before removal of the sacrificial layer for layer release. Referring to FIG. 100, step 752 (providing a substrate) corresponds to step 732 in FIG. 99; and step 754 (formation of porous silicon sacrificial layer) corresponds to step 734. In step 756, epitaxial silicon is selectively grown inside the template trenches only. In one embodiment, the epitaxial silicon layer is p-type, in-situ-boron-doped and has a thickness between 1 and 30 microns. No silicon layer is grown on the template top surface due to selective epitaxial growth, as there is a patterned dielectric (e.g., oxide and/or nitride) hard mask on top. Step 758 (substrate release) corresponds to step 738 in
  • FIG. 99. The hexagonal-prism 3-D thin-film TFSC substrate may then be used for subsequent 3-D TFSC fabrication. While FIGS. 99 and 100 show the use of porous silicon sacrificial layers for fabrication of dual-aperture TFSC substrates (without rear base layers), porous silicon can also be used as a sacrificial layer for fabrication of single-aperture TFSC substrates with rear base layers (using the appropriate template structure for single-aperture TFSC substrates, as described before).
  • The preceding FIGURES outline process flow embodiments which result in hexagonal-prism 3-D TFSC substrates made of a crystalline (monocrystalline or multicrystalline) semiconductor material (preferably crystalline silicon), through the use of conformal epitaxial deposition techniques. In alternative embodiments, 3-D TFSC substrates are made from polycrystalline or amorphous semiconductor materials (such as polysilicon or amorphous silicon). However, the resulting 3-D TFSCs may exhibit lower efficiencies compared to the 3-D TFSCs made from a crystalline semiconductor (e.g., monocrystalline or multicrystalline silicon).
  • FIGS. 101 and 102 depict embodiments of two process flows 760 and 780 for fabrication of self-supporting hexagonal-prism 3-D dual-aperture thin-film TFSC substrates without rear base layers using layer release processing but without the use of silicon epitaxy, unlike FIGS. 96 to 100 above. The template used in FIG. 101 has a patterned dielectric on the template frontside, while the template used in FIG. 102 has no dielectrics on either the frontside or backside. The sacrificial layer used in these process flows is simply a sacrificial dielectric layer such as SiO2. The silicon material is amorphous silicon and/or polysilicon, which may optionally be subsequently crystallized using laser crystallization to form large-grain polysilicon or multicrystalline silicon (and thermally annealed in order to reduce silicon film stress to facilitate release from the template). These process flows result in 3-D dual-aperture thin-film TFSC substrates with hexagonal-prism unit cells with open apertures on both top and rear.
  • Referring to FIG. 101, step 762 (providing a substrate) corresponds to step 752 from FIG. 100. Step 764 involves depositing a conformal sacrificial layer (or a layer stack). First, a thin layer of a sacrificial material is deposited by conformal layer formation (LPCVD or thermal oxidation). In one embodiment, the sacrificial material is SiO2, with a thickness of between 50 and 2000 nanometers. This sacrificial oxide layer conformally covers the hexagonal-prism trench walls and the template frontside. If subsequent laser crystallization is used (see step 772 below), step 764 also includes depositing a thin nitride layer by LPCVD. In one embodiment, this nitride layer is Si3N4, with a thickness between 100 and 1000 nanometers. The sacrificial layer may be made of porous silicon instead of oxide and/or nitride. Step 766 involves deposition of a blanket silicon layer using conformal deposition. In one embodiment, this blanket silicon layer may be amorphous silicon or polysilicon, p-type in-situ doped with boron, having a thickness between 1 and 30 microns. Step 768 uses selective silicon (wet or dry) etch to strip the top silicon layer, until the top surface of sacrificial layer (e.g., silicon dioxide or silicon nitride or porous silicon) is exposed. When using plasma (dry) etch process, one embodiment uses optical end-pointing to ensure complete removal of top silicon layer and exposure of the top porous silicon layer. If optional nitride is used, the top Si3N4 layer is etched using selective wet or dry etch. Step 770 involves 3-D thin-film TFSC substrate release. In one embodiment and when using a silicon dioxide sacrificial layer, hydrofluoric acid (HF) is used to etch the oxide sacrificial layer. In another embodiment and when using a porous silicon sacrificial layer, a mixture of ammonia, peroxide, and water (NH4OH+H2O2+H2O) or a mixture of hydrogen peroxide and hydrofluoric acid (H2O2+HF) or a suitable composition of tri-methyl-ammonium-hydroxide (TMAH) may be used. The etch composition and temperature may be adjusted to achieve maximum etch selectivity for porous silicon with respect to silicon. This process releases the hexagonal-prism 3-D thin-film TFSC substrate. An optional step 772 involves laser crystallization and/or thermal annealing of the released 3-D thin-film amorphous silicon or polysilicon substrate to form a large-grain polysilicon microstructure (and to reduce any residual stress for the embedded silicon structure), where the nitride layer serves as protective cap. The nitride layer is then selectively stripped. The hexagonal prism 3-D thin-film TFSC substrate may then be used for subsequent 3-D TFSC fabrication.
  • Referring to FIG. 102, in step 782, a patterned hexagonal-prism template is provided. This template has already been processed to form an embedded array of deep interconnected trenches. In this case, there are no dielectric hard mask layers on the template top and rear surfaces. Step 784 (conformal deposition of sacrificial layer) corresponds to step 764 of FIG. 101; step 786 (blanket silicon deposition) corresponds to step 766; step 788 (selective silicon etch) corresponds to step 768; step 790 (substrate release) corresponds to step 770; and step 792 (optional laser crystallization) corresponds to step 772. The hexagonal-prism 3-D thin-film TFSC substrate may then be used for subsequent 3-D TFSC fabrication.
  • FIGS. 103 through 107 show Y-Y cross-sectional views of the evolution of one prism unit cell of a template with through-wafer trenches 422, as it goes through several key process steps for fabricating a hexagonal-prism dual-aperture 3-D thin-film TFSC substrate without a rear base layer. The process flow outlined in these FIGURES includes the use of both blanket and selective epitaxial growth based on the relevant process flow embodiments described earlier. While shown with a dielectric stack on the template frontside and backside, the process flow using blanket epitaxial deposition may proceed without using the dielectric stack on the template frontside.
  • FIG. 103 shows a Y-Y cross-sectional view 800 of a template with through-wafer trenches 422 after deposition of a thin sacrificial layer (epitaxial GexSi1-x or porous silicon) 802 followed by deposition of a blanket in-situ-doped (e.g., boron-doped for p-type base) epitaxial silicon layer 804. The dielectric top hard mask layer is composed of a first top hard mask layer 436 of Si3N4 on top of a second top hard mask layer 438 of SiO2 on top of the template top surface 806. The sacrificial layer 802 forms a thin layer on both the sidewalls 808 and on the template top surface 806 (being formed on the top surface of the frontside dielectric 436). This sacrificial layer 802 forms a thin layer (e.g., 100 to 2000 nanometers thick) between the in-situ-doped (boron-doped) epitaxial silicon 804 and the template.
  • FIG. 104 shows a view 810 after a controlled silicon etch to remove the p-type silicon epitaxial layer 804 from the top of the template only (leaving epitaxial silicon in trenches). FIG. 105 shows a template view 820 after a highly selective wet etch process to remove the sacrificial layer 802 (GexSi1-x or porous silicon or another suitable layer) shown in FIG. 104. Removal of the sacrificial layer 802 results in the formation of a gap 972 between the template and the p-type silicon epitaxial layer (i.e., the 3-D thin-film TFSC substrate) 802, allowing for release and removal of the 3-D thin-film TFSC substrate from the template. Release of the substrate 804 may be facilitated by ultrasonic agitation and/or magnetically coupled etchant stirring during selective wet etching of the sacrificial layer 802. FIG. 106 shows a view 830 of the template after lifting off the p-type silicon epitaxial layer 804. The template 420 (see FIG. 39) is ready for multiple reuse cycles.
  • FIG. 107 shows three cross-sectional views. View 840 sh