US20170256541A1 - Method of forming super steep retrograde wells on finfet - Google Patents

Method of forming super steep retrograde wells on finfet Download PDF

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US20170256541A1
US20170256541A1 US15/599,751 US201715599751A US2017256541A1 US 20170256541 A1 US20170256541 A1 US 20170256541A1 US 201715599751 A US201715599751 A US 201715599751A US 2017256541 A1 US2017256541 A1 US 2017256541A1
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layer
fins
plurality
semiconductor structure
partial semiconductor
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Xusheng Wu
Qizhi Liu
David Harame
Renata Camillo-Castillo
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GlobalFoundries Inc
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GlobalFoundries Inc
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Priority to US15/010,189 priority Critical patent/US9721949B1/en
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Priority to US15/599,751 priority patent/US20170256541A1/en
Assigned to GLOBALFOUNDRIES INC. reassignment GLOBALFOUNDRIES INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CAMILLO-CASTILLO, RENATA, HARAME, DAVID, WU, XUSHENG, LIU, QIZHI
Publication of US20170256541A1 publication Critical patent/US20170256541A1/en
Assigned to WILMINGTON TRUST, NATIONAL ASSOCIATION reassignment WILMINGTON TRUST, NATIONAL ASSOCIATION SECURITY AGREEMENT Assignors: GLOBALFOUNDRIES INC.
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Abstract

A method of making a semiconductor structure is provided including providing a plurality of fins on a semiconductor substrate; depositing a layer containing silicon dioxide on the plurality of fins and on a surface of the semiconductor substrate; depositing a photoresist layer on one or more but less than all of the plurality of fins; etching the layer of silicon dioxide off of one or more of the plurality of fins on which the photoresist layer had not been deposited; stripping the photoresist layer; depositing a layer of pure boron on one or more of the plurality of fins on which a photoresist had not been deposited; and depositing a silicon nitride liner step on the plurality of fins. A partial semiconductor device fabricated by said method is also provided.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is a divisional of U.S. Non-Provisional Patent Application No. 15/010,189, which was filed on Jan. 29, 2016, which is hereby incorporated herein by reference in its entirety.
  • FIELD OF THE INVENTION
  • The present invention relates to semiconductor devices and methods of fabricating semiconductor devices, and more particularly, to methods and devices for forming super steep retrograde wells in FinFETs.
  • BACKGROUND OF THE INVENTION
  • Semiconductor structures, such as, integrated circuits are formed from semiconductor substrates within and upon whose surfaces may be formed electrical circuit elements such as transistors including field-effect transistors (FETs). Conventionally, field-effect transistors have been fabricated as planar circuit elements.
  • Fin field-effect transistor (FinFET) devices are currently being developed to replace conventional planar transistors, such as metal oxide semiconductor field-effect transistors (MOSFETs), in advanced complementary metal oxide semiconductor (CMOS) technology, due to their improved short channel effect immunity and higher on-current to off-current ratio (Ion/Ioff). As is known, the term “fin” refers to a vertical structure within or upon which are formed, for instance, one or more FinFETs or other fin devices, such as passive devices, including capacitors, diodes etc.
  • As described by Moore's Law, the semiconductor industry drives down pattern dimensions in order to reduce transistor size and enhance processor speed at a rapid pace. Further enhancements in fin device structures and fabrication methods therefor continue to be pursued for enhanced performance and commercial advantage. As the size of transistors, and components such as fin width and pitch, are reduced, obstacles pertaining to punchthrough of current may be encountered, hampering attempts to further reduce scale. The use of super steep retrograde wells (SSRW) in transistor design may ameliorate these difficulties, but conventional methodologies for forming SSRW preclude adopting fin widths and pitches below a certain minimum. Thus, an improved method for forming SSWR is needed.
  • SUMMARY OF THE INVENTION
  • The shortcomings of the prior art are overcome and additional advantages are provided through the provision, in one aspect, of a method of making a semiconductor structure including providing a plurality of fins on a semiconductor substrate; depositing a layer including silicon dioxide on the plurality of fins and on a surface of the semiconductor substrate; depositing a photoresist layer on one or more but less than all of the plurality of fins; etching the layer of silicon dioxide off of one or more of the plurality of fins on which the photoresist layer had not been deposited; stripping the photoresist layer; depositing a layer of pure boron on one or more of the plurality of fins on which a photoresist had not been deposited; and depositing a silicon nitride liner step on the plurality of fins.
  • In another aspect, the method includes depositing a layer of sacrificial oxide on the silicon nitride liner; recessing a portion of the layer of sacrificial oxide to expose a tip of the plurality of fins wherein the portion is less than all; removing the silicon nitride liner from the tip of the plurality of fins; removing a portion of the layer of phosphosilicate glass without removing a remainder of the layer of phosphosilicate glass and removing a portion of the layer of pure boron and without removing a remainder of the layer of pure boron, wherein the portion of the layer of phosphosilicate glass and the portion of the layer of pure boron are on the tip of the plurality of fins; and annealing the remainder of the layer of phosphosilicate glass and the remainder of the layer of pure boron to form a plurality of doped wells in the semiconductor substrate.
  • In another aspect, a partial semiconductor structure is provided, including a plurality of fins with sidewalls; a layer of pure boron on one or more of a first plurality of sidewalls; a first silicon nitride liner on the layer of pure boron; and a layer of oxide between the plurality of fins. In another aspect, the partial semiconductor substrate includes a layer of phosphosilicate glass on one or more of a second plurality of sidewalls; and a silicon nitride liner on the layer of phosphosilicate glass.
  • BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
  • One or more aspects of the present invention are particularly pointed out and distinctly claimed as examples in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
  • FIG. 1 depicts a partial semiconductor substrate in accordance with one or more aspects of the present invention;
  • FIG. 2 depicts the partial semiconductor substrate of FIG. 1 after layer of silicon dioxide has been deposited thereupon;
  • FIG. 3 depicts the partial semiconductor substrate of FIG. 2 after a lithographic patterning and etching of regions of the silicon;
  • FIG. 4 depicts the partial semiconductor substrate of FIG. 3 after stripping after the photoresist layer has been stripped to expose a silicon dioxide layer;
  • FIG. 5 depicts the partial semiconductor substrate of FIG. 4 after a pure boron layer has been selectively deposited over the substrate but not over the silicon dioxide layer;
  • FIG. 6 depicts the partial semiconductor substrate of FIG. 5 after deposition of a silicon nitride liner layer;
  • FIG. 7 depicts the partial semiconductor substrate of FIG. 6 deposition of an oxide layer followed by recessing the oxide layer to reveal the fins and etching the silicon nitride, boron, and silicon dioxide layers.
  • DETAILED DESCRIPTION OF THE INVENTION
  • Aspects of the present invention and certain features, advantages, and details thereof, are explained more fully below with reference to the non-limiting examples illustrated in the accompanying drawings. Descriptions of well-known materials, fabrication tools, processing techniques, etc., are omitted so as not to unnecessarily obscure the invention in detail. It should be understood, however, that the detailed description and the specific examples, while indicating aspects of the invention, are given by way of illustration only, and are not by way of limitation. Various substitutions, modifications, additions, and/or arrangements, within the spirit and/or scope of the underlying inventive concepts will be apparent to those skilled in the art from this disclosure.
  • Approximating language, as used herein throughout the specification and claims, may be applied to modify any quantitative representation that could permissibly vary without resulting in a change in the basic function to which it is related. Accordingly, a value modified by a term or terms, such as “about,” is not limited to the precise value specified. In some instances, the approximating language may correspond to the precision of an instrument for measuring the value.
  • The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprise” (and any form of comprise, such as “comprises” and “comprising”), “have” (and any form of have, such as “has” and “having”), “include (and any form of include, such as “includes” and “including”), and “contain” (and any form of contain, such as “contains” and “containing”) are open-ended linking verbs. As a result, a method or device that “comprises,” “has,” “includes” or “contains” one or more steps or elements possesses those one or more steps or elements, but is not limited to possessing only those one or more steps or elements. Likewise, a step of a method or an element of a device that “comprises,” “has,” “includes” or “contains” one or more features possesses those one or more features, but is not limited to possessing only those one or more features. Furthermore, a device or structure that is configured in a certain way is configured in at least that way, but may also be configured in ways that are not listed.
  • As used herein, the terms “may” and “may be” indicate a possibility of an occurrence within a set of circumstances; a possession of a specified property, characteristic or function; and/or qualify another verb by expressing one or more of an ability, capability, or possibility associated with the qualified verb. Accordingly, usage of “may” and “may be” indicates that a modified term is apparently appropriate, capable, or suitable for an indicated capacity, function, or usage, while taking into account that in some circumstances the modified term may sometimes not be appropriate, capable or suitable. For example, in some circumstances, an event or capacity can be expected, while in other circumstances the event or capacity cannot occur—this distinction is captured by the terms “may” and “may be.”
  • Reference is made below to the drawings, which are not drawn to scale for ease of understanding, wherein the same reference numbers may be used throughout different figures to designate the same or similar components.
  • Generally stated, disclosed herein is a method for forming super steep retrograde wells for n-doped and p-doped FinFETs. With progressively smaller dimensions of transistors, limitations arise that prevent optimal functioning. One difficulty is punchthrough, which results when depletion regions around the source and drain of a transistor merge by coming into contact with each other, which increases current leakage and drain and may short the channel. One solution is creating a super steep retrograde well (SSRW) to prevent merging of depletion regions. But the fabrication steps required for SSRW formation may themselves pose complications and further limitations on progressively reducing transistor scale.
  • Conventionally, SSRW are formed by depositing a thin layer of materials containing dopant on fins in a semiconductor device, followed by an annealing process to drive dopant into the substrate. For an NFET, a dopant such as boron may be deposited. Conventionally, boron-doped silicon dioxide in the form of borosilicate glass may be deposited, such as by chemical vapor deposition or other another appropriate method. For a PFET, a dopant source such as phosphosilicate glass may be used. After a dopant source is deposited, additional layers may be required, including a high quality oxide layer and cap layers such as silicon nitride cap. Minimum thicknesses of such layers may be on the order of 3 nm. This accumulating thickness of successive layers may ultimately occlude the space between fins. This may be particularly so for NFET SSRW because, during conventional fabrication, duplicative layers may need to be deposited during the formation of NFET SSRW.
  • For example, where NFET and PFET SSRW are both being fabricated on different fins of a semiconductor structure, depending on the order in which dopant-source layers are deposited before annealing, multiple cap layers may accumulate on NFET fins. For example, such fins may have a silicon nitride cap layer deposited on a boron-doped layer. During subsequent processing, a PFET dopant layer may be deposited elsewhere, followed by conformal deposition of a nitride cap layer on the PFET dopant layer which is also deposited on NFET fins, resulting in multiple nitride cap layers on NFET fins. Fabrication methods such as this that require deposition of functionally inconsequential layers undesirably limits the close spacing of fins that may otherwise permit further reductions of scale. For example, if adjacent NFET fins require conformal deposition of a boron-doped layer and nitride cap layer, a high quality oxide layer, and another nitride cap layer secondary to depositing a nitride cap layer on a dopant layer on PFET fins, there is a limit to how closely the NFET fins can be spaced before the space between them will be pinched off, leaving no room for, for example, depositing shallow trench isolation material therebetween, or creating gap fill complications even if the space is not completely pinched off.
  • The present invention eliminates the deposition of a functionally inconsequential nitride cap layer on NFET fins with a pre-anneal dopant-source layer for SSRW formation. A thin layer of pure boron may be conformally deposited as a dopant source for NFET SSRW, rather than boron-doped silicon dioxide, borosilicate glass, or other dopant sources. Moreover, pure boron may be selectively deposited on a silicon-based substrate and fins, without being deposited on areas where phosphate doped silicon dioxide, or where phosphosilicate glass, has been deposited as a dopant-source for PFET SSRW. This selective boron deposition, which may be done by chemical vapor deposition, allows for deposition of fewer, thinner layers during pre-anneal SSRW formation, in fewer overall steps, relative to conventional methods, facilitating processing, permitting a narrower pitch between fins and ameliorating complications due to gap fill problems for shallow trench isolation.
  • FIG. 1 shows a partial semiconductor structure 100 in which fins 110 have been defined on semiconductor substrate 120. Referring to FIG. 2, PFET SSRW dopant-source layer 200 is conformally deposited over the fins 110 and partial semiconductor substrate 100. In this example, PFET SSRW dopant-source layer 200 is deposited by chemical vapor deposition, and may be approximately 3 nm in thickness. Although PFET SSRW dopant-source layer 200 is conformally deposited over the fins 110, only some fins in this example are intended to have PFET SSRW. Patterning is required to remove PFET SSRW dopant-source layer 200 from fins that are not intended to have PFET SSRW.
  • FIG. 3 shows partial semiconductor substrate 100 after patterning regions for PFET SSRW formation. A lithographic process may be used to pattern intended PFET SSRW regions. In FIG. 3, resist layer 310 is shown, having been lithographically patterned over PFET SSRW fins 320, and nearby surface of substrate 120. No resist is present over fins 110. Subsequent to patterning resist 310, PFET SSRW dopant-source layer 200 was etched from fins 110 and adjacent surfaces of substrate 120 not protected by resist 310. Any etching process and etchant may be used for removing PFET SSRW dopant-source layer 200, such as a buffered hydrofluoric acid wet etch process to remove a silicon dioxide layer containing phosphorous as the PFET SSRW dopant-source layer 200.
  • After etching the PFET SSRW dopant-source layer 200, patterning resist layer 310 may be removed, resulting in the partial semiconductor structure 100 shown in FIG. 4. Subsequently, as shown in FIG. 5, a layer of pure boron 500 is conformally deposited over fins 100 and adjacent surface of semiconductor substrate 120. Specifically, a chemical vapor deposition process is used to deposit a thin layer selectively on surfaces lacking an exposed PFET SSRW dopant-source layer 200, such as a layer of silicon dioxide, or phosphosilicate glass. A thin layer of pure elemental boron 500, as thin as 1 nm, or thinner, may be deposited by conventional chemical deposition methods using an epitaxial chemical vapor deposition reactor, with diborane as the gas source and hydrogen gas as the carrier gas. Pure boron layer 500 will not deposit on PFET SSRW dopant-source layer 200, resulting in fins 320 and adjacent surfaces of semiconductor substrate 120 with a PFET SSRW dopant-source layer 200 deposited thereupon, and fins 110 and adjacent surfaces of semiconductor substrate 120 with an NFET SSRW dopant-source layer 500 deposited thereupon.
  • In FIG. 6, a silicon nitride cap layer has been conformally deposited over PFET SSRW dopant-source layer 200 and NFET SSRW dopant-source layer 500. Unlike conventional pre-anneal SSRW fabrication methods, only a single silicon nitride cap layer needs to be deposited in accordance with the present invention. FIG. 7 shows partial semiconductor device 100 several processing steps after that shown in FIG. 6, in accordance with some aspects of the present invention. In FIG. 7, a sacrificial oxide layer 700 has been deposited over fins 110 and 320 and semiconductor substrate 120 and was then etched back to reveal fins above sacrificial oxide layer 700. Silicon nitride cap layer 600, PFET SSRW dopant-source layer 200, and NFET SSRW dopant-source layer 500 may also be etched from the fin surfaces and sidewalls revealed above the recessed sacrificial oxide layer 700. A FET SSRW dopant-source layer 500 of pure boron may be removed by standard cleaning in HNO3 (at 110° C.−65° C.) followed by a HF dip etch to remove the resultant oxide. SSRW may then be formed by a standard annealing step to drive dopants from PFET SSRW dopant-source layer 200, and NFET SSRW dopant-source layer 500 into silicon to form wells.
  • The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprise” (and any form of comprise, such as “comprises” and “comprising”), “have” (and any form of have, such as “has” and “having”), “include” (and any form of include, such as “includes” and “including”), and “contain” (and any form contain, such as “contains” and “containing”) are open-ended linking verbs. As a result, a method or device that “comprises”, “has”, “includes” or “contains” one or more steps or elements possesses those one or more steps or elements, but is not limited to possessing only those one or more steps or elements. Likewise, a step of a method or an element of a device that “comprises”, “has”, “includes” or “contains” one or more features possesses those one or more features, but is not limited to possessing only those one or more features. Furthermore, a device or structure that is configured in a certain way is configured in at least that way, but may also be configured in ways that are not listed.
  • The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below, if any, are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiments were chosen and described in order to best explain the principles of one or more aspects of the invention and the practical application, and to enable others of ordinary skill in the art to understand one or more aspects of the invention for various embodiments with various modifications as are suited to the particular use contemplated.

Claims (20)

What is claimed is:
1. A partial semiconductor structure comprising:
a first plurality of fins comprising a first plurality of sidewalls;
a layer of pure boron on one or more sidewalls of the first plurality of sidewalls;
a silicon nitride liner on the layer of pure boron; and
a layer of oxide between two or more fins of first plurality of fins.
2. The partial semiconductor structure of claim 1 wherein a thickness of the layer of pure boron is less than 1 nm.
3. The partial semiconductor structure of claim 1 wherein a tip of one or more fin of the first plurality of fins is exposed above a top of the layer of oxide.
4. The partial semiconductor structure of claim 3 wherein the tip of one or more fin of the first plurality of fins is not covered by the layer of pure boron.
5. The partial semiconductor structure of claim 4 wherein a thickness of the layer of pure boron is less than 1 nm.
6. The partial semiconductor substrate of claim 1 further comprising:
a second plurality of fins comprising a second plurality of sidewalls;
a layer of phosphosilicate glass on one or more sidewalls of the second plurality of sidewalls;
a silicon nitride liner on the layer of phosphosilicate glass; and
a layer of oxide between two or more fins of the second plurality of fins.
7. The partial semiconductor structure of claim 6 wherein a thickness of the layer of pure boron is less than 1 nm.
8. The partial semiconductor structure of claim 6 wherein a tip of one or more fin of the first plurality of fins is exposed above a top of the layer of oxide.
9. The partial semiconductor structure of claim 8 wherein the tip of one or more fin of the first plurality of fins is not covered by the layer of pure boron.
10. The partial semiconductor structure of claim 9 wherein a thickness of the layer of pure boron is less than 1 nm.
11. The partial semiconductor structure of claim 6 wherein a tip of one or more fin of the second plurality of fins is exposed above a top of the layer of oxide.
12. The partial semiconductor structure of claim 11 wherein the tip of one or more fin of the second plurality of fins is not covered by the layer of phosphosilicate glass.
13. The partial semiconductor structure of claim 12 wherein a thickness of the layer of pure boron is less than 1 nm.
14. The partial semiconductor structure of claim 8 wherein a tip of one or more fin of the second plurality of fins is exposed above a top of the layer of oxide.
15. The partial semiconductor structure of claim 14 wherein the tip of one or more fin of the second plurality of fins is not covered by the layer phosphosilicate glass.
16. The partial semiconductor structure of claim 15 wherein a thickness of the layer of pure boron is less than 1 nm.
17. The partial semiconductor structure of claim 9 wherein a tip of one or more fin of the second plurality of fins is exposed above a top of the layer of oxide.
18. The partial semiconductor structure of claim 17 wherein the tip of one or more fin of the second plurality of fins is not covered by the layer of phosphosilicate glass.
19. The partial semiconductor structure of claim 18 wherein a thickness of the layer of pure boron is less than 1 nm.
20. A partial semiconductor structure comprising:
a first plurality of fins comprising a first plurality of sidewalls, a layer of pure boron on one or more sidewalls of the first plurality of sidewalls, a silicon nitride liner on the layer of pure boron, and a layer of oxide between two or more fins of first plurality of fins, wherein a thickness of the layer of pure boron is less than 1 nm, and a tip of one or more fin of the first plurality of fins is exposed above a top of the layer of oxide and is not covered by the layer of pure boron; and
a second plurality of fins comprising a second plurality of sidewalls, a layer of phosphosilicate glass on one or more sidewalls of the second plurality of sidewalls, a silicon nitride liner on the layer of phosphosilicate glass, and a layer of oxide between two or more fins of the second plurality of fins, wherein a tip of one or more fin of the second plurality of fins is exposed above a top of the layer of oxide and is not covered by the layer of phosphosilicate glass.
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US9607901B2 (en) * 2015-05-06 2017-03-28 Stmicroelectronics, Inc. Integrated tensile strained silicon NFET and compressive strained silicon-germanium PFET implemented in FINFET technology
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US8193080B2 (en) * 2009-07-27 2012-06-05 Panasonic Corporation Method for fabricating semiconductor device and plasma doping system

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