US20170184881A1 - Actively modulated plasmonic devices - Google Patents
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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- G02F1/025—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction in an optical waveguide structure
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Definitions
- the present disclosure relates generally to information systems, and more particularly to actively modulated plasmonic components.
- Information can be transferred electrically through copper wires, or optically through optical fibers and waveguides.
- efficient data transmission is the manipulation of the information-carrying signal, in order to transmit, route or receive information.
- the methods differ strongly between electrical and optical domains mainly because of their underlying physical mechanisms.
- active electronic building blocks e.g. transistors
- the optical counterparts are several 100 ⁇ m up to mm's in size, fundamentally limited by the diffraction limit and electro-optical manipulation efficiencies.
- These boundary conditions constitute a large size discrepancy being present between the electronic and optical building blocks. This offsets the greater bandwidth and speed advantages of photonic concepts and limits the attractiveness of a co-integration of optical and electronic components on the same platform with similar integration densities.
- SPPs Surface Plasmon Polaritons
- SPPs enable light to be confined to volumes of a few tens of nm 3 which enables light to be manipulated below the diffraction limit with very high efficiencies and further also guided along the dielectric-conductor interface at optical subwavelength dimensions and at optical frequencies.
- plasmon-based devices thus offer the potential of integrating optical components with dimensions much closer to state-of-the-art semiconductor electronic devices compared to today's photonic building blocks.
- micrometer-sized low-loss plasmonic modulators, switches, routers and mixers for co-integration of electronics and optics at nanometer dimensions below the diffraction limit, based on manipulation of plasmon propagations by controlling the free charge carrier concentration in a nano-metal sized semiconductor segment seamlessly embedded into the SPP-carrying waveguide and being electrically controlled causing a conductor-to insulator transition in the semiconductor segment.
- a plasmonic device may include: a conductor layer, an insulator layer, and a hybrid layer.
- the conductor may include electrical conducting materials such as metals, high doped semiconductors, and various nano-tubes.
- the conductor layer has a top surface and a bottom surface. The bottom surface of the conductor layer is generally disposed on a surface of a substrate.
- the conductor layer may include an input conductor segment, a manipulation conductor segment, and an output conductor segment.
- the insulator layer may include a top surface and a bottom surface, an input end, and an output end. The bottom surface of the insulator layer is disposed on the top surface of the conductor layer.
- the hybrid layer may include a top surface and a bottom surface. The bottom surface of the semiconductor layer is disposed on the top surface of the insulator layer.
- the hybrid layer may include an input segment, a semiconductor segment, and an output segment.
- a gate voltage V G is applied between two or more conductor segments of the hybrid layer such that surface plasmon polaritons (SPP) propagate from the input end to the output end of the insulator layer when the gate voltage V G is set to accumulate the semiconductor segment via an electric field.
- SPP surface plasmon polaritons
- one or two conductor layers are partially replaced by a semiconductor with an adjacent conductor layer to be employed as an electrical gate to induce a conductor-insulator transition in the semiconductor.
- a selected region of the plasmonic waveguide may be selectively turned off or on (or any state in between) to control signal transmission across this functional segment.
- the segments of the hybrid layer, and the conductor segment of the conductor layer may be arranged in various shapes to form various plamonic devices such as switches, modulators, routers, mixers, combiners, and splitters.
- FIG. 1 shows a sectional view of a hybrid conductor-semiconductor-conductor plasmonic device and a corresponding propagation distance-loss diagram in accordance with exemplary embodiments of the present disclosure
- FIG. 2 shows a sectional view of a dual-side gate and semiconductor plasmonic device and a corresponding propagation loss chart in accordance with certain embodiments of the present disclosure
- FIG. 3 is a top view of a plasmonic splitter along the A-A′ line of FIG. 2 in accordance with exemplary embodiments of the present disclosure
- FIG. 4 is a sectional view of a dual-side gate and semiconductor plasmonic mixer in accordance with certain exemplary embodiments of the present disclosure.
- FIG. 5 is a top view of the plasmonic mixer along the B-B′ line of FIG. 4 in accordance with exemplary embodiments of the present disclosure.
- pluricity means two or more.
- the terms “comprising,” “including,” “carrying,” “having,” “containing,” “involving,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to.
- FIGS. 1-5 in which certain exemplary embodiments of the present disclosure are shown.
- the present disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
- the hybrid conductor-semiconductor-conductor plasmonic device 100 may include: a conductor layer 130 , an insulator layer 120 , and a hybrid layer 110 .
- the conductor layer 130 has a top surface and a bottom surface. The bottom surface of the conductor layer 130 is disposed on a surface of a substrate.
- the conductor layer 130 may include an input segment 134 , a conductor segment 132 , and an output segment 136 .
- the segments 134 , 132 and 136 may include electrical conducting materials such as metals, high doped semiconductors, and various nano-tubes, and may be electronically isolated from one another by a thin dielectric layer.
- the insulator layer 120 may include a top surface and a bottom surface, an input end 122 , and an output end 124 .
- the bottom surface of the insulator layer 120 is disposed on the top surface of the conductor layer 130 .
- the hybrid layer 110 may include a top surface and a bottom surface.
- the bottom surface of the semiconductor layer 110 is disposed on the top surface of the insulator layer 120 .
- the hybrid layer 110 may include an input conductor segment 114 , a semiconductor segment 112 , and an output conductor segment 116 .
- the segments 112 , 114 and 116 may include electrical conducting materials such as metals, high doped semiconductors, and various nano-tubes, and may be electronically isolated from one another by a thin dielectric layer (not shown).
- the bottom surface of the hybrid layer 110 is in direct contact with the top surface of the insulator layer 120
- the top surface of the conductor layer 130 is in direct contact with the bottom surface of the insulator layer 120 , spatially forming a plasmonic conductor-insulator-conductor waveguide around the insulator layer 120 .
- SPPs Surface Plasmon Polaritons
- the plasmonic waveguide leads to a confinement of the propagating plasmonic waves so that most of its energy is contained within an insulator channel of the insulator layer 120 , and with evanescent fields penetrating into the conductor layer 130 and hybrid layer 110 on either side.
- one or more sections of the conductor cladding are replaced by one or more semiconductor segments. These semiconductor segments are in direct contact with the insulator layer 120 , forming a continuing path for SPP propagation. These semiconductor segments are electrically addressable enabling a bias to be applied in respect to the adjacent conductor layer. As shown in FIG. 1 , a gate voltage V G is applied between the semiconductor segment 112 of the hybrid layer 110 and the conductor segment 132 of the conductor layer 130 . By the electrically activated gate and the field effect in the semiconductor, the charge-carrier density in the semiconductor can be changed. Such charge-carrier density influences the propagation of SPPs along the semiconductor-insulator interface.
- the chart in FIG. 1 illustrates the propagation loss of the plasmonic device 100 when the V G is applied between the semiconductor segment 112 of the hybrid layer 110 and the conductor segment 132 of the conductor layer 130 .
- I in shows the SPP input density.
- the depleted semiconductor segment 112 suppress charge-carriers for SPP propagation along the depleted semiconductor segment 112 , therefore, the propagation loss is high and the I OUT is low, indicating an “OFF” state.
- the materials of the conductor layer 130 may include any good electrical conductor materials such gold, silver, copper, aluminum, titanium, platinum, and an alloy of these materials for applications in the visible range of the electromagnetic spectrum.
- these metals can also be replaced by highly doped semiconductors with possess less losses in the near-IR.
- the conductor should be able to sustain an SPP mode, i.e. it should have a negative real part of its permittivity and reasonably low optical losses.
- the materials of the semiconductor segment 112 of the hybrid layer 110 may include: GaAs, AlGaAs, InGaAsP, InP, GaP, GaN, ZnSe, ZnS, ZnO, HgCdTe, CdTe, InSb, GaSb, InAs, AgBr, AgF, AgCl, and CdS, as well as some 2D semiconductor materials such as WSe 2 , MoS 2 , black phosphorous, grapheme etc. where the charge-carrier density can be modified. It is important for the efficiency of modulation that the layer thickness is kept relatively thin (1-20 nm), so that the hybrid layer is modulated more or less throughout its thickness.
- the insulator layer 120 may use: air, SiO 2 , Al 2 O 3 , Si 3 N 4 , BaTiO 3 , ZrO 3 , a dielectric polymer, and any other suitable dielectric materials.
- a plasmonic modulator or a plasmonic switch can be made according to the structure of the plasmonic device 100 described above.
- the conductor segment 132 of the conductor layer 130 further comprises a second semiconductor segment 138 , which is separated from the conductor segment 132 by a thin dielectric layer 139 .
- the second semiconductor segment 138 may be disposed between the dielectric layer 139 , which is placed on top of the conductor segment 132 of the conductor layer 130 and the insulator layer 120 .
- the semiconductor segment 112 of the hybrid layer 110 further comprises a second conductor segment 118 , which is isolated from the hybrid segment 112 , by a thin dielectric layer 119 .
- the second conductor segment 118 may be disposed on the top surface of the thin dielectric layer 119 , which is placed directly adjacent to the semiconductor segment 112 of the hybrid layer 110 .
- a first gate voltage V i is applied between the second conductor segment 118 and the semiconductor segment 112 of the hybrid layer 210
- a second gate voltage V 2 is applied to the conductor segment 132 and the second semiconductor segment 138 of the conductor layer 130 to modulate the SPP propagation centered in the insulation layer 120 along the path from the input end 122 and the output end 124 of the insulator layer 120 .
- the dual-side gate and semiconductor plasmonic device 102 provides better performance as shown in the propagation loss chart of FIG. 2 .
- the first gate voltage V 1 and the second gate voltage V 2 are set to accumulation, a high accumulation carrier density is induced in both hybrid layers the SPPs propagate mainly inside the insulator layer 120 , this operation therefore, provides a high SPP density at the output end of the plasmonic device 102 , indicating an “ON” state.
- the carrier densities in the two hybrid layers is not sufficient to sustain an SPP mode, and the propagating SPPs inside the insulator layer 120 are completely shut off, therefore, provides zero SPP density at the output end of the plasmonic device 102 , indicating an “OFF” state.
- a plasmonic modulator or a plasmonic switch can be made according to the structure of the plasmonic device 102 described above.
- the output conductor segment 116 of the hybrid layer 110 may include one or more output conductor segments 116 - n (not shown in FIG. 3 ).
- the output segment 136 of the conductor layer 130 may include one or more output segments 136 - n.
- the semiconductor segment 112 of the hybrid layer 110 may include one or more semiconductor segments 112 - n (not shown in FIG. 3 ).
- the second conductor segment 118 of the hybrid layer 110 may include one or more second conductor segments 118 - n (not shown in FIG. 3 ).
- the conductor segment 132 of the conductor layer 130 may include one or more conductor segments 132 - n.
- the second semiconductor segment 138 of the conductor layer 130 may include one or more second semiconductor segments 138 - n.
- a thin dielectric layer is disposed between the output conductor segments 116 - n and the corresponding semiconductor segments 112 - n, between the input conductor segment 114 and the semiconductor segments 112 - n, between the output conductor segments 136 - n and the corresponding semiconductor segments 132 - n, between the input conductor segment 134 and the semiconductor segments 132 - n.
- the conductor segments 114 , 118 - n, 116 - n, 134 , 132 - n and 136 - n may include electrical conducting materials such as metals, high doped semiconductors, and various nano-tubes, and may be electronically isolated from one another by a thin dielectric layer.
- each of the semiconductor segments 112 - n of the hybrid layer 110 may have an input end, and an output end. Each of the input end of the semiconductor segments 112 - n of the hybrid layer 110 is plasmonically coupled to the input conductor segment 114 . Each of the output end of the semiconductor segments 112 - n of the hybrid layer 110 is plasmonically coupled to a corresponding one of the output conductor segments 116 - n of the hybrid layer 110 . Each of the second conductor segments 118 - n of the hybrid layer 110 may include an input end, and an output end. Each of the input end of the second conductor segments 118 - n of the hybrid layer 110 is plasmonically coupled to the input conductor segment 114 of the hybrid layer 110 . Each of the output end of the second conductor segments 118 - n of the hybrid layer 110 is plasmonically coupled to a corresponding one of the output conductor segments 116 - n of the hybrid layer 110 .
- Each of the conductor segments 132 - n of the conductor layer 130 may have an input end, and an output end, and each of the input end of the conductor segments 132 - n of the conductor layer 130 is plasmonically coupled to the input segment 134 of the conductor layer 130 .
- Each of the output end of the conductor segments 132 - n of the conductor layer 130 is plasmonically coupled to a corresponding one of the output segments 136 - n of the conductor layer 130 .
- Each of the second semiconductor segments 138 - n of the conductor later 130 may have an input end, and an output end.
- Each of the input end of the second semiconductor segments 138 - n of the conductor later 130 is plasmonically coupled to the input segment 134 of the conductor layer 130 .
- Each of the output end of the second semiconductor segments 138 - n of the conductor later 130 is plasmonically coupled to a corresponding one of the output segments 136 - n of the conductor layer 130 .
- Each of the first gate voltages V 1 - n is applied between a corresponding one of the semiconductor segments 112 - n and the second conductor segments 118 - n of the hybrid layer 110 to control the SPP propagation in the insulator layer 120 along the corresponding one of the semiconductor segments 112 - n and the second conductor segments 118 - n of the hybrid layer 110 , respectively.
- Each of the second gate voltages V 2 - n is applied between a corresponding one of the conductor segments 132 - n and the second semiconductor segments 138 - n of the conductor layer 130 to control the SPP propagation in the insulator layer 120 along the corresponding one of the conductor segments 132 - n and the second semiconductor segments 138 - n of the conductor layer 130 , respectively.
- a plasmonic splitter can be made according to the structure of the plasmonic device 104 described above.
- the SPP may propagate to input ends of the three semiconductor segments 112 - n of the hybrid layer 110 and three second semiconductor segments 138 - n of the conductor layer 130 .
- the SPP propagation paths along the three semiconductor segments 112 - n of the hybrid layer 110 and three second semiconductor segments 138 - n of the conductor layer 130 may be selectively shut off or turned on.
- the plasmonic device 104 is a two-way plasmonic splitter.
- the first SPP propagation path is formed by entering from the input segment 134 , propagating through the insulator layer 120 between the first semiconductor segments 112 - 1 of the hybrid layer 110 and the first second semiconductor segment 138 - 1 of the conductor layer 130 , and exiting through the insulator layer 120 between the first output conductor segment 116 - 1 and the first output segment 136 - 1 .
- the second SPP path is shut down by the negative V 1 - 2 and V 2 - 2 .
- the third SPP propagation path is formed by entering from the input segment 134 , propagating through the insulator layer 120 between the third semiconductor segments 112 - 3 of the hybrid layer 110 and the third second semiconductor segment 138 - 3 of the conductor layer 130 , and exiting through the insulator layer 120 between the third output conductor segment 116 - 3 and the third output segment 136 - 3 .
- the present invention relates to a plasmonic device 106 as shown in FIG. 4 and FIG. 5 .
- the input conductor segment 114 of the hybrid layer 110 may include one or more input conductor segments 114 - n (not shown in FIG. 5 ).
- the input segment 134 of the conductor layer 130 may include one or more input segments 134 - n .
- the semiconductor segment 112 of the hybrid layer 110 may include one or more input semiconductor segments 112 - 1 - n (not shown in FIG. 5 ).
- the second conductor segment 118 of the hybrid layer 110 may include one or more input second conductor segments 118 - 1 - n (not shown in FIG. 5 ).
- the conductor segment 132 of the conductor layer 130 may include one or more input conductor segments 132 - 1 - n .
- the second semiconductor segment 138 of the conductor layer 130 may include one or more input second semiconductor segments 138 - 1 - n.
- a thin dielectric layer is disposed between the input conductor segments 114 - n and the corresponding input semiconductor segments 112 - 1 - n , between the input segments 134 - n and the corresponding input semiconductor segments 138 - 1 - n , between the output conductor segments 116 - n and the corresponding output semiconductor segments 118 - 2 - n , between the output segments 136 - m and the corresponding output semiconductor segments 138 - 2 - m.
- a thin dielectric layer 119 - 1 is disposed between the input second conductor segments 118 - 1 - n (not shown in FIG. 5 ) and the corresponding input semiconductor segments 112 - 1 - n .
- a thin dielectric layer 139 - 1 is disposed between the input conductor segments 132 - 1 - n and the corresponding input semiconductor segments 138 - 1 - n .
- a thin dielectric layer 119 - 2 is disposed between the output second conductor segments 118 - 2 - m (not shown in FIG. 5 ) and the corresponding output semiconductor segments 112 - 2 - m.
- a thin dielectric layer 139 - 2 is disposed between the output conductor segments 132 - 2 - m and the corresponding output semiconductor segments 138 - 2 - m.
- the plasmonic device 106 may have the same number of the input conductor segments 114 - n , the input semiconductor segments 112 - 1 - n , and the input second conductor segments 118 - 1 - n of the hybrid layer 110 , and the input segments 134 - n, the conductor segments 132 - n , the second semiconductor segments 138 - n of the conductor layer 130 .
- each of the semiconductor segments 112 - 1 - n of the hybrid layer 110 may include an input end, and an output end. Each of the input end of the semiconductor segments 112 - 1 - n of the hybrid layer 110 is plasmonically coupled to a corresponding one of the input conductor segments 114 - n . Each of the output end of the semiconductor segments 112 - n of the hybrid layer 110 is plasmonically coupled to the output conductor segment 116 of the hybrid layer 110 . Each of the second conductor segments 118 - n of the hybrid layer 110 may include an input end, and an output end.
- Each of the input end of the second conductor segments 118 - n of the hybrid layer 110 is plasmonically coupled to a corresponding one of the input conductor segment 114 - n of the hybrid layer 110
- each of the output end of the second conductor segments 118 - n of the hybrid layer 110 is plasmonically coupled to the output conductor segment 116 of the hybrid layer 110 .
- Each of the conductor segments 132 - n of the conductor layer 130 may include an input end, and an output end. Each of the input end of the conductor segments 132 - n of the conductor layer 130 is plasmonically coupled to a corresponding one of the input segments 134 - n of the conductor layer 130 . Each of the output end of the conductor segments 132 - n of the conductor layer 130 is plasmonically coupled to the output segments 136 of the conductor layer 130 . Each of the second semiconductor segments 138 - n of the conductor later 130 may include an input end, and an output end.
- Each of the input end of the second semiconductor segments 138 - n of the conductor later 130 is plasmonically coupled to a corresponding one of the input segments 134 - n of the conductor layer 130 .
- Each of the output end of the second semiconductor segments 138 - n of the conductor later 130 is plasmonically coupled to the output segments 136 of the conductor layer 130 .
- the plasmonic device 106 may include equal number of first gate voltages V 1 - n and second gate voltages V 2 - n , as the same number of the input conductor segments 114 - n , the input semiconductor segments 112 - 1 - n , and the input second conductor segments 118 - 1 - n of the hybrid layer 110 , and the input segments 134 - n , the input conductor segments 132 - 1 - n , the input second semiconductor segments 138 - 1 - n of the conductor layer 130 .
- Each of the first gate voltages V 1 - n is applied between a corresponding one of the input semiconductor segments 112 - 1 - n and the input second conductor segments 118 - 1 - n of the hybrid layer 110 to control the SPP propagation in the insulator layer 120 along the corresponding input semiconductor segments 112 - 1 - n and the input second conductor segments 118 - 1 - n of the hybrid layer 110 .
- Each of the second gate voltages V 2 - n is applied between a corresponding one of the input conductor segments 132 - 1 - n and the input second semiconductor segments 138 - 1 - n of the conductor layer 130 to control the SPP propagation in the insulator layer 120 along the corresponding input conductor segments 132 - 1 - n and the input second semiconductor segments 138 - 1 - n of the conductor layer 130 .
- the plasmonic device 106 is a plasmonic mixer.
- the present invention relates to a plasmonic device 108 .
- the output conductor segment 116 of the hybrid layer 110 may include one or more output conductor segments 116 - m.
- the output segment 136 of the conductor layer 130 may include one or more output segments 136 - m.
- the semiconductor segment 112 of the hybrid layer 110 may further include one or more output semiconductor segments 112 - 2 - m.
- the second conductor segment 118 of the hybrid layer 110 may further include one or more output second conductor segments 118 - 2 - m.
- the conductor segment 132 of the conductor layer 130 may further include one or more output conductor segments 132 - 2 - m.
- the second semiconductor segment 138 of the conductor layer 130 may further include one or more output second semiconductor segments 138 - 2 - m.
- the number m may be different from the number n used in previous sections.
- the plasmonic device 108 may include same number of the output conductor segments 116 - m, the output semiconductor segments 112 - 2 - m, the output second conductor segments 118 - 2 - m of the hybrid layer 110 , and the output segments 136 - m, the output conductor segments 132 - 2 - m, the output second semiconductor segments 138 - 2 - m of the conductor layer 130 .
- each of the output semiconductor segments 112 - 2 - m of the hybrid layer 110 may include an input end, and an output end. Each of the input ends of the output semiconductor segments 112 - 2 - m of the hybrid layer 110 is plasmonically coupled to the output end of the input semiconductor segments 112 - 1 - n . Each of the output ends of the output semiconductor segments 112 - 2 - m of the hybrid layer 110 is plasmonically coupled to a corresponding one of the output conductor segments 116 - m of the hybrid layer 110 .
- Each of the output second conductor segments 118 - 2 - m of the hybrid layer 110 may include an input end, and an output end. Each of the input ends of the output second conductor segments 118 - 2 - m of the hybrid layer 110 is plasmonically coupled to the output end of the input semiconductor segments 112 - 1 - n . Each of the output ends of the output second conductor segments 118 - 2 - m of the hybrid layer 110 is plasmonically coupled to a corresponding one of the output conductor segments 116 - m of the hybrid layer 110 .
- Each of the output conductor segments 132 - 2 - m of the conductor layer 130 may include an input end, and an output end. Each of the input ends of the output conductor segments 132 - 2 - m of the conductor layer 130 is plasmonically coupled to the output end of the input conductor segments 132 - 1 - n of the conductor layer 130 . Each of the output ends of the output conductor segments 132 - 2 - m of the conductor layer 130 is plasmonically coupled to a corresponding one of the output segments 136 - m of the hybrid layer 110 .
- Each of the output second semiconductor segments 138 - 2 - m of the conductor later 130 may include an input end, and an output end. Each of the input ends of the output second semiconductor segments 138 - 2 - m of the conductor later 130 is plasmonically coupled to the output end of the input second semiconductor segments 138 - 1 - n of the conductor layer 130 . Each of the output ends of the output second semiconductor segments 138 - 2 - m of the conductor later 130 is plasmonically coupled to a corresponding one of the output segments 136 - m of the conductor layer 130 .
- the plasmonic device 108 may include equal number of third gate voltages V 3 - m and fourth gate voltages V 4 - m, as the same number of the output conductor segments 116 - n , the output semiconductor segments 112 - 2 - m, the output second conductor segments 118 - 2 - m of the hybrid layer 110 , and the output segments 136 - n , the output conductor segments 132 - 2 - m, the output second semiconductor segments 138 - 2 - m of the conductor layer 130 .
- Each of the third gate voltages V 3 - n is applied between a corresponding one of the output semiconductor segments 112 - 2 - m and the output second conductor segments 118 - 2 - m of the hybrid layer 110 to control the SPP propagation in the insulator layer 120 along the corresponding output semiconductor segments 112 - 2 - m and the output second conductor segments 118 - 2 - m of the hybrid layer 110 .
- Each of the fourth gate voltages V 4 - n is applied between a corresponding one of the output conductor segments 132 - 2 - m and the output second semiconductor segments 138 - 2 - m of the conductor layer 130 to control the SPP propagation in the insulator layer 120 along the corresponding output conductor segments 132 - 2 - m and the output second semiconductor segments 138 - 2 - m of the conductor layer 130 .
- the plasmonic device 108 is a plasmonic mixer.
- the present disclosure provides a solution to electrically manipulate SPP propagation in plasmonic waveguides, devices and circuits.
- This solution is fully compatible with large-scale manufacturing and integration. It enables the waveguides, devices and the circuits to process analog and digital signals in a much higher speed and greater bandwidths. It reduces the dimensions of the waveguides, devices, and circuits to sub-wavelength device dimensions, and provides high on/off contrast with low leakage and high extinction rates.
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Abstract
Description
- The present disclosure relates generally to information systems, and more particularly to actively modulated plasmonic components.
- Information can be transferred electrically through copper wires, or optically through optical fibers and waveguides. Of equal importance as efficient data transmission is the manipulation of the information-carrying signal, in order to transmit, route or receive information. Here, the methods differ strongly between electrical and optical domains mainly because of their underlying physical mechanisms. Whereas active electronic building blocks, e.g. transistors, are nowadays well below 100 nm in size, the optical counterparts are several 100 μm up to mm's in size, fundamentally limited by the diffraction limit and electro-optical manipulation efficiencies. These boundary conditions constitute a large size discrepancy being present between the electronic and optical building blocks. This offsets the greater bandwidth and speed advantages of photonic concepts and limits the attractiveness of a co-integration of optical and electronic components on the same platform with similar integration densities.
- Collective oscillations of electrons in a medium with free or mobile charge carriers, e.g. a metal or a highly-doped semiconductor, coupled to an optical wave at the interface of the metal and a dielectric are called Surface Plasmon Polaritons (SPP). SPPs enable light to be confined to volumes of a few tens of nm3 which enables light to be manipulated below the diffraction limit with very high efficiencies and further also guided along the dielectric-conductor interface at optical subwavelength dimensions and at optical frequencies. On the one hand, plasmon-based devices thus offer the potential of integrating optical components with dimensions much closer to state-of-the-art semiconductor electronic devices compared to today's photonic building blocks. This would enable not only increased bandwidth for short and long-range communication, electro-optical or all-optical switching etc., but furthermore a significant reduction in cost and total complexity due to the monolithic integration of electronic and optical components on a common platform. Therefore, it is desirable to create micrometer-sized low-loss plasmonic modulators, switches, routers and mixers for co-integration of electronics and optics at nanometer dimensions below the diffraction limit, based on manipulation of plasmon propagations by controlling the free charge carrier concentration in a nano-metal sized semiconductor segment seamlessly embedded into the SPP-carrying waveguide and being electrically controlled causing a conductor-to insulator transition in the semiconductor segment.
- Therefore, heretofore unaddressed needs still exist in the art to address the aforementioned deficiencies and inadequacies.
- In an embodiment of the present invention, a plasmonic device may include: a conductor layer, an insulator layer, and a hybrid layer. The conductor may include electrical conducting materials such as metals, high doped semiconductors, and various nano-tubes. The conductor layer has a top surface and a bottom surface. The bottom surface of the conductor layer is generally disposed on a surface of a substrate. In certain embodiments, the conductor layer may include an input conductor segment, a manipulation conductor segment, and an output conductor segment. The insulator layer may include a top surface and a bottom surface, an input end, and an output end. The bottom surface of the insulator layer is disposed on the top surface of the conductor layer. The hybrid layer may include a top surface and a bottom surface. The bottom surface of the semiconductor layer is disposed on the top surface of the insulator layer. In certain embodiments, the hybrid layer may include an input segment, a semiconductor segment, and an output segment.
- In certain embodiments, a gate voltage VG is applied between two or more conductor segments of the hybrid layer such that surface plasmon polaritons (SPP) propagate from the input end to the output end of the insulator layer when the gate voltage VG is set to accumulate the semiconductor segment via an electric field. When the gate voltage VG is set to deplete the semiconductor segment via the electric field, and the SPP propagation ceases.
- In certain embodiments, one or two conductor layers are partially replaced by a semiconductor with an adjacent conductor layer to be employed as an electrical gate to induce a conductor-insulator transition in the semiconductor. By local depletion or accumulation, a selected region of the plasmonic waveguide may be selectively turned off or on (or any state in between) to control signal transmission across this functional segment. In certain embodiments, the segments of the hybrid layer, and the conductor segment of the conductor layer may be arranged in various shapes to form various plamonic devices such as switches, modulators, routers, mixers, combiners, and splitters.
- These and other aspects of the present disclosure will become apparent from the following description of the preferred embodiment taken in conjunction with the following drawings and their captions, although variations and modifications therein may be affected without departing from the spirit and scope of the novel concepts of the disclosure.
- The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other features and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
-
FIG. 1 shows a sectional view of a hybrid conductor-semiconductor-conductor plasmonic device and a corresponding propagation distance-loss diagram in accordance with exemplary embodiments of the present disclosure; - FIG.2 shows a sectional view of a dual-side gate and semiconductor plasmonic device and a corresponding propagation loss chart in accordance with certain embodiments of the present disclosure;
- FIG.3 is a top view of a plasmonic splitter along the A-A′ line of
FIG. 2 in accordance with exemplary embodiments of the present disclosure; - FIG.4 is a sectional view of a dual-side gate and semiconductor plasmonic mixer in accordance with certain exemplary embodiments of the present disclosure; and
- FIG.5 is a top view of the plasmonic mixer along the B-B′ line of
FIG. 4 in accordance with exemplary embodiments of the present disclosure. - The present disclosure is more particularly described in the following examples that are intended as illustrative only since numerous modifications and variations therein will be apparent to those skilled in the art. Various embodiments of the disclosure are now described in detail. Referring to the drawings, like numbers, if any, indicate like components throughout the views. As used in the description herein and throughout the claims that follow, the meaning of “a”, “an”, and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein and throughout the claims that follow, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise. Moreover, titles or subtitles may be used in the specification for the convenience of a reader, which shall have no influence on the scope of the present disclosure. Additionally, some terms used in this specification are more specifically defined below.
- The terms used in this specification generally have their ordinary meanings in the art, within the context of the disclosure, and in the specific context where each term is used. Certain terms that are used to describe the disclosure are discussed below, or elsewhere in the specification, to provide additional guidance to the practitioner regarding the description of the disclosure. It will be appreciated that same thing can be said in more than one way. Consequently, alternative language and synonyms may be used for any one or more of the terms discussed herein, nor is any special significance to be placed upon whether or not a term is elaborated or discussed herein. The use of examples anywhere in this specification including examples of any terms discussed herein is illustrative only, and in no way limits the scope and meaning of the disclosure or of any exemplified term. Likewise, the disclosure is not limited to various embodiments given in this specification.
- Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. In the case of conflict, the present document, including definitions will control.
- As used herein, “plurality” means two or more. The terms “comprising,” “including,” “carrying,” “having,” “containing,” “involving,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to.
- “SPP” stands for Surface Plasmon Polaritons.
- The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings
FIGS. 1-5 , in which certain exemplary embodiments of the present disclosure are shown. The present disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. - Referring now to
FIG. 1 , a sectional view of a hybrid conductor-semiconductor-conductorplasmonic device 100 and a corresponding propagation distance-loss diagram in accordance with exemplary embodiments of the present disclosure are shown in accordance with exemplary embodiments of the present disclosure. The hybrid conductor-semiconductor-conductorplasmonic device 100 may include: aconductor layer 130, aninsulator layer 120, and ahybrid layer 110. Theconductor layer 130 has a top surface and a bottom surface. The bottom surface of theconductor layer 130 is disposed on a surface of a substrate. In certain exemplary embodiments, theconductor layer 130 may include aninput segment 134, aconductor segment 132, and anoutput segment 136. In certain embodiments, thesegments - In certain embodiments, the
insulator layer 120 may include a top surface and a bottom surface, aninput end 122, and anoutput end 124. The bottom surface of theinsulator layer 120 is disposed on the top surface of theconductor layer 130. Thehybrid layer 110 may include a top surface and a bottom surface. The bottom surface of thesemiconductor layer 110 is disposed on the top surface of theinsulator layer 120. In certain embodiments, thehybrid layer 110 may include aninput conductor segment 114, asemiconductor segment 112, and anoutput conductor segment 116. In certain embodiments, thesegments hybrid layer 110 is in direct contact with the top surface of theinsulator layer 120, and the top surface of theconductor layer 130 is in direct contact with the bottom surface of theinsulator layer 120, spatially forming a plasmonic conductor-insulator-conductor waveguide around theinsulator layer 120. Surface Plasmon Polaritons (SPPs) are propagating along conductor-insulator or semiconductor-insulator interfaces. The plasmonic waveguide leads to a confinement of the propagating plasmonic waves so that most of its energy is contained within an insulator channel of theinsulator layer 120, and with evanescent fields penetrating into theconductor layer 130 andhybrid layer 110 on either side. - In certain embodiments, one or more sections of the conductor cladding are replaced by one or more semiconductor segments. These semiconductor segments are in direct contact with the
insulator layer 120, forming a continuing path for SPP propagation. These semiconductor segments are electrically addressable enabling a bias to be applied in respect to the adjacent conductor layer. As shown inFIG. 1 , a gate voltage VG is applied between thesemiconductor segment 112 of thehybrid layer 110 and theconductor segment 132 of theconductor layer 130. By the electrically activated gate and the field effect in the semiconductor, the charge-carrier density in the semiconductor can be changed. Such charge-carrier density influences the propagation of SPPs along the semiconductor-insulator interface. When the VG is set to accumulate the semiconductor such that the semiconductor may change to “metal-like” (accumulated semiconductor). When the VG is set to deplete the semiconductor, the semiconductor may change to “insulator-like” (depleted semiconductor). The chart inFIG. 1 illustrates the propagation loss of theplasmonic device 100 when the VG is applied between thesemiconductor segment 112 of thehybrid layer 110 and theconductor segment 132 of theconductor layer 130. Iin shows the SPP input density. When the VG is set to accumulate thesemiconductor segment 112, the accumulatedsemiconductor segment 112 provides sufficient charge-carriers for SPP propagation along the accumulatedsemiconductor segment 112, therefore, the propagation loss is small and the IOUT is high, indicating an “ON” state. When the VG is set to deplete thesemiconductor segment 112, the depletedsemiconductor segment 112 suppress charge-carriers for SPP propagation along the depletedsemiconductor segment 112, therefore, the propagation loss is high and the IOUT is low, indicating an “OFF” state. By changing the gate voltage VG between accumulation to depletion, effectively controlling the SPP propagation in theinsulator layer 120 and turning the waveguide “on” or “off” for transmission. - In certain embodiments, the materials of the
conductor layer 130 may include any good electrical conductor materials such gold, silver, copper, aluminum, titanium, platinum, and an alloy of these materials for applications in the visible range of the electromagnetic spectrum. For near-Infrared applications, these metals can also be replaced by highly doped semiconductors with possess less losses in the near-IR. To serve as one side of a conductor-insolator-conductor waveguide the conductor should be able to sustain an SPP mode, i.e. it should have a negative real part of its permittivity and reasonably low optical losses. The materials of thesemiconductor segment 112 of thehybrid layer 110 may include: GaAs, AlGaAs, InGaAsP, InP, GaP, GaN, ZnSe, ZnS, ZnO, HgCdTe, CdTe, InSb, GaSb, InAs, AgBr, AgF, AgCl, and CdS, as well as some 2D semiconductor materials such as WSe2, MoS2, black phosphorous, grapheme etc. where the charge-carrier density can be modified. It is important for the efficiency of modulation that the layer thickness is kept relatively thin (1-20 nm), so that the hybrid layer is modulated more or less throughout its thickness. Theinsulator layer 120 may use: air, SiO2, Al2O3, Si3N4, BaTiO3, ZrO3, a dielectric polymer, and any other suitable dielectric materials. - A plasmonic modulator or a plasmonic switch can be made according to the structure of the
plasmonic device 100 described above. - Referring now to
FIG. 2 , a sectional view of a dual-side gate andsemiconductor plasmonic device 102 and a corresponding propagation loss chart are shown. In certain embodiments, theconductor segment 132 of theconductor layer 130 further comprises asecond semiconductor segment 138, which is separated from theconductor segment 132 by athin dielectric layer 139. Thesecond semiconductor segment 138 may be disposed between thedielectric layer 139, which is placed on top of theconductor segment 132 of theconductor layer 130 and theinsulator layer 120. Thesemiconductor segment 112 of thehybrid layer 110 further comprises asecond conductor segment 118, which is isolated from thehybrid segment 112, by athin dielectric layer 119. Thesecond conductor segment 118 may be disposed on the top surface of thethin dielectric layer 119, which is placed directly adjacent to thesemiconductor segment 112 of thehybrid layer 110. A first gate voltage Vi is applied between thesecond conductor segment 118 and thesemiconductor segment 112 of the hybrid layer 210, and a second gate voltage V2 is applied to theconductor segment 132 and thesecond semiconductor segment 138 of theconductor layer 130 to modulate the SPP propagation centered in theinsulation layer 120 along the path from theinput end 122 and theoutput end 124 of theinsulator layer 120. - In certain embodiments, the dual-side gate and
semiconductor plasmonic device 102 provides better performance as shown in the propagation loss chart ofFIG. 2 . When the first gate voltage V1 and the second gate voltage V2 are set to accumulation, a high accumulation carrier density is induced in both hybrid layers the SPPs propagate mainly inside theinsulator layer 120, this operation therefore, provides a high SPP density at the output end of theplasmonic device 102, indicating an “ON” state. When the first gate voltage V1 and the second gate voltage V2 are both set in depletion, the carrier densities in the two hybrid layers is not sufficient to sustain an SPP mode, and the propagating SPPs inside theinsulator layer 120 are completely shut off, therefore, provides zero SPP density at the output end of theplasmonic device 102, indicating an “OFF” state. - A plasmonic modulator or a plasmonic switch can be made according to the structure of the
plasmonic device 102 described above. - Another embodiment of the
plasmonic device 104 is shown inFIG. 3 according to certain embodiments of the present disclosure. Theoutput conductor segment 116 of the hybrid layer 110 (not shown inFIG. 3 ) may include one or more output conductor segments 116-n (not shown inFIG. 3 ). Theoutput segment 136 of theconductor layer 130 may include one or more output segments 136-n. Thesemiconductor segment 112 of the hybrid layer 110 (not shown inFIG. 3 ) may include one or more semiconductor segments 112-n (not shown inFIG. 3 ). Thesecond conductor segment 118 of the hybrid layer 110 (not shown inFIG. 3 ) may include one or more second conductor segments 118-n (not shown inFIG. 3 ). Theconductor segment 132 of theconductor layer 130 may include one or more conductor segments 132-n. Thesecond semiconductor segment 138 of theconductor layer 130 may include one or more second semiconductor segments 138-n. In certain embodiments, a thin dielectric layer is disposed between the output conductor segments 116-n and the corresponding semiconductor segments 112-n, between theinput conductor segment 114 and the semiconductor segments 112-n, between the output conductor segments 136-n and the corresponding semiconductor segments 132-n, between theinput conductor segment 134 and the semiconductor segments 132-n. In certain embodiments, theconductor segments 114, 118-n, 116-n, 134, 132-n and 136-n, may include electrical conducting materials such as metals, high doped semiconductors, and various nano-tubes, and may be electronically isolated from one another by a thin dielectric layer. - The
plasmonic device 104 shown inFIG. 3 , may be made by splitting thesemiconductor segment 112, thesecond conductor segment 118, and theoutput conductor segment 116 of thehybrid layer 110, theconductor segment 132, thesecond semiconductor segment 138, and theoutput segment 136 into n segments, here n=3. - In certain embodiments, each of the semiconductor segments 112-n of the
hybrid layer 110 may have an input end, and an output end. Each of the input end of the semiconductor segments 112-n of thehybrid layer 110 is plasmonically coupled to theinput conductor segment 114. Each of the output end of the semiconductor segments 112-n of thehybrid layer 110 is plasmonically coupled to a corresponding one of the output conductor segments 116-n of thehybrid layer 110. Each of the second conductor segments 118-n of thehybrid layer 110 may include an input end, and an output end. Each of the input end of the second conductor segments 118-n of thehybrid layer 110 is plasmonically coupled to theinput conductor segment 114 of thehybrid layer 110. Each of the output end of the second conductor segments 118-n of thehybrid layer 110 is plasmonically coupled to a corresponding one of the output conductor segments 116-n of thehybrid layer 110. - Each of the conductor segments 132-n of the
conductor layer 130 may have an input end, and an output end, and each of the input end of the conductor segments 132-n of theconductor layer 130 is plasmonically coupled to theinput segment 134 of theconductor layer 130. Each of the output end of the conductor segments 132-n of theconductor layer 130 is plasmonically coupled to a corresponding one of the output segments 136-n of theconductor layer 130. Each of the second semiconductor segments 138-n of the conductor later 130 may have an input end, and an output end. Each of the input end of the second semiconductor segments 138-n of the conductor later 130 is plasmonically coupled to theinput segment 134 of theconductor layer 130. Each of the output end of the second semiconductor segments 138-n of the conductor later 130 is plasmonically coupled to a corresponding one of the output segments 136-n of theconductor layer 130. - In certain embodiments, the
plasmonic device 104 may include equal number of first gate voltages V1-n and second gate voltages V2-n, as the same number of the output conductor segments 116-n, the semiconductor segments 112-n, and the second conductor segments 118-n of thehybrid layer 110, the output segments 136-n, the conductor segments 132-n, and the second semiconductor segments 138-n of theconductor layer 130, here n=3. Each of the first gate voltages V1-n is applied between a corresponding one of the semiconductor segments 112-n and the second conductor segments 118-n of thehybrid layer 110 to control the SPP propagation in theinsulator layer 120 along the corresponding one of the semiconductor segments 112-n and the second conductor segments 118-n of thehybrid layer 110, respectively. Each of the second gate voltages V2-n is applied between a corresponding one of the conductor segments 132-n and the second semiconductor segments 138-n of theconductor layer 130 to control the SPP propagation in theinsulator layer 120 along the corresponding one of the conductor segments 132-n and the second semiconductor segments 138-n of theconductor layer 130, respectively. - A plasmonic splitter can be made according to the structure of the
plasmonic device 104 described above. For example, when SPP enter theinsulator layer 120 through theinput end 122, the SPP may propagate to input ends of the three semiconductor segments 112-n of thehybrid layer 110 and three second semiconductor segments 138-n of theconductor layer 130. Depending on the first gate voltage V1-n and the second gate voltage V2-n, the SPP propagation paths along the three semiconductor segments 112-n of thehybrid layer 110 and three second semiconductor segments 138-n of theconductor layer 130 may be selectively shut off or turned on. - For example, when the V1-2 and V2-2 are both negative, and V1-1, V1-3, V2-1, V2-3 are both positive, the
plasmonic device 104 is a two-way plasmonic splitter. The first SPP propagation path is formed by entering from theinput segment 134, propagating through theinsulator layer 120 between the first semiconductor segments 112-1 of thehybrid layer 110 and the first second semiconductor segment 138-1 of theconductor layer 130, and exiting through theinsulator layer 120 between the first output conductor segment 116-1 and the first output segment 136-1. - The second SPP path is shut down by the negative V1-2 and V2-2.
- The third SPP propagation path is formed by entering from the
input segment 134, propagating through theinsulator layer 120 between the third semiconductor segments 112-3 of thehybrid layer 110 and the third second semiconductor segment 138-3 of theconductor layer 130, and exiting through theinsulator layer 120 between the third output conductor segment 116-3 and the third output segment 136-3. - In certain embodiments, the present invention relates to a
plasmonic device 106 as shown inFIG. 4 andFIG. 5 . Theinput conductor segment 114 of the hybrid layer 110 (not shown inFIG. 4 ) may include one or more input conductor segments 114-n (not shown inFIG. 5 ). Theinput segment 134 of theconductor layer 130 may include one or more input segments 134-n. Thesemiconductor segment 112 of thehybrid layer 110 may include one or more input semiconductor segments 112-1-n (not shown inFIG. 5 ). Thesecond conductor segment 118 of thehybrid layer 110 may include one or more input second conductor segments 118-1-n (not shown inFIG. 5 ). Theconductor segment 132 of theconductor layer 130 may include one or more input conductor segments 132-1-n. Thesecond semiconductor segment 138 of theconductor layer 130 may include one or more input second semiconductor segments 138-1-n. - In certain embodiments, a thin dielectric layer is disposed between the input conductor segments 114-n and the corresponding input semiconductor segments 112-1-n, between the input segments 134-n and the corresponding input semiconductor segments 138-1-n, between the output conductor segments 116-n and the corresponding output semiconductor segments 118-2-n, between the output segments 136-m and the corresponding output semiconductor segments 138-2-m.
- In certain embodiments, a thin dielectric layer 119-1 is disposed between the input second conductor segments 118-1-n (not shown in
FIG. 5 ) and the corresponding input semiconductor segments 112-1-n. A thin dielectric layer 139-1 is disposed between the input conductor segments 132-1-n and the corresponding input semiconductor segments 138-1-n. A thin dielectric layer 119-2 is disposed between the output second conductor segments 118-2-m (not shown inFIG. 5 ) and the corresponding output semiconductor segments 112-2-m. A thin dielectric layer 139-2 is disposed between the output conductor segments 132-2-m and the corresponding output semiconductor segments 138-2-m. - The
plasmonic device 106 may have the same number of the input conductor segments 114-n, the input semiconductor segments 112-1-n, and the input second conductor segments 118-1-n of thehybrid layer 110, and the input segments 134-n, the conductor segments 132-n, the second semiconductor segments 138-n of theconductor layer 130. - In certain embodiments, each of the semiconductor segments 112-1-n of the
hybrid layer 110 may include an input end, and an output end. Each of the input end of the semiconductor segments 112-1-n of thehybrid layer 110 is plasmonically coupled to a corresponding one of the input conductor segments 114-n. Each of the output end of the semiconductor segments 112-n of thehybrid layer 110 is plasmonically coupled to theoutput conductor segment 116 of thehybrid layer 110. Each of the second conductor segments 118-n of thehybrid layer 110 may include an input end, and an output end. Each of the input end of the second conductor segments 118-n of thehybrid layer 110 is plasmonically coupled to a corresponding one of the input conductor segment 114-n of thehybrid layer 110, and each of the output end of the second conductor segments 118-n of thehybrid layer 110 is plasmonically coupled to theoutput conductor segment 116 of thehybrid layer 110. - Each of the conductor segments 132-n of the
conductor layer 130 may include an input end, and an output end. Each of the input end of the conductor segments 132-n of theconductor layer 130 is plasmonically coupled to a corresponding one of the input segments 134-n of theconductor layer 130. Each of the output end of the conductor segments 132-n of theconductor layer 130 is plasmonically coupled to theoutput segments 136 of theconductor layer 130. Each of the second semiconductor segments 138-n of the conductor later 130 may include an input end, and an output end. Each of the input end of the second semiconductor segments 138-n of the conductor later 130 is plasmonically coupled to a corresponding one of the input segments 134-n of theconductor layer 130. Each of the output end of the second semiconductor segments 138-n of the conductor later 130 is plasmonically coupled to theoutput segments 136 of theconductor layer 130. - In certain embodiments, the
plasmonic device 106 may include equal number of first gate voltages V1-n and second gate voltages V2-n, as the same number of the input conductor segments 114-n, the input semiconductor segments 112-1-n, and the input second conductor segments 118-1-n of thehybrid layer 110, and the input segments 134-n, the input conductor segments 132-1-n, the input second semiconductor segments 138-1-n of theconductor layer 130. Each of the first gate voltages V1-n is applied between a corresponding one of the input semiconductor segments 112-1-n and the input second conductor segments 118-1-n of thehybrid layer 110 to control the SPP propagation in theinsulator layer 120 along the corresponding input semiconductor segments 112-1-n and the input second conductor segments 118-1-n of thehybrid layer 110. Each of the second gate voltages V2-n is applied between a corresponding one of the input conductor segments 132-1-n and the input second semiconductor segments 138-1-n of theconductor layer 130 to control the SPP propagation in theinsulator layer 120 along the corresponding input conductor segments 132-1-n and the input second semiconductor segments 138-1-n of theconductor layer 130. - In certain embodiments, the
plasmonic device 106 is a plasmonic mixer. - In certain embodiments, the present invention relates to a
plasmonic device 108. Theoutput conductor segment 116 of thehybrid layer 110 may include one or more output conductor segments 116-m. Theoutput segment 136 of theconductor layer 130 may include one or more output segments 136-m. Thesemiconductor segment 112 of thehybrid layer 110 may further include one or more output semiconductor segments 112-2-m. Thesecond conductor segment 118 of thehybrid layer 110 may further include one or more output second conductor segments 118-2-m. Theconductor segment 132 of theconductor layer 130 may further include one or more output conductor segments 132-2-m. Thesecond semiconductor segment 138 of theconductor layer 130 may further include one or more output second semiconductor segments 138-2-m. The number m may be different from the number n used in previous sections. - In certain embodiments, the
plasmonic device 108 may include same number of the output conductor segments 116-m, the output semiconductor segments 112-2-m, the output second conductor segments 118-2-m of thehybrid layer 110, and the output segments 136-m, the output conductor segments 132-2-m, the output second semiconductor segments 138-2-m of theconductor layer 130. - In certain embodiments, each of the output semiconductor segments 112-2-m of the
hybrid layer 110 may include an input end, and an output end. Each of the input ends of the output semiconductor segments 112-2-m of thehybrid layer 110 is plasmonically coupled to the output end of the input semiconductor segments 112-1-n. Each of the output ends of the output semiconductor segments 112-2-m of thehybrid layer 110 is plasmonically coupled to a corresponding one of the output conductor segments 116-m of thehybrid layer 110. - Each of the output second conductor segments 118-2-m of the
hybrid layer 110 may include an input end, and an output end. Each of the input ends of the output second conductor segments 118-2-m of thehybrid layer 110 is plasmonically coupled to the output end of the input semiconductor segments 112-1-n. Each of the output ends of the output second conductor segments 118-2-m of thehybrid layer 110 is plasmonically coupled to a corresponding one of the output conductor segments 116-m of thehybrid layer 110. - Each of the output conductor segments 132-2-m of the
conductor layer 130 may include an input end, and an output end. Each of the input ends of the output conductor segments 132-2-m of theconductor layer 130 is plasmonically coupled to the output end of the input conductor segments 132-1-n of theconductor layer 130. Each of the output ends of the output conductor segments 132-2-m of theconductor layer 130 is plasmonically coupled to a corresponding one of the output segments 136-m of thehybrid layer 110. - Each of the output second semiconductor segments 138-2-m of the conductor later 130 may include an input end, and an output end. Each of the input ends of the output second semiconductor segments 138-2-m of the conductor later 130 is plasmonically coupled to the output end of the input second semiconductor segments 138-1-n of the
conductor layer 130. Each of the output ends of the output second semiconductor segments 138-2-m of the conductor later 130 is plasmonically coupled to a corresponding one of the output segments 136-m of theconductor layer 130. - In certain embodiments, the
plasmonic device 108 may include equal number of third gate voltages V3-m and fourth gate voltages V4-m, as the same number of the output conductor segments 116-n, the output semiconductor segments 112-2-m, the output second conductor segments 118-2-m of thehybrid layer 110, and the output segments 136-n, the output conductor segments 132-2-m, the output second semiconductor segments 138-2-m of theconductor layer 130. - Each of the third gate voltages V3-n is applied between a corresponding one of the output semiconductor segments 112-2-m and the output second conductor segments 118-2-m of the
hybrid layer 110 to control the SPP propagation in theinsulator layer 120 along the corresponding output semiconductor segments 112-2-m and the output second conductor segments 118-2-m of thehybrid layer 110. - Each of the fourth gate voltages V4-n is applied between a corresponding one of the output conductor segments 132-2-m and the output second semiconductor segments 138-2-m of the
conductor layer 130 to control the SPP propagation in theinsulator layer 120 along the corresponding output conductor segments 132-2-m and the output second semiconductor segments 138-2-m of theconductor layer 130. - In certain embodiments, the
plasmonic device 108 is a plasmonic mixer. - The present disclosure provides a solution to electrically manipulate SPP propagation in plasmonic waveguides, devices and circuits. This solution is fully compatible with large-scale manufacturing and integration. It enables the waveguides, devices and the circuits to process analog and digital signals in a much higher speed and greater bandwidths. It reduces the dimensions of the waveguides, devices, and circuits to sub-wavelength device dimensions, and provides high on/off contrast with low leakage and high extinction rates.
- The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
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EP3428695A1 (en) * | 2017-07-13 | 2019-01-16 | Samsung Electronics Co., Ltd. | Optical modulation device and method of operating the same |
CN109901253A (en) * | 2019-03-22 | 2019-06-18 | 江南大学 | A kind of surface plasma fluid filter |
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EP3428695A1 (en) * | 2017-07-13 | 2019-01-16 | Samsung Electronics Co., Ltd. | Optical modulation device and method of operating the same |
US10670941B2 (en) | 2017-07-13 | 2020-06-02 | Samsung Electronics Co., Ltd. | Optical modulation device and method of operating the same |
US11480918B2 (en) * | 2019-02-28 | 2022-10-25 | Samsung Electronics Co., Ltd. | Active complex spatial light modulation method and apparatus for an ultra-low noise holographic display |
CN109901253A (en) * | 2019-03-22 | 2019-06-18 | 江南大学 | A kind of surface plasma fluid filter |
US20210157179A1 (en) * | 2019-11-25 | 2021-05-27 | Huawei Technologies Canada Co., Ltd. | Apparatus for plasmonic nanoantenna optical beam phase-shifter and steerer |
US11914190B2 (en) | 2021-01-25 | 2024-02-27 | Huawei Technologies Co., Ltd. | Optical-phased array beam-steerer |
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