US20170149440A1 - Method for adaptively regulating coding mode and digital correction circuit thereof - Google Patents
Method for adaptively regulating coding mode and digital correction circuit thereof Download PDFInfo
- Publication number
- US20170149440A1 US20170149440A1 US15/356,478 US201615356478A US2017149440A1 US 20170149440 A1 US20170149440 A1 US 20170149440A1 US 201615356478 A US201615356478 A US 201615356478A US 2017149440 A1 US2017149440 A1 US 2017149440A1
- Authority
- US
- United States
- Prior art keywords
- digital
- correction circuit
- detected value
- equal
- digital correction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
- H03M1/1033—Calibration over the full range of the converter, e.g. for correcting differential non-linearity
- H03M1/1038—Calibration over the full range of the converter, e.g. for correcting differential non-linearity by storing corrected or correction values in one or more digital look-up tables
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/44—Sequential comparisons in series-connected stages with change in value of analogue signal
- H03M1/442—Sequential comparisons in series-connected stages with change in value of analogue signal using switched capacitors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
- H03M1/468—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors in which the input S/H circuit is merged with the feedback DAC array
Definitions
- Step S 503 if the first detected value K is equal to (N+M ⁇ 1), the digital correction circuit 19 renews a (N+M) th digital bit in the digital bit sequence as an inverse of a (N+M ⁇ 1) th digital bit in the digital bit sequence.
- Step S 505 the digital correction circuit 19 uses a binary weighted ratio corresponding to (N+M) comparison cycles to encode the digital bit sequence to provide the digital output code corresponding to the analog signal.
Abstract
A method for adaptively regulating a coding mode and a digital correction circuit thereof are provided. The method is for a successive-approximation-register analog-to-digital converter (SAR ADC). In the method, whether to regulate a binary weight corresponding to each of digital bits is determined according to the number of completed comparison cycles to provide a first coding sequence. The first coding sequence is directly compensated according to uncompleted comparison cycles to provide a correct digital output code.
Description
- 1. Technical Field
- The present disclosure generally relates to a method for adaptively regulating a coding mode and a digital correction circuit thereof and, more particularly, to a method for adaptively regulating a coding mode and a digital correction circuit thereof for a successive-approximation-register analog-to-digital converter (SAR ADC).
- 2. Description of Related Art
- Conventionally, a SAR ADC uses a binary search algorithm to acquire a digital output code matched with the input analog signal. During the conversion process, the digital-to-analog converter (DAC) circuit of the SAR ADC generally adds/subtracts a binary ratio voltage to/from a reference voltage based on each of the comparison results of the comparator until the difference between the input signal and the reference voltage becomes smaller than a least significant bit (LSB) after a final required comparison cycle is completed.
- However, the conversion time of the SAR ADC may vary under different process-voltage-temperature (PVT) variations. For example, if the PVT variations shorten the conversion time, the SAR ADC fails to complete the final required comparison cycle within a given time period. In other words, the actual number of completed comparison cycles is smaller than an expected value, resulting in an incorrect output result.
- In view of this, there is a need for overcoming the problem of the conversion time of a SAR ADC varying due to PVT variations, in order to obtain a correct output result even with different numbers of completed comparison cycles.
- The present disclosure provides a method for adaptively regulating a coding mode and a digital correction circuit thereof. The method is for a successive-approximation-register analog-to-digital converter (SAR ADC). In the method, whether to regulate a binary weight corresponding to each of the digital bits is determined according to the number of completed comparison cycles to obtain a first coding sequence. The first coding sequence is directly compensated according to uncompleted comparison cycles to output a correct digital output code. Thereby, under different PVT variations, the SAR ADC effectively eliminates the conversion time variations due to PVT variations in order to obtain a correct output result even with different numbers of completed comparison cycles.
- In order to further understand the techniques, means and effects of the present disclosure, the following detailed descriptions and appended drawings are hereby referred to, such that, and through which, the purposes, features and aspects of the present disclosure can be thoroughly and concretely appreciated; however, the appended drawings are merely provided for reference and illustration, without any intention to be used for limiting the present disclosure.
- The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.
-
FIG. 1 is a schematic diagram of a SAR ADC according to one embodiment of the present disclosure; -
FIG. 2 is a flowchart of a method for adaptively regulating a coding mode according to one embodiment of the present disclosure; -
FIG. 3 is a schematic diagram of a SAR ADC according to another embodiment of the present disclosure; -
FIG. 4 is a flowchart of regulating a coding rule for a digital correction circuit according to one embodiment of the present disclosure to provide a digital output code; -
FIG. 5 is a flowchart of regulating a coding rule for a digital correction circuit according to another embodiment of the present disclosure to provide a digital output code; and -
FIG. 6 is a functional block diagram of a digital correction circuit according to one embodiment of the present disclosure. - The detailed description set forth below in connection with the appended drawings is intended as a description of certain embodiments of the present disclosure, and is not intended to represent the only forms that may be developed or utilized. The description sets forth the various functions in connection with the illustrated embodiments, but it is to be understood, however, that the same or equivalent functions may be accomplished by different embodiments that are also intended to be encompassed within the scope of the present disclosure.
- The method for adaptively regulating a coding mode and the digital correction circuit thereof according to the present disclosure can be applicable to any SAR ADC. In brief, the present disclosure is not limited to how a SAR ADC is implemented.
- For example, referring to
FIG. 1 ,FIG. 1 is a schematic diagram of a SAR ADC according to one embodiment of the present disclosure. The SAR ADC 1 includes twosymmetric capacitor arrays comparator 15, a SARcontrol logic circuit 17 and adigital correction circuit 19. Thecapacitor array 11 is switchably electrically connected to a positive analog input voltage terminal Vip, and thecapacitor array 13 is switchably electrically connected to a negative analog input voltage terminal Vin. - Furthermore, each of the
capacitor arrays capacitor arrays - Then, the
comparator 15 includes two input terminals configured to receive the output of thecapacitor arrays control logic circuit 17 is configured to sequentially analyze corresponding digital bits B1˜CN+M according to the output result of thecomparator 15, and sequentially control the switching contacts of the switching capacitors C1˜CN in each of thecapacitor arrays capacitor arrays digital correction circuit 19 is coupled to the SARcontrol logic circuit 17 and is configured to process the digital bits B1˜BN+M according to a conventional coding rule to provide a digital output code including N bits. It should be noted that the SAR ADC 1 is known to persons with ordinary skill in the art and thus detailed descriptions of the elements previously stated are not repeated herein. - In summary, the
SAR ADC 1 is capable of converting an analog signal to a relatively correct digital output code only after the SARcontrol logic circuit 17 has successfully completed (N+M) comparison cycles (in other word, the SARcontrol logic circuit 17 has to correspondingly analyze a digital bit sequence [B1:BN+M]). However, as previously stated, due to PVT variations, the SARcontrol logic circuit 17 may not complete the (N+M)th comparison cycle within a given time period, which results in an incorrect digital output code. Accordingly, the conventional art is limited by the foregoing problem. - Therefore, referring to
FIG. 2 ,FIG. 2 is a flowchart of a method for adaptively regulating a coding mode according to one embodiment of the present disclosure. It should be noted that the method inFIG. 2 is applicable to theSAR ADC 1 inFIG. 1 . Please also refer toFIG. 1 for better understanding. However, the present disclosure is not limited thereto. - First, in Step S201, the
digital correction circuit 19 detects the number of comparison cycles completed by the SARcontrol logic circuit 17 with respect to an analog signal as a first detected value K so that thedigital correction circuit 19 acquires the digital bit sequence correspondingly analyzed by the SARcontrol logic circuit 17. Moreover, in Step S203, thedigital correction circuit 19 determines whether the first detected value K is equal to (N+M). - Then, in Step S205, the
digital correction circuit 19 determines whether the first detected value K is larger than or equal to a pre-determined threshold value if the first detected value K is not equal to (N+M). Finally, in Step S207, thedigital correction circuit 19 regulates a coding rule so that thedigital correction circuit 19 provides a digital output code corresponding to the analog signal according to the regulated coding rule if the first detected value K is larger than or equal to the pre-determined threshold value. - More particularly, since the SAR
control logic circuit 17 is capable of counting the number of completed comparison cycles, Step S201 in the method according to the present disclosure enables thedigital correction circuit 19 to acquire the number of comparison cycles completed by the SARcontrol logic circuit 17 with respect to an analog signal by detecting the counted value of the SARcontrol logic circuit 17. - Then, the actual number of digital bits analyzed by the SAR
control logic circuit 17 can be evaluated according to the acquired number of comparison cycles completed (i.e., the first detected value K). For example, in Step S201, thedigital correction circuit 19 only acquires the digital bits B1˜B6 analyzed by the SARcontrol logic circuit 17 if the first detected value K is 6. - Moreover, as previously stated, the
digital correction circuit 19 is capable of processing the digital bit sequence [B1:BN+M] based on the conventional coding rule to provide the correct digital output code only after the SARcontrol logic circuit 17 has successfully completed (N+M) comparison cycles. Therefore, one of the aspects of the present disclosure is to enable thedigital correction circuit 19 to determine whether to regulate the coding rule by detecting the number of comparison cycles completed by the SARcontrol logic circuit 17 so as to prevent thedigital correction circuit 19 from using an inadequate coding rule to provide an incorrect digital output code. - On the other hand, if the first detected value K is equal to (N+M), it indicates that the SAR
control logic circuit 17 has successfully completed (N+M) comparison cycles. Therefore, thedigital correction circuit 19 can directly process the digital bit sequence [B1:BN+M] based on the conventional coding rule to provide a correct digital output code. Therefore, returning toFIG. 2 , if the first detected value K is equal to (N+M), Step S209 in the method of the present disclosure can be conducted to enable thedigital correction circuit 19 not to regulate the coding rule so that thedigital correction circuit 19 provides the digital output code corresponding to the analog signal according to the unregulated coding rule. - Moreover, from a more general point of view, if the first detected value K is smaller than a pre-determined threshold value (for example, N), it indicates that the SAR
control logic circuit 17 can only complete a very small number of comparison cycles. Therefore, whether or not thedigital correction circuit 19 regulates the conventional coding rule, theSAR ADC 1 may fail to provide the correct digital output code. In view of the above problem, the method of the present disclosure will not emphasize further research or investigations thereof Therefore, if the first detected value K is smaller than a pre-determined threshold value, the teachings of the present disclosure can still be used in Step S209. In summary, the present disclosure is not limited to any implementation when the first detected value K is smaller than a pre-determined threshold value. Persons with ordinary skill in the art may make any modifications according to practical demands or applications. Moreover, a detailed description on how the pre-determined threshold value is defined will be presented herein. - According to the teachings stated above, persons with ordinary skill in the art should understand that one of the aspects of the present disclosure is to dynamically regulate the coding rule of the
digital correction circuit 19 by detecting the number of comparison cycles completed by the SARcontrol logic circuit 17 so that thedigital correction circuit 19 may use an adequate coding rule to provide a correct digital output code. Accordingly, the output result of theSAR ADC 1 stays correct under ideal conditions (i.e., when (N+M) comparison cycles successfully completed). - Another example will be presented to further exemplify how the coding rule of the digital correction circuit is regulated to provide a correct digital output code in an adaptive regulating coding method provided by the present disclosure. Referring to
FIG. 3 ,FIG. 3 is a schematic diagram of a SAR ADC according to another embodiment of the present disclosure. Some elements inFIG. 3 identical to the elements inFIG. 1 are labeled in the same way as inFIG. 1 , and thus descriptions thereof are not repeated herein. Compared to theSAR ADC 1 inFIG. 1 , twocapacitor arrays 11′ and 13′ of theSAR ADC 1′ inFIG. 3 include, respectively, 4 switching capacitors C1˜C4 and 2 redundant capacitors C′1˜C′2 that are connected in parallel. In other words, the parameter N is 4, and the parameter M is 2. - Therefore, according to the teachings stated above, persons with ordinary skill in the art would understand that, in the
SAR ADC 1′, thedigital correction circuit 19 is capable of processing the digital bit sequence [B1:B6] based on the conventional coding rule to provide the 4-bit digital output code only after the SARcontrol logic circuit 17 has to complete 6 comparison cycles. However, due to PVT variations, thedigital correction circuit 19 can actually acquire only the digital bits B1˜B5 while the SARcontrol logic circuit 17 can complete only 5 comparison cycles. Therefore, thedigital correction circuit 19 will provide an incorrect 4-bit digital output code if thedigital correction circuit 19 inFIG. 3 processes the digital bit sequence [B1:B6] based on the conventional coding rule. - For example, as known from the conventional art, the processing of the digital bit sequence [B1:B6] based on the conventional coding rule uses the binary weighted ratio with respect to 6 (i.e., (N+M)) comparison cycles (for example, the weighting of the 6th digital bit B6 is set to be 1, the weighting of the 5th digital bit B5 is set to be 2, etc.) to encode the digital bit sequence [B1:B6]. However, since the 6th digital bit B6 in the digital bit sequence [B1:B6] cannot be analyzed, (in other words, the 6th digital bit B6 may not even exist), the digital output code [1, 2, 3, 4] which the
digital correction circuit 19 should provide may be replaced by an incorrect digital output code [0, 2, 2, 4]. It should be noted that encoding the digital bit sequence using the binary weighted ratio is known to persons with ordinary skill in the art, and thus descriptions thereof are not repeated herein. - Returning to
FIG. 3 , since the capacities of the last two redundant capacitors C′1˜C′2 in thecapacitor arrays 11′ and 13′ are both 1C, persons with ordinary skill in the art would understand that the SARcontrol logic circuit 17 only omits executing the switching on the last capacitor with a capacity of 1C when the SARcontrol logic circuit 17 inFIG. 3 completes 5 comparison cycles. Therefore, the method of the present disclosure can control thedigital correction circuit 19 inFIG. 3 to use the binary weighted ratio with respect to 5 comparison cycles (for example, the weighting of the 6th digital bit B6 is set to be 0, the weighting of the 5th digital bit B5 is set to be 1, etc.) to encode the digital bit sequence [B1:B6] to provide a first coding sequence [0, 1, 2, 3] including N elements and add 1 to each element in the first coding sequence [0, 1, 2, 3] (to compensate the omitted switching on the last capacitor with a capacity of 1C) to provide the digital output code corresponding to the analog signal. Accordingly, thedigital correction circuit 19 can provide the digital output code [1, 2, 3, 4] so that the output result stays correct under ideal conditions (i.e., when 6 comparison cycles are successfully completed). - Similarly, when the SAR
control logic circuit 17 inFIG. 3 only completes 4 comparison cycles (i.e., both the 5th digital bit B5 and the 6th digital bit B6 cannot be analyzed), the method of the present disclosure can control thedigital correction circuit 19 inFIG. 3 to use the binary weighted ratio with respect to 4 comparison cycles (for example, both the weighting of the 6th digital bit B6 and the weighting of the 5th digital bit B5 are set to be 0, the weighting of the 4th digital bit B4 is set to be 1, etc.) to encode the digital bit sequence [B1:B6] to provide a first coding sequence including N elements and add 2 to each element in the first coding sequence (to compensate the omitted switching on the last two capacitors with a capacity of 1C) to provide the correct digital output code [1, 2, 3, 4]. - Therefore, according to the teachings stated above, persons with ordinary skill in the art would understand that the method of the present disclosure determines whether to regulate the binary weight corresponding to the digital bits according to the number of completed comparison cycles (i.e., the first detected value K) to encode the digital bit sequence to provide a first coding sequence. Then, the first coding sequence is compensated with respect to the uncompleted comparison cycle to provide the correct digital output code. Accordingly, the output result stays correct under different numbers of comparison cycles completed by the SAR ADC.
- Based on the teachings stated above, the present disclosure further provides implementations of Step S207. Referring to
FIG. 4 ,FIG. 4 is a flowchart of regulating a coding rule for a digital correction circuit according to one embodiment of the present disclosure to provide a digital output code. Steps inFIG. 4 identical to the steps inFIG. 2 are labeled in the same way as inFIG. 2 , and thus descriptions thereof are not repeated herein. - Referring to
FIG. 1 ,FIG. 2 andFIG. 4 , Step S207 further includes Step S401˜Step S405. First, in Step S401, thedigital correction circuit 19 acquires a difference value between (N+M) and the first detected value. Then, in Step S403, thedigital correction circuit 19 uses a binary weighted ratio corresponding to the first detected value K to encode the digital bit sequence to provide a first coding sequence including N elements. Finally, in Step S405, thedigital correction circuit 19 adds the value of each of the N elements in the first coding sequence to the difference value, respectively, to provide the digital output code corresponding to the analog signal. It should be noted that, in Step S401, the acquired difference value can be regarded as the number R of comparison cycles uncompleted by the SARcontrol logic circuit 17 with respect to the analog signal. - On the other hand, as shown in
FIG. 1 , the capacity of each of the redundant capacitors C′1˜C′M is 1C. For the uncompleted comparison cycles, when the SARcontrol logic circuit 17 only omits executing the switching on the last R capacitor(s) with a capacity of 1C, Step S405 enables thedigital correction circuit 19 to add a value of each of the elements in the first coding sequence to the difference value, respectively, (to compensate the omitted switching on the last R capacitor(s) with a capacity of 1C). In other words, R is any positive integer within a range from 1 to M. Therefore, the pre-determined threshold value in Step S205 is a positive integer larger than or equal to N (i.e., the number of the switching capacitors C1˜CN) and smaller than (N+M). - Practically, the pre-determined threshold value in the method of the present disclosure can be set to be N to broaden the applications of adaptive regulation, to which the present disclosure is not limited thereof Furthermore, taking the
SAR ADC 1′ inFIG. 3 for example, when the pre-determined threshold value is set to be 4 (i.e., the number of the switching capacitors C1˜C4) and the SARcontrol logic circuit 17 successfully completes 4 or 5 comparison cycles, thedigital correction circuit 19 can use Step S401˜Step S405 inFIG. 4 to make the output result of theSAR ADC 1′ stay correct under ideal conditions (i.e., when 6 comparison cycles successfully completed). - Moreover, another example will be presented to further exemplify how the coding rule of the digital correction circuit is regulated to provide a correct digital output code according to the present disclosure. Referring to
FIG. 5 ,FIG. 5 is a flowchart of regulating a coding rule for a digital correction circuit according to another embodiment of the present disclosure to provide a digital output code. Steps inFIG. 5 identical to the steps inFIG. 2 are labeled in the same way as inFIG. 2 , and thus descriptions thereof are not repeated herein. - Referring to
FIG. 1 ,FIG. 2 andFIG. 5 , as previously stated, when the SARcontrol logic circuit 17 only completes (N+M−1) comparison cycles, it indicates that the SARcontrol logic circuit 17 only omits executing the switching on the last capacitor with a capacity of 1C. Therefore, compared to the steps inFIG. 4 , in Step S501, if the first detected value K is larger than or equal to a pre-determined threshold value, the method of the present disclosure enables thedigital correction circuit 19 to further determine whether the first detected value K is equal to (N+M−1). After that, in Step S503, if the first detected value K is equal to (N+M−1), thedigital correction circuit 19 renews a (N+M)th digital bit in the digital bit sequence as an inverse of a (N+M−1)th digital bit in the digital bit sequence. Finally, in Step S505, thedigital correction circuit 19 uses a binary weighted ratio corresponding to (N+M) comparison cycles to encode the digital bit sequence to provide the digital output code corresponding to the analog signal. - Taking the
SAR ADC 1′ inFIG. 3 for example, when the SARcontrol logic circuit 17 completes only 5 (i.e., (N+M−1)) comparison cycles, the method of the present disclosure renews the 6th digital bit B6 in the digital bit sequence [B1:B6] as an inverse of a 5th digital bit in the digital bit sequence, and uses a binary weighted ratio with respect to 6 comparison cycles to encode the renewed digital bit sequence [B1:B6] to provide the correct digital output code [1, 2, 3, 4]. - In order to describe the flowchart of the adaptive regulating coding method, the present disclosure further provides a digital correction circuit. Referring to
FIG. 6 ,FIG. 6 is a functional block diagram of a digital correction circuit according to one embodiment of the present disclosure. However, the description of thedigital correction circuit 19 is only an example of implementing the method, to which the present disclosure is not limited. It should be noted that thedigital correction circuit 19 inFIG. 6 is applicable to theSAR ADC 1 inFIG. 1 . Please refer toFIG. 1 for better understanding. - More particularly, the
digital correction circuit 19 includes a detecting and receivingunit 61 and a deciding andprocessing unit 63. These units can be implemented by hardware circuitry, or by hardware circuitry with firmware or with software. In summary, the present disclosure is not limited to the example of thedigital correction circuit 19. Moreover, the detecting and receivingunit 61 and the deciding andprocessing unit 63 can be integrated or disposed separately, to which the present disclosure is not limited. - Furthermore, the detecting and receiving
unit 61 is configured to detect a number of comparison cycles completed by the SARcontrol logic circuit 17 with respect to an analog signal as a first detected value K. The detecting and receivingunit 61 is configured to acquire the digital bit sequence correspondingly analyzed by the SARcontrol logic circuit 17. - The deciding and
processing unit 63 is configured to determine whether the first detected value K is equal to (N+M) to determine whether the first detected value K is larger than or equal to a pre-determined threshold value if the first detected value K is not equal to (N+M). The deciding andprocessing unit 63 regulates a coding rule to provide a digital output code corresponding to the analog signal according to the regulated coding rule if the first detected value K is larger than or equal to the pre-determined threshold value. - It should be noted that the deciding and
processing unit 63 is capable of executing the steps inFIG. 4 orFIG. 5 to regulate the coding rule of the digital correction circuit to provide the digital output code. Please refer toFIG. 4 andFIG. 5 for better understanding, and detailed descriptions thereof are not repeated herein. - As previously stated, the present disclosure provides a method for adaptively regulating a coding mode and a digital correction circuit thereof The coding rule of the digital correction circuit is dynamically regulated according to the detected number of comparison cycles completed by the SAR control logic circuit so that the digital correction circuit uses an adequate coding rule to provide a correct digital output code. Thereby, under different PVT variations, the SAR ADC effectively eliminates the conversion time variations due to PVT variations to obtain a correct output result with different numbers of completed comparison cycles.
- The above-mentioned descriptions represent merely the exemplary embodiment of the present disclosure, without any intention to limit the scope of the present disclosure thereto. Various equivalent changes, alterations or modifications based on the claims of the present disclosure are all consequently viewed as being embraced by the scope of the present disclosure.
Claims (10)
1. A method for adaptively regulating a coding mode for a successive-approximation-register analog-to-digital converter (SAR ADC), said SAR ADC comprising at least one capacitor array, a comparator, a SAR control logic circuit and a digital correction circuit, said capacitor array comprising N switching capacitors and M redundant capacitors that are connected in parallel, said SAR control logic circuit being configured to correspondingly analyze a digital bit sequence sequentially according to an output result of said comparator, and said method comprising:
(a) enabling said digital correction circuit to detect the number of comparison cycles completed by said SAR control logic circuit with respect to an analog signal as a first detected value so that said digital correction circuit acquires said digital bit sequence correspondingly analyzed by said SAR control logic circuit;
(b) enabling said digital correction circuit to determine whether said first detected value is equal to (N+M), and enabling said digital correction circuit to determine whether said first detected value is larger than or equal to a pre-determined threshold value if said first detected value is not equal to (N+M); and
(c) enabling said digital correction circuit to regulate a coding rule so that said digital correction circuit provides a digital output code corresponding to said analog signal according to said regulated coding rule if said first detected value is larger than or equal to said pre-determined threshold value;
wherein N is a positive integer larger than 1, and M is a positive integer larger than 1.
2. The method of claim 1 , wherein said pre-determined threshold value is a positive integer larger than or equal to N and smaller than (N+M).
3. The method of claim 1 , wherein said digital correction circuit does not regulate said coding rule so that said digital correction circuit provides said digital output code corresponding to said analog signal according to said coding rule unregulated if said first detected value is equal to (N+M).
4. The method of claim 1 , wherein step (c) comprises:
enabling said digital correction circuit to acquire a difference value between (N+M) and said first detected value;
enabling said digital correction circuit to use a binary weighted ratio corresponding to said first detected value to encode said digital bit sequence to provide a first coding sequence comprising N elements; and
enabling said digital correction circuit to add a value of each of said N elements in said first coding sequence to said difference value, respectively, to provide said digital output code corresponding to said analog signal.
5. The method of claim 1 , wherein step (c) comprises:
enabling said digital correction circuit to determine whether said first detected value is equal to (N+M−1);
enabling said digital correction circuit to renew a (N+M)th digital bit in said digital bit sequence as an inverse of a (N+M−1)th digital bit in said digital bit sequence if said first detected value is equal to (N+M−1); and
enabling said digital correction circuit to use a binary weighted ratio corresponding to (N+M) comparison cycles to encode said digital bit sequence to provide said digital output code corresponding to said analog signal.
6. A digital correction circuit for adaptively regulating a coding mode for a successive-approximation-register analog-to-digital converter (SAR ADC), said SAR ADC comprising at least one capacitor array, a comparator and a SAR control logic circuit, said capacitor array comprising N switching capacitors and M redundant capacitors that are connected in parallel, said SAR control logic circuit being configured to correspondingly analyze a digital bit sequence sequentially according to an output result of said comparator, and said digital correction circuit comprising:
a detecting and receiving unit configured to detect the number of comparison cycles completed by said SAR control logic circuit with respect to an analog signal as a first detected value to acquire said digital bit sequence correspondingly analyzed by said SAR control logic circuit; and
a deciding and processing unit configured to determine whether said first detected value is equal to (N+M), to determine whether said first detected value is larger than or equal to a pre-determined threshold value if said first detected value is not equal to (N+M), and to regulate a coding rule to provide a digital output code corresponding to said analog signal according to said regulated coding rule if said first detected value is larger than or equal to said pre-determined threshold value;
wherein N is a positive integer larger than 1, and M is a positive integer larger than 1.
7. The digital correction circuit of claim 6 , wherein said pre-determined threshold value is a positive integer larger than or equal to N and smaller than (N+M).
8. The digital correction circuit of claim 6 , wherein said deciding and processing unit does not regulate said coding rule so that said deciding and processing unit provides said digital output code corresponding to said analog signal according to said coding rule unregulated if said first detected value is equal to (N+M).
9. The digital correction circuit of claim 6 , wherein said deciding and processing unit is configured to:
acquire a difference value between (N+M) and said first detected value;
use a binary weighted ratio corresponding to said first detected value to encode said digital bit sequence to provide a first coding sequence comprising N elements; and
add a value of each of said N elements in said first coding sequence to said difference value, respectively, to provide said digital output code corresponding to said analog signal.
10. The digital correction circuit of claim 6 , wherein said deciding and processing unit is configured to:
determine whether said first detected value is equal to (N+M−1);
renew a (N+M)th digital bit in said digital bit sequence as an inverse of a (N+M−1)th digital bit in said digital bit sequence if said first detected value is equal to (N+M−1); and
use a binary weighted ratio corresponding to (N+M) comparison cycles to encode said digital bit sequence to provide said digital output code corresponding to said analog signal.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW104139157A TWI572144B (en) | 2015-11-25 | 2015-11-25 | Method and digital correction circuit for adaptive regulating coding mode |
TW104139157 | 2015-11-25 | ||
TW104139157A | 2015-11-25 |
Publications (2)
Publication Number | Publication Date |
---|---|
US9654127B1 US9654127B1 (en) | 2017-05-16 |
US20170149440A1 true US20170149440A1 (en) | 2017-05-25 |
Family
ID=58608359
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/356,478 Active US9654127B1 (en) | 2015-11-25 | 2016-11-18 | Method for adaptively regulating coding mode and digital correction circuit thereof |
Country Status (2)
Country | Link |
---|---|
US (1) | US9654127B1 (en) |
TW (1) | TWI572144B (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI665875B (en) * | 2018-02-13 | 2019-07-11 | 新唐科技股份有限公司 | Digital background calibration circuit |
CN113141182A (en) * | 2020-01-20 | 2021-07-20 | 瑞昱半导体股份有限公司 | Analog-digital converter device and capacitance weight correction method |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI656744B (en) * | 2017-05-19 | 2019-04-11 | 瑞昱半導體股份有限公司 | Capacitor layout of integrated circuit |
TWI653836B (en) | 2017-08-15 | 2019-03-11 | 瑞昱半導體股份有限公司 | Correcting device of successive approximation analog-to-digital conversion |
CN107733436B (en) | 2017-11-07 | 2018-11-30 | 深圳锐越微技术有限公司 | N mixed structure analog-digital converters and the IC chip comprising it |
TWI672006B (en) * | 2018-09-28 | 2019-09-11 | 新唐科技股份有限公司 | Successive approximation register analog-to-digital converter and control method thereof |
TWI779967B (en) * | 2021-12-14 | 2022-10-01 | 瑞昱半導體股份有限公司 | Comparison circuit and operation method thereof having adaptive comparison mechanism |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8164504B2 (en) * | 2010-03-16 | 2012-04-24 | Electronics And Telecommunications Research Institute | Successive approximation register analog-digital converter and method for operating the same |
US8451151B2 (en) * | 2011-08-15 | 2013-05-28 | Himax Technologies Limited | Successive approximation analog to digital converter with capacitor mismatch calibration and method thereof |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8471751B2 (en) * | 2011-06-30 | 2013-06-25 | Intel Corporation | Two-stage analog-to-digital converter using SAR and TDC |
TWI462489B (en) * | 2011-08-18 | 2014-11-21 | Himax Tech Ltd | Successive approximation analog to digital converter with capacitor mismatch calibration and method thereof |
TWI536748B (en) * | 2012-08-06 | 2016-06-01 | 瑞昱半導體股份有限公司 | Successive approximation analog-to-digital converter and successive approximation analog-to-digital conversion method |
TWI509996B (en) * | 2013-05-15 | 2015-11-21 | Realtek Semiconductor Corp | Successive-approximation-register analog-to-digital converter (sar adc) with programmable gain of amplitude of input signal and method therefor |
CN104734716B (en) * | 2013-12-24 | 2017-12-12 | 瑞昱半导体股份有限公司 | Continuous Approximation scratch pad analog-digital converter and its control method |
-
2015
- 2015-11-25 TW TW104139157A patent/TWI572144B/en active
-
2016
- 2016-11-18 US US15/356,478 patent/US9654127B1/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8164504B2 (en) * | 2010-03-16 | 2012-04-24 | Electronics And Telecommunications Research Institute | Successive approximation register analog-digital converter and method for operating the same |
US8451151B2 (en) * | 2011-08-15 | 2013-05-28 | Himax Technologies Limited | Successive approximation analog to digital converter with capacitor mismatch calibration and method thereof |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI665875B (en) * | 2018-02-13 | 2019-07-11 | 新唐科技股份有限公司 | Digital background calibration circuit |
US10511318B2 (en) | 2018-02-13 | 2019-12-17 | Nuvoton Technology Corporation | Digital background calibration circuit |
CN113141182A (en) * | 2020-01-20 | 2021-07-20 | 瑞昱半导体股份有限公司 | Analog-digital converter device and capacitance weight correction method |
Also Published As
Publication number | Publication date |
---|---|
US9654127B1 (en) | 2017-05-16 |
TWI572144B (en) | 2017-02-21 |
TW201720061A (en) | 2017-06-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9654127B1 (en) | Method for adaptively regulating coding mode and digital correction circuit thereof | |
US9432046B1 (en) | Successive approximation analog-to-digital converter | |
US8378863B2 (en) | Analog-to-digital converter and correction method thereof | |
US10069506B2 (en) | Calibration circuit and calibration method for DAC | |
EP3090488B1 (en) | Combining a coarse adc and a sar adc | |
US8896478B2 (en) | Successive approximation analog-to-digital converter using capacitor array with sub-capacitors configured by capacitor disassembling and related method thereof | |
US8599059B1 (en) | Successive approximation register analog-digital converter and method for operating the same | |
US9362939B1 (en) | Reduction of input dependent capacitor DAC switching current in flash-SAR analog-to-digital converters | |
US9071265B1 (en) | Successive approximation analog-to-digital converter with linearity error correction | |
US20090273501A1 (en) | Successive approximation register analog to digital converter with improved immunity to time varying noise | |
US9800255B2 (en) | Method and circuit for testing successive approximation ADC | |
US10084470B2 (en) | Analogue-digital converter of non-binary capacitor array with redundant bit and its chip | |
US10171097B1 (en) | Correcting device of successive approximation analog-to-digital conversion | |
CN111786675B (en) | Charge sharing type analog-to-digital converter quantization method based on dynamic tracking | |
US9312877B2 (en) | Systems and methods for capacitive digital to analog converters | |
US8493260B2 (en) | Successive approximation analog to digital converter | |
US10084465B2 (en) | Analog-to-digital converters with a plurality of comparators | |
KR101878593B1 (en) | Analog to digital converter and operating method thereof | |
US9172389B2 (en) | High-speed successive approximation analog-to-digital converter | |
US7075472B1 (en) | Averaging analog-to-digital converter with shared capacitor network | |
US10700694B2 (en) | Calibration method and related calibration system | |
CN110061740B (en) | processing circuit | |
US11128311B1 (en) | Analog-to-digital converting system and method with offset and bit-weighting correction mechanisms | |
CN106817128B (en) | Method for self-adaptive regulating coding mode and its digital correcting circuit | |
TWI698091B (en) | Successive approximation register analog-to-digital converter and operation method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: REALTEK SEMICONDUCTOR CORP., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LIN, SHENG HSIUNG;HUANG, SHIH-HSIUNG;REEL/FRAME:040373/0429 Effective date: 20161115 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |