US20170077097A1 - Semiconductor device having first and second gate electrodes and method of manufacturing the same - Google Patents
Semiconductor device having first and second gate electrodes and method of manufacturing the same Download PDFInfo
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- US20170077097A1 US20170077097A1 US15/010,327 US201615010327A US2017077097A1 US 20170077097 A1 US20170077097 A1 US 20170077097A1 US 201615010327 A US201615010327 A US 201615010327A US 2017077097 A1 US2017077097 A1 US 2017077097A1
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- gate electrode
- spacer
- semiconductor device
- dielectric layer
- gate
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
Definitions
- Example embodiments of inventive concepts relate to semiconductor devices including first and second gate electrodes and methods of manufacturing the same.
- FinFET fin field effect transistor
- a semiconductor device includes a substrate, an active region extending in a first direction on the substrate, a first gate electrode on the substrate, and a second gate electrode on the first gate electrode.
- the first gate electrode crosses the active region and extends in a second direction.
- the second gate electrode extends in the second direction.
- the first gate electrode has a first width in the first direction.
- the second gate electrode has a second width in the first direction. The second width is less than the first width.
- the first gate electrode may include a different material than a material of the second gate electrode.
- the second gate electrode may include a material having a resistivity that is less than a resistivity of the first gate electrode.
- the semiconductor device may further include a first spacer on the first gate electrode.
- the first spacer may be positioned at both sides of the second gate electrode.
- the semiconductor device may further include a second spacer positioned at both sides of the first gate electrode.
- the second spacer may extend along a sidewall of the first spacer.
- an inner sidewall of the second spacer may extend upwardly from an upper surface of the active region without bending.
- the first spacer may have a dielectric constant that is less than a dielectric constant of the second spacer.
- the semiconductor device may further include a gate dielectric layer covering the both sides of the first gate electrode.
- a bottom of the first gate electrode may be on the gate dielectric layer.
- an uppermost surface of the gate dielectric layer may be below the second gate electrode.
- the semiconductor device may further include a first spacer on an upper surface of the first gate electrode and a second spacer on the substrate.
- the first spacer may be positioned at both sides of the second gate electrode between the second spacer and the second gate electrode.
- a portion of the gate dielectric layer may be between the second spacer and the first gate electrode.
- An uppermost surface of the gate dielectric layer may contact a bottom of the first spacer.
- the first gate electrode may include a first conductive layer and a second conductive layer.
- the first conductive layer may include a first portion and a second portion. The first portion may extend parallel to an upper surface of the substrate. The second portion may extend in a vertical direction from the upper surface of the substrate.
- At least one of the first and second conductive layers may have a line shape extending in a direction.
- the second gate electrode may include substantially the same material as at least one of the first and second conductive layers.
- the semiconductor device may further include a source/drain region on the active region at both sides of the first and second gate electrodes.
- the source/drain region may include a silicon germanium epitaxial layer.
- the semiconductor device may further include a contact plug on the source/drain region.
- the active region may include a fin-type active region.
- a semiconductor device includes a substrate having an active region, a gate electrode crossing the active region on the substrate, and a first spacer.
- the gate electrode may include a first gate electrode on the active region, and a second gate electrode on the first gate electrode.
- the second gate electrode has a width that is less than a width of the first gate electrode.
- the first spacer is on an upper surface of the first gate electrode. The first spacer is positioned at both sides of the second gate electrode.
- the semiconductor device may further include a second spacer positioned at both sides of the gate electrode.
- the first spacer may be between the second gate electrode and the second spacer.
- a semiconductor device includes a substrate having an active region, a first gate electrode on the active region, a gate dielectric layer between the active region and the first gate electrode, a second gate electrode on the first gate electrode, and a first spacer positioned at a sidewall of the second gate electrode.
- the first spacer is on an upper portion of the first gate electrode.
- a portion of the gate dielectric layer extends along a sidewall of the first gate electrode,
- a bottom surface of the first spacer may contact an upper surface of the gate dielectric layer.
- the semiconductor device may further include a second spacer on the substrate at a sidewall of the first spacer. A lower portion of the second spacer may contact a sidewall of the gate dielectric layer.
- the first gate electrode may have a first width.
- the second gate electrode may have a second width that is less than the first width.
- a method of manufacturing a semiconductor device includes forming an insulating layer having an opening on a substrate, forming a conductive line in the opening by filling the opening with a conductive material, forming a first gate electrode by removing an upper portion of the conductive line, and forming a second gate electrode on an upper surface of the first gate electrode.
- a width of the second gate electrode may less than a width of the first gate electrode.
- the first gate electrode may include a different material than the second gate electrode.
- the method may further include forming a gate dielectric layer on an inner sidewall of the opening and on the substrate before the forming the conductive line.
- the forming the gate dielectric layer may include removing upper portion of the gate dielectric layer.
- the method may further include forming a first spacer on an inner sidewall of the opening and on the first gate electrode.
- a bottom of the first spacer may contact an uppermost surface of the gate dielectric layer.
- the forming the insulating layer may include forming a sacrificial gate structure on the substrate, forming a dielectric layer on the sacrificial gate structure, planarizing the dielectric layer to expose an upper surface of the sacrificial gate structure, and removing the sacrificial gate structure to expose an upper surface of the substrate.
- the method may further include forming a device isolation region on the substrate.
- the device isolation region may define a fin-type active region on the substrate.
- the fin-type active region may cross the sacrificial gate electrode and may be under the sacrificial gate electrode.
- the method may further include removing a portion of the fin-type active region at both sides of the sacrificial gate electrode, and forming a source/drain region on the removed upper portion of the fin-type active region.
- the method may further include forming a second spacer on the substrate at both sides of the sacrificial gate electrode before the forming the dielectric layer, and forming a interlayer dielectric layer on the source/drain region.
- the second spacer may contact the gate dielectric layer and the first spacer.
- a portion of the gate dielectric layer may be between the first gate electrode and the second spacer.
- a semiconductor device includes a substrate, an active region extending in a first direction on the substrate, a first gate electrode on the active region, a gate dielectric layer between the first gate electrode and the active region, a first spacer, and a second gate electrode.
- the active region is one of formed on the substrate and defined by trenches formed in the substrate.
- the first gate electrode extends in a second direction that crosses the first direction.
- the first spacer includes two first spacer structures on top of an upper surface of the first gate electrode and spaced apart from each other in the first direction.
- the second gate electrode is on the first gate electrode between the two first spacer structures.
- the semiconductor device may further include a second spacer on the active region.
- the second spacer may include two second spacer structures spaced apart from each other in the first direction.
- the first spacer structures, the gate dielectric layer, the first gate electrode, and the second gate electrode may be between the two second spacer structures.
- a dielectric constant of the first spacer may be less than a dielectric constant of the second spacer.
- the two first spacer structures may be in direct contact with an upper surface of the gate dielectric layer, or the two first spacer structures may be in direct contact with a side surface of the gate dielectric layer.
- the active region may include a fin-type active region.
- FIG. 1 is a perspective view illustrating a semiconductor device according to example embodiments of inventive concepts
- FIGS. 2A and 2B are cross-sectional views taken along the lines A-A′ and B-B′ of FIG. 1 , respectively;
- FIGS. 3 through 6 are cross-sectional views illustrating a semiconductor device according to example embodiments of inventive concepts
- FIGS. 7A through 7L are perspective views illustrating a method of manufacturing a semiconductor device according to example embodiments of inventive concepts
- FIGS. 8A through 8C are perspective views illustrating a method of manufacturing a semiconductor device according to example embodiments of inventive concepts
- FIGS. 9A through 9C are perspective views illustrating a method of manufacturing a semiconductor device according to example embodiments of inventive concepts.
- FIG. 10A is a plan view illustrating a semiconductor device according to example embodiments of inventive concepts.
- FIG. 10B is a cross-sectional view taken along the line C-C′ of FIG. 10A ;
- FIG. 11 is a circuit diagram illustrating a SRAM (Static Random Access Memory) unit cell according to example embodiments of inventive concepts
- FIG. 12 is a block diagram illustrating a storage device including a semiconductor device according to example embodiments of inventive concepts
- FIG. 13 is a block diagram illustrating an electronic device including a semiconductor device according to example embodiments of inventive concepts.
- FIG. 14 is a block diagram illustrating a system including a semiconductor device according to example embodiments of inventive concepts.
- first”, “second”, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. Unless the context indicates otherwise, these terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of example embodiments.
- spatially relative terms e.g., “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element(s) or feature(s), as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the example term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
- the term “and/or” includes any and all combinations of one or more of the associated listed items.
- the use of the terms “a” and “an” and “the” and similar referents in the context of describing embodiments (especially in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context.
- the terms “comprising,” “having,” “including,” and “containing” are to be construed as open-ended terms (i.e., meaning “including, but not limited to”) unless otherwise noted.
- Example embodiments will be described with reference to perspective views, cross-sectional views, and/or plan views.
- the profile of an example view may be modified according to, e.g., manufacturing techniques and/or allowances. Accordingly, the example embodiments are not intended to limit the scope, but cover all changes and modifications that can be caused due to, e.g., a change in manufacturing process.
- regions shown in the drawings are illustrated in schematic form and the shapes of the region are presented simply by way of illustration and not as a limitation.
- orientation, layout, location, shapes, sizes, amounts, or other measures do not necessarily mean an exactly identical orientation, layout, location, shape, size, amount, or other measure, but are intended to encompass nearly identical orientation, layout, location, shapes, sizes, amounts, or other measures within acceptable variations that may occur, for example, due to manufacturing processes.
- the term “substantially” may be used herein to reflect this meaning.
- the cross-sectional view(s) of device structures illustrated herein provide support for a plurality of device structures that extend along two different directions as would be illustrated in a plan view, and/or in three different directions as would be illustrated in a perspective view.
- the two different directions may or may not be orthogonal to each other.
- the three different directions may include a third direction that may be orthogonal to the two different directions.
- the plurality of device structures may be integrated in a same electronic device.
- an electronic device may include a plurality of the device structures (e.g., memory cell structures or transistor structures), as would be illustrated by a plan view of the electronic device.
- the plurality of device structures may be arranged in an array and/or in a two-dimensional pattern.
- FIG. 1 is a perspective view illustrating a semiconductor device according to example embodiments of inventive concepts.
- FIGS. 2A and 2B are cross-sectional views taken along the lines A-A′ and B-B′ of FIG. 1 , respectively.
- some of elements for example, an interlayer insulating layer 170 shown in FIGS. 2A and 2B , are omitted in FIG. 1 .
- a semiconductor device 100 may include a substrate 101 , an active region 105 , a source/drain region 110 , a gate dielectric layer 140 , a gate electrode 150 , and a contact plug 180 .
- the semiconductor device 100 may further include a device isolation region 107 , a first spacer 162 , a second spacer 164 , and an interlayer insulating layer 170 .
- the semiconductor device 100 may include a fin-type field effect transistor (FinFET) having a plurality of fin-type active regions.
- FinFET fin-type field effect transistor
- the substrate 101 may have an upper surface extending in X-direction and Y-direction.
- the substrate 101 may include a semiconductor material, e.g., a group IV compound semiconductor, a group III-V compound semiconductor, or a group II-VI silicon-oxide semiconductor.
- the group IV compound semiconductor may include silicon (Si), germanium (Ge), and/or silicon germanium (SiGe).
- the substrate 101 may be a bulk silicon wafer, an epitaxial layer, a silicon-on-insulator (SOI) substrate, or a semiconductor-on-insulator (SeOI) substrate.
- the device isolation region 107 may define the active region 105 on the substrate 101 .
- the device isolation region 107 may include a dielectric material, e.g., silicon oxide, silicon nitride, or the mixture thereof.
- the device isolation region 107 may be formed using a shallow trench isolation (STI) process.
- STI shallow trench isolation
- the active region 105 may extend in a first direction, e.g., the Y-direction.
- the active region 105 may be a fin-type active region that is protruding from the substrate 101 .
- the active region 105 may be a portion of the substrate 101 and/or include an epitaxial layer grown from the substrate 101 .
- the active region 105 may be recessed at both sides of a gate electrode 150 .
- the source/drain region 110 may be formed at both sides of the gate electrode 150 and on the recessed active region 105 .
- the source/drain region 110 may be provided a source region or a drain region of the semiconductor device 100 .
- the source/drain region 110 may have an elevated structure. Therefore, an upper surface of the source/drain region 110 may be higher than a bottom surface of the gate electrode 150 .
- the source/drain region 110 may have a pentagonal shape. However, it shall not be restricted or limited thereto.
- the source/drain region 110 may have a polygonal shape, a circle shape, or a rectangular shape.
- the source/drain region 110 may have a connected structure or a merged structure that is formed on three active regions. In example embodiments, the source/drain region 110 may do not have a connected structure or a merged structure.
- the source/drain region 110 may include silicon (Si) or silicon germanium (SiGe).
- the source/drain region 110 may be formed of an epitaxial layer. If the source/drain region 110 includes SiGe and a channel region includes Si in a PMOS transistor, the source/drain region 110 may induce a compressive stress into the channel region and thereby a hole mobility may be increased in the channel region of a PMOS transistor.
- the source/drain region 110 may have a plurality of regions having different impurities and different impurity concentrations each other.
- the gate dielectric layer 140 and the gate electrode 150 crossing the active region 105 may be formed on the fin-type active region.
- the gate electrode 150 may include a first gate electrode 152 and a second gate electrode 154 which are stacked on each other.
- the gate dielectric layer 140 may be disposed between the active region 105 and the first gate electrode 152 . A portion of the gate dielectric layer 140 may be extended along both sides of the first gate electrode 152 . In example embodiments, the gate dielectric layer 140 may be only formed beneath the first gate electrode 152 .
- the gate dielectric layer 140 may include an insulating layer, e.g., a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, and/or a high-k dielectric layer.
- the high-k dielectric layer may be an insulating material that has a dielectric constant that is greater than a dielectric constant of silicon oxide.
- the high-k dielectric layer may include at least one of aluminum oxide (Al 2 O 3 ), tantalum oxide (Ta 2 O 3 ), Yttrium oxide (Y 2 O 3 ), zirconium oxide (ZrO 2 ), zirconium silicon oxide (ZrSi x O y ), hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSi x O y ), lanthanum oxide (La 2 O 3 ), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), hafnium aluminum oxide (HfAl x O y ), and/or praseodymium oxide (Pr 2 O 3 ).
- the gate electrode 150 may be extended in the X-direction.
- the first gate electrode 152 may be formed on the gate dielectric layer 140 .
- the second gate electrode 154 may be formed on the first gate electrode 152 .
- a channel region may be formed in an upper portion of the active region 105 that is overlapped by the gate electrode 150 .
- the first spacer 162 includes two first spacer structures at opposite sides of the second gate electrode 154 .
- the second spacer 164 includes two second spacer structures.
- the first gate electrode 152 may have a first width L 1 in the first direction, e.g., the Y-direction.
- the second gate electrode 154 may have a second width L 2 less than the first width L 1 in the first direction.
- a contact plug 180 may be formed on the source/drain region 110 .
- a lower portion of the second gate electrode 154 may have a level that is substantially the same as a bottom of the contact plug 180 . Therefore, a parasitic capacitance between the second gate electrode 154 and the contact plug 180 may be reduced by reducing the second width L 2 of the second gate electrode 154 .
- An upper surface of the first gate electrode 152 may have a first height H 1 from an upper surface of the substrate 101 .
- An upper surface of the second gate electrode 154 may have a second height H 2 from the upper surface of the first gate electrode 152 .
- an interface between the first gate electrode 152 and the second gate electrode 154 may have a level less than or equal to the bottom surface of the contact plug 180 . However, it shall not be restricted or limited thereto.
- the upper surface of the first gate electrode 152 may have a third height H 3 from an upper surface of the active region 105 .
- the third height H 3 may be less than the first height H 1 .
- the upper surface of the second gate electrode 154 may have a fourth height H 4 from the upper surface of the active region 105 .
- the fourth height H 4 may be substantially the same as the second height H 2 . However, it shall not be restricted or limited thereto.
- the first gate electrode 152 may have a different material from the second gate electrode 154 .
- the first gate electrode 152 may include a material having a work-function that is available to form a proper threshold voltage of a transistor.
- the first gate electrode 152 may include a titanium nitride (TiN) layer, a titanium aluminum carbide (TiAlC) layer, and/or a tungsten (W) layer.
- the second gate electrode 154 may include a material having a lower resistivity.
- the second gate electrode 154 may include aluminum (Al), tungsten (W), copper (Cu), and/or molybdenum (Mo).
- a resistivity of the second gate electrode 154 may be less than a resistivity of the first gate electrode 152 .
- Each of the first and second gate electrodes 152 and 154 may include a plurality of conductive layers, respectively.
- a first spacer 162 and a second spacer 164 may be formed on both sides of the gate electrode 150 .
- the gate electrode 150 may be isolated from the source/drain region 110 by the first and second spacers 162 and 164 .
- the first spacer 162 may be formed both sides of the second gate electrode 154 .
- the first spacer 162 may be formed on the gate dielectric layer 140 and the first gate electrode 152 .
- a portion of the first spacer 162 may be formed on an upper portion of the first gate electrode 152 because the second width L 2 of the second gate electrode 154 is less than the first width L 1 of the first gate electrode 152 .
- the second spacer 164 may be formed on both sides of the first and second gate electrodes 152 and 154 .
- the second spacer 164 may be formed along a sidewall of the gate dielectric layer 140 and a sidewall of the first spacer 162 .
- An inner sidewall of the second spacer 164 may be extended upwardly from an upper surface of the active region without bending.
- Each of the first and second spacers 162 and 164 may include silicon oxide, silicon nitride, and/or silicon oxynitride, respectively.
- the first spacer 162 or the second spacer 164 may be formed of a low-k dielectric layer to reduce a capacitance between the gate electrode 150 and the contact plug 180 .
- the first and second spacers 162 and 164 may include polyimide, poly arylene ether (PAE), SiLKTM (a dielectric resin introduced by Dow Chemical), hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), BLACK DIAMONDTM (SiOC:H, a silica-based material introduced by Applied Materials that is obtained by doping silica with —CH 3 groups) and/or fluorine-doped silicate glass (FSG).
- PAE poly arylene ether
- SiLKTM a dielectric resin introduced by Dow Chemical
- HQ hydrogen silsesquioxane
- MSQ methyl silsesquioxane
- BLACK DIAMONDTM SiOC:H, a silica-based material introduced by Applied Materials that is obtained by doping silica with —CH 3 groups
- FSG fluorine-doped silicate glass
- a shortage between the second gate electrode 154 and the contact plug 180 may be reduced by reducing the second width L 2 of the second gate electrode 154 .
- the contact plug 180 may be formed on the source/drain region 110 and electrically connected to a conductive line (not shown in figures) for transferring electrical signals to the source/drain region 110 .
- the contact plug 180 may have a bar shape extending in the first direction or an elliptical shape.
- the contact plug 180 may pass through the interlayer insulating layer 170 and contact to the source/drain region 110 .
- an upper portion of the source/drain region 110 may have a recessed region and a bottom of the contact plug 180 may be disposed in the recessed portion.
- a lower portion of the contact plug 180 may have a diffusion barrier layer or a silicide layer.
- the contact plug 180 may contact a silicide layer that is formed on an upper portion of the source/drain region 110 .
- the contact plug 180 may include a conductive material, e.g., titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), aluminum (Al), copper (Cu), tungsten (W), or molybdenum (Mo).
- the interlayer insulating layer 170 may include a first interlayer insulating layer 172 and a second interlayer insulating layer 174 .
- the interlayer insulating layer 170 may be formed on the substrate 101 , the source/drain region 110 , and the gate electrode 150 .
- An upper surface of the first interlayer insulating layer 172 may be substantially coplanar with an upper surface of the gate electrode 150 .
- the first and second interlayer insulating layer 172 and 174 may include a silicon oxide layer, a silicon nitride layer, and/or a silicon oxynitride layer.
- the first interlayer insulating layer 172 may include a low-k dielectric layer.
- the first interlayer insulating layer 172 and the second interlayer insulating layer 174 may be formed of different materials.
- FIGS. 3 through 6 are cross-sectional views illustrating a semiconductor device according to example embodiments of inventive concepts.
- a semiconductor device 100 a may include a substrate 101 , a plurality of fin-type active regions 105 , a plurality of source/drain regions 110 , a gate dielectric layer 140 , a gate electrode 150 a , and a plurality of contact plugs 180 .
- the semiconductor device 100 may further include a device isolation region 107 , a first spacer 162 , and a second spacer 164 .
- the gate electrode 150 a may include a first gate electrode 152 and a second gate electrode 154 .
- the gate electrode 150 a may be formed on the gate dielectric layer 140 .
- the first gate electrode 152 may include a first conductive layer 152 A and a second conductive layer 152 B.
- the first conductive layer 152 A may be formed directly on the gate dielectric layer 140 .
- the first conductive layer 152 A may be formed beneath and on both sides of the second conductive layer 152 B.
- an upper surface of the second conductive layer 152 B may be substantially coplanar with an uppermost surface of the gate dielectric layer 140 .
- the second gate electrode 154 may be formed on the first conductive layer 152 A and the second conductive layer 152 B.
- the second gate electrode 154 may have a width less than a width of the first gate electrode 152 .
- the second gate electrode 154 may have a width greater than a width of the second conductive layer 152 B. However, it shall not be restricted or limited thereto.
- the first gate electrode 152 may include a different material from the second gate electrode 154 .
- the second conductive layer 152 B may include a material having a resistivity less than a resistivity of the first conductive layer 152 A.
- the second gate electrode 154 may include a material having a resistivity less than a resistivity of at least one of the first conductive layer 152 A and a second conductive layer 152 A.
- a semiconductor device 100 b may include a substrate 101 , a plurality of fin-type active regions 105 , a plurality of source/drain regions 110 , a gate dielectric layer 140 , a gate electrode 150 b , and a plurality of contact plugs 180 .
- the semiconductor device 100 b may further include a device isolation region 107 , a first spacer 162 , and a second spacer 164 .
- the gate electrode 150 b may include a first gate electrode 152 and a second gate electrode 154 .
- the gate electrode 150 b may be formed on the gate dielectric layer 140 .
- the first gate electrode 152 may include a first conductive layer 152 A′ and a second conductive layer 152 B′.
- the first conductive layer 152 A′ may be formed directly on the gate dielectric layer 140 .
- the first conductive layer 152 A′ may be formed beneath and on both sides of the second conductive layer 152 B′.
- an upper surface of the second conductive layer 152 B′ may be substantially coplanar with an uppermost surface of the gate dielectric layer 140 .
- the second gate electrode 154 may be formed on the first conductive layer 152 A′ and the second conductive layer 152 B′.
- the second gate electrode 154 may have a width less than a width of the first gate electrode 152 .
- the second gate electrode 154 may have a width substantially equal to a width of the second conductive layer 152 B′.
- the second gate electrode 154 may be formed of a conductive material that is substantially the same as the second conductive layer 152 B′. However, it shall not be restricted or limited thereto.
- the first conductive layer 152 A′ may include a different material from the second conductive layer 152 B′.
- the second conductive layer 152 B′ and/or the second gate electrode 154 may include a material having a resistivity less than that of the first conductive layer 152 A′.
- a semiconductor device 100 c may include a substrate 101 , a plurality of fin-type active regions 105 , a plurality of source/drain regions 110 , a gate dielectric layer 140 , a gate electrode 150 c , and a plurality of contact plugs 180 .
- the semiconductor device 100 c may further include a device isolation region 107 , a first spacer 162 a , and a second spacer 164 .
- the gate electrode 150 c may include a first gate electrode 152 and a second gate electrode 154 a .
- the gate electrode 150 c may be formed on the gate dielectric layer 140 .
- the first spacer 162 a formed on both sides of the second gate electrode 154 a may have a curved inner sidewall.
- a width L 5 of an upper portion of the second gate electrode 154 a may be greater than a width L 6 of a bottom portion of the second gate electrode 154 a.
- a semiconductor device 100 d may include a substrate 101 , a plurality of fin-type active regions 105 , a plurality of source/drain regions 110 , a gate dielectric layer 140 a , a gate electrode 150 , and a plurality of contact plugs 180 .
- the semiconductor device 100 d may further include a device isolation region 107 , a first spacer 162 , and a second spacer 164 .
- the gate dielectric layer 140 a may be formed between the fin-type active region 105 and the first gate electrode 152 . In example embodiments, a portion of the gate dielectric layer 140 a may be extended along a sidewall of the first spacer 162 that is formed on both sides of the second gate electrode 154 . In example embodiments, an uppermost surface of the gate dielectric layer 140 a may be substantially coplanar with an upper surface of the second gate electrode 154 .
- FIGS. 7A through 7L are perspective views illustrating a method of manufacturing a semiconductor device according to example embodiments of inventive concepts.
- a plurality of trenches TI may be formed on an upper portion of the substrate 101 .
- the trenches TI may define a plurality of fin-type active region 105 .
- a pad oxide pattern 122 and a mask pattern 124 may be formed on each of the fin-type active regions 105 .
- the pad oxide pattern 122 and the mask pattern 124 may be used as masks during the formation of the fin-type active regions 105 .
- the pad oxide pattern 122 and the mask pattern 124 may be omitted.
- the mask pattern 124 may include silicon oxide, silicon nitride, and/or carbide mixture.
- the mask pattern 124 may include multiple layers.
- the trenches TI may be formed by etching the substrate 101 using an anisotropic etching process.
- the trenches TI may have a high aspect ratio.
- Each of the trenches TI may have variable widths that are gradually reduced from an upper portion to a lower portion thereof. Therefore, each of the fin-type active regions 105 may have variable widths that are gradually reduced from a lower portion to an upper portion thereof.
- a device isolation region 107 may be formed in the trenches TI. Forming the device isolation region 107 may include forming an insulating layer in the trenches TI and performing a planarization process to the insulating layer. At least a portion of the pad oxide pattern 122 and the mask pattern 124 may be removed during the planarization process. In example embodiments, a thin liner layer may be formed in the trenches TI before forming the insulating layer. The insulating layer may be recessed to expose an upper portion of the fin-type active regions 105 after the planarization process. The insulating layer may be recessed by a wet etching process using the oxide pattern or the mask pattern as an etching mask.
- the fin-type active region 105 may be protruded from an upper surface of the device isolation region 107 .
- the oxide pattern 122 and the mask pattern 124 may be removed.
- the upper surface of the fin-type action regions 105 may have a height H 5 .
- a first sacrificial layer 132 and a second sacrificial layer 135 may be formed on the fin-type active regions 105 .
- the first and second sacrificial layers 132 and 135 may extend in the second direction.
- the first and second sacrificial layers 132 and 135 may be formed by an etching process using a mask layer 136 as an etching mask.
- the second spacer 164 may be formed on both sides of the first sacrificial layers 132 and the second sacrificial layer 135 .
- the first sacrificial layer 132 may include an insulating layer and the second sacrificial layer 135 may include a conductive layer.
- the first sacrificial layer 132 may include a silicon oxide layer and the second sacrificial layer 135 may include a polysilicon layer.
- the first and second sacrificial layers 132 and 135 may be merged and be formed of a single layer.
- the second spacer 164 may be formed on both sides of the first sacrificial layer 132 , the second sacrificial layer 135 , and the mask layer 136 . Forming the second spacer 164 may include forming a dielectric layer on and both sides of the mask layer 136 and the first and second sacrificial layers 132 and 135 , and performing an isotropic etching process to the dielectric layer to expose an upper surface of the mask layer 136 . In example embodiments, the second spacer 164 may be formed of multiple layers. At this moment, a third spacer 166 may be formed on both sides of the fin-type active regions 105 .
- some upper portions of the fin-type active regions 105 may be recessed by an etching process using the mask layer 136 and the second spacer 164 as etching masks.
- the etching process may include a dry etching process and/or a wet etching process.
- a curing process may be performed to an upper surface of the recessed fin-type active regions 105 .
- the upper surface of the recessed fin-type active regions 105 may be coplanar with an upper surface of the device isolation region 107 . However, it shall not be restricted or limited thereto.
- the upper surface of the recessed fin-type active regions 105 may have a level greater than or less than the upper surface of the device isolation region 107 .
- An impurity doping process may be performed to the recessed fin-type active regions 105 using the mask layer 136 and the second spacer 164 as masks.
- a plurality of source/drain regions 110 may be formed on the recessed fin-type active regions 105 and both sides of the second spacer 164 .
- the source/drain regions 110 may be formed using a selective epitaxial growth (SEG) process.
- the source/drain regions 110 may include silicon germanium (SiGe).
- the source/drain regions 110 may include several epitaxial layer having different germanium (Ge) concentrations, respectively. Some impurities, e.g., boron (B), may be doped in the source/drain regions 110 during or after the selective epitaxial growth (SEG) process.
- the source/drain regions 110 may have a pentagonal shape or a hexagonal shape. However, it shall not be restricted or limited thereto.
- the source/drain regions 110 may have a polygonal shape, a circle shape, or a rectangular shape.
- a first interlayer insulating layer 172 may be formed on the source/drain regions 110 .
- Forming the first interlayer insulating layer 172 may include forming an insulating layer on the source/drain regions 110 and performing a planarization process to the insulating layer to expose an upper surface of the second sacrificial layer 135 .
- the mask layer 136 may be removed during the forming the first interlayer insulating layer 172 .
- the first interlayer insulating layer 172 may include silicon oxide, silicon nitride, and/or silicon oxynitride. In example embodiments, the first interlayer insulating layer 172 may include a low-k dielectric material.
- the first and second sacrificial layers 132 and 135 may be removed to form a first opening E 1 .
- the first opening may expose an upper surface of the device isolation region 107 and the fin-type active regions 105 .
- the first and second sacrificial layers 132 and 135 may be removed using a wet etching process and/or a dry etching process.
- a preliminary gate dielectric layer 140 P and a first preliminary gate electrode 152 P in the first opening E 1 may be conformally formed along both sidewalls and a bottom of the first opening E 1 .
- the preliminary gate dielectric layer 140 P may include silicon oxide, silicon nitride, and/or a high-k dielectric material.
- the preliminary gate electrode 152 P may be formed on the preliminary gate dielectric layer 140 P.
- the preliminary gate electrode 152 P may include metal and/or semiconductor material.
- the preliminary gate electrode 152 P may include multiple layers.
- the preliminary gate dielectric layer 140 P and the first preliminary gate electrode 152 P may be planarized to expose an upper surface of the first interlayer insulating layer 172 using a chemical mechanical polishing (CMP) process.
- CMP chemical mechanical polishing
- an upper portions of the preliminary gate dielectric layer 140 P and the first preliminary gate electrode 152 P may be recessed to form the gate dielectric layer 140 and the first gate electrode 152 .
- the preliminary gate dielectric layer 140 P and the first preliminary gate electrode 152 P may be selectively recessed with respect to the second spacer 164 and the first interlayer insulating layer 172 using a single etching process or multiple etching processes.
- An upper surface of the gate dielectric layer 140 may be coplanar with an upper surface of the first gate electrode 152 .
- the preliminary gate dielectric layer 140 P may not be recessed as shown in FIG. 6 .
- a second opening E 2 may be formed after forming the gate dielectric layer 140 and the first gate electrode 152 .
- a first spacer 162 may be formed on both sidewalls of the second opening E 2 .
- the first spacer 162 may be formed on the gate dielectric layer 140 and a portion of the first gate electrode 152 .
- the first spacer 162 may be formed on a sidewall of the second spacer 164 that is exposed by the second opening E 2 .
- Forming the first spacer 162 may include forming a dielectric layer on the gate dielectric layer 140 , the first gate electrode 152 , and the first interlayer insulating layer 172 .
- Forming the first spacer 162 may further include etching the dielectric layer using an isotropic etching process.
- the first spacer 162 may have a substantially rectangular shape in a cross-sectional view.
- a sidewall of the first spacer 162 a may have a curved shape as shown in FIG. 5 .
- a second gate electrode 154 may be formed in the second opening E 2 .
- the second gate electrode 154 may be formed on the first gate electrode 152 .
- Forming the second gate electrode 154 may include forming a conductive layer in the second opening E 2 and on the first interlayer insulating layer 172 .
- Forming the second gate electrode 154 may further include performing a planarization process to the conductive layer using a CMP process to expose an upper surface of the first interlayer insulating layer 172 .
- a width of the first gate electrode 152 may be different from a width of the second gate electrode 154 in a cross-sectional view.
- a second interlayer insulating layer 174 may be formed on the first interlayer insulating layer 170 and the second gate electrode 154 .
- a plurality of contact holes OP may be formed in the first and second interlayer insulating layers 172 and 174 .
- the contact holes OP may expose an upper surface of the source/drain regions 110 .
- the upper surface of the source/drain regions 110 may be recessed during the forming the contact holes OP.
- a bottom portion of the contact holes OP may have a curved shape along an upper surface of the source/drain region 110 .
- the contact holes OP may be filled by a conductive layer to form a plurality of contact plugs 180 as shown in FIG. 1 .
- a silicide layer may be formed between the contact plugs 180 and the source/drain regions 110 . In example embodiments, the silicide layer may be a portion of the contact plugs 180 .
- FIGS. 8A through 8C are perspective views illustrating a method of manufacturing a semiconductor device according to example embodiments of inventive concepts. For convenience of description, some of explanation which is substantially the same description described above referring to FIGS. 7A through 7L will be omitted.
- a second preliminary gate electrode 154 P may be formed on the gate dielectric layer 140 and the first gate electrode 152 after FIG. 7I . More specifically, the second preliminary gate electrode 154 P may fill the second opening E 2 shown in FIG. 7I .
- a mask layer 126 extending in the second direction may be formed on the second preliminary gate electrode 154 P. Both side end portions of the second preliminary gate electrode 154 P may be exposed by the mask layer 126 .
- the mask layer 126 may include a photoresist layer. However, it shall not be restricted or limited thereto.
- the mask layer 126 may have a width L 7 less than the width L 1 (See FIG. 1 ) of the first gate electrode 152 in a cross-sectional view.
- the both side end portions of the second preliminary gate electrode 154 P may be removed to form a second gate electrode 154 having a width less than the width L 1 of the first gate electrode 152 .
- the mask layer 126 may be removed after forming the second gate electrode 154 .
- a first spacer 162 may be formed after forming the second gate electrode 154 .
- the first spacer 162 may be formed by filling a dielectric layer on both sides of the second gate electrode 154 (refer FIG. 7K ).
- the second gate electrode and the first spacer is formed by oxidizing a portion of the second preliminary gate electrode 154 P that is exposed by the mask layer 126 in FIG. 8B , for example, an oxygen plasma or an oxygen-implant process.
- FIGS. 9A through 9C are perspective views illustrating a method of manufacturing a semiconductor device according to example embodiments of inventive concepts. For convenience of description, some of explanation which is substantially the same description described above referring to FIGS. 7A through 7L will be omitted.
- a preliminary gate dielectric layer 140 P, a preliminary first conductive layer 152 PA′, and a third sacrificial layer 138 may be formed in the first opening E 1 after FIG. 7G .
- the preliminary gate dielectric layer 140 P and the preliminary first conductive layer 152 PA′ may be conformally formed along both sidewalls and a bottom of the first opening E 1 .
- the preliminary gate dielectric layer 140 P may include silicon oxide, silicon nitride, and/or a high-k material.
- the preliminary first conductive layer 152 PA′ may include metal and/or metal compounds.
- the third sacrificial layer 138 may have an etching selectivity with respect to the preliminary gate dielectric layer 140 P, the preliminary first conductive layer 152 PA′, and the second spacer 164 .
- the preliminary gate dielectric layer 140 P, the preliminary first conductive layer 152 PA′, and the third sacrificial layer 138 may be planarized to exposed an upper surface of the first interlayer insulating layer 172 using a CMP process.
- upper portions of the preliminary gate dielectric layer 140 P and the preliminary first conductive layer 152 PA′ may be recessed to form a gate dielectric layer 140 and a first conductive layer 152 A′ using an etch-back process.
- the third sacrificial layer 138 may be simultaneously recessed during the etch-back process.
- a second opening E 2 may be formed on the gate dielectric layer 140 and a first conductive layer 152 A′ after the etch-back process.
- the third sacrificial layer 138 may not be recessed during the etch-back process.
- a first spacer 162 may be formed on both sidewalls of the second opening E 2 .
- a sidewall of the first spacer 162 may contact a sidewall of the second spacer 164 that is exposed by the second opening E 2 .
- a thickness of the first spacer 162 may be substantially the same as the sum of the thicknesses of the gate dielectric layer 140 and the first conductive layer 152 A′ on a sidewall of the second spacer 164 . However, it shall not be restricted or limited thereto.
- the third sacrificial layer 138 may be removed after forming the first spacer 162 .
- a second conductive layer 152 B′ on the first conductive layer 152 g may be formed of the first conductive layer 152 A′ and the second conductive layer 152 B′.
- a second gate electrode 154 may be formed on the first gate electrode 152 ′.
- the second conductive layer 152 B′ and the second gate electrode 154 may be simultaneously formed of same material.
- FIG. 10A is a plan view illustrating a semiconductor device according to example embodiments of inventive concepts.
- FIG. 10B is a cross-sectional view taken along the line C-C′ of FIG. 10A .
- a semiconductor device 200 may include a substrate 201 , an active region 205 , a first source/drain region 212 , a second source/drain 214 , a gate dielectric layer 240 , a gate electrode 250 , a first contact plug 282 , and a second contact plug 284 .
- the semiconductor device 200 may further include a device isolation region 207 , a first spacer 262 , a second spacer 264 , and an interlayer insulating layer 270 .
- the active region 205 extending in X-direction may be formed on the substrate 201 .
- the gate electrode 250 extending in Y-direction may be formed on the active region 205 .
- the semiconductor device 200 may include a planar type transistor.
- the substrate 201 may have an upper surface extending in the X-direction and the Y-direction.
- the substrate 201 may include a semiconductor material, e.g., a group IV compound semiconductor, a group III-V compound semiconductor, or a group II-VI silicon-oxide semiconductor.
- the group IV compound semiconductor may include silicon (Si), germanium (Ge), and/or silicon germanium (SiGe).
- the substrate 101 may be a bulk silicon wafer, an epitaxial layer, a silicon-on-insulator ( 501 ) substrate, or a semiconductor-on-insulator (SeOI) substrate.
- the device isolation region 207 may define the active region 205 on the substrate 201 .
- the device isolation region 207 may include a dielectric material, e.g., silicon oxide, silicon nitride, or the mixture thereof.
- the device isolation region 207 may be formed using a shallow trench isolation (STI) process.
- STI shallow trench isolation
- the active region 205 may be extended in the X-direction and defined by the device isolation region 207 .
- the first and second source/drain regions 212 and 214 may be formed at both sides of the gate electrode 250 and in the active region 205 .
- the first and second source/drain regions 212 and 214 may have elevated structures. Therefore, upper surfaces of the first and second source/drain regions 212 and 214 may be higher than a bottom surface of the gate electrode 250 .
- the gate dielectric layer 240 and the gate electrode 250 crossing the active region 205 may be formed on the active region 205 .
- the gate electrode 250 may include a first gate electrode 252 and a second gate electrode 254 which are stacked on each other.
- the gate dielectric layer 240 may include an insulating layer, e.g., a silicon oxide layer, a silicon oxynitride layer, and/or a silicon nitride layer.
- the first and second gate electrodes 252 and 254 may be extended in the Y-direction.
- the first and second gate electrodes 252 and 254 may have different widths in the X-direction and include different material from each other.
- the second gate electrode 254 may include a material having a lower resistivity less than that of the first gate electrode 252 .
- the first spacer 262 may be formed on both sides of the second gate electrode 254 .
- the second spacer 264 may be formed on both sides of the first and second gate electrodes 252 and 254 .
- an inner sidewall of the second spacer 264 may contact sidewalls of the gate dielectric layer 240 and the first spacer 262 .
- the first and second spacers 262 and 264 may include silicon oxide, silicon nitride, and/or silicon oxynitride, respectively.
- the first and second spacers 262 and 264 may include multiple layers, respectively.
- the interlayer insulating layer 270 may be formed on the substrate 201 , the first and second source/drain regions 212 and 214 , and the gate electrode 250 .
- the interlayer insulating layer 270 may include silicon oxide, silicon nitride, and/or silicon oxynitride.
- the first and second contact plugs 282 and 284 may be formed on the first and second source/drain region 212 and 214 , respectively.
- first and second conductive lines may be formed on the first and second contact plugs 282 and 284 , respectively.
- the first and second contact plugs 282 and 284 may include a conductive material, e.g., aluminum (Al), copper (Cu), and/or tungsten (W).
- the semiconductor 200 may include a vertical structured transistor having a vertical channel region.
- FIG. 11 is a circuit diagram illustrating a SRAM (Static Random Access Memory) cell according to example embodiments of inventive concepts.
- the SRAM cell may have a first inverter and a second inverter which are formed between a power supply node Vdd and a ground node Vss.
- the first inverter having an input node and an output node, may comprise a first pull-up transistor TP 1 and a first pull-down transistor TN 1 .
- the second inverter having an input node and an output node, may have a second pull-up transistor TP 2 and a second pull-down transistor TN 2 .
- the input node of the first inverter may be connected to a source/drain region of a second pass transistor TN 4 as well as to the output node of the second inverter.
- the input node of the second inverter may be connected to a source/drain region of a first pass transistor TN 4 as well as to the output node of the first inverter.
- Gate electrodes of the first and second pass transistors TN 3 and TN 4 may be connected to a word line WL.
- a bit line BL may be connected to a source/drain region of the first pass transistor TN 3 .
- a bit line bar/BL may be connected to a source/drain region of the second pass transistor TN 4 .
- the first and second pull-up transistors TP 1 and TP 2 may be PMOS transistors.
- the first and second pull-down transistors TN 1 and TN 2 and the first and second pass transistors TN 3 and TN 4 may be NMOS transistors.
- the first and second pull-up transistors TP 1 and TP 2 may be formed according to example embodiments of inventive concepts.
- FIG. 12 is a block diagram of a storage device including a semiconductor device according to example embodiments of inventive concepts.
- a storage apparatus 1000 may include a controller 1010 communicating with a Host, and memories 1020 - 1 , 1020 - 2 and 1020 - 3 storing data.
- the respective memories 1020 - 1 , 1020 - 2 and 1020 - 3 may include one of the semiconductor devices according to example embodiments of inventive concepts described with reference to FIGS. 1 through 10B .
- Examples of the host communicating with the controller 1010 may include various electronic devices on which the storage apparatus 1000 is mounted.
- the host may be, for example, a smartphone, a digital camera, a desktop computer, a laptop computer, a portable media player or the like.
- the controller 1010 may receive a data writing or reading request transferred from the host to store data in the memories 1020 - 1 , 1020 - 2 and 1020 - 3 or generate a command for retrieving data from the memories 1020 - 1 , 1020 - 2 and 1020 - 3 .
- At least one or more memories 1020 - 1 , 1020 - 2 and 1020 - 3 may be connected to the controller 1010 in parallel in the storage apparatus 1000 .
- the plurality of memories 1020 - 1 , 1020 - 2 and 1020 - 3 may be connected to the controller 1010 in parallel, whereby the storage apparatus 1000 having high capacity such as a solid state drive may be implemented.
- FIG. 13 is a block diagram of an electronic device including a semiconductor device according to example embodiments of inventive concepts
- an electronic apparatus 2000 may include a communications unit 2010 , an input unit 2020 , an output unit 2030 , a memory 2040 , and a processor 2050 .
- the communications unit 2010 may include a wired or wireless communications module, a wireless Internet module, a local area communications module, a global positioning system (GPS) module, a mobile communications module and the like.
- the wired or wireless communications module included in the communications unit 2010 may be connected to external communications networks according to various communications standard specification to transmit and receive data.
- the input unit 2020 may be a module provided to control an operation of the electronic apparatus 2000 by a user and may include a mechanical switch, a touch screen, a voice recognition module, and the like.
- the input unit 2020 may include a mouse operating in a track ball or a laser pointer scheme or a finger mouse device.
- the input unit 2020 may further include various sensor modules allowing for a user to input data thereto.
- the output unit 2030 may output information processed in the electronic apparatus 2000 in a sound or image form, and the memory 2040 may store programs for the processing and the control of the processor 2050 .
- the memory 2040 may include at least one semiconductor device according to various example embodiments of inventive concepts as described with reference to FIGS. 1 through 10B .
- the processor 2050 may transfer a command to the memory 2040 according to a required operation to thereby store or retrieve data.
- the memory 2040 may be embedded in the electronic apparatus 2000 to communicate with the processor 2050 or communicate with the processor 2050 through a separate interface.
- the processor 2050 may store or retrieve data, through various interface standards such as SD, SDHC, SDXC, MICRO SD, USB and the like.
- the processor 2050 may control operations of respective components included in the electronic apparatus 2000 .
- the processor 2050 may perform control and processing in association with voice communications, video telephony, data communications and the like, or may perform control and processing for multimedia reproduction and management.
- the processor 2050 may process an input transferred from a user through the input unit 2020 and may output results thereof through the output unit 2030 .
- the processor 2050 may store data required in controlling the operation of the electronic apparatus 2000 as described above, in the memory 2040 , or fetch data from the memory 2040 .
- FIG. 14 is a block diagram of a system including a semiconductor device according to example embodiments of inventive concepts.
- a system 3000 may include a controller 3100 , an input/output device 3200 , a memory 3300 , and an interface 3400 .
- the system 3000 may transmit or receive mobile system or information. Examples of the mobile system may include PDAs, portable computers, web tablets, wireless phones, mobile phones, digital music players and memory cards.
- the controller 3100 may execute a program and control the system 3000 .
- the controller 3100 may be a microprocessor, a digital signal processor, a microcontroller or device similar thereto.
- the input/output device 3200 may be used to input or output data to or from the system 3000 .
- the system 3000 may be connected to an external device, for example, a personal computer or networks and may exchange data with the external device.
- the input/output device 3200 may be a keypad, a keyboard, or a display device.
- the memory 3300 may store a code and/or data for operating the controller 3100 and/or store data having been processed by the controller 3100 .
- the memory 3300 may include the semiconductor device according to one of the example embodiments of inventive concepts.
- the interface 3400 may be a data transmission path between the system 3000 and an external device.
- the controller 3100 , the input/output device 3200 , the memory 3300 , and the interface 3400 may be in communication with one another via a bus 3500 .
- At least one of the controller 3100 or the memory 3300 may include at least one of the semiconductor devices described with reference to FIGS. 1 through 10B .
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Abstract
Description
- This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2015-0131151, filed on Sep. 16, 2015, in the Korean Intellectual Property Office (KIPO), the contents of which are herein incorporated by reference in their entirety.
- 1. Technical Field
- Example embodiments of inventive concepts relate to semiconductor devices including first and second gate electrodes and methods of manufacturing the same.
- 2. Description of the Related Art
- Recently, semiconductor devices having a plurality of gate electrodes have become highly integrated. Therefore, a fin field effect transistor (FinFET) having a three-dimensional structure has been researched and developed in order to reduce short channel effects.
- According to example embodiments of inventive concepts, a semiconductor device includes a substrate, an active region extending in a first direction on the substrate, a first gate electrode on the substrate, and a second gate electrode on the first gate electrode. The first gate electrode crosses the active region and extends in a second direction. The second gate electrode extends in the second direction. The first gate electrode has a first width in the first direction. The second gate electrode has a second width in the first direction. The second width is less than the first width.
- In example embodiments, the first gate electrode may include a different material than a material of the second gate electrode.
- In example embodiments, the second gate electrode may include a material having a resistivity that is less than a resistivity of the first gate electrode.
- In example embodiments, the semiconductor device may further include a first spacer on the first gate electrode. The first spacer may be positioned at both sides of the second gate electrode.
- In example embodiments, the semiconductor device may further include a second spacer positioned at both sides of the first gate electrode. The second spacer may extend along a sidewall of the first spacer.
- In example embodiments, an inner sidewall of the second spacer may extend upwardly from an upper surface of the active region without bending.
- In example embodiments, the first spacer may have a dielectric constant that is less than a dielectric constant of the second spacer.
- In example embodiments, the semiconductor device may further include a gate dielectric layer covering the both sides of the first gate electrode. A bottom of the first gate electrode may be on the gate dielectric layer.
- In example embodiments, an uppermost surface of the gate dielectric layer may be below the second gate electrode.
- In example embodiments, the semiconductor device may further include a first spacer on an upper surface of the first gate electrode and a second spacer on the substrate. The first spacer may be positioned at both sides of the second gate electrode between the second spacer and the second gate electrode. A portion of the gate dielectric layer may be between the second spacer and the first gate electrode. An uppermost surface of the gate dielectric layer may contact a bottom of the first spacer.
- In example embodiments, the first gate electrode may include a first conductive layer and a second conductive layer. The first conductive layer may include a first portion and a second portion. The first portion may extend parallel to an upper surface of the substrate. The second portion may extend in a vertical direction from the upper surface of the substrate.
- In example embodiments, at least one of the first and second conductive layers may have a line shape extending in a direction.
- In example embodiments, the second gate electrode may include substantially the same material as at least one of the first and second conductive layers.
- In example embodiments, the semiconductor device may further include a source/drain region on the active region at both sides of the first and second gate electrodes. The source/drain region may include a silicon germanium epitaxial layer. The semiconductor device may further include a contact plug on the source/drain region.
- In example embodiments, the active region may include a fin-type active region.
- According to example embodiments of inventive concepts, a semiconductor device includes a substrate having an active region, a gate electrode crossing the active region on the substrate, and a first spacer. The gate electrode may include a first gate electrode on the active region, and a second gate electrode on the first gate electrode. The second gate electrode has a width that is less than a width of the first gate electrode. The first spacer is on an upper surface of the first gate electrode. The first spacer is positioned at both sides of the second gate electrode.
- In example embodiments, the semiconductor device may further include a second spacer positioned at both sides of the gate electrode. The first spacer may be between the second gate electrode and the second spacer.
- According to example embodiments of inventive concepts, a semiconductor device includes a substrate having an active region, a first gate electrode on the active region, a gate dielectric layer between the active region and the first gate electrode, a second gate electrode on the first gate electrode, and a first spacer positioned at a sidewall of the second gate electrode. The first spacer is on an upper portion of the first gate electrode. A portion of the gate dielectric layer extends along a sidewall of the first gate electrode,
- In example embodiments, a bottom surface of the first spacer may contact an upper surface of the gate dielectric layer.
- In example embodiments, the semiconductor device may further include a second spacer on the substrate at a sidewall of the first spacer. A lower portion of the second spacer may contact a sidewall of the gate dielectric layer. The first gate electrode may have a first width. The second gate electrode may have a second width that is less than the first width.
- According to example embodiments of inventive concepts, a method of manufacturing a semiconductor device includes forming an insulating layer having an opening on a substrate, forming a conductive line in the opening by filling the opening with a conductive material, forming a first gate electrode by removing an upper portion of the conductive line, and forming a second gate electrode on an upper surface of the first gate electrode. A width of the second gate electrode may less than a width of the first gate electrode.
- In example embodiments, the first gate electrode may include a different material than the second gate electrode.
- In example embodiments, the method may further include forming a gate dielectric layer on an inner sidewall of the opening and on the substrate before the forming the conductive line. The forming the gate dielectric layer may include removing upper portion of the gate dielectric layer.
- In example embodiments, the method may further include forming a first spacer on an inner sidewall of the opening and on the first gate electrode. A bottom of the first spacer may contact an uppermost surface of the gate dielectric layer.
- In example embodiments, the forming the insulating layer may include forming a sacrificial gate structure on the substrate, forming a dielectric layer on the sacrificial gate structure, planarizing the dielectric layer to expose an upper surface of the sacrificial gate structure, and removing the sacrificial gate structure to expose an upper surface of the substrate.
- In example embodiments, the method may further include forming a device isolation region on the substrate. The device isolation region may define a fin-type active region on the substrate. The fin-type active region may cross the sacrificial gate electrode and may be under the sacrificial gate electrode. The method may further include removing a portion of the fin-type active region at both sides of the sacrificial gate electrode, and forming a source/drain region on the removed upper portion of the fin-type active region.
- In example embodiments, the method may further include forming a second spacer on the substrate at both sides of the sacrificial gate electrode before the forming the dielectric layer, and forming a interlayer dielectric layer on the source/drain region.
- In example embodiments, the second spacer may contact the gate dielectric layer and the first spacer. A portion of the gate dielectric layer may be between the first gate electrode and the second spacer.
- According to example embodiments of inventive concepts, a semiconductor device includes a substrate, an active region extending in a first direction on the substrate, a first gate electrode on the active region, a gate dielectric layer between the first gate electrode and the active region, a first spacer, and a second gate electrode. The active region is one of formed on the substrate and defined by trenches formed in the substrate. The first gate electrode extends in a second direction that crosses the first direction. The first spacer includes two first spacer structures on top of an upper surface of the first gate electrode and spaced apart from each other in the first direction. The second gate electrode is on the first gate electrode between the two first spacer structures.
- In example embodiments, the semiconductor device may further include a second spacer on the active region. The second spacer may include two second spacer structures spaced apart from each other in the first direction. The first spacer structures, the gate dielectric layer, the first gate electrode, and the second gate electrode may be between the two second spacer structures.
- In example embodiments, a dielectric constant of the first spacer may be less than a dielectric constant of the second spacer.
- In example embodiments, the two first spacer structures may be in direct contact with an upper surface of the gate dielectric layer, or the two first spacer structures may be in direct contact with a side surface of the gate dielectric layer.
- In example embodiments, the active region may include a fin-type active region.
- The above aspects and features of inventive concepts will become more apparent by describing in detail example embodiments thereof with reference to the attached drawings, in which:
-
FIG. 1 is a perspective view illustrating a semiconductor device according to example embodiments of inventive concepts; -
FIGS. 2A and 2B are cross-sectional views taken along the lines A-A′ and B-B′ ofFIG. 1 , respectively; -
FIGS. 3 through 6 are cross-sectional views illustrating a semiconductor device according to example embodiments of inventive concepts; -
FIGS. 7A through 7L are perspective views illustrating a method of manufacturing a semiconductor device according to example embodiments of inventive concepts; -
FIGS. 8A through 8C are perspective views illustrating a method of manufacturing a semiconductor device according to example embodiments of inventive concepts; -
FIGS. 9A through 9C are perspective views illustrating a method of manufacturing a semiconductor device according to example embodiments of inventive concepts; -
FIG. 10A is a plan view illustrating a semiconductor device according to example embodiments of inventive concepts; -
FIG. 10B is a cross-sectional view taken along the line C-C′ ofFIG. 10A ; -
FIG. 11 is a circuit diagram illustrating a SRAM (Static Random Access Memory) unit cell according to example embodiments of inventive concepts; -
FIG. 12 is a block diagram illustrating a storage device including a semiconductor device according to example embodiments of inventive concepts; -
FIG. 13 is a block diagram illustrating an electronic device including a semiconductor device according to example embodiments of inventive concepts; and -
FIG. 14 is a block diagram illustrating a system including a semiconductor device according to example embodiments of inventive concepts. - Example embodiments of inventive concepts will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the example embodiments set forth herein.
- It will be understood that when an element is referred to as being “on,” “connected” or “coupled” to another element, it can be directly on, connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as “contacting,” or being “directly on,” “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements or layers should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” “under” versus “directly under”).
- It will be understood that, although the terms “first”, “second”, etc., may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. Unless the context indicates otherwise, these terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of example embodiments.
- In the drawing figures, the dimensions of layers and regions may be exaggerated for clarity of illustration. Like reference numerals refer to like elements throughout. The same reference numbers indicate the same components throughout the specification.
- Spatially relative terms, e.g., “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element(s) or feature(s), as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the example term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
- The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list.
- As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. The use of the terms “a” and “an” and “the” and similar referents in the context of describing embodiments (especially in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. The terms “comprising,” “having,” “including,” and “containing” are to be construed as open-ended terms (i.e., meaning “including, but not limited to”) unless otherwise noted.
- Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. It is noted that the use of any and all examples, or example terms provided herein is intended merely to better illuminate the example embodiments and is not a limitation on the scope of inventive concepts unless otherwise specified.
- Example embodiments will be described with reference to perspective views, cross-sectional views, and/or plan views. The profile of an example view may be modified according to, e.g., manufacturing techniques and/or allowances. Accordingly, the example embodiments are not intended to limit the scope, but cover all changes and modifications that can be caused due to, e.g., a change in manufacturing process. Thus, regions shown in the drawings are illustrated in schematic form and the shapes of the region are presented simply by way of illustration and not as a limitation.
- Unless the context indicates otherwise, terms such as “same,” “equal,” “planar,” or “coplanar,” as used herein when referring to orientation, layout, location, shapes, sizes, amounts, or other measures do not necessarily mean an exactly identical orientation, layout, location, shape, size, amount, or other measure, but are intended to encompass nearly identical orientation, layout, location, shapes, sizes, amounts, or other measures within acceptable variations that may occur, for example, due to manufacturing processes. The term “substantially” may be used herein to reflect this meaning.
- Although corresponding plan views and/or perspective views of some cross-sectional view(s) may not be shown, the cross-sectional view(s) of device structures illustrated herein provide support for a plurality of device structures that extend along two different directions as would be illustrated in a plan view, and/or in three different directions as would be illustrated in a perspective view. The two different directions may or may not be orthogonal to each other. The three different directions may include a third direction that may be orthogonal to the two different directions. The plurality of device structures may be integrated in a same electronic device. For example, when a device structure (e.g., a memory cell structure or a transistor structure) is illustrated in a cross-sectional view, an electronic device may include a plurality of the device structures (e.g., memory cell structures or transistor structures), as would be illustrated by a plan view of the electronic device. The plurality of device structures may be arranged in an array and/or in a two-dimensional pattern.
- Hereinafter, example embodiments of inventive concepts will be described in detail with reference to the accompanying drawings.
-
FIG. 1 is a perspective view illustrating a semiconductor device according to example embodiments of inventive concepts.FIGS. 2A and 2B are cross-sectional views taken along the lines A-A′ and B-B′ ofFIG. 1 , respectively. For convenience of description, some of elements, for example, aninterlayer insulating layer 170 shown inFIGS. 2A and 2B , are omitted inFIG. 1 . - Referring to
FIGS. 1, 2A, and 2B , asemiconductor device 100 may include asubstrate 101, anactive region 105, a source/drain region 110, agate dielectric layer 140, agate electrode 150, and acontact plug 180. Thesemiconductor device 100 may further include adevice isolation region 107, afirst spacer 162, asecond spacer 164, and an interlayer insulatinglayer 170. - In example embodiments, the
semiconductor device 100 may include a fin-type field effect transistor (FinFET) having a plurality of fin-type active regions. - The
substrate 101 may have an upper surface extending in X-direction and Y-direction. Thesubstrate 101 may include a semiconductor material, e.g., a group IV compound semiconductor, a group III-V compound semiconductor, or a group II-VI silicon-oxide semiconductor. For example, the group IV compound semiconductor may include silicon (Si), germanium (Ge), and/or silicon germanium (SiGe). Thesubstrate 101 may be a bulk silicon wafer, an epitaxial layer, a silicon-on-insulator (SOI) substrate, or a semiconductor-on-insulator (SeOI) substrate. - The
device isolation region 107 may define theactive region 105 on thesubstrate 101. Thedevice isolation region 107 may include a dielectric material, e.g., silicon oxide, silicon nitride, or the mixture thereof. Thedevice isolation region 107 may be formed using a shallow trench isolation (STI) process. - The
active region 105 may extend in a first direction, e.g., the Y-direction. Theactive region 105 may be a fin-type active region that is protruding from thesubstrate 101. In example embodiments, theactive region 105 may be a portion of thesubstrate 101 and/or include an epitaxial layer grown from thesubstrate 101. Theactive region 105 may be recessed at both sides of agate electrode 150. - The source/
drain region 110 may be formed at both sides of thegate electrode 150 and on the recessedactive region 105. The source/drain region 110 may be provided a source region or a drain region of thesemiconductor device 100. The source/drain region 110 may have an elevated structure. Therefore, an upper surface of the source/drain region 110 may be higher than a bottom surface of thegate electrode 150. In example embodiments, the source/drain region 110 may have a pentagonal shape. However, it shall not be restricted or limited thereto. For example, the source/drain region 110 may have a polygonal shape, a circle shape, or a rectangular shape. The source/drain region 110 may have a connected structure or a merged structure that is formed on three active regions. In example embodiments, the source/drain region 110 may do not have a connected structure or a merged structure. - The source/
drain region 110 may include silicon (Si) or silicon germanium (SiGe). The source/drain region 110 may be formed of an epitaxial layer. If the source/drain region 110 includes SiGe and a channel region includes Si in a PMOS transistor, the source/drain region 110 may induce a compressive stress into the channel region and thereby a hole mobility may be increased in the channel region of a PMOS transistor. In example embodiments, the source/drain region 110 may have a plurality of regions having different impurities and different impurity concentrations each other. - The
gate dielectric layer 140 and thegate electrode 150 crossing theactive region 105 may be formed on the fin-type active region. Thegate electrode 150 may include afirst gate electrode 152 and asecond gate electrode 154 which are stacked on each other. - The
gate dielectric layer 140 may be disposed between theactive region 105 and thefirst gate electrode 152. A portion of thegate dielectric layer 140 may be extended along both sides of thefirst gate electrode 152. In example embodiments, thegate dielectric layer 140 may be only formed beneath thefirst gate electrode 152. - The
gate dielectric layer 140 may include an insulating layer, e.g., a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, and/or a high-k dielectric layer. The high-k dielectric layer may be an insulating material that has a dielectric constant that is greater than a dielectric constant of silicon oxide. For example, the high-k dielectric layer may include at least one of aluminum oxide (Al2O3), tantalum oxide (Ta2O3), Yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSixOy), hafnium oxide (HfO2), hafnium silicon oxide (HfSixOy), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlxOy), lanthanum hafnium oxide (LaHfxOy), hafnium aluminum oxide (HfAlxOy), and/or praseodymium oxide (Pr2O3). - The
gate electrode 150 may be extended in the X-direction. Thefirst gate electrode 152 may be formed on thegate dielectric layer 140. Thesecond gate electrode 154 may be formed on thefirst gate electrode 152. A channel region may be formed in an upper portion of theactive region 105 that is overlapped by thegate electrode 150. Thefirst spacer 162 includes two first spacer structures at opposite sides of thesecond gate electrode 154. Thesecond spacer 164 includes two second spacer structures. - The
first gate electrode 152 may have a first width L1 in the first direction, e.g., the Y-direction. Thesecond gate electrode 154 may have a second width L2 less than the first width L1 in the first direction. - A
contact plug 180 may be formed on the source/drain region 110. In example embodiments, a lower portion of thesecond gate electrode 154 may have a level that is substantially the same as a bottom of thecontact plug 180. Therefore, a parasitic capacitance between thesecond gate electrode 154 and thecontact plug 180 may be reduced by reducing the second width L2 of thesecond gate electrode 154. - An upper surface of the
first gate electrode 152 may have a first height H1 from an upper surface of thesubstrate 101. An upper surface of thesecond gate electrode 154 may have a second height H2 from the upper surface of thefirst gate electrode 152. In example embodiments, an interface between thefirst gate electrode 152 and thesecond gate electrode 154 may have a level less than or equal to the bottom surface of thecontact plug 180. However, it shall not be restricted or limited thereto. - As shown in
FIG. 2A , the upper surface of thefirst gate electrode 152 may have a third height H3 from an upper surface of theactive region 105. The third height H3 may be less than the first height H1. The upper surface of thesecond gate electrode 154 may have a fourth height H4 from the upper surface of theactive region 105. The fourth height H4 may be substantially the same as the second height H2. However, it shall not be restricted or limited thereto. - The
first gate electrode 152 may have a different material from thesecond gate electrode 154. Thefirst gate electrode 152 may include a material having a work-function that is available to form a proper threshold voltage of a transistor. In example embodiments, thefirst gate electrode 152 may include a titanium nitride (TiN) layer, a titanium aluminum carbide (TiAlC) layer, and/or a tungsten (W) layer. Thesecond gate electrode 154 may include a material having a lower resistivity. Thesecond gate electrode 154 may include aluminum (Al), tungsten (W), copper (Cu), and/or molybdenum (Mo). A resistivity of thesecond gate electrode 154 may be less than a resistivity of thefirst gate electrode 152. Each of the first andsecond gate electrodes - A
first spacer 162 and asecond spacer 164 may be formed on both sides of thegate electrode 150. Thegate electrode 150 may be isolated from the source/drain region 110 by the first andsecond spacers - In example embodiments, the
first spacer 162 may be formed both sides of thesecond gate electrode 154. Thefirst spacer 162 may be formed on thegate dielectric layer 140 and thefirst gate electrode 152. A portion of thefirst spacer 162 may be formed on an upper portion of thefirst gate electrode 152 because the second width L2 of thesecond gate electrode 154 is less than the first width L1 of thefirst gate electrode 152. Thesecond spacer 164 may be formed on both sides of the first andsecond gate electrodes second spacer 164 may be formed along a sidewall of thegate dielectric layer 140 and a sidewall of thefirst spacer 162. An inner sidewall of thesecond spacer 164 may be extended upwardly from an upper surface of the active region without bending. - Each of the first and
second spacers first spacer 162 or thesecond spacer 164 may be formed of a low-k dielectric layer to reduce a capacitance between thegate electrode 150 and thecontact plug 180. For example, the first andsecond spacers - According to example embodiments of inventive concepts, a shortage between the
second gate electrode 154 and thecontact plug 180 may be reduced by reducing the second width L2 of thesecond gate electrode 154. - The
contact plug 180 may be formed on the source/drain region 110 and electrically connected to a conductive line (not shown in figures) for transferring electrical signals to the source/drain region 110. Thecontact plug 180 may have a bar shape extending in the first direction or an elliptical shape. - The
contact plug 180 may pass through the interlayer insulatinglayer 170 and contact to the source/drain region 110. In example embodiments, an upper portion of the source/drain region 110 may have a recessed region and a bottom of thecontact plug 180 may be disposed in the recessed portion. However, it shall not be restricted or limited thereto. - A lower portion of the
contact plug 180 may have a diffusion barrier layer or a silicide layer. In example embodiments, thecontact plug 180 may contact a silicide layer that is formed on an upper portion of the source/drain region 110. Thecontact plug 180 may include a conductive material, e.g., titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), aluminum (Al), copper (Cu), tungsten (W), or molybdenum (Mo). - The interlayer insulating
layer 170 may include a firstinterlayer insulating layer 172 and a secondinterlayer insulating layer 174. The interlayer insulatinglayer 170 may be formed on thesubstrate 101, the source/drain region 110, and thegate electrode 150. An upper surface of the firstinterlayer insulating layer 172 may be substantially coplanar with an upper surface of thegate electrode 150. - The first and second
interlayer insulating layer interlayer insulating layer 172 may include a low-k dielectric layer. The firstinterlayer insulating layer 172 and the secondinterlayer insulating layer 174 may be formed of different materials. -
FIGS. 3 through 6 are cross-sectional views illustrating a semiconductor device according to example embodiments of inventive concepts. - Referring to
FIG. 3 , asemiconductor device 100 a may include asubstrate 101, a plurality of fin-typeactive regions 105, a plurality of source/drain regions 110, agate dielectric layer 140, agate electrode 150 a, and a plurality of contact plugs 180. Thesemiconductor device 100 may further include adevice isolation region 107, afirst spacer 162, and asecond spacer 164. - The
gate electrode 150 a may include afirst gate electrode 152 and asecond gate electrode 154. Thegate electrode 150 a may be formed on thegate dielectric layer 140. - The
first gate electrode 152 may include a firstconductive layer 152A and a secondconductive layer 152B. The firstconductive layer 152A may be formed directly on thegate dielectric layer 140. The firstconductive layer 152A may be formed beneath and on both sides of the secondconductive layer 152B. In example embodiments, an upper surface of the secondconductive layer 152B may be substantially coplanar with an uppermost surface of thegate dielectric layer 140. - The
second gate electrode 154 may be formed on the firstconductive layer 152A and the secondconductive layer 152B. Thesecond gate electrode 154 may have a width less than a width of thefirst gate electrode 152. Thesecond gate electrode 154 may have a width greater than a width of the secondconductive layer 152B. However, it shall not be restricted or limited thereto. - The
first gate electrode 152 may include a different material from thesecond gate electrode 154. The secondconductive layer 152B may include a material having a resistivity less than a resistivity of the firstconductive layer 152A. Thesecond gate electrode 154 may include a material having a resistivity less than a resistivity of at least one of the firstconductive layer 152A and a secondconductive layer 152A. - Referring to
FIG. 4 , asemiconductor device 100 b may include asubstrate 101, a plurality of fin-typeactive regions 105, a plurality of source/drain regions 110, agate dielectric layer 140, agate electrode 150 b, and a plurality of contact plugs 180. Thesemiconductor device 100 b may further include adevice isolation region 107, afirst spacer 162, and asecond spacer 164. - The
gate electrode 150 b may include afirst gate electrode 152 and asecond gate electrode 154. Thegate electrode 150 b may be formed on thegate dielectric layer 140. - The
first gate electrode 152 may include a firstconductive layer 152A′ and a secondconductive layer 152B′. The firstconductive layer 152A′ may be formed directly on thegate dielectric layer 140. The firstconductive layer 152A′ may be formed beneath and on both sides of the secondconductive layer 152B′. In example embodiments, an upper surface of the secondconductive layer 152B′ may be substantially coplanar with an uppermost surface of thegate dielectric layer 140. - The
second gate electrode 154 may be formed on the firstconductive layer 152A′ and the secondconductive layer 152B′. Thesecond gate electrode 154 may have a width less than a width of thefirst gate electrode 152. Thesecond gate electrode 154 may have a width substantially equal to a width of the secondconductive layer 152B′. Thesecond gate electrode 154 may be formed of a conductive material that is substantially the same as the secondconductive layer 152B′. However, it shall not be restricted or limited thereto. - The first
conductive layer 152A′ may include a different material from the secondconductive layer 152B′. The secondconductive layer 152B′ and/or thesecond gate electrode 154 may include a material having a resistivity less than that of the firstconductive layer 152A′. - Referring to
FIG. 5 , asemiconductor device 100 c may include asubstrate 101, a plurality of fin-typeactive regions 105, a plurality of source/drain regions 110, agate dielectric layer 140, agate electrode 150 c, and a plurality of contact plugs 180. Thesemiconductor device 100 c may further include adevice isolation region 107, afirst spacer 162 a, and asecond spacer 164. - The
gate electrode 150 c may include afirst gate electrode 152 and asecond gate electrode 154 a. Thegate electrode 150 c may be formed on thegate dielectric layer 140. - In example embodiments, the
first spacer 162 a formed on both sides of thesecond gate electrode 154 a may have a curved inner sidewall. As the result, a width L5 of an upper portion of thesecond gate electrode 154 a may be greater than a width L6 of a bottom portion of thesecond gate electrode 154 a. - Referring to
FIG. 6 , asemiconductor device 100 d may include asubstrate 101, a plurality of fin-typeactive regions 105, a plurality of source/drain regions 110, agate dielectric layer 140 a, agate electrode 150, and a plurality of contact plugs 180. Thesemiconductor device 100 d may further include adevice isolation region 107, afirst spacer 162, and asecond spacer 164. - The
gate dielectric layer 140 a may be formed between the fin-typeactive region 105 and thefirst gate electrode 152. In example embodiments, a portion of thegate dielectric layer 140 a may be extended along a sidewall of thefirst spacer 162 that is formed on both sides of thesecond gate electrode 154. In example embodiments, an uppermost surface of thegate dielectric layer 140 a may be substantially coplanar with an upper surface of thesecond gate electrode 154. -
FIGS. 7A through 7L are perspective views illustrating a method of manufacturing a semiconductor device according to example embodiments of inventive concepts. - Referring to
FIG. 7A , a plurality of trenches TI may be formed on an upper portion of thesubstrate 101. The trenches TI may define a plurality of fin-typeactive region 105. - A
pad oxide pattern 122 and amask pattern 124 may be formed on each of the fin-typeactive regions 105. Thepad oxide pattern 122 and themask pattern 124 may be used as masks during the formation of the fin-typeactive regions 105. In example embodiments, thepad oxide pattern 122 and themask pattern 124 may be omitted. Themask pattern 124 may include silicon oxide, silicon nitride, and/or carbide mixture. Themask pattern 124 may include multiple layers. - In example embodiments, the trenches TI may be formed by etching the
substrate 101 using an anisotropic etching process. The trenches TI may have a high aspect ratio. Each of the trenches TI may have variable widths that are gradually reduced from an upper portion to a lower portion thereof. Therefore, each of the fin-typeactive regions 105 may have variable widths that are gradually reduced from a lower portion to an upper portion thereof. - Referring to
FIG. 7B , adevice isolation region 107 may be formed in the trenches TI. Forming thedevice isolation region 107 may include forming an insulating layer in the trenches TI and performing a planarization process to the insulating layer. At least a portion of thepad oxide pattern 122 and themask pattern 124 may be removed during the planarization process. In example embodiments, a thin liner layer may be formed in the trenches TI before forming the insulating layer. The insulating layer may be recessed to expose an upper portion of the fin-typeactive regions 105 after the planarization process. The insulating layer may be recessed by a wet etching process using the oxide pattern or the mask pattern as an etching mask. As the result, the fin-typeactive region 105 may be protruded from an upper surface of thedevice isolation region 107. Theoxide pattern 122 and themask pattern 124 may be removed. The upper surface of the fin-type action regions 105 may have a height H5. - Referring to
FIG. 7C , a firstsacrificial layer 132 and a secondsacrificial layer 135 may be formed on the fin-typeactive regions 105. The first and secondsacrificial layers sacrificial layers mask layer 136 as an etching mask. - The
second spacer 164 may be formed on both sides of the firstsacrificial layers 132 and the secondsacrificial layer 135. The firstsacrificial layer 132 may include an insulating layer and the secondsacrificial layer 135 may include a conductive layer. However, it shall not be restricted or limited thereto. For example, the firstsacrificial layer 132 may include a silicon oxide layer and the secondsacrificial layer 135 may include a polysilicon layer. In example embodiments, the first and secondsacrificial layers - In example embodiments, the
second spacer 164 may be formed on both sides of the firstsacrificial layer 132, the secondsacrificial layer 135, and themask layer 136. Forming thesecond spacer 164 may include forming a dielectric layer on and both sides of themask layer 136 and the first and secondsacrificial layers mask layer 136. In example embodiments, thesecond spacer 164 may be formed of multiple layers. At this moment, athird spacer 166 may be formed on both sides of the fin-typeactive regions 105. - Referring to
FIG. 7D , some upper portions of the fin-typeactive regions 105 may be recessed by an etching process using themask layer 136 and thesecond spacer 164 as etching masks. The etching process may include a dry etching process and/or a wet etching process. A curing process may be performed to an upper surface of the recessed fin-typeactive regions 105. The upper surface of the recessed fin-typeactive regions 105 may be coplanar with an upper surface of thedevice isolation region 107. However, it shall not be restricted or limited thereto. In example embodiments, the upper surface of the recessed fin-typeactive regions 105 may have a level greater than or less than the upper surface of thedevice isolation region 107. - An impurity doping process may be performed to the recessed fin-type
active regions 105 using themask layer 136 and thesecond spacer 164 as masks. - Referring to
FIG. 7E , a plurality of source/drain regions 110 may be formed on the recessed fin-typeactive regions 105 and both sides of thesecond spacer 164. The source/drain regions 110 may be formed using a selective epitaxial growth (SEG) process. The source/drain regions 110 may include silicon germanium (SiGe). - In example embodiments, the source/
drain regions 110 may include several epitaxial layer having different germanium (Ge) concentrations, respectively. Some impurities, e.g., boron (B), may be doped in the source/drain regions 110 during or after the selective epitaxial growth (SEG) process. The source/drain regions 110 may have a pentagonal shape or a hexagonal shape. However, it shall not be restricted or limited thereto. For example, the source/drain regions 110 may have a polygonal shape, a circle shape, or a rectangular shape. - Referring to
FIG. 7F , a firstinterlayer insulating layer 172 may be formed on the source/drain regions 110. Forming the firstinterlayer insulating layer 172 may include forming an insulating layer on the source/drain regions 110 and performing a planarization process to the insulating layer to expose an upper surface of the secondsacrificial layer 135. Themask layer 136 may be removed during the forming the firstinterlayer insulating layer 172. - The first
interlayer insulating layer 172 may include silicon oxide, silicon nitride, and/or silicon oxynitride. In example embodiments, the firstinterlayer insulating layer 172 may include a low-k dielectric material. - Referring to
FIG. 7G , the first and secondsacrificial layers device isolation region 107 and the fin-typeactive regions 105. The first and secondsacrificial layers - Referring to
FIG. 7H , a preliminarygate dielectric layer 140P and a firstpreliminary gate electrode 152P in the first opening E1. The preliminarygate dielectric layer 140P may be conformally formed along both sidewalls and a bottom of the first opening E1. The preliminarygate dielectric layer 140P may include silicon oxide, silicon nitride, and/or a high-k dielectric material. - The
preliminary gate electrode 152P may be formed on the preliminarygate dielectric layer 140P. Thepreliminary gate electrode 152P may include metal and/or semiconductor material. Thepreliminary gate electrode 152P may include multiple layers. - The preliminary
gate dielectric layer 140P and the firstpreliminary gate electrode 152P may be planarized to expose an upper surface of the firstinterlayer insulating layer 172 using a chemical mechanical polishing (CMP) process. - Referring to
FIG. 7I , an upper portions of the preliminarygate dielectric layer 140P and the firstpreliminary gate electrode 152P may be recessed to form thegate dielectric layer 140 and thefirst gate electrode 152. The preliminarygate dielectric layer 140P and the firstpreliminary gate electrode 152P may be selectively recessed with respect to thesecond spacer 164 and the firstinterlayer insulating layer 172 using a single etching process or multiple etching processes. An upper surface of thegate dielectric layer 140 may be coplanar with an upper surface of thefirst gate electrode 152. However, it shall not be restricted or limited thereto. For example, the preliminarygate dielectric layer 140P may not be recessed as shown inFIG. 6 . - A second opening E2 may be formed after forming the
gate dielectric layer 140 and thefirst gate electrode 152. - Referring to
FIG. 7J , afirst spacer 162 may be formed on both sidewalls of the second opening E2. In example embodiments, thefirst spacer 162 may be formed on thegate dielectric layer 140 and a portion of thefirst gate electrode 152. - The
first spacer 162 may be formed on a sidewall of thesecond spacer 164 that is exposed by the second opening E2. Forming thefirst spacer 162 may include forming a dielectric layer on thegate dielectric layer 140, thefirst gate electrode 152, and the firstinterlayer insulating layer 172. Forming thefirst spacer 162 may further include etching the dielectric layer using an isotropic etching process. Thefirst spacer 162 may have a substantially rectangular shape in a cross-sectional view. In example embodiments, a sidewall of thefirst spacer 162 a may have a curved shape as shown inFIG. 5 . - Referring to
FIG. 7K , asecond gate electrode 154 may be formed in the second opening E2. Thesecond gate electrode 154 may be formed on thefirst gate electrode 152. Forming thesecond gate electrode 154 may include forming a conductive layer in the second opening E2 and on the firstinterlayer insulating layer 172. Forming thesecond gate electrode 154 may further include performing a planarization process to the conductive layer using a CMP process to expose an upper surface of the firstinterlayer insulating layer 172. - A width of the
first gate electrode 152 may be different from a width of thesecond gate electrode 154 in a cross-sectional view. - Referring to
FIG. 7L , a secondinterlayer insulating layer 174 may be formed on the firstinterlayer insulating layer 170 and thesecond gate electrode 154. A plurality of contact holes OP may be formed in the first and secondinterlayer insulating layers drain regions 110. The upper surface of the source/drain regions 110 may be recessed during the forming the contact holes OP. A bottom portion of the contact holes OP may have a curved shape along an upper surface of the source/drain region 110. The contact holes OP may be filled by a conductive layer to form a plurality of contact plugs 180 as shown inFIG. 1 . A silicide layer may be formed between the contact plugs 180 and the source/drain regions 110. In example embodiments, the silicide layer may be a portion of the contact plugs 180. -
FIGS. 8A through 8C are perspective views illustrating a method of manufacturing a semiconductor device according to example embodiments of inventive concepts. For convenience of description, some of explanation which is substantially the same description described above referring toFIGS. 7A through 7L will be omitted. - Referring to
FIG. 8A , a secondpreliminary gate electrode 154P may be formed on thegate dielectric layer 140 and thefirst gate electrode 152 afterFIG. 7I . More specifically, the secondpreliminary gate electrode 154P may fill the second opening E2 shown inFIG. 7I . - Referring to
FIG. 8B , amask layer 126 extending in the second direction may be formed on the secondpreliminary gate electrode 154P. Both side end portions of the secondpreliminary gate electrode 154P may be exposed by themask layer 126. Themask layer 126 may include a photoresist layer. However, it shall not be restricted or limited thereto. Themask layer 126 may have a width L7 less than the width L1 (SeeFIG. 1 ) of thefirst gate electrode 152 in a cross-sectional view. - Referring to
FIG. 8C , the both side end portions of the secondpreliminary gate electrode 154P may be removed to form asecond gate electrode 154 having a width less than the width L1 of thefirst gate electrode 152. Themask layer 126 may be removed after forming thesecond gate electrode 154. - In example embodiments, a
first spacer 162 may be formed after forming thesecond gate electrode 154. For example, thefirst spacer 162 may be formed by filling a dielectric layer on both sides of the second gate electrode 154 (referFIG. 7K ). - Alternatively, the second gate electrode and the first spacer (see 162 in
FIG. 1 ) is formed by oxidizing a portion of the secondpreliminary gate electrode 154P that is exposed by themask layer 126 inFIG. 8B , for example, an oxygen plasma or an oxygen-implant process. -
FIGS. 9A through 9C are perspective views illustrating a method of manufacturing a semiconductor device according to example embodiments of inventive concepts. For convenience of description, some of explanation which is substantially the same description described above referring toFIGS. 7A through 7L will be omitted. - Referring to
FIG. 9A , a preliminarygate dielectric layer 140P, a preliminary first conductive layer 152PA′, and a thirdsacrificial layer 138 may be formed in the first opening E1 afterFIG. 7G . - The preliminary
gate dielectric layer 140P and the preliminary first conductive layer 152PA′ may be conformally formed along both sidewalls and a bottom of the first opening E1. The preliminarygate dielectric layer 140P may include silicon oxide, silicon nitride, and/or a high-k material. The preliminary first conductive layer 152PA′ may include metal and/or metal compounds. The thirdsacrificial layer 138 may have an etching selectivity with respect to the preliminarygate dielectric layer 140P, the preliminary first conductive layer 152PA′, and thesecond spacer 164. - The preliminary
gate dielectric layer 140P, the preliminary first conductive layer 152PA′, and the thirdsacrificial layer 138 may be planarized to exposed an upper surface of the firstinterlayer insulating layer 172 using a CMP process. - Referring to
FIG. 9B , upper portions of the preliminarygate dielectric layer 140P and the preliminary first conductive layer 152PA′ may be recessed to form agate dielectric layer 140 and a firstconductive layer 152A′ using an etch-back process. - In example embodiments, the third
sacrificial layer 138 may be simultaneously recessed during the etch-back process. A second opening E2 may be formed on thegate dielectric layer 140 and a firstconductive layer 152A′ after the etch-back process. However, it shall not be restricted or limited thereto. For example, the thirdsacrificial layer 138 may not be recessed during the etch-back process. - Referring to
FIG. 9C , afirst spacer 162 may be formed on both sidewalls of the second opening E2. A sidewall of thefirst spacer 162 may contact a sidewall of thesecond spacer 164 that is exposed by the second opening E2. A thickness of thefirst spacer 162 may be substantially the same as the sum of the thicknesses of thegate dielectric layer 140 and the firstconductive layer 152A′ on a sidewall of thesecond spacer 164. However, it shall not be restricted or limited thereto. The thirdsacrificial layer 138 may be removed after forming thefirst spacer 162. - Referring to
FIG. 4 again, a secondconductive layer 152B′ on the first conductive layer 152 g. Afirst gate electrode 152′ may be formed of the firstconductive layer 152A′ and the secondconductive layer 152B′. Asecond gate electrode 154 may be formed on thefirst gate electrode 152′. In example embodiments, the secondconductive layer 152B′ and thesecond gate electrode 154 may be simultaneously formed of same material. -
FIG. 10A is a plan view illustrating a semiconductor device according to example embodiments of inventive concepts.FIG. 10B is a cross-sectional view taken along the line C-C′ ofFIG. 10A . - Referring to
FIGS. 10A and 10B , asemiconductor device 200 may include asubstrate 201, anactive region 205, a first source/drain region 212, a second source/drain 214, agate dielectric layer 240, agate electrode 250, afirst contact plug 282, and asecond contact plug 284. Thesemiconductor device 200 may further include adevice isolation region 207, afirst spacer 262, asecond spacer 264, and an interlayer insulatinglayer 270. Theactive region 205 extending in X-direction may be formed on thesubstrate 201. Thegate electrode 250 extending in Y-direction may be formed on theactive region 205. Thesemiconductor device 200 may include a planar type transistor. - The
substrate 201 may have an upper surface extending in the X-direction and the Y-direction. Thesubstrate 201 may include a semiconductor material, e.g., a group IV compound semiconductor, a group III-V compound semiconductor, or a group II-VI silicon-oxide semiconductor. For example, the group IV compound semiconductor may include silicon (Si), germanium (Ge), and/or silicon germanium (SiGe). Thesubstrate 101 may be a bulk silicon wafer, an epitaxial layer, a silicon-on-insulator (501) substrate, or a semiconductor-on-insulator (SeOI) substrate. - The
device isolation region 207 may define theactive region 205 on thesubstrate 201. Thedevice isolation region 207 may include a dielectric material, e.g., silicon oxide, silicon nitride, or the mixture thereof. Thedevice isolation region 207 may be formed using a shallow trench isolation (STI) process. - The
active region 205 may be extended in the X-direction and defined by thedevice isolation region 207. - The first and second source/
drain regions gate electrode 250 and in theactive region 205. The first and second source/drain regions drain regions gate electrode 250. - The
gate dielectric layer 240 and thegate electrode 250 crossing theactive region 205 may be formed on theactive region 205. Thegate electrode 250 may include afirst gate electrode 252 and asecond gate electrode 254 which are stacked on each other. Thegate dielectric layer 240 may include an insulating layer, e.g., a silicon oxide layer, a silicon oxynitride layer, and/or a silicon nitride layer. - The first and
second gate electrodes second gate electrodes second gate electrode 254 may include a material having a lower resistivity less than that of thefirst gate electrode 252. - The
first spacer 262 may be formed on both sides of thesecond gate electrode 254. Thesecond spacer 264 may be formed on both sides of the first andsecond gate electrodes second spacer 264 may contact sidewalls of thegate dielectric layer 240 and thefirst spacer 262. The first andsecond spacers second spacers - The interlayer insulating
layer 270 may be formed on thesubstrate 201, the first and second source/drain regions gate electrode 250. The interlayer insulatinglayer 270 may include silicon oxide, silicon nitride, and/or silicon oxynitride. - The first and second contact plugs 282 and 284 may be formed on the first and second source/
drain region - In example embodiments, the
semiconductor 200 may include a vertical structured transistor having a vertical channel region. -
FIG. 11 is a circuit diagram illustrating a SRAM (Static Random Access Memory) cell according to example embodiments of inventive concepts. - Referring to
FIG. 11 , the SRAM cell may have a first inverter and a second inverter which are formed between a power supply node Vdd and a ground node Vss. The first inverter, having an input node and an output node, may comprise a first pull-up transistor TP1 and a first pull-down transistor TN1. The second inverter, having an input node and an output node, may have a second pull-up transistor TP2 and a second pull-down transistor TN2. The input node of the first inverter may be connected to a source/drain region of a second pass transistor TN4 as well as to the output node of the second inverter. The input node of the second inverter may be connected to a source/drain region of a first pass transistor TN4 as well as to the output node of the first inverter. Gate electrodes of the first and second pass transistors TN3 and TN4 may be connected to a word line WL. A bit line BL may be connected to a source/drain region of the first pass transistor TN3. A bit line bar/BL may be connected to a source/drain region of the second pass transistor TN4. The first and second pull-up transistors TP1 and TP2 may be PMOS transistors. The first and second pull-down transistors TN1 and TN2 and the first and second pass transistors TN3 and TN4 may be NMOS transistors. The first and second pull-up transistors TP1 and TP2 may be formed according to example embodiments of inventive concepts. -
FIG. 12 is a block diagram of a storage device including a semiconductor device according to example embodiments of inventive concepts. - Referring to
FIG. 12 , astorage apparatus 1000 according to example embodiments of inventive concepts may include acontroller 1010 communicating with a Host, and memories 1020-1, 1020-2 and 1020-3 storing data. The respective memories 1020-1, 1020-2 and 1020-3 may include one of the semiconductor devices according to example embodiments of inventive concepts described with reference toFIGS. 1 through 10B . - Examples of the host communicating with the
controller 1010 may include various electronic devices on which thestorage apparatus 1000 is mounted. For example, the host may be, for example, a smartphone, a digital camera, a desktop computer, a laptop computer, a portable media player or the like. Thecontroller 1010 may receive a data writing or reading request transferred from the host to store data in the memories 1020-1, 1020-2 and 1020-3 or generate a command for retrieving data from the memories 1020-1, 1020-2 and 1020-3. - As illustrated in
FIG. 12 , at least one or more memories 1020-1, 1020-2 and 1020-3 may be connected to thecontroller 1010 in parallel in thestorage apparatus 1000. The plurality of memories 1020-1, 1020-2 and 1020-3 may be connected to thecontroller 1010 in parallel, whereby thestorage apparatus 1000 having high capacity such as a solid state drive may be implemented. -
FIG. 13 is a block diagram of an electronic device including a semiconductor device according to example embodiments of inventive concepts - Referring to
FIG. 13 , anelectronic apparatus 2000 according to example embodiments may include acommunications unit 2010, aninput unit 2020, anoutput unit 2030, amemory 2040, and aprocessor 2050. - The
communications unit 2010 may include a wired or wireless communications module, a wireless Internet module, a local area communications module, a global positioning system (GPS) module, a mobile communications module and the like. The wired or wireless communications module included in thecommunications unit 2010 may be connected to external communications networks according to various communications standard specification to transmit and receive data. - The
input unit 2020 may be a module provided to control an operation of theelectronic apparatus 2000 by a user and may include a mechanical switch, a touch screen, a voice recognition module, and the like. In addition, theinput unit 2020 may include a mouse operating in a track ball or a laser pointer scheme or a finger mouse device. In addition to these, theinput unit 2020 may further include various sensor modules allowing for a user to input data thereto. - The
output unit 2030 may output information processed in theelectronic apparatus 2000 in a sound or image form, and thememory 2040 may store programs for the processing and the control of theprocessor 2050. Thememory 2040 may include at least one semiconductor device according to various example embodiments of inventive concepts as described with reference toFIGS. 1 through 10B . Theprocessor 2050 may transfer a command to thememory 2040 according to a required operation to thereby store or retrieve data. - The
memory 2040 may be embedded in theelectronic apparatus 2000 to communicate with theprocessor 2050 or communicate with theprocessor 2050 through a separate interface. In a case in which thememory 2040 communicates with theprocessor 2050 through a separate interface, theprocessor 2050 may store or retrieve data, through various interface standards such as SD, SDHC, SDXC, MICRO SD, USB and the like. - The
processor 2050 may control operations of respective components included in theelectronic apparatus 2000. Theprocessor 2050 may perform control and processing in association with voice communications, video telephony, data communications and the like, or may perform control and processing for multimedia reproduction and management. In addition, theprocessor 2050 may process an input transferred from a user through theinput unit 2020 and may output results thereof through theoutput unit 2030. In addition, theprocessor 2050 may store data required in controlling the operation of theelectronic apparatus 2000 as described above, in thememory 2040, or fetch data from thememory 2040. -
FIG. 14 is a block diagram of a system including a semiconductor device according to example embodiments of inventive concepts. - Referring to
FIG. 14 , asystem 3000 may include acontroller 3100, an input/output device 3200, amemory 3300, and aninterface 3400. Thesystem 3000 may transmit or receive mobile system or information. Examples of the mobile system may include PDAs, portable computers, web tablets, wireless phones, mobile phones, digital music players and memory cards. - The
controller 3100 may execute a program and control thesystem 3000. Thecontroller 3100 may be a microprocessor, a digital signal processor, a microcontroller or device similar thereto. - The input/
output device 3200 may be used to input or output data to or from thesystem 3000. Thesystem 3000 may be connected to an external device, for example, a personal computer or networks and may exchange data with the external device. The input/output device 3200 may be a keypad, a keyboard, or a display device. - The
memory 3300 may store a code and/or data for operating thecontroller 3100 and/or store data having been processed by thecontroller 3100. Thememory 3300 may include the semiconductor device according to one of the example embodiments of inventive concepts. - The
interface 3400 may be a data transmission path between thesystem 3000 and an external device. Thecontroller 3100, the input/output device 3200, thememory 3300, and theinterface 3400 may be in communication with one another via abus 3500. - At least one of the
controller 3100 or thememory 3300 may include at least one of the semiconductor devices described with reference toFIGS. 1 through 10B . - The above-disclosed subject matter is to be considered illustrative and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the true spirit and scope of inventive concepts. Descriptions of features or aspects within each device or method according to example embodiments should typically be considered as available for other similar features or aspects in other devices or methods according to example embodiments. Thus, the scope of inventive concepts is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.
Claims (23)
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10121873B2 (en) * | 2016-07-29 | 2018-11-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal gate and contact plug design and method forming same |
US20190006236A1 (en) * | 2016-11-29 | 2019-01-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-Aligned Spacers and Method Forming Same |
US10505021B2 (en) | 2017-09-29 | 2019-12-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFet device and method of forming the same |
US20210175346A1 (en) * | 2018-01-04 | 2021-06-10 | Stmicroelectronics (Rousset) Sas | Mos transistor spacers and method of manufacturing the same |
US20220336452A1 (en) * | 2018-10-23 | 2022-10-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated Circuits with FinFET Gate Structures |
US11532504B2 (en) * | 2017-04-07 | 2022-12-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Low-resistance contact plugs and method forming same |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20160141034A (en) * | 2015-05-27 | 2016-12-08 | 삼성전자주식회사 | Semiconductor devices and methods of manufacturing semiconductor devices |
US9583486B1 (en) * | 2015-11-19 | 2017-02-28 | International Business Machines Corporation | Stable work function for narrow-pitch devices |
US9865703B2 (en) * | 2015-12-31 | 2018-01-09 | International Business Machines Corporation | High-K layer chamfering to prevent oxygen ingress in replacement metal gate (RMG) process |
KR102308779B1 (en) * | 2017-04-10 | 2021-10-05 | 삼성전자주식회사 | Integrated circuit having heterogeneous contacts and semiconductor device including the same |
KR102472571B1 (en) * | 2018-07-20 | 2022-12-01 | 삼성전자주식회사 | Semiconductor device |
US10727317B2 (en) | 2018-10-04 | 2020-07-28 | International Business Machines Corporation | Bottom contact formation for vertical transistor devices |
KR20220040024A (en) * | 2020-09-23 | 2022-03-30 | 삼성전자주식회사 | Semiconductor device and method for fabricating thereof |
KR20220119821A (en) * | 2021-02-22 | 2022-08-30 | 삼성전자주식회사 | Semiconductor devices |
CN115224119A (en) * | 2021-04-21 | 2022-10-21 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100532204B1 (en) * | 2004-03-04 | 2005-11-29 | 삼성전자주식회사 | Transistor having the Fin structure and Method of manufacturing the same |
KR100532353B1 (en) * | 2004-03-11 | 2005-11-30 | 삼성전자주식회사 | FinFET and Method of manufacturing the same |
US7888195B2 (en) | 2008-08-26 | 2011-02-15 | United Microelectronics Corp. | Metal gate transistor and method for fabricating the same |
US8084824B2 (en) | 2008-09-11 | 2011-12-27 | United Microelectronics Corp. | Metal gate transistor and method for fabricating the same |
US8258587B2 (en) | 2008-10-06 | 2012-09-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Transistor performance with metal gate |
DE102009046245B4 (en) | 2009-10-30 | 2016-08-04 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Production of Metallgateelektrodenstrukturen with a separate removal of Platzhaltermaterialien in transistors of different conductivity |
US8329546B2 (en) | 2010-08-31 | 2012-12-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Modified profile gate structure for semiconductor device and methods of forming thereof |
KR101815527B1 (en) | 2010-10-07 | 2018-01-05 | 삼성전자주식회사 | Semiconductor device and method for manufacturing the same |
US8426300B2 (en) | 2010-12-02 | 2013-04-23 | International Business Machines Corporation | Self-aligned contact for replacement gate devices |
US9070625B2 (en) | 2012-01-04 | 2015-06-30 | International Business Machines Corporation | Selective etch chemistry for gate electrode materials |
US8603837B1 (en) | 2012-07-31 | 2013-12-10 | Intermolecular, Inc. | High productivity combinatorial workflow for post gate etch clean development |
US8722491B2 (en) | 2012-09-05 | 2014-05-13 | Globalfoundries Inc. | Replacement metal gate semiconductor device formation using low resistivity metals |
US8896030B2 (en) | 2012-09-07 | 2014-11-25 | Intel Corporation | Integrated circuits with selective gate electrode recess |
US20140103404A1 (en) * | 2012-10-17 | 2014-04-17 | International Business Machines Corporation | Replacement gate with an inner dielectric spacer |
KR102068980B1 (en) * | 2013-08-01 | 2020-01-22 | 삼성전자 주식회사 | Semiconductor device and method for fabricating the same |
TWI593111B (en) * | 2013-08-06 | 2017-07-21 | 聯華電子股份有限公司 | Semiconductor device |
FR3011386B1 (en) | 2013-09-30 | 2018-04-20 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | TRANSISTOR MOS WITH AIR SPACERS |
US9018711B1 (en) | 2013-10-17 | 2015-04-28 | Globalfoundries Inc. | Selective growth of a work-function metal in a replacement metal gate of a semiconductor device |
KR102167625B1 (en) * | 2013-10-24 | 2020-10-19 | 삼성전자주식회사 | Semiconductor devices and methods of manufacturing the same |
US9293551B2 (en) | 2013-11-25 | 2016-03-22 | Globalfoundries Inc. | Integrated multiple gate length semiconductor device including self-aligned contacts |
US9331072B2 (en) * | 2014-01-28 | 2016-05-03 | Samsung Electronics Co., Ltd. | Integrated circuit devices having air-gap spacers defined by conductive patterns and methods of manufacturing the same |
-
2015
- 2015-09-16 KR KR1020150131151A patent/KR102480219B1/en active IP Right Grant
-
2016
- 2016-01-29 US US15/010,327 patent/US9576959B1/en active Active
- 2016-05-03 DE DE102016108158.2A patent/DE102016108158B4/en active Active
- 2016-05-11 TW TW105114492A patent/TWI732758B/en active
- 2016-08-16 CN CN201610674649.0A patent/CN106549042B/en active Active
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TWI732758B (en) | 2021-07-11 |
CN106549042A (en) | 2017-03-29 |
DE102016108158B4 (en) | 2023-09-28 |
KR102480219B1 (en) | 2022-12-26 |
CN106549042B (en) | 2020-05-26 |
KR20170033494A (en) | 2017-03-27 |
US9576959B1 (en) | 2017-02-21 |
TW201712863A (en) | 2017-04-01 |
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