US20170062614A1 - Semiconductor device including dual spacer and uniform epitaxial buffer interface of embedded sige source/drain - Google Patents
Semiconductor device including dual spacer and uniform epitaxial buffer interface of embedded sige source/drain Download PDFInfo
- Publication number
- US20170062614A1 US20170062614A1 US14/834,481 US201514834481A US2017062614A1 US 20170062614 A1 US20170062614 A1 US 20170062614A1 US 201514834481 A US201514834481 A US 201514834481A US 2017062614 A1 US2017062614 A1 US 2017062614A1
- Authority
- US
- United States
- Prior art keywords
- source
- semiconductor
- drain
- fin
- drain regions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 86
- 125000006850 spacer group Chemical group 0.000 title claims description 38
- 230000009977 dual effect Effects 0.000 title description 3
- 239000000463 material Substances 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 description 31
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 24
- 238000002955 isolation Methods 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 239000002019 doping agent Substances 0.000 description 10
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 230000000903 blocking effect Effects 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 238000000407 epitaxy Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
- H01L29/41783—Raised source or drain electrodes self aligned with the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
Definitions
- the present invention relates to semiconductor devices, and more specifically, to three-dimensional (3D) transistor devices.
- Recent semiconductor fabrication methods have been developed to replace all or a portion of pure silicon (Si) fins with silicon germanium (SiGe) material, especially in p-type finFET devices.
- SiGe material reduces the threshold voltage (Vt) of a p-type semiconductor device, thereby increasing the drive current that flows through the channel.
- SiGe material provides higher carrier mobility than fins consisting of only Si. Accordingly, SiGe fins typically have improved hole mobility performance compared to Si fins.
- the benefits of SiGe material described above have led to design trends that form fins with embedded SiGe (eSiGe) source/drain regions.
- FIGS. 1-2 a conventional method of forming a finFET device 100 including eSiGe source/drain regions is illustrated.
- Conventional methods typically utilize only a single spacer layer followed by a directional etch to expose the underlying Si source/drain regions 102 of the fin while forming a single pair of spacers 104 on opposing sidewalls of the gate structure 106 (see FIG. 1 ).
- the exposed Si source/drain regions 102 are utilized as seed regions capable of epitaxially growing a semiconductor material therefrom.
- Conventional eSiGe source/drain regions 108 typically include an epitaxially grown SiGe buffer layer 110 interposed between the original Si source/drain regions 102 and a subsequently grown highly-doped main SiGe layer 112 as further shown in FIG. 2 .
- the buffer layer 110 serves to inhibit dopants of the highly-doped main SiGe layer 112 from diffusing into the fin channel region to prevent source/drain-channel shorting.
- the SiGe buffer layer 110 is formed having an asymmetrical shape as further illustrated in FIG. 2 .
- the side portions 114 a of the SiGe buffer layer 110 i.e., grown from the Si sidewalls of the fin 102
- the base portions 114 b i.e., grown on the lower portion of Si source/drain regions of the fin 102 .
- This asymmetrical shape i.e., thickness delta
- the side portions 114 a of the buffer layer 110 have a first total height (H 1 ) while the highly-doped main SiGe layer 112 has a second total height (H 2 ) that is less than H 1 . Consequently, a non-uniform eSiGe junction is formed, particularly at the corner region 116 of the buffer layer 110 .
- a semiconductor device includes at least one semiconductor fin on an upper surface of a semiconductor substrate.
- the semiconductor fin includes a channel region formed of a first semiconductor material interposed between opposing embedded source/drain regions formed of a second semiconductor material different from the first semiconductor material.
- At least one gate stack is formed on the upper surface of the semiconductor substrate and wraps around the channel region.
- the embedded source/drain regions have a symmetrical shape, and a uniform embedded interface.
- a method of forming a finFET device having symmetrically-shaped embedded source/drain regions comprises recessing source/drain regions of at least one semiconductor fin with respect to channel region of the semiconductor fin.
- the method further includes epitaxially growing a first semiconductor material from the at least one semiconductor fin.
- the first semiconductor material includes a side portion grown from opposing sidewalls of the channel region and a base portion grown from recessed portions of the source/drain regions.
- the method further includes selectively removing the base portion while maintaining the side portion to define a first height of the side portion.
- the method further includes epitaxially growing a second semiconductor material from the side portion and from the recessed source/drain regions so as to form embedded source/drain regions having a second height.
- the second height substantially matches the first height so as to form the symmetrically-shaped embedded source/drain regions
- a method of fabricating a semiconductor device comprises forming at least one semiconductor fin on an upper surface of a semiconductor substrate.
- the at least one semiconductor fin includes a channel region interposed between opposing source/drain regions.
- the method further includes recessing a portion of the source/drain regions with respect to the channel region.
- the method further includes epitaxially growing a first semiconductor material from opposing sidewalls of the channel region and from the recessed source/drain regions.
- the method further includes selectively removing a base portion of the first semiconductor material formed on the recessed source/drain regions while maintaining a side portion of the of the first semiconductor material formed on respective sidewalls of the channel region.
- the method further includes epitaxially growing a second semiconductor material from the side portions and from the recessed source/drain regions so as to form embedded source/drain regions having a symmetrical shape.
- FIGS. 1-2 illustrate a conventional method of fabricating a finFET device including eSiGe source/drain regions.
- FIGS. 3A-9B are a series of diagrams illustrating a method of fabricating a semiconductor device including eSiGe source/drain regions according to a non-limiting embodiment, in which:
- FIG. 3A is a perspective view of an intermediate semiconductor device including a semiconductor fin formed atop a substrate, and a gate structure wrapping around a channel region of the semiconductor fin;
- FIG. 3B is cross-sectional view of the intermediate semiconductor device taken along the line A-A showing initial source/drain regions of the fin abutting gate spacers formed on sidewalls of the gate structure;
- FIG. 4A is a perspective view of the semiconductor device illustrated in FIGS. 3A-3B following a first directional etch process that stops on the upper surface of the substrate so as to recesses the initial source/drain regions;
- FIG. 4B is a cross-sectional view of the semiconductor device illustrated in FIG. 4A showing the recessed source/drain regions being flush with the upper surface of the substrate;
- FIG. 5A is a perspective view of the semiconductor device illustrated in FIGS. 4A-4B after epitaxially growing a semiconductor buffer layer from exposed portions of the recessed source/drain regions and sidewalls of the fin;
- FIG. 5B is a cross-sectional view of the semiconductor device illustrated in FIG. 5A showing the buffer layer having a thin side portion formed against the sidewall of the fin and extending from the recessed source/drain region to a bottom portion of the gate spacers, and a thick base portion formed on the recessed source/drain regions;
- FIG. 6A is a perspective view of the semiconductor device illustrated in FIGS. 5A-5B after depositing an outer conformal spacer layer on an upper surface of the substrate so as to cover the buffer layer, the gate spacers and the upper surface of the gate structure;
- FIG. 6B is a cross-sectional view of the semiconductor device illustrated in FIG. 6A showing the outer spacer layer conforming to an upper surface of the buffer layer such that the buffer layer is interposed between the outer spacer layer and the fin;
- FIG. 7A is a perspective view of the semiconductor device illustrated in FIGS. 6A-6B following a second directional etch process selective to the buffer layer so as to form outer spacers on the sidewalls of the gate spacers;
- FIG. 7B is a cross-sectional view of the semiconductor device illustrated in FIG. 7A showing the side portion of the buffer layer covered by the outer spacer while the base portion of the buffer layer is exposed;
- FIG. 8A is a perspective view of the semiconductor device illustrated in FIGS. 7A-7B following a third directional etch process selective to the substrate and the fin such that the base portion of the buffer layer is removed while the side portion of the buffer layer located beneath the outer spacers is preserved;
- FIG. 8B is a cross-sectional view of the semiconductor device illustrated in FIG. 8A showing the preserved side portion extended from the outer spacer to the recessed source drain region of the fin to define a first total height;
- FIG. 9A is a perspective view of the semiconductor device illustrated in FIGS. 8A-8B after epitaxially growing a highly-doped raised source/drain region from the preserved side portion of the buffer layer and the recessed source/drain regions of the fin;
- FIG. 9B is a cross-sectional view of the semiconductor device illustrated in FIG. 9A showing the highly-doped raised source/drain region having an upper surface that is flush with an upper surface of the preserved side portion and has a second total height equal to the first height of the preserved side portion so as to define a uniform epitaxially grown source/drain region.
- a semiconductor device including a dual spacer that defines an epitaxial buffer interface of an embedded SiGe source/drain region.
- the dual spacer protects the buffer layer during a second directional etch process that selectively removes a portion of the buffer layer from the original Si source/drain region of the fin. In this manner, the buffer layer is formed on only the sidewall of the fin channel region, while the lower etched region of original Si source/drain region is re-exposed.
- the highly-doped main SiGe portion can be grown directly from the Si source/drain region and sidewalls of the buffer layer such that the base portion of the buffer layer is formed uniform with respect to the highly-doped main SiGe portion from top of the fin channel to the bottom of the fin channel.
- the semiconductor structure 200 includes a semiconductor substrate 202 including one or more isolation regions 204 formed therein.
- the semiconductor substrate 202 extends along a first axis (e.g., an X-axis) to define a length, a second axis (e.g., a Y-axis) to define a width, and a third axis (e.g., a Z-axis) to define a height.
- the substrate 202 is a bulk substrate formed from, for example, silicon (Si).
- the isolation region 204 is a shallow trench isolation (STI) region formed by depositing one or more dielectric materials such as silicon dioxide (SiO 2 ) in the bulk substrate 202 as understood by one of ordinary skill in the art.
- STI shallow trench isolation
- dielectric materials such as silicon dioxide (SiO 2 )
- SiO 2 silicon dioxide
- a bulk substrate 202 including an isolation region 204 is discussed going forward, it should be appreciated that the semiconductor substrate 202 may also be formed as a semiconductor-on-insulator (SOI) substrate without departing from the scope of the invention.
- One or more semiconductor fins 206 are formed on an upper surface of the substrate 202 .
- the fin 206 extends along the length (e.g., X-axis) of the substrate 202 to define a fin length.
- the fin is formed semiconductor material such as, for example, Si.
- a suitable hardmask blocking layer (not shown) formed of silicon dioxide (SiO 2 ), for example, can be initially deposited on an upper surface of the bulk substrate 202 .
- a suitable hardmask cap layer (not shown) formed of silicon nitride (SiN), for example, is deposited atop the hardmask blocking layer.
- the hardmask cap layer and the hardmask blocking layer will be used to pattern the underlying bulk substrate 202 while serving to protect the fin 206 during the formation of the isolation region 204 .
- the hardmask blocking layer and the hardmask cap layer are etched to define the desired fin pattern.
- a developed photoresist mask (not shown) is typically used to define the desired fin pattern.
- the hardmask blocking layer and hardmask cap layer can then be patterned selective to the developed photoresist mask according to a reactive ion etch (RIE) process.
- RIE reactive ion etch
- the patterned hardmask layers will then be used to transfer the desired fin pattern into the underlying bulk substrate layer 202 according to a RIE process to define one or more of the semiconductor fins 206 . It should be appreciated that the length and width of the patterning can be determined according to the desired fin dimensions for the particular application.
- the semiconductor structure 200 further includes one or more gate structures 208 formed atop the isolation region 206 .
- the gate structure 208 extends along a width (e.g. Y-axis) of the substrate 202 so as to wrap around the sidewalls and upper surface of the fin 206 .
- the arrangement of the gate structure 208 and the fin 206 defines a covered channel region 210 interposed between a pair of exposed fin regions 212 a - 212 b which are reserved for the source/drain regions of the semiconductor device 200 (see FIG. 3B ). Going forward, these reserved fin regions 212 a - 212 b will be referred to as initial source/drain regions 212 a - 212 b.
- the gate structure 208 includes a gate stack 214 and gate spacers 216 formed on opposing sidewalls of the gate stack 214 .
- the gate stack 214 is formed from various conductive gate materials understood by those of ordinary skill in the art, and has a length ranging from approximately X nm to approximately Y nm.
- the gate spacers 216 are formed from a low-k material such as, for example, silicon nitride (SiN), and have a thickness (e.g., along the X-axis) ranging from approximately 8 nm to approximately 10 nm.
- a gate dielectric layer e.g., a high-k gate dielectric layer
- work function metal layers e.g., a high-k gate dielectric layer
- the gate dielectric layer may be interposed between the fin 206 and the gate stack 214 .
- the work function metal layers include, but are not limited to, a titanium nitride (TiN) liner and a tantalum nitride (TaN) liner, which are formed on sidewalls of the gate stack 214 as understood by one of ordinary skill in the art.
- the gate structure 208 includes the gate stack 214 , the gate dielectric layer, the work function metals, and the gate spacers 216 .
- the semiconductor device 200 is illustrated following a first anisotropic directional etching process.
- a reactive ion etch (RIE) for example, that is selective to the material of the gate spacers 216 (e.g., SiN) and the material of the isolation region 204 (e.g., SiO 2 ) may be performed so as to etch the reserved fin regions 212 a - 212 b (i.e., the uncovered portions of the fin 206 ) while stopping on the isolation region 204 .
- the gate structure 208 serves as a mask to protect the channel region 210 when recessing the source/drain regions 212 a - 212 b.
- remaining fin base portions 218 a - 218 b are formed flush with the upper surface of the isolation region 204 , while remaining fin side portions 220 a - 220 b are formed flush with sidewalls of the gate spacers 216 .
- buffer layers 222 a - 22 b are formed on exposed portions of the fin 206 .
- various well-known epitaxy processes may be used to grow a semiconductor material from the base portions 218 a - 218 b and the fin side portions 220 a - 220 b, respectively.
- the epitaxial grown semiconductor material includes, for example, undoped silicon germanium (SiGe) or SiGe having a low concentration of dopants including, but not limited to, boron (B).
- the dopant concentration of the buffer layers 222 a - 222 b may range from approximately 0/cm 3 (i.e., un-doped) to approximately 10 19 /cm 3 .
- the buffer layers 222 a - 222 b may serve to inhibit diffusion of dopants into the channel region when exposing the semiconductor device 200 to various thermal anneal processes understood by one of ordinary skill in the art.
- a p-FET device is described going forward, it should be appreciated that an n-FET device may be formed in a similar manner as described above.
- the epitaxial grown semiconductor material is undoped Si, or Si having a low concentration of dopants including, but not limited to, phosphorous (P).
- the buffer layers 222 a - 222 b each include a side portion 224 a - 224 b and a base portion 226 a - 226 b as further illustrated in FIG. 5B .
- the side portions 224 a - 224 b extend from the recessed surface of the reserved source/drain regions 218 a - 218 b to an upper surface of the preserved fin 204 (i.e., the portion of the fin 206 defining an interface between the gate structure 208 and the fin 204 ) to thereby defining a first total height (H 1 ) equal or approximately equal to the fin 206 and a first total thickness (T 1 ) ranging from approximately 3 nm to approximately 5 nm.
- the base portions 226 a - 226 b extend from the recessed surface at a second total height (H 2 ) ranging from approximately 8 nm to approximately 10 nm.
- a second total thickness (T 2 ) depends on the lateral dimension of source/drain. Accordingly, T 2 may range from approximately 20 nm to approximately 40 nm.
- a conformal outer spacer layer 228 is deposited on the upper surface of the substrate 202 so as to cover the buffer layers 222 a - 222 b, the sidewalls of the gate spacers 216 and an upper surface of the gate stack 214 .
- Various disposition processes may be used to deposit the outer spacer layer 229 such as, for example, chemical vapor deposition (CVD).
- the outer spacer layer 228 has a thickness ranging for example, from approximately 4 nm to approximately 8 nm, and is formed from various nitride-based materials including, but not limited to, silicon nitride (SiN).
- the semiconductor device 200 is illustrated following a second selective directional etch process that etches the outer spacer layer 220 to form outer spacers 230 on the sidewalls of the gate spacers 216 .
- the second directional etch process includes a dry RIE process that is selective to the material of the buffer layers 222 a - 222 b and the isolation region 204 .
- the portion of the outer spacer material covering the base portions 226 a - 226 b is etched at a faster rate than the portion of the outer spacer layer 229 covering the side portions 224 a - 224 b. Accordingly, the side portions 224 a - 224 b are preserved and remain covered by respective outer spacers 230 while the base portions 226 a - 226 b are exposed.
- the semiconductor device is illustrated following a third selective directional etch process that removes the base portion 226 a - 226 b of the buffer layers 222 a - 222 b from the upper surface of the recessed source/drain regions 218 a - 218 b.
- the third etch process includes, for example, a dry anisotropic RIE process selective to the material of the isolation region 204 , the fin 206 and the outer spacers 230 can be performed such that the base portions 226 a - 226 b are removed while the side portions 224 a - 224 b located beneath respective outer spacers 230 are preserved. In this manner, the side portions 224 a - 224 b are formed flush with the respective outer spacers 230 , while the recessed source/drain regions 218 a - 218 b are re-exposed.
- FIGS. 9A-9B the semiconductor device 200 is illustrated after epitaxially growing highly-doped raised source/drain layers 232 a - 232 b from the recessed source/drain regions 218 a - 218 b and the preserved buffer layer side portions 224 a - 224 b, respectively.
- a lower portion of the raised source/drain layers 232 a - 232 b may be formed directly against a surface of the initial fin 206 (i.e., the recessed source/drain regions 218 a - 218 b ), while sides of the raised source/drain layers 232 a - 232 b are formed directly against the buffer layer 222 a - 222 b (i.e., the side portions 224 a - 224 b ).
- the combination of the remaining buffer layers 222 a - 222 b (i.e., the preserved side portions 224 a - 224 b ) and the highly-doped raised source/drain layers 232 a - 232 b can be viewed as embedded SiGe (eSiGe) source/drain layers 234 a - 234 b.
- the highly-doped raised source/drain layers 232 a - 232 b have an upper surface that is flush with an upper surface of a respective preserved side portion 224 a - 224 b.
- the highly-doped raised source/drain layers 232 a - 232 b have a total height (H 3 ) equal or substantially equal to the first height of the preserved side portions 218 a - 218 b (H 1 ) so as to define symmetrical eSiGe source/drain regions 234 a - 234 b as further illustrated in FIG. 9B .
- each buffer layer 222 a - 222 b entirely contacts a respective raised source/drain layer 232 a - 232 b so as to define an embedded interface 233 a - 233 b therebetween.
- the embedded interface extends from the upper surface of substrate 202 (e.g., the surface of the recessed source/drain regions 218 a - 218 b ) to an upper surface of the channel region 210 . Accordingly, embedded interface 233 a - 233 b between the buffer layers 222 a - 222 b (i.e., the preserved side portions 224 a - 224 b ) and the raised source/drain layers 232 a - 232 b is uniform.
- the epitaxial grown semiconductor material includes, for example, in-situ doped silicon germanium (SiGe) having a high concentration of dopants including, but not limited to, boron (B).
- the dopant concentration of the raised source/drain layers 232 a - 232 b may range from approximately 5 ⁇ 10 19 /cm 3 to approximately 10 21 /cm 3 .
- uniform eSiGe source/drain regions 234 a - 234 b are formed including buffer layers 222 a - 222 b (i.e., the preserved buffer layer side portions 224 a - 224 b ) which serve to inhibit diffusion of dopants into the channel region when exposing the semiconductor device 200 to one or more well-known subsequent thermal anneal processes.
- buffer layers 222 a - 222 b i.e., the preserved buffer layer side portions 224 a - 224 b
- an n-FET device may be formed in a similar manner as described above.
- the raised source/drain layers 232 a - 232 b may include in-situ doped epitaxial grown Si, having a high concentration of dopants including, but not limited to, phosphorous (P).
- each buffer layer 222 a - 222 b is removed prior to forming the raised source/drain layers 232 a - 232 b.
- the uniformity of the eSiGe source/drain region 234 a - 234 b is substantially improved compared to conventional finFET devices that utilize eSiGe source/drain regions. Accordingly, a finFET device having a uniform eSiGe source/drain region profile is provided, thereby improving the overall performance the semiconductor device 200 .
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- Materials Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A semiconductor device includes at least one semiconductor fin on an upper surface of a semiconductor substrate. The semiconductor fin includes a channel region formed of a first semiconductor material interposed between opposing embedded source/drain regions formed of a second semiconductor material different from the first semiconductor material. At least one gate stack is formed on the upper surface of the semiconductor substrate and wraps around the channel region. The embedded source/drain regions have a symmetrical shape and a uniform embedded interface.
Description
- The present invention relates to semiconductor devices, and more specifically, to three-dimensional (3D) transistor devices.
- Recent semiconductor fabrication methods have been developed to replace all or a portion of pure silicon (Si) fins with silicon germanium (SiGe) material, especially in p-type finFET devices. SiGe material reduces the threshold voltage (Vt) of a p-type semiconductor device, thereby increasing the drive current that flows through the channel. Further, SiGe material provides higher carrier mobility than fins consisting of only Si. Accordingly, SiGe fins typically have improved hole mobility performance compared to Si fins. The benefits of SiGe material described above have led to design trends that form fins with embedded SiGe (eSiGe) source/drain regions.
- Referring to
FIGS. 1-2 , a conventional method of forming afinFET device 100 including eSiGe source/drain regions is illustrated. Conventional methods typically utilize only a single spacer layer followed by a directional etch to expose the underlying Si source/drain regions 102 of the fin while forming a single pair ofspacers 104 on opposing sidewalls of the gate structure 106 (seeFIG. 1 ). The exposed Si source/drain regions 102 are utilized as seed regions capable of epitaxially growing a semiconductor material therefrom. - Conventional eSiGe source/
drain regions 108 typically include an epitaxially grownSiGe buffer layer 110 interposed between the original Si source/drain regions 102 and a subsequently grown highly-dopedmain SiGe layer 112 as further shown inFIG. 2 . When performing a thermal anneal process to activate dopants of themain SiGe layer 112, for example, thebuffer layer 110 serves to inhibit dopants of the highly-dopedmain SiGe layer 112 from diffusing into the fin channel region to prevent source/drain-channel shorting. - However, due to the natural asymmetrical directional growth of SiGe from Si, the
SiGe buffer layer 110 is formed having an asymmetrical shape as further illustrated inFIG. 2 . For example, theside portions 114 a of the SiGe buffer layer 110 (i.e., grown from the Si sidewalls of the fin 102) are thinner than thebase portions 114 b (i.e., grown on the lower portion of Si source/drain regions of the fin 102). This asymmetrical shape (i.e., thickness delta) causes a non-uniform extension junction profile from the top of the fin channel to the bottom of the fin channel which can potentially affect the overall performance of the finFET device. For instance, theside portions 114 a of thebuffer layer 110 have a first total height (H1) while the highly-dopedmain SiGe layer 112 has a second total height (H2) that is less than H1. Consequently, a non-uniform eSiGe junction is formed, particularly at thecorner region 116 of thebuffer layer 110. - According to a non-limiting embodiment of the present invention, a semiconductor device includes at least one semiconductor fin on an upper surface of a semiconductor substrate. The semiconductor fin includes a channel region formed of a first semiconductor material interposed between opposing embedded source/drain regions formed of a second semiconductor material different from the first semiconductor material. At least one gate stack is formed on the upper surface of the semiconductor substrate and wraps around the channel region. The embedded source/drain regions have a symmetrical shape, and a uniform embedded interface.
- According to another non-limiting embodiment, a method of forming a finFET device having symmetrically-shaped embedded source/drain regions comprises recessing source/drain regions of at least one semiconductor fin with respect to channel region of the semiconductor fin. The method further includes epitaxially growing a first semiconductor material from the at least one semiconductor fin. The first semiconductor material includes a side portion grown from opposing sidewalls of the channel region and a base portion grown from recessed portions of the source/drain regions. The method further includes selectively removing the base portion while maintaining the side portion to define a first height of the side portion. The method further includes epitaxially growing a second semiconductor material from the side portion and from the recessed source/drain regions so as to form embedded source/drain regions having a second height. The second height substantially matches the first height so as to form the symmetrically-shaped embedded source/drain regions
- According to still another non-limiting embodiment, a method of fabricating a semiconductor device comprises forming at least one semiconductor fin on an upper surface of a semiconductor substrate. The at least one semiconductor fin includes a channel region interposed between opposing source/drain regions. The method further includes recessing a portion of the source/drain regions with respect to the channel region. The method further includes epitaxially growing a first semiconductor material from opposing sidewalls of the channel region and from the recessed source/drain regions. The method further includes selectively removing a base portion of the first semiconductor material formed on the recessed source/drain regions while maintaining a side portion of the of the first semiconductor material formed on respective sidewalls of the channel region. The method further includes epitaxially growing a second semiconductor material from the side portions and from the recessed source/drain regions so as to form embedded source/drain regions having a symmetrical shape.
- Additional features are realized through the techniques of the present invention. Other embodiments are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with the features, refer to the description and to the drawings.
-
FIGS. 1-2 illustrate a conventional method of fabricating a finFET device including eSiGe source/drain regions. -
FIGS. 3A-9B are a series of diagrams illustrating a method of fabricating a semiconductor device including eSiGe source/drain regions according to a non-limiting embodiment, in which: -
FIG. 3A is a perspective view of an intermediate semiconductor device including a semiconductor fin formed atop a substrate, and a gate structure wrapping around a channel region of the semiconductor fin; -
FIG. 3B is cross-sectional view of the intermediate semiconductor device taken along the line A-A showing initial source/drain regions of the fin abutting gate spacers formed on sidewalls of the gate structure; -
FIG. 4A is a perspective view of the semiconductor device illustrated inFIGS. 3A-3B following a first directional etch process that stops on the upper surface of the substrate so as to recesses the initial source/drain regions; -
FIG. 4B is a cross-sectional view of the semiconductor device illustrated inFIG. 4A showing the recessed source/drain regions being flush with the upper surface of the substrate; -
FIG. 5A is a perspective view of the semiconductor device illustrated inFIGS. 4A-4B after epitaxially growing a semiconductor buffer layer from exposed portions of the recessed source/drain regions and sidewalls of the fin; -
FIG. 5B is a cross-sectional view of the semiconductor device illustrated inFIG. 5A showing the buffer layer having a thin side portion formed against the sidewall of the fin and extending from the recessed source/drain region to a bottom portion of the gate spacers, and a thick base portion formed on the recessed source/drain regions; -
FIG. 6A is a perspective view of the semiconductor device illustrated inFIGS. 5A-5B after depositing an outer conformal spacer layer on an upper surface of the substrate so as to cover the buffer layer, the gate spacers and the upper surface of the gate structure; -
FIG. 6B is a cross-sectional view of the semiconductor device illustrated inFIG. 6A showing the outer spacer layer conforming to an upper surface of the buffer layer such that the buffer layer is interposed between the outer spacer layer and the fin; -
FIG. 7A is a perspective view of the semiconductor device illustrated inFIGS. 6A-6B following a second directional etch process selective to the buffer layer so as to form outer spacers on the sidewalls of the gate spacers; -
FIG. 7B is a cross-sectional view of the semiconductor device illustrated inFIG. 7A showing the side portion of the buffer layer covered by the outer spacer while the base portion of the buffer layer is exposed; -
FIG. 8A is a perspective view of the semiconductor device illustrated inFIGS. 7A-7B following a third directional etch process selective to the substrate and the fin such that the base portion of the buffer layer is removed while the side portion of the buffer layer located beneath the outer spacers is preserved; -
FIG. 8B is a cross-sectional view of the semiconductor device illustrated inFIG. 8A showing the preserved side portion extended from the outer spacer to the recessed source drain region of the fin to define a first total height; -
FIG. 9A is a perspective view of the semiconductor device illustrated inFIGS. 8A-8B after epitaxially growing a highly-doped raised source/drain region from the preserved side portion of the buffer layer and the recessed source/drain regions of the fin; -
FIG. 9B is a cross-sectional view of the semiconductor device illustrated inFIG. 9A showing the highly-doped raised source/drain region having an upper surface that is flush with an upper surface of the preserved side portion and has a second total height equal to the first height of the preserved side portion so as to define a uniform epitaxially grown source/drain region. - Various non-limiting embodiments of the invention provide a semiconductor device including a dual spacer that defines an epitaxial buffer interface of an embedded SiGe source/drain region. The dual spacer protects the buffer layer during a second directional etch process that selectively removes a portion of the buffer layer from the original Si source/drain region of the fin. In this manner, the buffer layer is formed on only the sidewall of the fin channel region, while the lower etched region of original Si source/drain region is re-exposed. Accordingly, the highly-doped main SiGe portion can be grown directly from the Si source/drain region and sidewalls of the buffer layer such that the base portion of the buffer layer is formed uniform with respect to the highly-doped main SiGe portion from top of the fin channel to the bottom of the fin channel.
- With reference now to
FIGS. 3A-3B , asemiconductor structure 200 which serves as a starting point for fabricating a finFET device in accordance with an exemplary embodiment is shown. In exemplary embodiments, thesemiconductor structure 200 includes asemiconductor substrate 202 including one ormore isolation regions 204 formed therein. Thesemiconductor substrate 202 extends along a first axis (e.g., an X-axis) to define a length, a second axis (e.g., a Y-axis) to define a width, and a third axis (e.g., a Z-axis) to define a height. According to a non-limiting embodiment, thesubstrate 202 is a bulk substrate formed from, for example, silicon (Si). Theisolation region 204 is a shallow trench isolation (STI) region formed by depositing one or more dielectric materials such as silicon dioxide (SiO2) in thebulk substrate 202 as understood by one of ordinary skill in the art. Although abulk substrate 202 including anisolation region 204 is discussed going forward, it should be appreciated that thesemiconductor substrate 202 may also be formed as a semiconductor-on-insulator (SOI) substrate without departing from the scope of the invention. - One or
more semiconductor fins 206 are formed on an upper surface of thesubstrate 202. Thefin 206 extends along the length (e.g., X-axis) of thesubstrate 202 to define a fin length. According to a non-limiting embodiment, the fin is formed semiconductor material such as, for example, Si. - Various patterning techniques may be used to form the
semiconductor fin 206. For example, a suitable hardmask blocking layer (not shown) formed of silicon dioxide (SiO2), for example, can be initially deposited on an upper surface of thebulk substrate 202. Next, a suitable hardmask cap layer (not shown) formed of silicon nitride (SiN), for example, is deposited atop the hardmask blocking layer. The hardmask cap layer and the hardmask blocking layer will be used to pattern theunderlying bulk substrate 202 while serving to protect thefin 206 during the formation of theisolation region 204. - Next, the hardmask blocking layer and the hardmask cap layer are etched to define the desired fin pattern. A developed photoresist mask (not shown) is typically used to define the desired fin pattern. The hardmask blocking layer and hardmask cap layer can then be patterned selective to the developed photoresist mask according to a reactive ion etch (RIE) process. The patterned hardmask layers will then be used to transfer the desired fin pattern into the underlying
bulk substrate layer 202 according to a RIE process to define one or more of thesemiconductor fins 206. It should be appreciated that the length and width of the patterning can be determined according to the desired fin dimensions for the particular application. - The
semiconductor structure 200 further includes one ormore gate structures 208 formed atop theisolation region 206. Thegate structure 208 extends along a width (e.g. Y-axis) of thesubstrate 202 so as to wrap around the sidewalls and upper surface of thefin 206. The arrangement of thegate structure 208 and thefin 206 defines a coveredchannel region 210 interposed between a pair of exposed fin regions 212 a-212 b which are reserved for the source/drain regions of the semiconductor device 200 (seeFIG. 3B ). Going forward, these reserved fin regions 212 a-212 b will be referred to as initial source/drain regions 212 a-212 b. - The
gate structure 208 includes agate stack 214 andgate spacers 216 formed on opposing sidewalls of thegate stack 214. Thegate stack 214 is formed from various conductive gate materials understood by those of ordinary skill in the art, and has a length ranging from approximately X nm to approximately Y nm. The gate spacers 216 are formed from a low-k material such as, for example, silicon nitride (SiN), and have a thickness (e.g., along the X-axis) ranging from approximately 8 nm to approximately 10 nm. Although not illustrated, a gate dielectric layer (e.g., a high-k gate dielectric layer) and one or more work function metal layers. The gate dielectric layer may be interposed between thefin 206 and thegate stack 214. The work function metal layers include, but are not limited to, a titanium nitride (TiN) liner and a tantalum nitride (TaN) liner, which are formed on sidewalls of thegate stack 214 as understood by one of ordinary skill in the art. In this case, it should be appreciated that thegate structure 208 includes thegate stack 214, the gate dielectric layer, the work function metals, and thegate spacers 216. - Referring to
FIGS. 4A-4B , thesemiconductor device 200 is illustrated following a first anisotropic directional etching process. A reactive ion etch (RIE), for example, that is selective to the material of the gate spacers 216 (e.g., SiN) and the material of the isolation region 204 (e.g., SiO2) may be performed so as to etch the reserved fin regions 212 a-212 b (i.e., the uncovered portions of the fin 206) while stopping on theisolation region 204. Moreover, thegate structure 208 serves as a mask to protect thechannel region 210 when recessing the source/drain regions 212 a-212 b. In this manner, remaining fin base portions 218 a-218 b are formed flush with the upper surface of theisolation region 204, while remaining fin side portions 220 a-220 b are formed flush with sidewalls of thegate spacers 216. - Referring to
FIGS. 5A-5B , buffer layers 222 a-22 b are formed on exposed portions of thefin 206. For instance, various well-known epitaxy processes may be used to grow a semiconductor material from the base portions 218 a-218 b and the fin side portions 220 a-220 b, respectively. The epitaxial grown semiconductor material includes, for example, undoped silicon germanium (SiGe) or SiGe having a low concentration of dopants including, but not limited to, boron (B). The dopant concentration of the buffer layers 222 a-222 b may range from approximately 0/cm3 (i.e., un-doped) to approximately 1019 /cm3. In this manner, the buffer layers 222 a-222 b may serve to inhibit diffusion of dopants into the channel region when exposing thesemiconductor device 200 to various thermal anneal processes understood by one of ordinary skill in the art. Although a p-FET device is described going forward, it should be appreciated that an n-FET device may be formed in a similar manner as described above. When forming an n-FET device, the epitaxial grown semiconductor material is undoped Si, or Si having a low concentration of dopants including, but not limited to, phosphorous (P). - The buffer layers 222 a-222 b each include a side portion 224 a-224 b and a base portion 226 a-226 b as further illustrated in
FIG. 5B . The side portions 224 a-224 b extend from the recessed surface of the reserved source/drain regions 218 a-218 b to an upper surface of the preserved fin 204 (i.e., the portion of thefin 206 defining an interface between thegate structure 208 and the fin 204) to thereby defining a first total height (H1) equal or approximately equal to thefin 206 and a first total thickness (T1) ranging from approximately 3 nm to approximately 5 nm. During the epitaxy process, however, crystal growth of the buffer layers 222 a-222 b naturally grows slower in the lateral direction (e.g., along the X-axis) compared to the vertical direction (e.g., along the Z-axis). Therefore, the base portions 226 a-226 b extend from the recessed surface at a second total height (H2) ranging from approximately 8 nm to approximately 10 nm. A second total thickness (T2) depends on the lateral dimension of source/drain. Accordingly, T2 may range from approximately 20 nm to approximately 40 nm. - Referring to
FIGS. 6A-6B , a conformalouter spacer layer 228 is deposited on the upper surface of thesubstrate 202 so as to cover the buffer layers 222 a-222 b, the sidewalls of thegate spacers 216 and an upper surface of thegate stack 214. Various disposition processes may be used to deposit the outer spacer layer 229 such as, for example, chemical vapor deposition (CVD). Theouter spacer layer 228 has a thickness ranging for example, from approximately 4 nm to approximately 8 nm, and is formed from various nitride-based materials including, but not limited to, silicon nitride (SiN). - Turning to
FIGS. 7A-7B , thesemiconductor device 200 is illustrated following a second selective directional etch process that etches the outer spacer layer 220 to formouter spacers 230 on the sidewalls of thegate spacers 216. According to a non-limiting embodiment, the second directional etch process includes a dry RIE process that is selective to the material of the buffer layers 222 a-222 b and theisolation region 204. Further, the portion of the outer spacer material covering the base portions 226 a-226 b is etched at a faster rate than the portion of the outer spacer layer 229 covering the side portions 224 a-224 b. Accordingly, the side portions 224 a-224 b are preserved and remain covered by respectiveouter spacers 230 while the base portions 226 a-226 b are exposed. - Referring to
FIGS. 8A-8B , the semiconductor device is illustrated following a third selective directional etch process that removes the base portion 226 a-226 b of the buffer layers 222 a-222 b from the upper surface of the recessed source/drain regions 218 a-218 b. The third etch process includes, for example, a dry anisotropic RIE process selective to the material of theisolation region 204, thefin 206 and theouter spacers 230 can be performed such that the base portions 226 a-226 b are removed while the side portions 224 a-224 b located beneath respectiveouter spacers 230 are preserved. In this manner, the side portions 224 a-224 b are formed flush with the respectiveouter spacers 230, while the recessed source/drain regions 218 a-218 b are re-exposed. - Turning now to
FIGS. 9A-9B , thesemiconductor device 200 is illustrated after epitaxially growing highly-doped raised source/drain layers 232 a-232 b from the recessed source/drain regions 218 a-218 b and the preserved buffer layer side portions 224 a-224 b, respectively. Accordingly, a lower portion of the raised source/drain layers 232 a-232 b may be formed directly against a surface of the initial fin 206 (i.e., the recessed source/drain regions 218 a-218 b), while sides of the raised source/drain layers 232 a-232 b are formed directly against the buffer layer 222 a-222 b (i.e., the side portions 224 a-224 b). - The combination of the remaining buffer layers 222 a-222 b (i.e., the preserved side portions 224 a-224 b) and the highly-doped raised source/drain layers 232 a-232 b can be viewed as embedded SiGe (eSiGe) source/drain layers 234 a-234 b. As further illustrated in
FIG. 9B , the highly-doped raised source/drain layers 232 a-232 b have an upper surface that is flush with an upper surface of a respective preserved side portion 224 a-224 b. Accordingly, the highly-doped raised source/drain layers 232 a-232 b have a total height (H3) equal or substantially equal to the first height of the preserved side portions 218 a-218 b (H1) so as to define symmetrical eSiGe source/drain regions 234 a-234 b as further illustrated inFIG. 9B . Further, each buffer layer 222 a-222 b entirely contacts a respective raised source/drain layer 232 a-232 b so as to define an embedded interface 233 a-233 b therebetween. The embedded interface extends from the upper surface of substrate 202 (e.g., the surface of the recessed source/drain regions 218 a-218 b) to an upper surface of thechannel region 210. Accordingly, embedded interface 233 a-233 b between the buffer layers 222 a-222 b (i.e., the preserved side portions 224 a-224 b) and the raised source/drain layers 232 a-232 b is uniform. - Various epitaxy processes may be used to grow the highly-doped raised source/drain layers 232 a-232 b from the base portions 218 a-218 b and the buffer layer side portions 224 a-224 b. The epitaxial grown semiconductor material includes, for example, in-situ doped silicon germanium (SiGe) having a high concentration of dopants including, but not limited to, boron (B). The dopant concentration of the raised source/drain layers 232 a-232 b may range from approximately 5×1019/cm3 to approximately 1021/cm3. In this manner, uniform eSiGe source/drain regions 234 a-234 b are formed including buffer layers 222 a-222 b (i.e., the preserved buffer layer side portions 224 a-224 b) which serve to inhibit diffusion of dopants into the channel region when exposing the
semiconductor device 200 to one or more well-known subsequent thermal anneal processes. Although a p-FET device is described going forward, it should be appreciated that an n-FET device may be formed in a similar manner as described above. When forming an n-FET device, the raised source/drain layers 232 a-232 b may include in-situ doped epitaxial grown Si, having a high concentration of dopants including, but not limited to, phosphorous (P). - As described in detail above, the base portions 226 a-226 b of each buffer layer 222 a-222 b is removed prior to forming the raised source/drain layers 232 a-232 b. In this manner, the uniformity of the eSiGe source/drain region 234 a-234 b is substantially improved compared to conventional finFET devices that utilize eSiGe source/drain regions. Accordingly, a finFET device having a uniform eSiGe source/drain region profile is provided, thereby improving the overall performance the
semiconductor device 200. - The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (7)
1.-14. (canceled)
15. A semiconductor device comprising:
at least one semiconductor fin on an upper surface of a semiconductor substrate, the at least one semiconductor fin including a channel region comprising a first semiconductor material interposed between opposing embedded source/drain regions comprising a second semiconductor material different from the first semiconductor material; and
at least one gate stack on the upper surface of the semiconductor substrate and wrapping around the channel region; and
a first pair of gate spacers on opposing sidewalls of the gate stack, and a second pair of outer spacers on opposing sidewalls of the gate spacers,
wherein the embedded source/drain regions each include a buffer layer and a raised source/drain layer, the raised source/drain layer having a different doping concentration with respect to the buffer layer, and
wherein an entire portion of the buffer layer is located beneath only the outer spacers, and wherein the embedded source/drain regions have a substantially symmetrical shape.
16. (canceled)
17. The semiconductor device of claim 15 , wherein a first side of each buffer layer contacts a second side of a respective raised source/drain layer thereby defining a single respective embedded interface having a uniform shape.
18. The semiconductor device of claim 17 , wherein a total height of each buffer layer is approximately equal to a total height of the raised source/drain region coupled at a respective embedded interface.
19. (canceled)
20. (canceled)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/834,481 US9601621B1 (en) | 2015-08-25 | 2015-08-25 | Semiconductor device including dual spacer and uniform epitaxial buffer interface of embedded SiGe source/drain |
US14/951,660 US9595597B1 (en) | 2015-08-25 | 2015-11-25 | Semiconductor device including dual spacer and uniform epitaxial buffer interface of embedded SiGe source/drain |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/834,481 US9601621B1 (en) | 2015-08-25 | 2015-08-25 | Semiconductor device including dual spacer and uniform epitaxial buffer interface of embedded SiGe source/drain |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/951,660 Continuation US9595597B1 (en) | 2015-08-25 | 2015-11-25 | Semiconductor device including dual spacer and uniform epitaxial buffer interface of embedded SiGe source/drain |
Publications (2)
Publication Number | Publication Date |
---|---|
US20170062614A1 true US20170062614A1 (en) | 2017-03-02 |
US9601621B1 US9601621B1 (en) | 2017-03-21 |
Family
ID=58095902
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/834,481 Active US9601621B1 (en) | 2015-08-25 | 2015-08-25 | Semiconductor device including dual spacer and uniform epitaxial buffer interface of embedded SiGe source/drain |
US14/951,660 Expired - Fee Related US9595597B1 (en) | 2015-08-25 | 2015-11-25 | Semiconductor device including dual spacer and uniform epitaxial buffer interface of embedded SiGe source/drain |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/951,660 Expired - Fee Related US9595597B1 (en) | 2015-08-25 | 2015-11-25 | Semiconductor device including dual spacer and uniform epitaxial buffer interface of embedded SiGe source/drain |
Country Status (1)
Country | Link |
---|---|
US (2) | US9601621B1 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20170278962A1 (en) * | 2016-03-25 | 2017-09-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
CN109994541A (en) * | 2017-11-28 | 2019-07-09 | 台湾积体电路制造股份有限公司 | Asymmetric source electrode and drain electrode structure in semiconductor devices |
US10658513B2 (en) * | 2015-03-05 | 2020-05-19 | International Business Machines Corporation | Formation of FinFET junction |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2019066970A1 (en) * | 2017-09-29 | 2019-04-04 | Intel Corporation | Device, method and system to provide a stressed channel of a transistor |
US11239363B2 (en) | 2019-01-08 | 2022-02-01 | Samsung Electronics Co., Ltd. | Semiconductor devices |
US11031502B2 (en) | 2019-01-08 | 2021-06-08 | Samsung Electronics Co., Ltd. | Semiconductor devices |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5714413A (en) | 1995-12-11 | 1998-02-03 | Intel Corporation | Method of making a transistor having a deposited dual-layer spacer structure |
KR100275733B1 (en) | 1998-06-12 | 2001-01-15 | 윤종용 | Method for forming MOS transistor having bi-layer spacer |
US6306702B1 (en) | 1999-08-24 | 2001-10-23 | Advanced Micro Devices, Inc. | Dual spacer method of forming CMOS transistors with substantially the same sub 0.25 micron gate length |
US6995065B2 (en) | 2003-12-10 | 2006-02-07 | International Business Machines Corporation | Selective post-doping of gate structures by means of selective oxide growth |
US7365378B2 (en) | 2005-03-31 | 2008-04-29 | International Business Machines Corporation | MOSFET structure with ultra-low K spacer |
WO2008072164A1 (en) | 2006-12-15 | 2008-06-19 | Nxp B.V. | Transistor device and method of manufacturing such a transistor device |
US7704835B2 (en) | 2006-12-29 | 2010-04-27 | Intel Corporation | Method of forming a selective spacer in a semiconductor device |
US8383503B2 (en) | 2009-08-05 | 2013-02-26 | GlobalFoundries, Inc. | Methods for forming semiconductor structures using selectively-formed sidewall spacers |
US8207038B2 (en) * | 2010-05-24 | 2012-06-26 | International Business Machines Corporation | Stressed Fin-FET devices with low contact resistance |
US8367498B2 (en) * | 2010-10-18 | 2013-02-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin-like field effect transistor (FinFET) device and method of manufacturing same |
US8685825B2 (en) * | 2011-07-27 | 2014-04-01 | Advanced Ion Beam Technology, Inc. | Replacement source/drain finFET fabrication |
US8652891B1 (en) * | 2012-07-25 | 2014-02-18 | The Institute of Microelectronics Chinese Academy of Science | Semiconductor device and method of manufacturing the same |
US20140167163A1 (en) * | 2012-12-17 | 2014-06-19 | International Business Machines Corporation | Multi-Fin FinFETs with Epitaxially-Grown Merged Source/Drains |
CN105470135B (en) * | 2014-09-11 | 2018-11-06 | 中国科学院微电子研究所 | Semiconductor device manufacturing method |
US9859423B2 (en) * | 2014-12-31 | 2018-01-02 | Stmicroelectronics, Inc. | Hetero-channel FinFET |
-
2015
- 2015-08-25 US US14/834,481 patent/US9601621B1/en active Active
- 2015-11-25 US US14/951,660 patent/US9595597B1/en not_active Expired - Fee Related
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10658513B2 (en) * | 2015-03-05 | 2020-05-19 | International Business Machines Corporation | Formation of FinFET junction |
US20170278962A1 (en) * | 2016-03-25 | 2017-09-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US9837538B2 (en) * | 2016-03-25 | 2017-12-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US10269966B2 (en) | 2016-03-25 | 2019-04-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device including a fin structure |
CN109994541A (en) * | 2017-11-28 | 2019-07-09 | 台湾积体电路制造股份有限公司 | Asymmetric source electrode and drain electrode structure in semiconductor devices |
US12057503B2 (en) | 2017-11-28 | 2024-08-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Asymmetric source and drain structures in semiconductor devices |
Also Published As
Publication number | Publication date |
---|---|
US20170062588A1 (en) | 2017-03-02 |
US9601621B1 (en) | 2017-03-21 |
US9595597B1 (en) | 2017-03-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10964799B2 (en) | FinFETs and methods for forming the same | |
KR101802715B1 (en) | Semiconductor device and manufacturing method thereof | |
US9082851B2 (en) | FinFET having suppressed leakage current | |
US8928093B2 (en) | FinFET body contact and method of making same | |
KR101511423B1 (en) | Finfets and methods for forming the same | |
US9837415B2 (en) | FinFET structures having silicon germanium and silicon fins with suppressed dopant diffusion | |
US8871584B2 (en) | Replacement source/drain finFET fabrication | |
US9595597B1 (en) | Semiconductor device including dual spacer and uniform epitaxial buffer interface of embedded SiGe source/drain | |
US9024355B2 (en) | Embedded planar source/drain stressors for a finFET including a plurality of fins | |
US9472470B2 (en) | Methods of forming FinFET with wide unmerged source drain EPI | |
KR20120047032A (en) | Semiconductor device and method of manufacturing thereof | |
US20190296144A1 (en) | Semiconductor device including fin field effect transistor and method of manufacturing the same | |
US8835255B2 (en) | Method of forming a semiconductor structure including a vertical nanowire | |
US9947649B1 (en) | Large area electrostatic dischage for vertical transistor structures | |
US9748336B2 (en) | Semiconductor device including dual-layer source/drain region | |
US10535773B2 (en) | FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation | |
US20150287743A1 (en) | Multi-height fin field effect transistors | |
US9660030B2 (en) | Replacement gate electrode with a self-aligned dielectric spacer | |
US20090085075A1 (en) | Method of fabricating mos transistor and mos transistor fabricated thereby | |
US20120064687A1 (en) | Method of manufacturing semiconductor device | |
US20230317791A1 (en) | Semiconductor device and manufacturing method thereof | |
US20210134995A1 (en) | Vertical channel device | |
CN111627815B (en) | Forming method of non-planar field effect transistor |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BASKER, VEERARAGHAVAN S.;LIU, ZUOGUANG;YAMASHITA, TENKO;AND OTHERS;REEL/FRAME:036407/0519 Effective date: 20150824 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |