US20160190441A1 - Resistive Memory Cell With Sloped Bottom Electrode - Google Patents
Resistive Memory Cell With Sloped Bottom Electrode Download PDFInfo
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- US20160190441A1 US20160190441A1 US15/065,193 US201615065193A US2016190441A1 US 20160190441 A1 US20160190441 A1 US 20160190441A1 US 201615065193 A US201615065193 A US 201615065193A US 2016190441 A1 US2016190441 A1 US 2016190441A1
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- H10N70/801—Constructional details of multistable switching devices
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- H10N70/8418—Electrodes adapted for focusing electric field or current, e.g. tip-shaped
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- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
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- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Patterning of the switching material
- H10N70/063—Patterning of the switching material by etching of pre-deposited switching material layers, e.g. lithography
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- H10N70/061—Patterning of the switching material
- H10N70/068—Patterning of the switching material by processes specially adapted for achieving sub-lithographic dimensions, e.g. using spacers
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- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
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- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
- H10N70/245—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
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- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
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- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
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- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
- H10N70/8828—Tellurides, e.g. GeSbTe
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- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
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- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
- H10N70/8833—Binary metal oxides, e.g. TaOx
Definitions
- the present disclosure relates to resistive memory cells, e.g., conductive bridging random access memory (CBRAM) or resistive random-access memory (ReRAM) cells, having a sloped bottom electrode.
- resistive memory cells e.g., conductive bridging random access memory (CBRAM) or resistive random-access memory (ReRAM) cells, having a sloped bottom electrode.
- CBRAM conductive bridging random access memory
- ReRAM resistive random-access memory
- Resistive memory cells such as conductive bridging memory (CBRAM) and resistive RAM (ReRAM) cells are a new type of non-volatile memory cells that provide scaling and cost advantages over conventional Flash memory cells.
- a CBRAM is based on the physical re-location of ions within a solid electrolyte.
- a CBRAM memory cell can be made of two solid metal electrodes, one relatively inert (e.g., tungsten) the other electrochemically active (e.g., silver or copper), separated from each other by a thin layer or film of non-conducting material.
- the CBRAM cell generates programmable conducting filaments across the non-conducting film through the application of a bias voltage across the non-conducting film.
- the conducting filaments may be formed by single or very few nanometer-scale ions.
- the non-conducting film may be referred to as an electrolyte because it provides for the propagation of the conductive filament(s) across the film through an oxidation/reduction process much like in a battery.
- the conduction occurs through creation of a vacancy chain in an insulator.
- the generation of the conductive filament(s)/vacancy-chain(s) creates an on-state (high conduction between the electrodes), while the dissolution of the conductive filament(s)/vacancy-chain(s), e.g., by applying a similar polarity with Joule heating current or an opposite polarity but at smaller currents, reverts the electrolyte/insulator back to its nonconductive off-state.
- both the electrolyte film, layer, or region of a CBRAM cell and the insulator film, layer, or region of a ReRAM cell are referred to as an “electrolyte,” for the sake of simplicity.
- a wide range of materials have been demonstrated for possible use in resistive memory cells, both for the electrolyte and the electrodes.
- One example is the Cu/SiOx based cell in which the Cu is the active metal-source electrode and the SiOx is the electrolyte.
- resistive memory cells One common problem facing resistive memory cells is the on-state retention, i.e., the ability of the conductive path (filament or vacancy chain) to be stable, especially at the elevated temperatures that the memory parts may typically be qualified to (e.g., 85 C/125 C).
- FIG. 1 shows a conventional CBRAM cell 1 A, having a top electrode 10 (e.g., copper) arranged over a bottom electrode 12 (e.g., tungsten), with the electrolyte or middle electrode 14 (e.g., SiO 2 ) arranged between the top and bottom electrodes.
- Conductive filaments 18 propagate from the bottom electrode 12 to the top electrode 10 through the electrolyte 14 when a bias voltage is applied to the cell 1 A.
- This structure has various potential limitations or drawbacks.
- the effective cross-sectional area for filament formation which may be referred to as the “confinement zone” or the “filament formation area” indicated as A FF , is relatively large and unconfined, making the filament formation area susceptible to extrinsic defects.
- multi-filament root formation may be likely, due to a relatively large area, which may lead to weaker (less robust) filaments.
- the larger the ratio between the diameter or width of the filament formation area A FF (indicated by “x”) to the filament propagation distance from the bottom electrode 12 to the top electrode 10 (in this case, the thickness of the electrolyte 14 , indicated by “y”) the greater the chance of multi-root filament formation.
- a large electrolyte area surrounds the filament, which provides diffusion paths for the filament and thus may provide poor retention.
- restricting the volume of the electrolyte material in which the conductive path forms may provide a more robust filament due to spatial confinement.
- the volume of the electrolyte material in which the conductive path forms may be restricted by reducing the area in contact between the bottom electrode 12 and the electrolyte 14 .
- conductive path refers a conductive filament (e.g., in a CBRAM cell), vacancy chain (e.g., in an oxygen vacancy based ReRAM cell), or any other type of conductive path for connecting the electrodes of a non-volatile memory cell, typically through an electrolyte layer or region arranged between the electrodes.
- electrolyte layer or ““electrolyte region” refers to an electrolyte/insulator/memory layer or region between the bottom and top electrodes through which the conductive path propagates.
- FIG. 2 shows certain principles of a CBRAM cell formation.
- Conductive paths 18 may form and grow laterally, or branch into multiple parallel paths. Further, locations of the conductive paths may change with each program/erase cycle. This may contribute to a marginal switching performance, variability, high-temp retention issues, and/or switching endurance. Restricting switching volume has shown to benefit the operation. These principles apply to ReRAM and CBRAM cells. A key obstacle for adoption of these technologies is switching uniformity.
- FIGS. 3A and 3B show a schematic view and an electron microscope image of an example known bottom electrode configuration 1 B for a CBRAM cell (e.g., having a 1T1R architecture).
- the bottom electrode 12 is a cylindrical via, e.g., a tungsten-filled via with a Ti/TiN liner.
- a top contact and/or anode 20 may be connected to the top electrode 10 as shown.
- the bottom electrode 12 may provide a relatively large filament formation area A FF of about 30,000 nm 2 , for example, which may lead to one or more of the problems or disadvantages discussed above.
- Some embodiments provide resistive memory cells, e.g., CBRAM or ReRAM cells, and methods of forming such resistive memory cells, having a bottom electrode formed with one or more sloped surfaces that define an upwardly-pointed tip, which may be a point, edge, or surface, depending on the embodiment.
- the bottom electrode may have any shape that defines an upwardly-pointed tip.
- the bottom electrode may have an elongated prism shape with a triangular cross-section that extends across one or multiple bottom electrode connections, or a concave bowl shape defining an upwardly-pointed ring-shaped tip edge, or an upwardly-pointed pyramid shape.
- the upwardly-pointing tip of the bottom electrode may focus the electric field more precisely than in known cells, which may provide more consistent filament formation, thus improving the consistency of programming voltage and cell predictability, e.g., as compared with certain conventional designs.
- a method of forming a resistive memory cell comprises forming a plurality of bottom electrode connections; depositing a bottom electrode layer over the bottom electrode connections; performing a first etch to remove portions of the bottom electrode layer such that the remaining bottom electrode layer defines at least one sloped surface; forming an oxidation layer on each sloped surface of the remaining bottom electrode layer; performing a second etch on the remaining bottom electrode layer and oxidation layer on each sloped surface to define at least one upwardly-pointing bottom electrode region above each bottom electrode connection, each upwardly-pointing bottom electrode region defining a bottom electrode tip; and forming an electrolyte region and a top electrode over each bottom electrode tip such that the electrolyte region is arranged between the top electrode and the respective bottom electrode top.
- a resistive memory cell comprises a plurality of bottom electrode connections; at least one bottom electrode region formed over and conductively coupled to the bottom electrode connections, each bottom electrode region having at least one sloped sidewall and defining an upwardly-pointing tip; an electrolyte region and a top electrode over each bottom electrode tip such that the electrolyte region is arranged between the top electrode and the respective bottom electrode top; and a top electrode connection conductively coupled to each top electrode.
- a method of forming a resistive memory cell comprises forming a plurality of bottom electrode connections; depositing a bottom electrode layer over the bottom electrode connections; performing an etch to remove portions of the bottom electrode layer to form at least one upwardly-pointing bottom electrode region above the bottom electrode connections, each upwardly-pointing bottom electrode region defining a bottom electrode tip; and forming an electrolyte region and a top electrode over each bottom electrode tip such that the electrolyte region is arranged between the top electrode and the respective bottom electrode top.
- a resistive memory cell comprises a plurality of bottom electrode connections; at least one bottom electrode region formed over and conductively coupled to the bottom electrode connections, each bottom electrode region having at least two sloped sidewalls and defining an upwardly-pointing tip; an electrolyte region and a top electrode over each bottom electrode tip such that the electrolyte region is arranged between the top electrode and the respective bottom electrode top; and a top electrode connection conductively coupled to each top electrode.
- FIG. 1 shows an example conventional CBRAM cell
- FIG. 2 shows certain principles of CBRAM cell formation
- FIGS. 3A and 3B show a schematic view and an electron microscope image of an example known CBRAM cell configuration
- FIGS. 4 A 1 - 4 N 2 illustrate an example method for forming a resistive memory cell structure, e.g., a CBRAM or ReRAM cell structure, including bottom electrodes having a sloped surface defining a pointed upper-edge, according to one embodiment of the present invention
- FIGS. 5 A 1 - 5 N 2 illustrate an another example method for forming a resistive memory cell structure, e.g., a CBRAM or ReRAM cell structure, including sloped ring-shaped bottom electrodes defining a ring-shaped pointed upper-edge, according to one embodiment of the present invention
- FIGS. 6 A 1 - 6 L 2 illustrate an another example method for forming a resistive memory cell structure, e.g., a CBRAM or ReRAM cell structure, including bottom electrodes having a pair of sloped side walls defining a pointed upper-edge, according to one embodiment of the present invention
- FIGS. 7 A 1 - 7 K 2 illustrate an another example method for forming a resistive memory cell structure, e.g., a CBRAM or ReRAM cell structure, including pyramid shaped bottom electrodes having four sloped sides meeting at an upwardly pointed tip, according to one embodiment of the present invention
- FIGS. 8A-8C illustrate an another example method for forming a resistive memory cell structure, e.g., a CBRAM or ReRAM cell structure, including pyramid shaped bottom electrodes having three sloped sides meeting at an upwardly pointed tip, according to one embodiment of the present invention.
- a resistive memory cell structure e.g., a CBRAM or ReRAM cell structure
- pyramid shaped bottom electrodes having three sloped sides meeting at an upwardly pointed tip
- embodiments of the present invention may provide resistive memory cells, e.g., CBRAM or ReRAM cells, and methods of forming such resistive memory cells, having a bottom electrode formed with one or more sloped surfaces that define an upwardly-pointed tip, e.g., a triangular shaped bottom electrode, a concave bowl-shaped bottom electrode with a ring-shaped tip edge, or a pyramid shaped bottom electrode.
- the upwardly-pointed tip of the bottom electrode may focus the electric field and provide a reduced filament formation area A FF , which may provide more consistent filament formation, thus improving the consistency of programming voltage and cell predictability, e.g., as compared with certain conventional designs.
- FIGS. 4 A 1 - 4 N 2 illustrate an example method for forming a resistive memory cell structure, e.g., a CBRAM or ReRAM cell structure, including bottom electrodes having a sloped surface defining a pointed upper-edge, according to one embodiment of the present invention.
- a resistive memory cell structure e.g., a CBRAM or ReRAM cell structure
- an array of bottom electrode connectors 102 are formed in a substrate 100 .
- Bottom electrode connectors 102 and substrate 100 may be formed in any suitable manner (e.g., using conventional semiconductor fabrication techniques) and from any suitable materials.
- substrate 100 may be formed from an insulator, e.g., SiO 2
- each bottom electrode connector 102 may have a conductor region 104 formed from copper (Cu) or other conductive material, and a connection region 106 formed from tungsten (W) or other suitable material.
- each bottom electrode connector 102 is formed with a circular via-type shape.
- each bottom electrode connector 102 may be formed with any other suitable shape, e.g., an elongated line or elongated rectangular shape, a square shape, etc.
- Bottom electrode layer 110 may comprise any suitable conductive material or materials, e.g., polysilicon, doped polysilicon, amorphous silicon, doped amorphous silicon, or any other suitable material, and may be deposited or formed in any suitable manner.
- Hard mask layer 112 may be formed from any suitable materials (e.g., SiN, SiON, or other dielectric material) and may be deposited or formed in any suitable manner as known in the art.
- the hard mask 112 is patterned, e.g., by forming and patterning a photoresist layer 116 over the hard mask 112 , using any suitable photolithography techniques. As shown, the photoresist layer 116 is patterned with openings 118 that expose particular areas of the underlying hard mask 112 . In this embodiment, openings 118 are formed as elongated trenches extending between or alongside rows of underlying bottom electrode connectors 102 , as shown in FIG. 4 C 2 .
- openings 118 may alternatively be formed with any other shape, e.g., circular via-type openings, and/or may correspond with underlying bottom electrode connectors 102 in a one-to-one manner (as opposed to the illustrated one-to-multiple arrangement). Also, in the illustrated embodiment, the openings 118 are located such that each underlying bottom electrode connector 102 has a single corresponding opening wall 120 overlying that bottom electrode connector 102 , wherein the single corresponding opening wall 120 for bottom electrode connector 102 provides the basis for a single sloped bottom electrode sidewall formed over that bottom electrode connector 102 according to the following process steps.
- opening wall 120 A overlies bottom electrode connector 102 A
- opening wall 120 B overlies bottom electrode connector 102 B
- opening wall 120 C overlies bottom electrode connector 102 C.
- the openings 118 are shaped and/or located such that multiple opening walls 120 overly each bottom electrode connector 102 , e.g., such that multiple sloped bottom electrode sidewalls may be formed over each bottom electrode connector 102 .
- etch and strip/removal processes are performed to transfer the photoresist pattern into the hard mask 112 and remove the remaining photoresist, thereby forming a patterned hard mask 112 having an array of openings 124 .
- FIGS. 4 E 1 - 4 G 2 illustrate a progression of the etch process, in particular showing “snapshots” of the structure at three different points in time along the progression of the etch.
- FIGS. 4 E 1 and 4 E 2 show a snapshot at a first instant in time during the etch
- FIGS. 4 F 1 and 4 F 2 show a snapshot at a second instant in time during the etch
- FIGS. 4 G 1 and 4 G 2 show a snapshot at or after completion of the etch.
- the etch process may continue to remove material from bottom electrode layer 110 until the remaining portions of the bottom electrode layer 110 define a sloped sidewall surface 130 above each bottom electrode connector 102 .
- the etch process may separate bottom electrode layer 110 into discrete bottom electrode layer regions, e.g., regions 110 A and 110 B shown in FIGS. 4 G 1 and 4 G 2 .
- the exposed sloped sidewall surfaces 130 of bottom electrode layer regions 110 A and 110 B are oxidized using any suitable process, to form an oxidized layer 134 on each sloped region 130 .
- the hard mask 112 is removed using any suitable process, e.g., by etching or stripping.
- the bottom electrode layer regions 110 A and 110 B are etched utilizing the oxidized regions as a hardmask to block the etching of bottom electrode underneath. And the oxidized layers 134 are removed, thereby forming discrete bottom electrodes 140 , each having an upwardly-pointing region defining a sloped side wall surface 142 and a tip 144 .
- the etch and oxide removal process may be performed in two steps, e.g., using a highly selective etch that preserves the oxide layers 134 and then gently removing the oxide layers 134 in a subsequent step, or alternatively may be performed in a single step, e.g., using a slightly higher oxide etch rate that removes the oxide layers 134 along with portions of the bottom electrode layer material.
- Electrolyte layer 150 may comprise any suitable dielectric or memristive type material or materials, for example, SiOx (e.g., SiO 2 ), GeS, CuS, TaO x , TiO 2 , Ge 2 Sb 2 Te 5 , GdO, HfO, CuO, Al 2 O 3 , or any other suitable material.
- Top electrode layer 152 may comprise any suitable conductive material or materials, e.g., Ag, Al, Cu, Ta, TaN, Ti, TiN, Al, W or any other suitable material, and may be deposited or formed in any suitable manner.
- the electrolyte layer 150 and top electrode layer 152 are patterned by forming and patterning a photoresist layer 160 over the top electrode layer 152 , using any suitable photolithography techniques.
- the photoresist layer 160 is patterned with openings 162 that expose particular areas of the top electrode layer 152 .
- openings 162 are formed as elongated trenches between adjacent rows of bottom electrodes 140 , as shown in FIG. 4 L 2 .
- photoresist layer 160 may be patterned in any other suitable manner.
- photoresist layer 160 may be patterned such that a discrete photoresist region remains over each bottom electrode 140 (rather than spanning multiple bottom electrodes 140 as shown in FIG. 4 L 2 ).
- etch and strip/removal processes are performed to transfer the photoresist pattern into the electrolyte layer 150 and top electrode layer 152 and remove the remaining photoresist, thereby dividing the electrolyte layer 150 and top electrode layer 152 into discrete electrolyte regions 170 and corresponding top electrodes 172 .
- each electrolyte region 170 /top electrode 172 forms a row spanning multiple bottom electrodes 140 .
- top electrode interconnects 180 may be formed in an insulator material 182 deposited over the stack, using any suitable techniques.
- the insulator material 182 may comprise any suitable insulator (e.g., SiO 2 ), which may or may not be the same material as substrate 100 .
- Top electrode interconnects 180 may be formed from any suitable conductor (e.g., Cu), and may be formed at any suitable locations relative to top electrodes 172 .
- a top electrode interconnect 180 is formed over each elongated top electrode 172 at the end of each column (i.e., the connection may be periodic rather than over each bitcell).
- the bottom electrode 140 has an upwardly-pointing region defining a sloped side wall 142 and a pointed tip 144 .
- conductive filament propagation from each respective bottom electrode 140 is substantially confined to the pointed tip 144 , as the electric field naturally concentrates at the point, edge, or surface having the smallest radius of curvature.
- the sharper the point of tip 144 the greater the concentration of the filament-generating electric field, and thus the smaller the effective filament formation area A FF .
- the pointed tip shaped bottom electrode 140 may provide a substantially reduced effective filament formation area A FF , as compared with conventional bottom electrode structures.
- FIGS. 5 A 1 - 5 N 2 illustrate an example method for forming a resistive memory cell structure, e.g., a CBRAM or ReRAM cell structure, including sloped ring-shaped bottom electrodes defining a ring-shaped pointed upper-edge, according to one embodiment of the present invention.
- a resistive memory cell structure e.g., a CBRAM or ReRAM cell structure
- an array of bottom electrode connectors 202 are formed in a substrate 200 .
- Bottom electrode connectors 202 and substrate 200 may be formed in any suitable manner (e.g., using conventional semiconductor fabrication techniques) and from any suitable materials.
- substrate 200 may be formed from an insulator, e.g., SiO 2
- each bottom electrode connector 202 may have a conductor region 204 formed from copper (Cu) or other conductive material, and a connection region 206 formed from tungsten (W) or other suitable material.
- each bottom electrode connector 202 is formed with a circular via-type shape.
- each bottom electrode connector 202 may be formed with any other suitable shape, e.g., an elongated line or elongated rectangular shape, a square shape, etc.
- Bottom electrode layer 210 may comprise any suitable conductive material or materials, e.g., polysilicon, doped polysilicon, amorphous silicon, doped amorphous silicon, or any other suitable material, and may be deposited or formed in any suitable manner.
- Hard mask layer 212 may be formed from any suitable materials (e.g., SiN, SiON, or other dielectric material) and may be deposited or formed in any suitable manner as known in the art.
- the hard mask 212 is patterned, e.g., by forming and patterning a photoresist layer 216 over the hard mask 212 , using any suitable photolithography techniques. As shown, the photoresist layer 216 is patterned with openings 218 that expose particular areas of the underlying hard mask 212 .
- openings 218 are formed as circular openings over each bottom electrode connector 202 , with the perimeter of each circular opening 218 being smaller than and aligned concentrically within the perimeter of the respective bottom electrode connector 202 , as shown in FIG. 5 C 2 . In other embodiments, circular openings 218 may align in an overlapping manner with respect to their respective bottom electrode connectors 202 , as viewed from the top view.
- FIG. 5 D 1 cross-sectional side view
- FIG. 5 D 2 top view
- an etch is performed to transfer the photoresist pattern into the hard mask 212 , thereby forming a patterned hard mask 212 having an array of openings 224 .
- the remaining photoresist is removed, e.g., by stripping or other suitable process.
- bottom electrode layer 210 may be etched through the openings 224 in the patterned hard mask 212 using any suitable isotropic etch process.
- FIGS. 5 F 1 and 5 F 2 illustrate a snapshot of the structure at an instant during the etch process
- FIGS. 5 G 1 and 5 G 2 show a snapshot at or after completion of the etch.
- the etch process may remove material from bottom electrode layer 210 until the remaining portions of the bottom electrode layer 210 define a concave, bowl-shaped structure having a sloped U-shaped (in the cross-sectional side view), ring-shaped (in the top view) sidewall 230 above each bottom electrode connector 202 .
- the etch process may etch fully through the bottom electrode layer 210 and down to the bottom electrode connection region 206 to expose a top surface area of connection region 206 , e.g., at the bottom center of the etched area. In other embodiments, the etch process may not extend fully through the bottom electrode layer 210 , such that a portion of the bottom electrode material 210 remains over the top surface of connection region 206 , even at the bottom center of the etched area.
- the exposed sloped U-shaped (side view), ring-shaped (top view) sidewalls 230 defined in bottom electrode layer 210 are oxidized using any suitable process, to form an oxidized layer 234 on each sloped region 230 .
- hard mask 212 is removed using any suitable process, e.g., by etching or stripping.
- each bottom electrode 240 comprises a concave, bowl-shaped structure having a sloped U-shaped (cross-sectional side view), ring-shaped (in the top view) sidewall surface 242 and an upwardly-pointed ring-shaped tip 244 .
- the etch and oxide removal process may be performed in two steps, e.g., using a highly selective etch that preserves the oxide layers 234 and then gently removing the oxide layers 234 in a subsequent step, or alternatively may be performed in a single step, e.g., using a slightly higher oxide etch rate that removes the oxide layers 234 along with portions of the bottom electrode layer material.
- each bottom electrode 240 may have an central opening that exposes a top surface area of the underlying connection region 206 . In other embodiments, a portion of the bottom electrode material 210 remains over the top surface of connection region 206 , even at the bottom center of the bowl-shaped structure, such that the top surface of the underlying connection region 206 is not exposed through the center of the bottom electrode 240 .
- Electrolyte layer 250 may comprise any suitable dielectric or memristive type material or materials, for example, SiOx (e.g., SiO 2 ), GeS, CuS, TaO x , TiO 2 , Ge 2 Sb 2 Te 5 , GdO, HfO, CuO, Al 2 O 3 , or any other suitable material.
- Top electrode layer 252 may comprise any suitable conductive material or materials, e.g., Ag, Al, Cu, Ta, TaN, Ti, TiN, Al, W or any other suitable material, and may be deposited or formed in any suitable manner.
- the electrolyte layer 250 and top electrode layer 252 are patterned and etched to divide the electrolyte layer 250 and top electrode layer 252 into discrete electrolyte 270 /top electrode 272 regions, each covering one or multiple bottom electrodes 202 .
- the electrolyte layer 250 and top electrode layer 252 are patterned and etched to form a discrete electrolyte 270 /top electrode 272 region over each individual bottom electrode 202 .
- the electrolyte layer 250 and top electrode layer 252 are patterned and etched to form elongated electrolyte 270 /top electrode 272 regions, each spanning a row of multiple bottom electrodes 202 .
- top electrode interconnects 280 may be formed in an insulator material 282 deposited over the stack, using any suitable techniques.
- the insulator material 282 may comprise any suitable insulator (e.g., SiO 2 ), which may or may not be the same material as substrate 200 .
- Top electrode interconnects 280 may be formed from any suitable conductor (e.g., Cu), and may be formed at any suitable locations relative to top electrodes 272 . In this example embodiment, as shown in FIG. 5 M 2 , a discrete top electrode interconnect 280 is formed over each top electrode 272 .
- FIG. 5 N 1 cross-sectional side view
- FIG. 5 N 2 top view
- a top electrode interconnect 280 is formed over and connected to each elongated top electrode 272 , at the end of each column (i.e., the connection may be periodic rather than over each bitcell), as shown in FIG. 5 N 2 .
- each bottom electrode 240 has a concave bowl-shaped structure defining an upwardly-pointed ring-shaped tip 244 .
- conductive filament propagation from each respective bottom electrode 240 is substantially confined to the ring-shaped pointed tip 244 , as the electric field naturally concentrates at the point, edge, or surface having the smallest radius of curvature.
- the sharper the point of ring-shaped tip 244 the greater the concentration of the filament-generating electric field, and thus the smaller the effective filament formation area A FF .
- the ring-shaped pointed tip of each bottom electrode 240 may provide a substantially reduced effective filament formation area A FF , as compared with conventional bottom electrode structures.
- FIGS. 6 A 1 - 6 L 2 illustrate an example method for forming a resistive memory cell structure, e.g., a CBRAM or ReRAM cell structure, including bottom electrodes having a pair of sloped side walls defining a pointed upper-edge, according to one embodiment of the present invention.
- a resistive memory cell structure e.g., a CBRAM or ReRAM cell structure
- an array of bottom electrode connectors 302 are formed in a substrate 300 .
- Bottom electrode connectors 302 and substrate 300 may be formed in any suitable manner (e.g., using conventional semiconductor fabrication techniques) and from any suitable materials.
- substrate 300 may be formed from an insulator, e.g., SiO 2
- each bottom electrode connector 302 may have a conductor region 304 formed from copper (Cu) or other conductive material, and a connection region 306 formed from tungsten (W) or other suitable material.
- each bottom electrode connector 302 is formed with a circular via-type shape.
- each bottom electrode connector 302 may be formed with any other suitable shape, e.g., an elongated line or elongated rectangular shape, a square shape, etc.
- Bottom electrode layer 310 may comprise any suitable conductive material or materials, e.g., polysilicon, doped polysilicon, amorphous silicon, doped amorphous silicon, or any other suitable material, and may be deposited or formed in any suitable manner.
- Hard mask layer 312 may be formed from any suitable materials (e.g., SiN, SiON, or other dielectric material) and may be deposited or formed in any suitable manner as known in the art.
- the hard mask 312 is patterned, e.g., by forming and patterning a photoresist layer 316 over the hard mask 312 , using any suitable photolithography techniques. As shown, the photoresist layer 316 is patterned with openings 318 that expose particular areas of the underlying hard mask 312 . In this embodiment, openings 318 are formed as elongated trenches extending between adjacent rows of underlying bottom electrode connectors 302 , as shown in FIG. 6 C 2 .
- openings 318 may alternatively be formed with any other shape, e.g., circular via-type openings, and/or may correspond with underlying bottom electrode connectors 302 in a one-to-one manner (as opposed to the illustrated one-to-multiple arrangement).
- etch and strip/removal processes are performed to transfer the photoresist pattern into the hard mask 312 and remove the remaining photoresist, thereby forming a patterned hard mask 312 having an array of openings 324 .
- FIGS. 6 E 1 - 6 G 2 illustrate a progression of the etch process, in particular showing “snapshots” of the structure at three different points in time along the progression of the etch.
- FIGS. 6 E 1 and 6 E 2 show a snapshot at a first instant in time during the etch
- FIGS. 6 F 1 and 6 F 2 show a snapshot at a second instant in time during the etch
- FIGS. 6 G 1 and 6 G 2 show a snapshot at or after completion of the etch.
- the etch process may remove material from bottom electrode layer 310 until the remaining portions of the bottom electrode layer 310 define elongated bottom electrode regions 310 A, 310 B, and 310 C above respective rows of bottom electrode connectors 302 , each bottom electrode region 310 A, 310 B, and 310 C having a pair of sloped sidewalls 330 meeting at an upwardly-pointing edge tip 332 , thus defining a triangular cross-sectional shape.
- triangular means three sided, wherein each side may be linear or may be non-linear (e.g., curved, irregular, or otherwise non-linear).
- the hard mask 312 is removed using any suitable process, e.g., by etching or stripping, leaving a series of bottom electrodes 340 (corresponding to bottom electrode regions 310 A, 310 B, and 310 C).
- Electrolyte layer 350 may comprise any suitable dielectric or memristive type material or materials, for example, SiOx (e.g., SiO 2 ), GeS, CuS, TaO x , TiO 2 , Ge 2 Sb 2 Te 5 , GdO, HfO, CuO, Al 2 O 3 , or any other suitable material.
- Top electrode layer 352 may comprise any suitable conductive material or materials, e.g., Ag, Al, Cu, Ta, TaN, Ti, TiN, Al, W or any other suitable material, and may be deposited or formed in any suitable manner.
- the electrolyte layer 350 and top electrode layer 352 are patterned by forming and patterning a photoresist layer 360 over the top electrode layer 352 , using any suitable photolithography techniques.
- the photoresist layer 360 is patterned with openings 362 that expose particular areas of the top electrode layer 352 .
- openings 362 are formed as elongated trenches between adjacent rows of bottom electrodes 340 , as shown in FIG. 6 J 2 .
- photoresist layer 360 may be patterned in any other suitable manner.
- photoresist layer 360 may be patterned such that a discrete photoresist region remains over each bottom electrode 340 (rather than spanning multiple bottom electrodes 340 as shown in FIG. 6 J 2 ).
- each electrolyte region 370 /top electrode 372 forms a row spanning multiple bottom electrodes 340 .
- top electrode interconnects 380 may be formed in an insulator material 382 deposited over the stack, using any suitable techniques.
- the insulator material 382 may comprise any suitable insulator (e.g., SiO 2 ), which may or may not be the same material as substrate 300 .
- Top electrode interconnects 380 may be formed from any suitable conductor (e.g., Cu), and may be formed at any suitable locations relative to top electrodes 372 .
- a top electrode interconnect 380 is formed over each elongated top electrode 372 at the end of each column (i.e., the connection may be periodic rather than over each bitcell).
- each bottom electrode 340 has an upwardly-pointing triangular cross-section defining a pair of sloped side walls 330 meeting at a pointed tip 332 .
- conductive filament propagation from each respective bottom electrode 340 is substantially confined to the pointed tip 332 , as the electric field naturally concentrates at the point, edge, or surface having the smallest radius of curvature.
- the sharper the point of tip 332 the greater the concentration of the filament-generating electric field, and thus the smaller the effective filament formation area A FF .
- the generally triangular, pointed tip shaped bottom electrode 340 may provide a substantially reduced effective filament formation area A FF , as compared with conventional bottom electrode structures.
- FIGS. 7 A 1 - 7 K 2 illustrate an example method for forming a resistive memory cell structure, e.g., a CBRAM or ReRAM cell structure, including pyramid shaped bottom electrodes having four sloped sides meeting at an upwardly pointed tip, according to one embodiment of the present invention.
- a resistive memory cell structure e.g., a CBRAM or ReRAM cell structure, including pyramid shaped bottom electrodes having four sloped sides meeting at an upwardly pointed tip, according to one embodiment of the present invention.
- an array of bottom electrode connectors 402 are formed in a substrate 400 .
- Bottom electrode connectors 402 and substrate 400 may be formed in any suitable manner (e.g., using conventional semiconductor fabrication techniques) and from any suitable materials.
- substrate 400 may be formed from an insulator, e.g., SiO 2
- each bottom electrode connector 402 may have a conductor region 404 formed from copper (Cu) or other conductive material, and a connection region 406 formed from tungsten (W) or other suitable material.
- each bottom electrode connector 402 is formed with a circular via-type shape.
- each bottom electrode connector 402 may be formed with any other suitable shape, e.g., an elongated line or elongated rectangular shape, a square shape, etc.
- Bottom electrode layer 410 is deposited or formed over the substrate 400 and bottom electrode connectors 402 .
- Bottom electrode layer 410 may comprise any suitable conductive material or materials, e.g., polysilicon, doped polysilicon, amorphous silicon, doped amorphous silicon, or any other suitable material, and may be deposited or formed in any suitable manner.
- Hard mask layer 412 is formed over the bottom electrode layer 410 .
- Hard mask layer 412 may be formed from any suitable materials (e.g., SiN, SiON, or other dielectric material), and patterned in any suitable manner known in the art.
- hard mask layer 412 may be patterned using a photoresist layer and suitable patterning and etch process.
- hard mask layer 412 is patterned with a two-dimensional array of circular openings 424 located in the areas between (i.e., not overlying) the underlying bottom electrode connection regions 406 .
- openings 424 may alternatively be formed with any other shape, e.g., elongated trench-type openings, and/or may be partially or fully located above underlying bottom electrode connection regions 406 .
- bottom electrode layer 410 may be etched through the openings 424 in the patterned hard mask 412 using any suitable etch process.
- FIGS. 7 D 1 - 7 F 2 illustrate a progression of the etch process, in particular showing “snapshots” of the structure at three different points in time along the progression of the etch.
- FIGS. 7D 1 and 7 D 2 show a snapshot at a first instant in time during the etch
- FIGS. 7 E 1 and 7 E 2 show a snapshot at a second instant in time during the etch
- FIGS. 7F 1 and 7 F 2 show a snapshot at or after completion of the etch.
- the etch process may remove material from bottom electrode layer 410 until the remaining portions of the bottom electrode layer 410 define a two-dimensional array of pyramid shaped bottom electrodes 440 , each located above a respective bottom electrode connector 402 .
- Each pyramid shaped bottom electrode 440 has four sloped sidewalls 430 meeting at an upwardly-pointing tip 432 .
- pyramid means a three-dimensional shape having three or more triangular or generally triangular outer sides that meet at a point or relatively small edge or surface, and a base having a trilateral, quadrilateral, or any other polygon shape.
- Each generally triangular outer side may be planar or non-planar (e.g., concave, convex, irregular, or otherwise non-planar).
- each pyramid shaped bottom electrode 440 are triangular or generally triangular and concave or generally concave, due to the etch process that form the pyramid shapes.
- the hard mask 412 is removed using any suitable process, e.g., by etching or stripping, leaving the two-dimensional array of pyramid-shaped bottom electrodes 440 .
- the patterning hard mask layer 412 with the two-dimensional array of openings shown in FIGS. 7 C 1 and 7 C 2 provides for a two-dimensional array of pyramid-shaped bottom electrodes, one per bottom electrode connection 406 , as opposed to patterning the hard mask with elongated trench openings that lead to elongated bottom electrodes, as disclosed in the example steps shown in FIGS. 6 C 1 - 6 H 2 discussed above.
- Electrolyte layer 450 may comprise any suitable dielectric or memristive type material or materials, for example, SiOx (e.g., SiO 2 ), GeS, CuS, TaO x , TiO 2 , Ge 2 Sb 2 Te 5 , GdO, HfO, CuO, Al 2 O 3 , or any other suitable material.
- Top electrode layer 452 may comprise any suitable conductive material or materials, e.g., Ag, Al, Cu, Ta, TaN, Ti, TiN, Al, W or any other suitable material, and may be deposited or formed in any suitable manner.
- the electrolyte layer 450 and top electrode layer 452 are patterned by forming and patterning a photoresist layer 460 over the top electrode layer 452 , using any suitable photolithography techniques.
- the photoresist layer 460 is patterned with openings 462 that expose particular areas of the top electrode layer 452 .
- openings 462 are formed as elongated trenches between adjacent rows of bottom electrodes 440 , as shown in FIG. 712 .
- photoresist layer 460 may be patterned in any other suitable manner.
- photoresist layer 460 may be patterned such that a discrete photoresist region remains over each bottom electrode 440 (rather than spanning multiple bottom electrodes 440 as shown in FIG. 712 ).
- each electrolyte region 470 /top electrode 472 forms a row spanning multiple bottom electrodes 440 .
- top electrode interconnects 480 may be formed in an insulator material 482 deposited over the stack, using any suitable techniques.
- the insulator material 482 may comprise any suitable insulator (e.g., SiO 2 ), which may or may not be the same material as substrate 400 .
- Top electrode interconnects 480 may be formed from any suitable conductor (e.g., Cu), and may be formed at any suitable locations relative to top electrodes 472 .
- a top electrode interconnect 480 is formed over each elongated top electrode 472 at the end of each column (i.e., the connection may be periodic rather than over each bitcell).
- each bottom electrode 440 has an upwardly-pointing pyramid shape have four sloped side walls 430 meeting at a pointed tip 432 .
- conductive filament propagation from each respective bottom electrode 440 is substantially confined to the pointed pyramid tip 432 , as the electric field naturally concentrates at the point, edge, or surface having the smallest radius of curvature.
- the sharper the point of the pyramid tip 432 the greater the concentration of the filament-generating electric field, and thus the smaller the effective filament formation area A FF .
- the generally triangular, pointed tip shaped bottom electrode 440 may provide a substantially reduced effective filament formation area A FF , as compared with conventional bottom electrode structures.
- FIGS. 8A-8C illustrate steps in an example method for forming a resistive memory cell structure, e.g., a CBRAM or ReRAM cell structure, including pyramid shaped bottom electrodes having three sloped sides meeting at an upwardly pointed tip, according to one embodiment of the present invention.
- a resistive memory cell structure e.g., a CBRAM or ReRAM cell structure
- pyramid shaped bottom electrodes having three sloped sides meeting at an upwardly pointed tip
- FIG. 8A is a top view of a two-dimensional pattern of bottom electrode connections 506 formed in an insulator 500 , e.g., analogous to the views shown in FIGS. 4 A 2 , 5 A 2 , 6 A 2 , and 7 A 2 .
- bottom electrode connections 506 are arranged in staggered rows that form a hexagonal pattern, as opposed to the aligned n rows by m columns patterns shown in FIGS. 4 A 2 , 5 A 2 , 6 A 2 , and 7 A 2 .
- FIG. 8B is a top view of a patterned hard mask layer 512 formed over a bottom electrode layer 510 deposited over bottom electrode connection regions 506 , e.g., analogous to the views shown in FIGS. 4 D 2 , 5 E 2 , 6 D 2 , and 7 C 2 .
- mask layer 512 is patterned with a two-dimensional array of circular openings 524 located in the areas between (i.e., not overlying) the underlying bottom electrode connection regions 506 .
- FIG. 8C is a top view of a two-dimensional pattern of bottom electrodes 540 formed by etching the bottom electrode layer 510 through the two-dimensional array of circular openings 524 shown in FIG. 8B , and then removing the hard mask 512 , e.g., in a manner similar to the example embodiments discussed above.
- the extent of etching through each hard mask openings 524 is shown in FIG. 8C by a large circle 536 .
- the portions of the bottom electrode layer 510 remaining after the etch process define an array of pyramid shaped bottom electrodes 540 , e.g., similar to the pyramid shaped bottom electrodes 440 formed by the steps show in FIGS. 7B 1 to 7 G 2 , described above.
- pyramid shaped bottom electrode 540 shown in FIG. 8C have three sloped sides instead of four, due to the arrangement of openings 524 in patterned hard mask layer 512 . That is, each pyramid shaped bottom electrode 540 has three sloped side walls meeting at an upwardly pointed tip 532 . In one embodiment, the three sloped sidewalls of each pyramid shaped bottom electrode 540 are triangular or generally triangular and concave or generally concave, due to the etch process that form the pyramid shapes.
- Using a hexagonal array as shown in FIGS. 8A-8C may allow for a more dense packing of the resulting bitcells, e.g., by reducing the array area for a particular number of bitcells by a factor of ( ⁇ 3)/2 (i.e., about 13%), as compared with a rectangular “n ⁇ m” array.
- each bottom electrode 540 may provide a substantially reduced effective filament formation area A FF , as compared with conventional bottom electrode structures.
Abstract
Description
- The present disclosure relates to resistive memory cells, e.g., conductive bridging random access memory (CBRAM) or resistive random-access memory (ReRAM) cells, having a sloped bottom electrode.
- Resistive memory cells, such as conductive bridging memory (CBRAM) and resistive RAM (ReRAM) cells are a new type of non-volatile memory cells that provide scaling and cost advantages over conventional Flash memory cells. A CBRAM is based on the physical re-location of ions within a solid electrolyte. A CBRAM memory cell can be made of two solid metal electrodes, one relatively inert (e.g., tungsten) the other electrochemically active (e.g., silver or copper), separated from each other by a thin layer or film of non-conducting material. The CBRAM cell generates programmable conducting filaments across the non-conducting film through the application of a bias voltage across the non-conducting film. The conducting filaments may be formed by single or very few nanometer-scale ions. The non-conducting film may be referred to as an electrolyte because it provides for the propagation of the conductive filament(s) across the film through an oxidation/reduction process much like in a battery. In a ReRAM cell, the conduction occurs through creation of a vacancy chain in an insulator. The generation of the conductive filament(s)/vacancy-chain(s) creates an on-state (high conduction between the electrodes), while the dissolution of the conductive filament(s)/vacancy-chain(s), e.g., by applying a similar polarity with Joule heating current or an opposite polarity but at smaller currents, reverts the electrolyte/insulator back to its nonconductive off-state. In this disclosure both the electrolyte film, layer, or region of a CBRAM cell and the insulator film, layer, or region of a ReRAM cell are referred to as an “electrolyte,” for the sake of simplicity.
- A wide range of materials have been demonstrated for possible use in resistive memory cells, both for the electrolyte and the electrodes. One example is the Cu/SiOx based cell in which the Cu is the active metal-source electrode and the SiOx is the electrolyte.
- One common problem facing resistive memory cells is the on-state retention, i.e., the ability of the conductive path (filament or vacancy chain) to be stable, especially at the elevated temperatures that the memory parts may typically be qualified to (e.g., 85 C/125 C).
-
FIG. 1 shows aconventional CBRAM cell 1A, having a top electrode 10 (e.g., copper) arranged over a bottom electrode 12 (e.g., tungsten), with the electrolyte or middle electrode 14 (e.g., SiO2) arranged between the top and bottom electrodes.Conductive filaments 18 propagate from thebottom electrode 12 to thetop electrode 10 through theelectrolyte 14 when a bias voltage is applied to thecell 1A. This structure has various potential limitations or drawbacks. For example, the effective cross-sectional area for filament formation, which may be referred to as the “confinement zone” or the “filament formation area” indicated as AFF, is relatively large and unconfined, making the filament formation area susceptible to extrinsic defects. Also, multi-filament root formation may be likely, due to a relatively large area, which may lead to weaker (less robust) filaments. In general, the larger the ratio between the diameter or width of the filament formation area AFF (indicated by “x”) to the filament propagation distance from thebottom electrode 12 to the top electrode 10 (in this case, the thickness of theelectrolyte 14, indicated by “y”), the greater the chance of multi-root filament formation. Further, a large electrolyte area surrounds the filament, which provides diffusion paths for the filament and thus may provide poor retention. Thus, restricting the volume of the electrolyte material in which the conductive path forms may provide a more robust filament due to spatial confinement. The volume of the electrolyte material in which the conductive path forms may be restricted by reducing the area in contact between thebottom electrode 12 and theelectrolyte 14. - As used herein, “conductive path” refers a conductive filament (e.g., in a CBRAM cell), vacancy chain (e.g., in an oxygen vacancy based ReRAM cell), or any other type of conductive path for connecting the electrodes of a non-volatile memory cell, typically through an electrolyte layer or region arranged between the electrodes. As used herein the “electrolyte layer” or ““electrolyte region” refers to an electrolyte/insulator/memory layer or region between the bottom and top electrodes through which the conductive path propagates.
-
FIG. 2 shows certain principles of a CBRAM cell formation.Conductive paths 18 may form and grow laterally, or branch into multiple parallel paths. Further, locations of the conductive paths may change with each program/erase cycle. This may contribute to a marginal switching performance, variability, high-temp retention issues, and/or switching endurance. Restricting switching volume has shown to benefit the operation. These principles apply to ReRAM and CBRAM cells. A key obstacle for adoption of these technologies is switching uniformity. -
FIGS. 3A and 3B show a schematic view and an electron microscope image of an example knownbottom electrode configuration 1B for a CBRAM cell (e.g., having a 1T1R architecture). In this example, thebottom electrode 12 is a cylindrical via, e.g., a tungsten-filled via with a Ti/TiN liner. A top contact and/oranode 20 may be connected to thetop electrode 10 as shown. Thebottom electrode 12 may provide a relatively large filament formation area AFF of about 30,000 nm2, for example, which may lead to one or more of the problems or disadvantages discussed above. - Some embodiments provide resistive memory cells, e.g., CBRAM or ReRAM cells, and methods of forming such resistive memory cells, having a bottom electrode formed with one or more sloped surfaces that define an upwardly-pointed tip, which may be a point, edge, or surface, depending on the embodiment. The bottom electrode may have any shape that defines an upwardly-pointed tip. For example, the bottom electrode may have an elongated prism shape with a triangular cross-section that extends across one or multiple bottom electrode connections, or a concave bowl shape defining an upwardly-pointed ring-shaped tip edge, or an upwardly-pointed pyramid shape.
- When a voltage bias is applied to such resistive memory cell, the upwardly-pointing tip of the bottom electrode may focus the electric field more precisely than in known cells, which may provide more consistent filament formation, thus improving the consistency of programming voltage and cell predictability, e.g., as compared with certain conventional designs.
- According to one embodiment, a method of forming a resistive memory cell comprises forming a plurality of bottom electrode connections; depositing a bottom electrode layer over the bottom electrode connections; performing a first etch to remove portions of the bottom electrode layer such that the remaining bottom electrode layer defines at least one sloped surface; forming an oxidation layer on each sloped surface of the remaining bottom electrode layer; performing a second etch on the remaining bottom electrode layer and oxidation layer on each sloped surface to define at least one upwardly-pointing bottom electrode region above each bottom electrode connection, each upwardly-pointing bottom electrode region defining a bottom electrode tip; and forming an electrolyte region and a top electrode over each bottom electrode tip such that the electrolyte region is arranged between the top electrode and the respective bottom electrode top.
- According to another embodiment, a resistive memory cell comprises a plurality of bottom electrode connections; at least one bottom electrode region formed over and conductively coupled to the bottom electrode connections, each bottom electrode region having at least one sloped sidewall and defining an upwardly-pointing tip; an electrolyte region and a top electrode over each bottom electrode tip such that the electrolyte region is arranged between the top electrode and the respective bottom electrode top; and a top electrode connection conductively coupled to each top electrode.
- According to another embodiment, a method of forming a resistive memory cell comprises forming a plurality of bottom electrode connections; depositing a bottom electrode layer over the bottom electrode connections; performing an etch to remove portions of the bottom electrode layer to form at least one upwardly-pointing bottom electrode region above the bottom electrode connections, each upwardly-pointing bottom electrode region defining a bottom electrode tip; and forming an electrolyte region and a top electrode over each bottom electrode tip such that the electrolyte region is arranged between the top electrode and the respective bottom electrode top.
- According to another embodiment, a resistive memory cell comprises a plurality of bottom electrode connections; at least one bottom electrode region formed over and conductively coupled to the bottom electrode connections, each bottom electrode region having at least two sloped sidewalls and defining an upwardly-pointing tip; an electrolyte region and a top electrode over each bottom electrode tip such that the electrolyte region is arranged between the top electrode and the respective bottom electrode top; and a top electrode connection conductively coupled to each top electrode.
- Example embodiments are discussed below with reference to the drawings, in which:
-
FIG. 1 shows an example conventional CBRAM cell; -
FIG. 2 shows certain principles of CBRAM cell formation; -
FIGS. 3A and 3B show a schematic view and an electron microscope image of an example known CBRAM cell configuration; - FIGS. 4A1-4N2 illustrate an example method for forming a resistive memory cell structure, e.g., a CBRAM or ReRAM cell structure, including bottom electrodes having a sloped surface defining a pointed upper-edge, according to one embodiment of the present invention;
- FIGS. 5A1-5N2 illustrate an another example method for forming a resistive memory cell structure, e.g., a CBRAM or ReRAM cell structure, including sloped ring-shaped bottom electrodes defining a ring-shaped pointed upper-edge, according to one embodiment of the present invention;
- FIGS. 6A1-6L2 illustrate an another example method for forming a resistive memory cell structure, e.g., a CBRAM or ReRAM cell structure, including bottom electrodes having a pair of sloped side walls defining a pointed upper-edge, according to one embodiment of the present invention;
- FIGS. 7A1-7K2 illustrate an another example method for forming a resistive memory cell structure, e.g., a CBRAM or ReRAM cell structure, including pyramid shaped bottom electrodes having four sloped sides meeting at an upwardly pointed tip, according to one embodiment of the present invention; and
-
FIGS. 8A-8C illustrate an another example method for forming a resistive memory cell structure, e.g., a CBRAM or ReRAM cell structure, including pyramid shaped bottom electrodes having three sloped sides meeting at an upwardly pointed tip, according to one embodiment of the present invention. - As discussed above, embodiments of the present invention may provide resistive memory cells, e.g., CBRAM or ReRAM cells, and methods of forming such resistive memory cells, having a bottom electrode formed with one or more sloped surfaces that define an upwardly-pointed tip, e.g., a triangular shaped bottom electrode, a concave bowl-shaped bottom electrode with a ring-shaped tip edge, or a pyramid shaped bottom electrode. In operation, the upwardly-pointed tip of the bottom electrode may focus the electric field and provide a reduced filament formation area AFF, which may provide more consistent filament formation, thus improving the consistency of programming voltage and cell predictability, e.g., as compared with certain conventional designs.
- FIGS. 4A1-4N2 illustrate an example method for forming a resistive memory cell structure, e.g., a CBRAM or ReRAM cell structure, including bottom electrodes having a sloped surface defining a pointed upper-edge, according to one embodiment of the present invention.
- As shown in FIG. 4A1 (cross-sectional side view) and FIG. 4A2 (top view), an array of
bottom electrode connectors 102 are formed in asubstrate 100.Bottom electrode connectors 102 andsubstrate 100 may be formed in any suitable manner (e.g., using conventional semiconductor fabrication techniques) and from any suitable materials. For example,substrate 100 may be formed from an insulator, e.g., SiO2, and eachbottom electrode connector 102 may have aconductor region 104 formed from copper (Cu) or other conductive material, and aconnection region 106 formed from tungsten (W) or other suitable material. In this example, eachbottom electrode connector 102 is formed with a circular via-type shape. However, eachbottom electrode connector 102 may be formed with any other suitable shape, e.g., an elongated line or elongated rectangular shape, a square shape, etc. - Next, as shown in FIG. 4B1 (cross-sectional side view) and FIG. 4B2 (top view), a bottom electrode (or cathode)
layer 110 and ahard mask 112 are deposited or formed over thesubstrate 100 andbottom electrode connectors 102.Bottom electrode layer 110 may comprise any suitable conductive material or materials, e.g., polysilicon, doped polysilicon, amorphous silicon, doped amorphous silicon, or any other suitable material, and may be deposited or formed in any suitable manner.Hard mask layer 112 may be formed from any suitable materials (e.g., SiN, SiON, or other dielectric material) and may be deposited or formed in any suitable manner as known in the art. - Next, as shown in FIG. 4C1 (cross-sectional side view) and FIG. 4C2 (top view), the
hard mask 112 is patterned, e.g., by forming and patterning aphotoresist layer 116 over thehard mask 112, using any suitable photolithography techniques. As shown, thephotoresist layer 116 is patterned withopenings 118 that expose particular areas of the underlyinghard mask 112. In this embodiment,openings 118 are formed as elongated trenches extending between or alongside rows of underlyingbottom electrode connectors 102, as shown in FIG. 4C2. However,openings 118 may alternatively be formed with any other shape, e.g., circular via-type openings, and/or may correspond with underlyingbottom electrode connectors 102 in a one-to-one manner (as opposed to the illustrated one-to-multiple arrangement). Also, in the illustrated embodiment, theopenings 118 are located such that each underlyingbottom electrode connector 102 has a single corresponding opening wall 120 overlying thatbottom electrode connector 102, wherein the single corresponding opening wall 120 forbottom electrode connector 102 provides the basis for a single sloped bottom electrode sidewall formed over thatbottom electrode connector 102 according to the following process steps. In particular, openingwall 120A overliesbottom electrode connector 102A, openingwall 120B overliesbottom electrode connector 102B, and openingwall 120C overliesbottom electrode connector 102C. In other embodiments, theopenings 118 are shaped and/or located such that multiple opening walls 120 overly eachbottom electrode connector 102, e.g., such that multiple sloped bottom electrode sidewalls may be formed over eachbottom electrode connector 102. - Next, as shown in FIG. 4D1 (cross-sectional side view) and FIG. 4D2 (top view), etch and strip/removal processes are performed to transfer the photoresist pattern into the
hard mask 112 and remove the remaining photoresist, thereby forming a patternedhard mask 112 having an array ofopenings 124. - Next,
bottom electrode layer 110 may be etched through theopenings 124 in the patternedhard mask 112 using any suitable isotropic etch process. FIGS. 4E1-4G2 illustrate a progression of the etch process, in particular showing “snapshots” of the structure at three different points in time along the progression of the etch. Thus, FIGS. 4E1 and 4E2 show a snapshot at a first instant in time during the etch; FIGS. 4F1 and 4F2 show a snapshot at a second instant in time during the etch; and FIGS. 4G1 and 4G2 show a snapshot at or after completion of the etch. As shown in these figures, the etch process may continue to remove material frombottom electrode layer 110 until the remaining portions of thebottom electrode layer 110 define a slopedsidewall surface 130 above eachbottom electrode connector 102. In some embodiments, the etch process may separatebottom electrode layer 110 into discrete bottom electrode layer regions, e.g.,regions - Next, as shown in FIG. 4H1 (cross-sectional side view) and FIG. 4H2 (top view), the exposed sloped sidewall surfaces 130 of bottom
electrode layer regions layer 134 on eachsloped region 130. - Next, as shown in
FIG. 411 (cross-sectional side view) andFIG. 412 (top view), thehard mask 112 is removed using any suitable process, e.g., by etching or stripping. - Next, as shown in FIG. 4J1 (cross-sectional side view) and FIG. 4J2 (top view), the bottom
electrode layer regions oxidized layers 134 are removed, thereby forming discretebottom electrodes 140, each having an upwardly-pointing region defining a slopedside wall surface 142 and atip 144. The etch and oxide removal process may be performed in two steps, e.g., using a highly selective etch that preserves the oxide layers 134 and then gently removing the oxide layers 134 in a subsequent step, or alternatively may be performed in a single step, e.g., using a slightly higher oxide etch rate that removes the oxide layers 134 along with portions of the bottom electrode layer material. - Next, as shown in FIG. 4K1 (cross-sectional side view) and FIG. 4K2 (top view), an insulator or
electrolyte layer 150 and a top electrode (anode)layer 152 are formed over the stack, and in particular, over eachbottom electrode 140.Electrolyte layer 150 may comprise any suitable dielectric or memristive type material or materials, for example, SiOx (e.g., SiO2), GeS, CuS, TaOx, TiO2, Ge2Sb2Te5, GdO, HfO, CuO, Al2O3, or any other suitable material.Top electrode layer 152 may comprise any suitable conductive material or materials, e.g., Ag, Al, Cu, Ta, TaN, Ti, TiN, Al, W or any other suitable material, and may be deposited or formed in any suitable manner. - Next, as shown in FIG. 4L1 (cross-sectional side view) and FIG. 4L2 (top view), the
electrolyte layer 150 andtop electrode layer 152 are patterned by forming and patterning aphotoresist layer 160 over thetop electrode layer 152, using any suitable photolithography techniques. As shown, thephotoresist layer 160 is patterned withopenings 162 that expose particular areas of thetop electrode layer 152. In this embodiment,openings 162 are formed as elongated trenches between adjacent rows ofbottom electrodes 140, as shown in FIG. 4L2. However,photoresist layer 160 may be patterned in any other suitable manner. For example,photoresist layer 160 may be patterned such that a discrete photoresist region remains over each bottom electrode 140 (rather than spanning multiplebottom electrodes 140 as shown in FIG. 4L2). - Next, as shown in FIG. 4M1 (cross-sectional side view) and FIG. 4M2 (top view), etch and strip/removal processes are performed to transfer the photoresist pattern into the
electrolyte layer 150 andtop electrode layer 152 and remove the remaining photoresist, thereby dividing theelectrolyte layer 150 andtop electrode layer 152 intodiscrete electrolyte regions 170 and correspondingtop electrodes 172. As shown in FIG. 4M2, eachelectrolyte region 170/top electrode 172 forms a row spanning multiplebottom electrodes 140. - Next, as shown in FIG. 4N1 (cross-sectional side view) and FIG. 4N2 (top view),
top electrode interconnects 180 may be formed in aninsulator material 182 deposited over the stack, using any suitable techniques. Theinsulator material 182 may comprise any suitable insulator (e.g., SiO2), which may or may not be the same material assubstrate 100. Top electrode interconnects 180 may be formed from any suitable conductor (e.g., Cu), and may be formed at any suitable locations relative totop electrodes 172. In the illustrated example, as shown in FIG. 4N2, atop electrode interconnect 180 is formed over each elongatedtop electrode 172 at the end of each column (i.e., the connection may be periodic rather than over each bitcell). - In this manner, an array of resistive memory cells is formed, in which the
bottom electrode 140 has an upwardly-pointing region defining asloped side wall 142 and apointed tip 144. In operation, conductive filament propagation from each respectivebottom electrode 140 is substantially confined to thepointed tip 144, as the electric field naturally concentrates at the point, edge, or surface having the smallest radius of curvature. Thus, the sharper the point oftip 144, the greater the concentration of the filament-generating electric field, and thus the smaller the effective filament formation area AFF. Thus, the pointed tip shapedbottom electrode 140 may provide a substantially reduced effective filament formation area AFF, as compared with conventional bottom electrode structures. - FIGS. 5A1-5N2 illustrate an example method for forming a resistive memory cell structure, e.g., a CBRAM or ReRAM cell structure, including sloped ring-shaped bottom electrodes defining a ring-shaped pointed upper-edge, according to one embodiment of the present invention.
- As shown in FIG. 5A1 (cross-sectional side view) and FIG. 5A2 (top view), an array of
bottom electrode connectors 202 are formed in asubstrate 200.Bottom electrode connectors 202 andsubstrate 200 may be formed in any suitable manner (e.g., using conventional semiconductor fabrication techniques) and from any suitable materials. For example,substrate 200 may be formed from an insulator, e.g., SiO2, and eachbottom electrode connector 202 may have aconductor region 204 formed from copper (Cu) or other conductive material, and aconnection region 206 formed from tungsten (W) or other suitable material. In this example, eachbottom electrode connector 202 is formed with a circular via-type shape. However, eachbottom electrode connector 202 may be formed with any other suitable shape, e.g., an elongated line or elongated rectangular shape, a square shape, etc. - Next, as shown in FIG. 5B1 (cross-sectional side view) and FIG. 5B2 (top view), a bottom electrode (or cathode)
layer 210 and ahard mask 212 are deposited or formed over thesubstrate 200 andbottom electrode connectors 202.Bottom electrode layer 210 may comprise any suitable conductive material or materials, e.g., polysilicon, doped polysilicon, amorphous silicon, doped amorphous silicon, or any other suitable material, and may be deposited or formed in any suitable manner.Hard mask layer 212 may be formed from any suitable materials (e.g., SiN, SiON, or other dielectric material) and may be deposited or formed in any suitable manner as known in the art. - Next, as shown in FIG. 5C1 (cross-sectional side view) and FIG. 5C2 (top view), the
hard mask 212 is patterned, e.g., by forming and patterning aphotoresist layer 216 over thehard mask 212, using any suitable photolithography techniques. As shown, thephotoresist layer 216 is patterned withopenings 218 that expose particular areas of the underlyinghard mask 212. In this embodiment,openings 218 are formed as circular openings over eachbottom electrode connector 202, with the perimeter of eachcircular opening 218 being smaller than and aligned concentrically within the perimeter of the respectivebottom electrode connector 202, as shown in FIG. 5C2. In other embodiments,circular openings 218 may align in an overlapping manner with respect to their respectivebottom electrode connectors 202, as viewed from the top view. - Next, as shown in FIG. 5D1 (cross-sectional side view) and FIG. 5D2 (top view), an etch is performed to transfer the photoresist pattern into the
hard mask 212, thereby forming a patternedhard mask 212 having an array ofopenings 224. Then, as shown in FIG. 5E1 (cross-sectional side view) and FIG. 5E2 (top view), the remaining photoresist is removed, e.g., by stripping or other suitable process. - Next,
bottom electrode layer 210 may be etched through theopenings 224 in the patternedhard mask 212 using any suitable isotropic etch process. FIGS. 5F1 and 5F2 illustrate a snapshot of the structure at an instant during the etch process, and FIGS. 5G1 and 5G2 show a snapshot at or after completion of the etch. As shown in these figures, the etch process may remove material frombottom electrode layer 210 until the remaining portions of thebottom electrode layer 210 define a concave, bowl-shaped structure having a sloped U-shaped (in the cross-sectional side view), ring-shaped (in the top view) sidewall 230 above eachbottom electrode connector 202. In some embodiments, the etch process may etch fully through thebottom electrode layer 210 and down to the bottomelectrode connection region 206 to expose a top surface area ofconnection region 206, e.g., at the bottom center of the etched area. In other embodiments, the etch process may not extend fully through thebottom electrode layer 210, such that a portion of thebottom electrode material 210 remains over the top surface ofconnection region 206, even at the bottom center of the etched area. - Next, as shown in FIG. 5H1 (cross-sectional side view) and FIG. 5H2 (top view), the exposed sloped U-shaped (side view), ring-shaped (top view) sidewalls 230 defined in
bottom electrode layer 210 are oxidized using any suitable process, to form an oxidizedlayer 234 on eachsloped region 230. - Next, as shown in
FIG. 511 (cross-sectional side view) andFIG. 512 (top view),hard mask 212 is removed using any suitable process, e.g., by etching or stripping. - Next, as shown in FIG. 5J1 (cross-sectional side view) and FIG. 5J2 (top view), the remaining
bottom electrode layer 210 is etched utilizing the oxidized regions as a hardmask to block the etching of bottom electrode underneath. And theoxidized layers 234 are removed, thereby forming a discretebottom electrode 240 over eachbottom electrode connection 206. As shown, eachbottom electrode 240 comprises a concave, bowl-shaped structure having a sloped U-shaped (cross-sectional side view), ring-shaped (in the top view) sidewall surface 242 and an upwardly-pointed ring-shapedtip 244. The etch and oxide removal process may be performed in two steps, e.g., using a highly selective etch that preserves the oxide layers 234 and then gently removing the oxide layers 234 in a subsequent step, or alternatively may be performed in a single step, e.g., using a slightly higher oxide etch rate that removes the oxide layers 234 along with portions of the bottom electrode layer material. - In some embodiments, each
bottom electrode 240 may have an central opening that exposes a top surface area of theunderlying connection region 206. In other embodiments, a portion of thebottom electrode material 210 remains over the top surface ofconnection region 206, even at the bottom center of the bowl-shaped structure, such that the top surface of theunderlying connection region 206 is not exposed through the center of thebottom electrode 240. - Next, as shown in FIG. 5K1 (cross-sectional side view) and FIG. 5K2 (top view), an insulator or
electrolyte layer 250 and a top electrode (anode)layer 252 are formed over the stack, and in particular, over eachbottom electrode 240.Electrolyte layer 250 may comprise any suitable dielectric or memristive type material or materials, for example, SiOx (e.g., SiO2), GeS, CuS, TaOx, TiO2, Ge2Sb2Te5, GdO, HfO, CuO, Al2O3, or any other suitable material.Top electrode layer 252 may comprise any suitable conductive material or materials, e.g., Ag, Al, Cu, Ta, TaN, Ti, TiN, Al, W or any other suitable material, and may be deposited or formed in any suitable manner. - Next, the
electrolyte layer 250 andtop electrode layer 252 are patterned and etched to divide theelectrolyte layer 250 andtop electrode layer 252 intodiscrete electrolyte 270/top electrode 272 regions, each covering one or multiplebottom electrodes 202. In the example shown in FIG. 5L1 (cross-sectional side view) and FIG. 5L2 (top view), theelectrolyte layer 250 andtop electrode layer 252 are patterned and etched to form adiscrete electrolyte 270/top electrode 272 region over eachindividual bottom electrode 202. (In an alternative embodiment shown in FIGS. 5N1 and 5N2 (discussed below), theelectrolyte layer 250 andtop electrode layer 252 are patterned and etched to formelongated electrolyte 270/top electrode 272 regions, each spanning a row of multiplebottom electrodes 202.) - Next, as shown in FIG. 5M1 (cross-sectional side view) and FIG. 5M2 (top view),
top electrode interconnects 280 may be formed in aninsulator material 282 deposited over the stack, using any suitable techniques. Theinsulator material 282 may comprise any suitable insulator (e.g., SiO2), which may or may not be the same material assubstrate 200. Top electrode interconnects 280 may be formed from any suitable conductor (e.g., Cu), and may be formed at any suitable locations relative totop electrodes 272. In this example embodiment, as shown in FIG. 5M2, a discretetop electrode interconnect 280 is formed over eachtop electrode 272. - FIG. 5N1 (cross-sectional side view) and FIG. 5N2 (top view) illustrate an alternative embodiment in which the
electrolyte layer 250 andtop electrode layer 252 are formed aselongated electrolyte 270/top electrode 272 regions, each spanning a row of multiplebottom electrodes 202. Atop electrode interconnect 280 is formed over and connected to each elongatedtop electrode 272, at the end of each column (i.e., the connection may be periodic rather than over each bitcell), as shown in FIG. 5N2. - In the manner shown in FIGS. 5A1-5N2, an array of resistive memory cells is formed, in which each
bottom electrode 240 has a concave bowl-shaped structure defining an upwardly-pointed ring-shapedtip 244. In operation, conductive filament propagation from each respectivebottom electrode 240 is substantially confined to the ring-shapedpointed tip 244, as the electric field naturally concentrates at the point, edge, or surface having the smallest radius of curvature. Thus, the sharper the point of ring-shapedtip 244, the greater the concentration of the filament-generating electric field, and thus the smaller the effective filament formation area AFF. Thus, the ring-shaped pointed tip of eachbottom electrode 240 may provide a substantially reduced effective filament formation area AFF, as compared with conventional bottom electrode structures. - FIGS. 6A1-6L2 illustrate an example method for forming a resistive memory cell structure, e.g., a CBRAM or ReRAM cell structure, including bottom electrodes having a pair of sloped side walls defining a pointed upper-edge, according to one embodiment of the present invention.
- As shown in FIG. 6A1 (cross-sectional side view) and FIG. 6A2 (top view), an array of
bottom electrode connectors 302 are formed in asubstrate 300.Bottom electrode connectors 302 andsubstrate 300 may be formed in any suitable manner (e.g., using conventional semiconductor fabrication techniques) and from any suitable materials. For example,substrate 300 may be formed from an insulator, e.g., SiO2, and eachbottom electrode connector 302 may have aconductor region 304 formed from copper (Cu) or other conductive material, and aconnection region 306 formed from tungsten (W) or other suitable material. In this example, eachbottom electrode connector 302 is formed with a circular via-type shape. However, eachbottom electrode connector 302 may be formed with any other suitable shape, e.g., an elongated line or elongated rectangular shape, a square shape, etc. - Next, as shown in FIG. 6B1 (cross-sectional side view) and FIG. 6B2 (top view), a bottom electrode (or cathode)
layer 310 and ahard mask 312 are deposited or formed over thesubstrate 300 andbottom electrode connectors 302.Bottom electrode layer 310 may comprise any suitable conductive material or materials, e.g., polysilicon, doped polysilicon, amorphous silicon, doped amorphous silicon, or any other suitable material, and may be deposited or formed in any suitable manner.Hard mask layer 312 may be formed from any suitable materials (e.g., SiN, SiON, or other dielectric material) and may be deposited or formed in any suitable manner as known in the art. - Next, as shown in FIG. 6C1 (cross-sectional side view) and FIG. 6C2 (top view), the
hard mask 312 is patterned, e.g., by forming and patterning aphotoresist layer 316 over thehard mask 312, using any suitable photolithography techniques. As shown, thephotoresist layer 316 is patterned withopenings 318 that expose particular areas of the underlyinghard mask 312. In this embodiment,openings 318 are formed as elongated trenches extending between adjacent rows of underlyingbottom electrode connectors 302, as shown in FIG. 6C2. However,openings 318 may alternatively be formed with any other shape, e.g., circular via-type openings, and/or may correspond with underlyingbottom electrode connectors 302 in a one-to-one manner (as opposed to the illustrated one-to-multiple arrangement). - Next, as shown in FIG. 6D1 (cross-sectional side view) and FIG. 6D2 (top view), etch and strip/removal processes are performed to transfer the photoresist pattern into the
hard mask 312 and remove the remaining photoresist, thereby forming a patternedhard mask 312 having an array ofopenings 324. - Next,
bottom electrode layer 310 may be etched through theopenings 324 in the patternedhard mask 312 using any suitable isotropic etch process. FIGS. 6E1-6G2 illustrate a progression of the etch process, in particular showing “snapshots” of the structure at three different points in time along the progression of the etch. Thus, FIGS. 6E1 and 6E2 show a snapshot at a first instant in time during the etch; FIGS. 6F1 and 6F2 show a snapshot at a second instant in time during the etch; and FIGS. 6G1 and 6G2 show a snapshot at or after completion of the etch. As shown in these figures, the etch process may remove material frombottom electrode layer 310 until the remaining portions of thebottom electrode layer 310 define elongatedbottom electrode regions bottom electrode connectors 302, eachbottom electrode region sidewalls 330 meeting at an upwardly-pointing edge tip 332, thus defining a triangular cross-sectional shape. As used herein, triangular means three sided, wherein each side may be linear or may be non-linear (e.g., curved, irregular, or otherwise non-linear). - Next, as shown in FIG. 6H1 (cross-sectional side view) and FIG. 6H2 (top view), the
hard mask 312 is removed using any suitable process, e.g., by etching or stripping, leaving a series of bottom electrodes 340 (corresponding tobottom electrode regions - Next, as shown in
FIG. 611 (cross-sectional side view) andFIG. 612 (top view), an insulator orelectrolyte layer 350 and a top electrode (anode)layer 352 are formed over the stack, and in particular, over eachbottom electrode 340.Electrolyte layer 350 may comprise any suitable dielectric or memristive type material or materials, for example, SiOx (e.g., SiO2), GeS, CuS, TaOx, TiO2, Ge2Sb2Te5, GdO, HfO, CuO, Al2O3, or any other suitable material.Top electrode layer 352 may comprise any suitable conductive material or materials, e.g., Ag, Al, Cu, Ta, TaN, Ti, TiN, Al, W or any other suitable material, and may be deposited or formed in any suitable manner. - Next, as shown in FIG. 6J1 (cross-sectional side view) and FIG. 6J2 (top view), the
electrolyte layer 350 andtop electrode layer 352 are patterned by forming and patterning aphotoresist layer 360 over thetop electrode layer 352, using any suitable photolithography techniques. As shown, thephotoresist layer 360 is patterned withopenings 362 that expose particular areas of thetop electrode layer 352. In this embodiment,openings 362 are formed as elongated trenches between adjacent rows ofbottom electrodes 340, as shown in FIG. 6J2. However,photoresist layer 360 may be patterned in any other suitable manner. For example,photoresist layer 360 may be patterned such that a discrete photoresist region remains over each bottom electrode 340 (rather than spanning multiplebottom electrodes 340 as shown in FIG. 6J2). - Next, as shown in FIG. 6K1 (cross-sectional side view) and FIG. 6K2 (top view), etch and strip/removal processes are performed to transfer the photoresist pattern into the
electrolyte layer 350 andtop electrode layer 352 and remove the remaining photoresist, thereby dividing theelectrolyte layer 350 andtop electrode layer 352 intodiscrete electrolyte regions 370 and correspondingtop electrodes 372. As shown in FIG. 6K2, eachelectrolyte region 370/top electrode 372 forms a row spanning multiplebottom electrodes 340. - Next, as shown in FIG. 6L1 (cross-sectional side view) and FIG. 6L2 (top view),
top electrode interconnects 380 may be formed in aninsulator material 382 deposited over the stack, using any suitable techniques. Theinsulator material 382 may comprise any suitable insulator (e.g., SiO2), which may or may not be the same material assubstrate 300. Top electrode interconnects 380 may be formed from any suitable conductor (e.g., Cu), and may be formed at any suitable locations relative totop electrodes 372. In the illustrated example, as shown in FIG. 6L2, atop electrode interconnect 380 is formed over each elongatedtop electrode 372 at the end of each column (i.e., the connection may be periodic rather than over each bitcell). - In this manner, an array of resistive memory cells is formed, in which each
bottom electrode 340 has an upwardly-pointing triangular cross-section defining a pair of slopedside walls 330 meeting at apointed tip 332. In operation, conductive filament propagation from each respectivebottom electrode 340 is substantially confined to thepointed tip 332, as the electric field naturally concentrates at the point, edge, or surface having the smallest radius of curvature. Thus, the sharper the point oftip 332, the greater the concentration of the filament-generating electric field, and thus the smaller the effective filament formation area AFF. Thus, the generally triangular, pointed tip shapedbottom electrode 340 may provide a substantially reduced effective filament formation area AFF, as compared with conventional bottom electrode structures. - FIGS. 7A1-7K2 illustrate an example method for forming a resistive memory cell structure, e.g., a CBRAM or ReRAM cell structure, including pyramid shaped bottom electrodes having four sloped sides meeting at an upwardly pointed tip, according to one embodiment of the present invention.
- As shown in FIG. 7A1 (cross-sectional side view) and FIG. 7A2 (top view), an array of
bottom electrode connectors 402 are formed in asubstrate 400.Bottom electrode connectors 402 andsubstrate 400 may be formed in any suitable manner (e.g., using conventional semiconductor fabrication techniques) and from any suitable materials. For example,substrate 400 may be formed from an insulator, e.g., SiO2, and eachbottom electrode connector 402 may have aconductor region 404 formed from copper (Cu) or other conductive material, and aconnection region 406 formed from tungsten (W) or other suitable material. In this example, eachbottom electrode connector 402 is formed with a circular via-type shape. However, eachbottom electrode connector 402 may be formed with any other suitable shape, e.g., an elongated line or elongated rectangular shape, a square shape, etc. - Next, as shown in FIG. 7B1 (cross-sectional side view) and FIG. 7B2 (top view), a bottom electrode (or cathode)
layer 410 is deposited or formed over thesubstrate 400 andbottom electrode connectors 402.Bottom electrode layer 410 may comprise any suitable conductive material or materials, e.g., polysilicon, doped polysilicon, amorphous silicon, doped amorphous silicon, or any other suitable material, and may be deposited or formed in any suitable manner. - Next, as shown in FIG. 7C1 (cross-sectional side view) and FIG. 7C2 (top view), a patterned
hard mask layer 412 is formed over thebottom electrode layer 410.Hard mask layer 412 may be formed from any suitable materials (e.g., SiN, SiON, or other dielectric material), and patterned in any suitable manner known in the art. For example,hard mask layer 412 may be patterned using a photoresist layer and suitable patterning and etch process. In the illustrated embodiment,hard mask layer 412 is patterned with a two-dimensional array ofcircular openings 424 located in the areas between (i.e., not overlying) the underlying bottomelectrode connection regions 406. However, it should be understood that in other embodiments,openings 424 may alternatively be formed with any other shape, e.g., elongated trench-type openings, and/or may be partially or fully located above underlying bottomelectrode connection regions 406. - Next,
bottom electrode layer 410 may be etched through theopenings 424 in the patternedhard mask 412 using any suitable etch process. - FIGS. 7D1-7F2 illustrate a progression of the etch process, in particular showing “snapshots” of the structure at three different points in time along the progression of the etch. Thus,
FIGS. 7D 1 and 7D2 show a snapshot at a first instant in time during the etch; FIGS. 7E1 and 7E2 show a snapshot at a second instant in time during the etch; andFIGS. 7F 1 and 7F2 show a snapshot at or after completion of the etch. As shown in these figures, the etch process may remove material frombottom electrode layer 410 until the remaining portions of thebottom electrode layer 410 define a two-dimensional array of pyramid shapedbottom electrodes 440, each located above a respectivebottom electrode connector 402. Each pyramid shapedbottom electrode 440 has four slopedsidewalls 430 meeting at an upwardly-pointing tip 432. - As used herein, pyramid means a three-dimensional shape having three or more triangular or generally triangular outer sides that meet at a point or relatively small edge or surface, and a base having a trilateral, quadrilateral, or any other polygon shape. Each generally triangular outer side may be planar or non-planar (e.g., concave, convex, irregular, or otherwise non-planar).
- In one embodiment, the four sloped
sidewalls 430 of each pyramid shapedbottom electrode 440 are triangular or generally triangular and concave or generally concave, due to the etch process that form the pyramid shapes. - Next, as shown in FIG. 7G1 (cross-sectional side view) and FIG. 7G2 (top view), the
hard mask 412 is removed using any suitable process, e.g., by etching or stripping, leaving the two-dimensional array of pyramid-shapedbottom electrodes 440. - Thus, the patterning
hard mask layer 412 with the two-dimensional array of openings shown in FIGS. 7C1 and 7C2 provides for a two-dimensional array of pyramid-shaped bottom electrodes, one perbottom electrode connection 406, as opposed to patterning the hard mask with elongated trench openings that lead to elongated bottom electrodes, as disclosed in the example steps shown in FIGS. 6C1-6H2 discussed above. - Next, as shown in FIG. 7H1 (cross-sectional side view) and FIG. 7H2 (top view), an insulator or
electrolyte layer 450 and a top electrode (anode)layer 452 are formed over the stack, and in particular, over eachbottom electrode 440.Electrolyte layer 450 may comprise any suitable dielectric or memristive type material or materials, for example, SiOx (e.g., SiO2), GeS, CuS, TaOx, TiO2, Ge2Sb2Te5, GdO, HfO, CuO, Al2O3, or any other suitable material.Top electrode layer 452 may comprise any suitable conductive material or materials, e.g., Ag, Al, Cu, Ta, TaN, Ti, TiN, Al, W or any other suitable material, and may be deposited or formed in any suitable manner. - Next, as shown in
FIG. 711 (cross-sectional side view) andFIG. 712 (top view), theelectrolyte layer 450 andtop electrode layer 452 are patterned by forming and patterning aphotoresist layer 460 over thetop electrode layer 452, using any suitable photolithography techniques. As shown, thephotoresist layer 460 is patterned withopenings 462 that expose particular areas of thetop electrode layer 452. In this embodiment,openings 462 are formed as elongated trenches between adjacent rows ofbottom electrodes 440, as shown inFIG. 712 . However,photoresist layer 460 may be patterned in any other suitable manner. For example,photoresist layer 460 may be patterned such that a discrete photoresist region remains over each bottom electrode 440 (rather than spanning multiplebottom electrodes 440 as shown inFIG. 712 ). - Next, as shown in FIG. 7J1 (cross-sectional side view) and FIG. 7J2 (top view), etch and strip/removal processes are performed to transfer the photoresist pattern into the
electrolyte layer 450 andtop electrode layer 452 and remove the remaining photoresist, thereby dividing theelectrolyte layer 450 andtop electrode layer 452 intodiscrete electrolyte regions 470 and correspondingtop electrodes 472. As shown in FIG. 7J2, eachelectrolyte region 470/top electrode 472 forms a row spanning multiplebottom electrodes 440. - Next, as shown in FIG. 7K1 (cross-sectional side view) and FIG. 7K2 (top view),
top electrode interconnects 480 may be formed in aninsulator material 482 deposited over the stack, using any suitable techniques. Theinsulator material 482 may comprise any suitable insulator (e.g., SiO2), which may or may not be the same material assubstrate 400. Top electrode interconnects 480 may be formed from any suitable conductor (e.g., Cu), and may be formed at any suitable locations relative totop electrodes 472. In the illustrated example, as shown in FIG. 7K2, atop electrode interconnect 480 is formed over each elongatedtop electrode 472 at the end of each column (i.e., the connection may be periodic rather than over each bitcell). - In this manner, an array of resistive memory cells is formed, in which each
bottom electrode 440 has an upwardly-pointing pyramid shape have four slopedside walls 430 meeting at apointed tip 432. In operation, conductive filament propagation from each respectivebottom electrode 440 is substantially confined to thepointed pyramid tip 432, as the electric field naturally concentrates at the point, edge, or surface having the smallest radius of curvature. Thus, the sharper the point of thepyramid tip 432, the greater the concentration of the filament-generating electric field, and thus the smaller the effective filament formation area AFF. Thus, the generally triangular, pointed tip shapedbottom electrode 440 may provide a substantially reduced effective filament formation area AFF, as compared with conventional bottom electrode structures. -
FIGS. 8A-8C illustrate steps in an example method for forming a resistive memory cell structure, e.g., a CBRAM or ReRAM cell structure, including pyramid shaped bottom electrodes having three sloped sides meeting at an upwardly pointed tip, according to one embodiment of the present invention. -
FIG. 8A is a top view of a two-dimensional pattern ofbottom electrode connections 506 formed in aninsulator 500, e.g., analogous to the views shown in FIGS. 4A2, 5A2, 6A2, and 7A2. As shown,bottom electrode connections 506 are arranged in staggered rows that form a hexagonal pattern, as opposed to the aligned n rows by m columns patterns shown in FIGS. 4A2, 5A2, 6A2, and 7A2. -
FIG. 8B is a top view of a patternedhard mask layer 512 formed over abottom electrode layer 510 deposited over bottomelectrode connection regions 506, e.g., analogous to the views shown in FIGS. 4D2, 5E2, 6D2, and 7C2. As shown,mask layer 512 is patterned with a two-dimensional array ofcircular openings 524 located in the areas between (i.e., not overlying) the underlying bottomelectrode connection regions 506. - Finally,
FIG. 8C is a top view of a two-dimensional pattern ofbottom electrodes 540 formed by etching thebottom electrode layer 510 through the two-dimensional array ofcircular openings 524 shown inFIG. 8B , and then removing thehard mask 512, e.g., in a manner similar to the example embodiments discussed above. The extent of etching through eachhard mask openings 524 is shown inFIG. 8C by alarge circle 536. The portions of thebottom electrode layer 510 remaining after the etch process define an array of pyramid shapedbottom electrodes 540, e.g., similar to the pyramid shapedbottom electrodes 440 formed by the steps show inFIGS. 7B 1 to 7G2, described above. However, unlike the pyramid shapedbottom electrodes 440, pyramid shapedbottom electrode 540 shown inFIG. 8C have three sloped sides instead of four, due to the arrangement ofopenings 524 in patternedhard mask layer 512. That is, each pyramid shapedbottom electrode 540 has three sloped side walls meeting at an upwardly pointed tip 532. In one embodiment, the three sloped sidewalls of each pyramid shapedbottom electrode 540 are triangular or generally triangular and concave or generally concave, due to the etch process that form the pyramid shapes. - Using a hexagonal array as shown in
FIGS. 8A-8C may allow for a more dense packing of the resulting bitcells, e.g., by reducing the array area for a particular number of bitcells by a factor of (√3)/2 (i.e., about 13%), as compared with a rectangular “n×m” array. - As with the pointed bottom electrodes discussed above, conductive filament propagation from each
bottom electrode 540 is substantially confined to the pointed pyramid tip 532, as the electric field naturally concentrates at the point, edge, or surface having the smallest radius of curvature. Thus, the generally triangular, pointed tip shapedbottom electrode 540 may provide a substantially reduced effective filament formation area AFF, as compared with conventional bottom electrode structures. - Although the disclosed embodiments are described in detail in the present disclosure, it should be understood that various changes, substitutions and alterations can be made to the embodiments without departing from their spirit and scope.
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20160315257A1 (en) * | 2014-02-19 | 2016-10-27 | Microchip Technology Incorporated | Resistive Memory Cell Having A Reduced Conductive Path Area |
US9865813B2 (en) | 2014-02-19 | 2018-01-09 | Microchip Technology Incorporated | Method for forming resistive memory cell having a spacer region under an electrolyte region and a top electrode |
US9917251B2 (en) | 2014-02-19 | 2018-03-13 | Microchip Technology Incorporated | Resistive memory cell having a reduced conductive path area |
US10003021B2 (en) | 2014-02-19 | 2018-06-19 | Microchip Technology Incorporated | Resistive memory cell with sloped bottom electrode |
US10056545B2 (en) | 2013-03-13 | 2018-08-21 | Microchip Technology Incorporated | Sidewall-type memory cell |
US11043634B2 (en) * | 2019-04-09 | 2021-06-22 | International Business Machines Corporation | Confining filament at pillar center for memory devices |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR3050071B1 (en) * | 2016-04-08 | 2018-05-18 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | RESISTIVE MEMORY, ASSOCIATED MANUFACTURING AND PROGRAMMING METHODS |
US11737289B2 (en) | 2020-12-09 | 2023-08-22 | International Business Machines Corporation | High density ReRAM integration with interconnect |
US11411049B2 (en) | 2020-12-21 | 2022-08-09 | International Business Machines Corporation | Symmetric read operation resistive random-access memory cell with bipolar junction selector |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5687112A (en) * | 1996-04-19 | 1997-11-11 | Energy Conversion Devices, Inc. | Multibit single cell memory element having tapered contact |
US20040085833A1 (en) * | 2002-11-01 | 2004-05-06 | Young-Nam Hwang | Phase changeable memory devices and methods of forming the same in which an upper electrode includes a tip that extends toward a lower electrode |
US20060097238A1 (en) * | 2002-07-26 | 2006-05-11 | Laurent Breuil | Non-volatile memory element and production method thereof and storage memory arrangement |
US20060131618A1 (en) * | 2004-12-16 | 2006-06-22 | Ming-Hsiang Hsueh | Chalcogenide random access memory and method of fabricating the same |
US20130001501A1 (en) * | 2011-07-01 | 2013-01-03 | Micron Technology, Inc. | Memory cell structures |
Family Cites Families (48)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3030368B2 (en) | 1993-10-01 | 2000-04-10 | 株式会社半導体エネルギー研究所 | Semiconductor device and manufacturing method thereof |
US6147395A (en) | 1996-10-02 | 2000-11-14 | Micron Technology, Inc. | Method for fabricating a small area of contact between electrodes |
US5986931A (en) | 1997-01-02 | 1999-11-16 | Caywood; John M. | Low voltage single CMOS electrically erasable read-only memory |
US5790455A (en) | 1997-01-02 | 1998-08-04 | John Caywood | Low voltage single supply CMOS electrically erasable read-only memory |
US6031287A (en) | 1997-06-18 | 2000-02-29 | Micron Technology, Inc. | Contact structure and memory element incorporating the same |
US6300183B1 (en) | 1999-03-19 | 2001-10-09 | Microchip Technology Incorporated | Independently programmable memory segments within a PMOS electrically erasable programmable read only memory array achieved by N-well separation and method therefor |
US6943365B2 (en) | 1999-03-25 | 2005-09-13 | Ovonyx, Inc. | Electrically programmable memory element with reduced area of contact and method for making same |
KR100297734B1 (en) | 1999-07-07 | 2001-11-01 | 윤종용 | Trench isolation method of semiconductor integrated circuit |
US6567293B1 (en) | 2000-09-29 | 2003-05-20 | Ovonyx, Inc. | Single level metal memory cell using chalcogenide cladding |
US6670628B2 (en) | 2002-04-04 | 2003-12-30 | Hewlett-Packard Company, L.P. | Low heat loss and small contact area composite electrode for a phase change media memory device |
US6890833B2 (en) | 2003-03-26 | 2005-05-10 | Infineon Technologies Ag | Trench isolation employing a doped oxide trench fill |
US6914255B2 (en) | 2003-08-04 | 2005-07-05 | Ovonyx, Inc. | Phase change access device for memories |
US7279380B2 (en) * | 2004-11-10 | 2007-10-09 | Macronix International Co., Ltd. | Method of forming a chalcogenide memory cell having an ultrasmall cross-sectional area and a chalcogenide memory cell produced by the method |
US7374174B2 (en) * | 2004-12-22 | 2008-05-20 | Micron Technology, Inc. | Small electrode for resistance variable devices |
US7671356B2 (en) | 2005-11-03 | 2010-03-02 | Elpida Memory, Inc. | Electrically rewritable non-volatile memory element and method of manufacturing the same |
JP4061328B2 (en) | 2005-12-02 | 2008-03-19 | シャープ株式会社 | Variable resistance element and manufacturing method thereof |
JP4017650B2 (en) | 2005-12-02 | 2007-12-05 | シャープ株式会社 | Variable resistance element and manufacturing method thereof |
US20070267618A1 (en) | 2006-05-17 | 2007-11-22 | Shoaib Zaidi | Memory device |
US7466591B2 (en) | 2006-06-01 | 2008-12-16 | Microchip Technology Incorporated | Method for programming and erasing an array of NMOS EEPROM cells that minimizes bit disturbances and voltage withstand requirements for the memory array and supporting circuits |
US20080012079A1 (en) | 2006-07-17 | 2008-01-17 | Shoaib Zaidi | Memory cell having active region sized for low reset current and method of fabricating such memory cells |
US7981759B2 (en) | 2007-07-11 | 2011-07-19 | Paratek Microwave, Inc. | Local oxidation of silicon planarization for polysilicon layers under thin film structures |
TWI392087B (en) | 2007-07-26 | 2013-04-01 | Ind Tech Res Inst | Solid state electrolytes memory device and method of fabricating the same |
DE102007049786A1 (en) | 2007-10-17 | 2009-04-23 | Qimonda Ag | Integrated circuit has multiple resistance change memory cells, where each memory cell has top electrode, bottom electrode and resistance changing material provided between top electrode and bottom electrode |
KR100996172B1 (en) | 2008-07-24 | 2010-11-24 | 주식회사 하이닉스반도체 | Resistive memory device and method for manufacturing the same |
US8701887B2 (en) | 2008-07-31 | 2014-04-22 | Silgan Containers Llc | Stackable container |
US8063394B2 (en) | 2008-10-08 | 2011-11-22 | Qimonda Ag | Integrated circuit |
EP2202816B1 (en) | 2008-12-24 | 2012-06-20 | Imec | Method for manufacturing a resistive switching memory device |
TWI401796B (en) | 2008-12-30 | 2013-07-11 | Ind Tech Res Inst | Conductive bridging random access memory device and method of manufacturing the same |
US8431921B2 (en) * | 2009-01-13 | 2013-04-30 | Hewlett-Packard Development Company, L.P. | Memristor having a triangular shaped electrode |
TWI394231B (en) * | 2009-02-03 | 2013-04-21 | Nanya Technology Corp | Non-volatile memory cell and fabrication method thereof |
JP5446393B2 (en) * | 2009-04-02 | 2014-03-19 | ソニー株式会社 | Memory element, method of manufacturing the same, and semiconductor memory device |
US8084760B2 (en) | 2009-04-20 | 2011-12-27 | Macronix International Co., Ltd. | Ring-shaped electrode and manufacturing method for same |
KR101070291B1 (en) | 2009-12-18 | 2011-10-06 | 주식회사 하이닉스반도체 | Resistive memory device and method for manufacturing the same |
CN102130145B (en) | 2010-01-12 | 2013-07-17 | 中芯国际集成电路制造(上海)有限公司 | Phase change storage and manufacturing method thereof |
US8134139B2 (en) | 2010-01-25 | 2012-03-13 | Macronix International Co., Ltd. | Programmable metallization cell with ion buffer layer |
JP5079927B2 (en) | 2010-02-23 | 2012-11-21 | パナソニック株式会社 | Nonvolatile memory device manufacturing method, nonvolatile memory element, and nonvolatile memory device |
US8541765B2 (en) | 2010-05-25 | 2013-09-24 | Micron Technology, Inc. | Resistance variable memory cell structures and methods |
WO2012057772A1 (en) | 2010-10-29 | 2012-05-03 | Hewlett-Packard Development Company, L.P. | Memristive devices and memristors with ribbon-like junctions and methods for fabricating the same |
JP5270046B2 (en) | 2011-01-20 | 2013-08-21 | パナソニック株式会社 | Resistance change element and manufacturing method thereof |
US8816314B2 (en) | 2011-05-13 | 2014-08-26 | Adesto Technologies Corporation | Contact structure and method for variable impedance memory element |
KR101802434B1 (en) | 2011-05-17 | 2017-11-28 | 삼성전자주식회사 | Variable Resistance memory device and method of forming the same |
US8941089B2 (en) | 2012-02-22 | 2015-01-27 | Adesto Technologies Corporation | Resistive switching devices and methods of formation thereof |
US8946078B2 (en) | 2012-03-22 | 2015-02-03 | United Microelectronics Corp. | Method of forming trench in semiconductor substrate |
KR101911361B1 (en) | 2012-06-18 | 2019-01-04 | 삼성전자주식회사 | Non-volatile memory device having multi level cell and method of forming the same |
US9362496B2 (en) | 2013-03-13 | 2016-06-07 | Microchip Technology Incorporated | Resistive memory cell with trench-shaped bottom electrode |
US9444040B2 (en) | 2013-03-13 | 2016-09-13 | Microchip Technology Incorporated | Sidewall type memory cell |
US9385313B2 (en) | 2014-02-19 | 2016-07-05 | Microchip Technology Incorporated | Resistive memory cell having a reduced conductive path area |
US9318702B2 (en) | 2014-02-19 | 2016-04-19 | Microchip Technology Incorporated | Resistive memory cell having a reduced conductive path area |
-
2014
- 2014-02-19 US US14/183,953 patent/US9412942B2/en not_active Expired - Fee Related
-
2015
- 2015-02-18 EP EP15707484.0A patent/EP3108513A1/en not_active Withdrawn
- 2015-02-18 WO PCT/US2015/016268 patent/WO2015126875A1/en active Application Filing
- 2015-02-18 CN CN201580004568.3A patent/CN105917481A/en active Pending
- 2015-02-18 KR KR1020167017457A patent/KR20160122121A/en unknown
- 2015-02-24 TW TW104105946A patent/TW201539733A/en unknown
-
2016
- 2016-03-09 US US15/065,193 patent/US20160190441A1/en not_active Abandoned
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5687112A (en) * | 1996-04-19 | 1997-11-11 | Energy Conversion Devices, Inc. | Multibit single cell memory element having tapered contact |
US20060097238A1 (en) * | 2002-07-26 | 2006-05-11 | Laurent Breuil | Non-volatile memory element and production method thereof and storage memory arrangement |
US20040085833A1 (en) * | 2002-11-01 | 2004-05-06 | Young-Nam Hwang | Phase changeable memory devices and methods of forming the same in which an upper electrode includes a tip that extends toward a lower electrode |
US20060131618A1 (en) * | 2004-12-16 | 2006-06-22 | Ming-Hsiang Hsueh | Chalcogenide random access memory and method of fabricating the same |
US20130001501A1 (en) * | 2011-07-01 | 2013-01-03 | Micron Technology, Inc. | Memory cell structures |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10056545B2 (en) | 2013-03-13 | 2018-08-21 | Microchip Technology Incorporated | Sidewall-type memory cell |
US20160315257A1 (en) * | 2014-02-19 | 2016-10-27 | Microchip Technology Incorporated | Resistive Memory Cell Having A Reduced Conductive Path Area |
US9865813B2 (en) | 2014-02-19 | 2018-01-09 | Microchip Technology Incorporated | Method for forming resistive memory cell having a spacer region under an electrolyte region and a top electrode |
US9865814B2 (en) * | 2014-02-19 | 2018-01-09 | Microchip Technology Incorporated | Resistive memory cell having a single bottom electrode and two top electrodes |
US9917251B2 (en) | 2014-02-19 | 2018-03-13 | Microchip Technology Incorporated | Resistive memory cell having a reduced conductive path area |
US10003021B2 (en) | 2014-02-19 | 2018-06-19 | Microchip Technology Incorporated | Resistive memory cell with sloped bottom electrode |
US11043634B2 (en) * | 2019-04-09 | 2021-06-22 | International Business Machines Corporation | Confining filament at pillar center for memory devices |
Also Published As
Publication number | Publication date |
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EP3108513A1 (en) | 2016-12-28 |
WO2015126875A1 (en) | 2015-08-27 |
CN105917481A (en) | 2016-08-31 |
US20150236256A1 (en) | 2015-08-20 |
KR20160122121A (en) | 2016-10-21 |
US9412942B2 (en) | 2016-08-09 |
TW201539733A (en) | 2015-10-16 |
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