US20160055901A1 - Induced thermal gradients - Google Patents

Induced thermal gradients Download PDF

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US20160055901A1
US20160055901A1 US14/838,994 US201514838994A US2016055901A1 US 20160055901 A1 US20160055901 A1 US 20160055901A1 US 201514838994 A US201514838994 A US 201514838994A US 2016055901 A1 US2016055901 A1 US 2016055901A1
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thermal
die
memory
thermal sensor
offset bit
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US14/838,994
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Kenneth D. Shoemaker
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Intel Corp
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Intel Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40626—Temperature related aspects of refresh operations
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01K—MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR
    • G01K3/00—Thermometers giving results other than momentary value of temperature
    • G01K3/08—Thermometers giving results other than momentary value of temperature giving differences of values; giving differentiated values
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/20—Cooling means
    • G06F1/206—Cooling means comprising thermal management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3275—Power saving in memory, e.g. RAM, cache
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4067—Refresh in standby or low power modes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • Embodiments of the invention relate to semiconductor devices. More particularly, embodiments of the invention relate to techniques for tolerating induced thermal gradients in semiconductor devices.
  • Thermal energy when operating. Because the thermal energy may not be uniform, a thermal gradient may exist. As systems become smaller and semiconductor devices are more closely packed, which may result in mechanical coupling between devices. This tight mechanical coupling may result in unexpected induced thermal gradients between one and another of the semiconductor devices.
  • FIG. 1 is a block diagram of one embodiment of a package having one or more memory dies stacked with a processor/logic die.
  • FIG. 2 is a block diagram of one embodiment of a first die having a single sensor and a second die having multiple sensors.
  • FIG. 3 is a flow diagram of one embodiment of a technique to operate a memory array using temperature difference information.
  • FIG. 4 is a block diagram of one embodiment of an electronic system.
  • Logic chips typically contain several thermal sensors that are used to monitor the temperature on various parts of the logic chip and are typically placed where localized hot spots are expected. Logic chips may exhibit high thermal gradients across the die corresponding to more and less active regions in the logic chip.
  • DRAM chips may exhibit variable retention times based on temperature. Lower-power DRAM chips may use this property in a feature called “temperature compensated self refresh.” This may reduce the refresh frequency during self refresh thereby reducing standby power consumption at lower temperatures.
  • a DRAM chip has a single thermal sensor because DRAM chips typically have a relatively uniform power distribution. However, when closely coupled with a logic chip that has a non-uniform power distribution, the DRAM thermal sensor may not be located near the hottest spot of the DRAM chip. This may cause the DRAM to refresh at an inappropriately low rate, which may lead to data loss.
  • the location of a thermal sensor may be standardized for all devices on a stack.
  • the location may be specified, for example, as a certain offset from a standardized vertical interconnect array in an area that cannot be used for the memory array in the DRAM.
  • a SoC (or other computational element) may calculate a temperature difference between a hottest spot and the standard location.
  • a mode register may be utilized by the SoC (or other computational element) to communicate with the DRAM regarding the temperature difference between the standard location and the hot spot. The DRAM can then utilize this difference to set refresh rates accordingly.
  • the techniques may be adapted to function without a standard thermal sensor location.
  • the SoC (or other computational element) may calculate a maximum temperature gradient across its die and use that information to program the DRAM offset temperature. This may allow the DRAM to refresh its contents more often than absolutely necessary, which may lead to increased power consumption, but would prevent data loss.
  • FIG. 1 is a block diagram of one embodiment of a package having one or more memory dies stacked with a processor/logic die.
  • FIG. 1 several dies containing memory arrays (e.g., DRAM) are illustrated; however any number of memory dies may be supported.
  • memory arrays e.g., DRAM
  • Integrated circuit package 120 may be any type of package known in the art with any type of interface known in the art (e.g., ball grid array, etc.). Within package 120 , logic die 140 may be electrically coupled to the interface. One or more memory modules 150 may be electrically coupled with logic die 140 . Logic die 140 may be, for example, a processor die, a system on a chip (SoC) die, or any other die that may have uneven thermal patterns.
  • SoC system on a chip
  • One or more memory modules 150 may also be physically connected to logic die 140 , which my have thermal consequences for one or more of the dice. Because logic die 140 may have an uneven thermal gradient the physical connection between logic die 140 and one or more of memory modules 150 , the thermal gradient of one or more of memory modules 150 may not be as expected. Typically, memory modules, for example DRAMs, have a relatively consistent temperature across the die because circuit utilization on the memory module is relatively distributed.
  • thermal sensor may be relatively unimportant. That is, when the memory module is operating without any outside thermal influences, a single thermal sensor may be sufficient and the location of thermal sensor may be relatively flexible.
  • logic dice In contrast to memory modules, logic dice have circuits that are used consistently and frequently which result in higher operating temperatures in those regions. Therefore, logic dice typically have thermal sensors located a places of higher expected temperature so that these hot spots may be monitored. When a logic die comes in to physical contact with another die, for example, memory die 150 , the hot spots on the logic die may create corresponding hot spots on the memory die. Thus, the thermal information from the memory die thermal sensor may be inaccurate.
  • memory die 150 has a thermal sensor in a known location. That is, each memory die may have the same thermal sensor location.
  • Logic die 140 may have a corresponding thermal sensor in a location that is immediately adjacent to or substantially adjacent to the thermal sensor of memory die 150 .
  • Logic die 140 may also have thermal sensors in other locations, for example, corresponding to one or more hot spots.
  • logic die may determine a temperature difference between a thermal sensor at a hot spot and a thermal sensor corresponding to a thermal sensor in the memory module.
  • the temperature difference between the thermal sensors on the logic die may be used by the memory module to determine an adjustment to the temperature indicated by the thermal sensor on the memory module.
  • the behavior of the memory module may be modified based on the adjusted temperature rather than the measured temperature.
  • FIG. 2 is a block diagram of one embodiment of a first die having a single sensor and a second die having multiple sensors.
  • the example of FIG. 2 illustrates two dice that may be stacked so that the heat from one die may transfer to the other die.
  • the example of FIG. 2 illustrates only two dice, but the concepts illustrated are applicable to any number of stacked dice.
  • Die 220 may include any type of circuitry, for example, DRAM arrays, or other memory structures 235 .
  • Die 220 includes thermal sensor 240 coupled with management logic 230 .
  • management logic 230 may operate to read temperature information from thermal sensor 240 and may use that temperature information to modify behavior or operation of memory array 235 .
  • the refresh rate of memory array 235 may be adjusted by management logic 230 based on information from thermal sensor 240 .
  • Die 250 may include logic circuitry, for example, a processor core, a graphics processor, a system on a chip (SoC), or other logic 275 .
  • Die 250 may have multiple types of circuits, for example, a processor core, a cache memory, a transceiver, etc. Because die 250 may have circuits with irregular thermal gradients, die 250 may have multiple thermal sensors (e.g., 260 , 265 ), one of which is to be aligned with thermal sensor 240 .
  • SoC system on a chip
  • thermal sensor 240 may be placed in a predetermined location on die 220 that is known to designers and/or manufacturers of die 250 .
  • Thermal sensor 260 is positioned so that when die 220 is stacked on die 250 , thermal sensors 240 and 260 will be aligned or close enough spatially that temperature information from thermal sensor 260 may be utilized with temperature information from thermal sensor 240 .
  • Control circuit 270 is coupled with thermal sensors 260 and 265 to collect temperature information. In one embodiment, control circuit 270 determines a temperature difference between thermal sensor 265 and thermal sensor 260 . Control circuit 270 may transmit this difference (or information indicating a difference range), to management logic 230 . In one embodiment, a bit in a register in management logic 230 is set to indicate a temperature difference (e.g., 0 indicates 0-10 degree difference, 1 indicates a 10+degree difference). In another embodiment, more bits may be used to provide a more granular range, or an actual temperature difference may be transmitted.
  • Management logic 230 uses the temperature difference information from control circuit 270 with temperature information from thermal sensor 240 to manage operation of memory array 235 .
  • management logic 230 controls a refresh rate for memory array 235 .
  • Management logic 230 may combine the temperature difference information with the temperature information from thermal sensor 240 to determine an operational temperature value that is used for management of memory array 235 . For example, if the temperature difference indicates a higher temperature, management logic 230 may increase the refresh rate for memory array 235 .
  • FIG. 3 is a flow diagram of one embodiment of a technique to operate a memory array using temperature difference information. The operations described with respect to FIG. 3 may be performed by control and/or management circuitry spread across one or more dice.
  • FIG. 3 The operation of FIG. 3 is applicable to a configuration of multiple dice that are physically in contact with one another so that thermal transfer may occur.
  • at least one thermal sensor on the lower die is aligned with at least one sensor on the upper die.
  • the lower die contains a logic circuit, for example, a processor core or a system on a chip.
  • the upper die may contain a memory structure, for example, a DRAM.
  • the logic circuit is on the upper die and the memory module is on the lower die.
  • Temperature information from two or more thermal sensors is collected on the logic die, 310 .
  • the logic die may have any number of thermal sensors and, one or more circuits on the logic die may manage operation of the logic die by utilizing the temperature information collected from the multiple thermal sensors.
  • Temperature difference information is determined for at least one pair of thermal sensors on the logic die, 320 .
  • at least one of the thermal sensors for which a temperature difference is determined is aligned with a corresponding thermal sensor on the memory module die.
  • the temperature difference information is transmitted between the logic die and the memory die, 330 .
  • the temperature difference may be communicated by one or more bits that indicate temperature differential ranges, or a number indicating an actual temperature difference may be transmitted.
  • a 0 may indicate a temperature difference in a first range (e.g., 0-5 degrees, 0-10 degrees, 0-12 degrees) and a 1 may indicate a temperature difference in a second range (e.g., >5 degrees, >10 degrees, >12 degrees).
  • a 00 may indicate a first range (e.g., 0-5 degrees, 0-7 degrees, 0-10 degrees)
  • a 01 may indicate a second range (e.g., 6-10 degrees, 8-15 degrees, 11-20 degrees)
  • a 10 may indicate a third range (e.g., 11-15 degrees, 16-20 degrees, 21-25 degrees)
  • a 11 may indicate a fourth range (e.g., >15 degrees, >20 degrees, >25 degrees).
  • Other embodiments with different numbers of bits may be similarly supported.
  • Temperature information is gathered for the memory module, 340 .
  • the memory module has only one thermal sensor that is aligned with one of the thermal sensors of the logic die.
  • the memory module may have multiple thermal sensors.
  • the memory module may have management (or other control) circuitry that utilizes temperature information to manage operation of the memory module.
  • the refresh rate for the memory array is determined based, at least in part, on the operating temperature of the memory module.
  • the management circuitry utilizes the temperature information from the memory module thermal senor and the temperature difference information to adjust, if necessary, the operational parameters of the memory module, 350 .
  • the refresh rate of the memory module may be determined based on the measured temperature as adjusted by the temperature difference information. Other operational parameters may also be adjusted.
  • temperature difference information may be shared between the dice, which will allow the respective control circuits to have more accurate information upon which to base operational parameters.
  • FIG. 4 is a block diagram of one embodiment of an electronic system.
  • the electronic system illustrated in FIG. 4 is intended to represent a range of electronic systems (either wired or wireless) including, for example, desktop computer systems, laptop computer systems, cellular telephones, personal digital assistants (PDAs) including cellular-enabled PDAs, set top boxes.
  • Alternative electronic systems may include more, fewer and/or different components.
  • One or more of the components illustrated in FIG. 4 may be on dice that are in physical contact as described above.
  • processors 410 and one or more DRAM modules that are part of memory 420 may be arranged as described above.
  • Other components may be similarly arranged.
  • Electronic system 400 includes bus 405 or other communication device to communicate information, and processor 410 coupled to bus 405 that may process information. While electronic system 400 is illustrated with a single processor, electronic system 400 may include multiple processors and/or co-processors. Electronic system 400 further may include random access memory (RAM) or other dynamic storage device 420 (referred to as main memory), coupled to bus 405 and may store information and instructions that may be executed by processor 410 . Main memory 420 may also be used to store temporary variables or other intermediate information during execution of instructions by processor 410 .
  • RAM random access memory
  • main memory main memory
  • Electronic system 400 may also include read only memory (ROM) and/or other static storage device 430 coupled to bus 405 that may store static information and instructions for processor 410 .
  • Data storage device 440 may be coupled to bus 405 to store information and instructions.
  • Data storage device 440 such as a magnetic disk or optical disc and corresponding drive may be coupled to electronic system 400 .
  • Electronic system 400 may also be coupled via bus 405 to display device 450 , such as a cathode ray tube (CRT) or liquid crystal display (LCD), to display information to a user.
  • display device 450 such as a cathode ray tube (CRT) or liquid crystal display (LCD)
  • Alphanumeric input device 460 may be coupled to bus 405 to communicate information and command selections to processor 410 .
  • cursor control 470 such as a mouse, a trackball, or cursor direction keys to communicate direction information and command selections to processor 410 and to control cursor movement on display 450 .
  • Electronic system 400 further may include network interface(s) 480 to provide access to a network, such as a local area network.
  • Network interface(s) 480 may include, for example, a wireless network interface having antenna 485 , which may represent one or more antenna(e).
  • Network interface(s) 480 may also include, for example, a wired network interface to communicate with remote devices via network cable 487 , which may be, for example, an Ethernet cable, a coaxial cable, a fiber optic cable, a serial cable, or a parallel cable.
  • network interface(s) 480 may provide access to a local area network, for example, by conforming to IEEE 802.11b and/or IEEE 802.11g standards, and/or the wireless network interface may provide access to a personal area network, for example, by conforming to Bluetooth standards. Other wireless network interfaces and/or protocols can also be supported.
  • IEEE 802.11b corresponds to IEEE Std. 802.11b-1999 entitled “Local and Metropolitan Area Networks, Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications: Higher-Speed Physical Layer Extension in the 2.4 GHz Band,” approved Sep. 16, 1999 as well as related documents.
  • IEEE 802.11g corresponds to IEEE Std. 802.11g-2003 entitled “Local and Metropolitan Area Networks, Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications, Amendment 4: Further Higher Rate Extension in the 2.4 GHz Band,” approved Jun. 27, 2003 as well as related documents.
  • Bluetooth protocols are described in “Specification of the Bluetooth System: Core, Version 1.1,” published Feb. 22, 2001 by the Bluetooth Special Interest Group, Inc. Associated as well as previous or subsequent versions of the Bluetooth standard may also be supported.
  • network interface(s) 480 may provide wireless communications using, for example, Time Division, Multiple Access (TDMA) protocols, Global System for Mobile Communications (GSM) protocols, Code Division, Multiple Access (CDMA) protocols, and/or any other type of wireless communications protocol.
  • TDMA Time Division, Multiple Access
  • GSM Global System for Mobile Communications
  • CDMA Code Division, Multiple Access

Abstract

A temperature difference between a first thermal sensor and a second thermal sensor on a first die is determined. The temperature difference is transmitted from the first die to a circuit on a second die. A temperature from a thermal sensor on the second die is determined. The temperature difference and the temperature from the thermal sensor are utilized on the second die to modify operational characteristics of one or more circuits on the second die.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This application is a continuation of U.S. patent application Ser. No. 13/077,661 filed on Mar. 31, 2011, which application is incorporated herein by reference in its entirety.
    • TECHNICAL FIELD
  • Embodiments of the invention relate to semiconductor devices. More particularly, embodiments of the invention relate to techniques for tolerating induced thermal gradients in semiconductor devices.
    • BACKGROUND
  • Semiconductor devices produce thermal energy when operating. Because the thermal energy may not be uniform, a thermal gradient may exist. As systems become smaller and semiconductor devices are more closely packed, which may result in mechanical coupling between devices. This tight mechanical coupling may result in unexpected induced thermal gradients between one and another of the semiconductor devices.
  • These unexpected thermal gradients may result in operating errors. For example, in a dynamic random access memory (DRAM), unexpected thermal gradients may result in inappropriate refresh frequencies and even data loss.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • Embodiments of the invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements.
  • FIG. 1 is a block diagram of one embodiment of a package having one or more memory dies stacked with a processor/logic die.
  • FIG. 2 is a block diagram of one embodiment of a first die having a single sensor and a second die having multiple sensors.
  • FIG. 3 is a flow diagram of one embodiment of a technique to operate a memory array using temperature difference information.
  • FIG. 4 is a block diagram of one embodiment of an electronic system.
    •  DETAILED DESCRIPTION
  • In the following description, numerous specific details are set forth. However, embodiments of the invention may be practiced without these specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail in order not to obscure the understanding of this description.
  • When a processor (or System on a Chip, SoC) and DRAM dies are stacked there may be little thermal gradient between the DRAM and the logic chip. Logic chips typically contain several thermal sensors that are used to monitor the temperature on various parts of the logic chip and are typically placed where localized hot spots are expected. Logic chips may exhibit high thermal gradients across the die corresponding to more and less active regions in the logic chip.
  • DRAM chips may exhibit variable retention times based on temperature. Lower-power DRAM chips may use this property in a feature called “temperature compensated self refresh.” This may reduce the refresh frequency during self refresh thereby reducing standby power consumption at lower temperatures. Typically a DRAM chip has a single thermal sensor because DRAM chips typically have a relatively uniform power distribution. However, when closely coupled with a logic chip that has a non-uniform power distribution, the DRAM thermal sensor may not be located near the hottest spot of the DRAM chip. This may cause the DRAM to refresh at an inappropriately low rate, which may lead to data loss.
  • The techniques described herein address this problem by one or more strategies. In one embodiment, the location of a thermal sensor may be standardized for all devices on a stack. The location may be specified, for example, as a certain offset from a standardized vertical interconnect array in an area that cannot be used for the memory array in the DRAM. In one embodiment, a SoC (or other computational element) may calculate a temperature difference between a hottest spot and the standard location. In one embodiment, a mode register may be utilized by the SoC (or other computational element) to communicate with the DRAM regarding the temperature difference between the standard location and the hot spot. The DRAM can then utilize this difference to set refresh rates accordingly.
  • In alternate embodiments, the techniques may be adapted to function without a standard thermal sensor location. In these embodiments, the SoC (or other computational element) may calculate a maximum temperature gradient across its die and use that information to program the DRAM offset temperature. This may allow the DRAM to refresh its contents more often than absolutely necessary, which may lead to increased power consumption, but would prevent data loss.
  • FIG. 1 is a block diagram of one embodiment of a package having one or more memory dies stacked with a processor/logic die. In the example of FIG. 1, several dies containing memory arrays (e.g., DRAM) are illustrated; however any number of memory dies may be supported.
  • Integrated circuit package 120 may be any type of package known in the art with any type of interface known in the art (e.g., ball grid array, etc.). Within package 120, logic die 140 may be electrically coupled to the interface. One or more memory modules 150 may be electrically coupled with logic die 140. Logic die 140 may be, for example, a processor die, a system on a chip (SoC) die, or any other die that may have uneven thermal patterns.
  • One or more memory modules 150 may also be physically connected to logic die 140, which my have thermal consequences for one or more of the dice. Because logic die 140 may have an uneven thermal gradient the physical connection between logic die 140 and one or more of memory modules 150, the thermal gradient of one or more of memory modules 150 may not be as expected. Typically, memory modules, for example DRAMs, have a relatively consistent temperature across the die because circuit utilization on the memory module is relatively distributed.
  • Because of this, the placement of a thermal sensor on the memory module die may be relatively unimportant. That is, when the memory module is operating without any outside thermal influences, a single thermal sensor may be sufficient and the location of thermal sensor may be relatively flexible.
  • In contrast to memory modules, logic dice have circuits that are used consistently and frequently which result in higher operating temperatures in those regions. Therefore, logic dice typically have thermal sensors located a places of higher expected temperature so that these hot spots may be monitored. When a logic die comes in to physical contact with another die, for example, memory die 150, the hot spots on the logic die may create corresponding hot spots on the memory die. Thus, the thermal information from the memory die thermal sensor may be inaccurate.
  • In one embodiment, memory die 150 has a thermal sensor in a known location. That is, each memory die may have the same thermal sensor location. Logic die 140 may have a corresponding thermal sensor in a location that is immediately adjacent to or substantially adjacent to the thermal sensor of memory die 150. Logic die 140 may also have thermal sensors in other locations, for example, corresponding to one or more hot spots.
  • In one embodiment, logic die may determine a temperature difference between a thermal sensor at a hot spot and a thermal sensor corresponding to a thermal sensor in the memory module. The temperature difference between the thermal sensors on the logic die may be used by the memory module to determine an adjustment to the temperature indicated by the thermal sensor on the memory module. The behavior of the memory module may be modified based on the adjusted temperature rather than the measured temperature.
  • FIG. 2 is a block diagram of one embodiment of a first die having a single sensor and a second die having multiple sensors. The example of FIG. 2 illustrates two dice that may be stacked so that the heat from one die may transfer to the other die. The example of FIG. 2 illustrates only two dice, but the concepts illustrated are applicable to any number of stacked dice.
  • Die 220 may include any type of circuitry, for example, DRAM arrays, or other memory structures 235. Die 220 includes thermal sensor 240 coupled with management logic 230. In one embodiment, when die 220 includes DRAM, management logic 230 may operate to read temperature information from thermal sensor 240 and may use that temperature information to modify behavior or operation of memory array 235. In one embodiment, the refresh rate of memory array 235 may be adjusted by management logic 230 based on information from thermal sensor 240.
  • Die 250 may include logic circuitry, for example, a processor core, a graphics processor, a system on a chip (SoC), or other logic 275. Die 250 may have multiple types of circuits, for example, a processor core, a cache memory, a transceiver, etc. Because die 250 may have circuits with irregular thermal gradients, die 250 may have multiple thermal sensors (e.g., 260, 265), one of which is to be aligned with thermal sensor 240.
  • In one embodiment, thermal sensor 240 may be placed in a predetermined location on die 220 that is known to designers and/or manufacturers of die 250. Thermal sensor 260 is positioned so that when die 220 is stacked on die 250, thermal sensors 240 and 260 will be aligned or close enough spatially that temperature information from thermal sensor 260 may be utilized with temperature information from thermal sensor 240.
  • Control circuit 270 is coupled with thermal sensors 260 and 265 to collect temperature information. In one embodiment, control circuit 270 determines a temperature difference between thermal sensor 265 and thermal sensor 260. Control circuit 270 may transmit this difference (or information indicating a difference range), to management logic 230. In one embodiment, a bit in a register in management logic 230 is set to indicate a temperature difference (e.g., 0 indicates 0-10 degree difference, 1 indicates a 10+degree difference). In another embodiment, more bits may be used to provide a more granular range, or an actual temperature difference may be transmitted.
  • Management logic 230 uses the temperature difference information from control circuit 270 with temperature information from thermal sensor 240 to manage operation of memory array 235. In one embodiment, management logic 230 controls a refresh rate for memory array 235. Management logic 230 may combine the temperature difference information with the temperature information from thermal sensor 240 to determine an operational temperature value that is used for management of memory array 235. For example, if the temperature difference indicates a higher temperature, management logic 230 may increase the refresh rate for memory array 235.
  • FIG. 3 is a flow diagram of one embodiment of a technique to operate a memory array using temperature difference information. The operations described with respect to FIG. 3 may be performed by control and/or management circuitry spread across one or more dice.
  • The operation of FIG. 3 is applicable to a configuration of multiple dice that are physically in contact with one another so that thermal transfer may occur. In one embodiment, at least one thermal sensor on the lower die is aligned with at least one sensor on the upper die. In one embodiment, the lower die contains a logic circuit, for example, a processor core or a system on a chip. The upper die may contain a memory structure, for example, a DRAM. In an alternate embodiment, the logic circuit is on the upper die and the memory module is on the lower die.
  • Temperature information from two or more thermal sensors is collected on the logic die, 310. The logic die may have any number of thermal sensors and, one or more circuits on the logic die may manage operation of the logic die by utilizing the temperature information collected from the multiple thermal sensors.
  • Temperature difference information is determined for at least one pair of thermal sensors on the logic die, 320. In one embodiment, at least one of the thermal sensors for which a temperature difference is determined is aligned with a corresponding thermal sensor on the memory module die.
  • The temperature difference information is transmitted between the logic die and the memory die, 330. In one embodiment, the temperature difference may be communicated by one or more bits that indicate temperature differential ranges, or a number indicating an actual temperature difference may be transmitted. For example, in a single-bit embodiment, a 0 may indicate a temperature difference in a first range (e.g., 0-5 degrees, 0-10 degrees, 0-12 degrees) and a 1 may indicate a temperature difference in a second range (e.g., >5 degrees, >10 degrees, >12 degrees).
  • In a two-bit embodiment, four ranges may be supported. For example, a 00 may indicate a first range (e.g., 0-5 degrees, 0-7 degrees, 0-10 degrees), a 01 may indicate a second range (e.g., 6-10 degrees, 8-15 degrees, 11-20 degrees), a 10 may indicate a third range (e.g., 11-15 degrees, 16-20 degrees, 21-25 degrees), and a 11 may indicate a fourth range (e.g., >15 degrees, >20 degrees, >25 degrees). Other embodiments with different numbers of bits may be similarly supported.
  • Temperature information is gathered for the memory module, 340. In one embodiment, the memory module has only one thermal sensor that is aligned with one of the thermal sensors of the logic die. In alternate embodiments, the memory module may have multiple thermal sensors. The memory module may have management (or other control) circuitry that utilizes temperature information to manage operation of the memory module. In one embodiment, the refresh rate for the memory array is determined based, at least in part, on the operating temperature of the memory module.
  • The management circuitry utilizes the temperature information from the memory module thermal senor and the temperature difference information to adjust, if necessary, the operational parameters of the memory module, 350. In one embodiment, the refresh rate of the memory module may be determined based on the measured temperature as adjusted by the temperature difference information. Other operational parameters may also be adjusted.
  • In alternate embodiments, other adjustments may be made utilizing the temperature difference information. For example, if two logic dice are stacked and the respective thermal sensors are not aligned, temperature difference information may be shared between the dice, which will allow the respective control circuits to have more accurate information upon which to base operational parameters.
  • FIG. 4 is a block diagram of one embodiment of an electronic system. The electronic system illustrated in FIG. 4 is intended to represent a range of electronic systems (either wired or wireless) including, for example, desktop computer systems, laptop computer systems, cellular telephones, personal digital assistants (PDAs) including cellular-enabled PDAs, set top boxes. Alternative electronic systems may include more, fewer and/or different components.
  • One or more of the components illustrated in FIG. 4 may be on dice that are in physical contact as described above. For example, one or more of processors 410 and one or more DRAM modules that are part of memory 420 may be arranged as described above. Other components may be similarly arranged.
  • Electronic system 400 includes bus 405 or other communication device to communicate information, and processor 410 coupled to bus 405 that may process information. While electronic system 400 is illustrated with a single processor, electronic system 400 may include multiple processors and/or co-processors. Electronic system 400 further may include random access memory (RAM) or other dynamic storage device 420 (referred to as main memory), coupled to bus 405 and may store information and instructions that may be executed by processor 410. Main memory 420 may also be used to store temporary variables or other intermediate information during execution of instructions by processor 410.
  • Electronic system 400 may also include read only memory (ROM) and/or other static storage device 430 coupled to bus 405 that may store static information and instructions for processor 410. Data storage device 440 may be coupled to bus 405 to store information and instructions. Data storage device 440 such as a magnetic disk or optical disc and corresponding drive may be coupled to electronic system 400.
  • Electronic system 400 may also be coupled via bus 405 to display device 450, such as a cathode ray tube (CRT) or liquid crystal display (LCD), to display information to a user. Alphanumeric input device 460, including alphanumeric and other keys, may be coupled to bus 405 to communicate information and command selections to processor 410. Another type of user input device is cursor control 470, such as a mouse, a trackball, or cursor direction keys to communicate direction information and command selections to processor 410 and to control cursor movement on display 450.
  • Electronic system 400 further may include network interface(s) 480 to provide access to a network, such as a local area network. Network interface(s) 480 may include, for example, a wireless network interface having antenna 485, which may represent one or more antenna(e). Network interface(s) 480 may also include, for example, a wired network interface to communicate with remote devices via network cable 487, which may be, for example, an Ethernet cable, a coaxial cable, a fiber optic cable, a serial cable, or a parallel cable.
  • In one embodiment, network interface(s) 480 may provide access to a local area network, for example, by conforming to IEEE 802.11b and/or IEEE 802.11g standards, and/or the wireless network interface may provide access to a personal area network, for example, by conforming to Bluetooth standards. Other wireless network interfaces and/or protocols can also be supported.
  • IEEE 802.11b corresponds to IEEE Std. 802.11b-1999 entitled “Local and Metropolitan Area Networks, Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications: Higher-Speed Physical Layer Extension in the 2.4 GHz Band,” approved Sep. 16, 1999 as well as related documents. IEEE 802.11g corresponds to IEEE Std. 802.11g-2003 entitled “Local and Metropolitan Area Networks, Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications, Amendment 4: Further Higher Rate Extension in the 2.4 GHz Band,” approved Jun. 27, 2003 as well as related documents. Bluetooth protocols are described in “Specification of the Bluetooth System: Core, Version 1.1,” published Feb. 22, 2001 by the Bluetooth Special Interest Group, Inc. Associated as well as previous or subsequent versions of the Bluetooth standard may also be supported.
  • In addition to, or instead of, communication via wireless LAN standards, network interface(s) 480 may provide wireless communications using, for example, Time Division, Multiple Access (TDMA) protocols, Global System for Mobile Communications (GSM) protocols, Code Division, Multiple Access (CDMA) protocols, and/or any other type of wireless communications protocol.
  • Reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment.
  • While the invention has been described in terms of several embodiments, those skilled in the art will recognize that the invention is not limited to the embodiments described, but can be practiced with modification and alteration within the spirit and scope of the appended claims. The description is thus to be regarded as illustrative instead of limiting.

Claims (32)

1. An apparatus comprising:
a memory die including dynamic random access memory (DRAM), a mode register including a storage location for a thermal offset bit, and a memory thermal sensor; and
a second die including logic circuitry thermally coupled with the memory die, the second die further including a first thermal sensor and a second thermal sensor, the first and second thermal sensors to detect a thermal gradient, and the logic circuitry to provide a thermal offset bit to the storage location for the thermal offset bit of the mode register on the memory die responsive to detection of a change in the thermal gradient, the memory thermal sensor of the memory die being aligned with or in close proximity with the first thermal sensor of the second die, and the second thermal sensor of the second die being located at a hot spot of the second die;
wherein the memory die includes a temperature compensated self-refresh (TCSR) logic, the TCSR logic to modify a self-refresh rate of the DRAM responsive, at least in part, to the thermal offset bit.
2. The apparatus of claim 1, wherein a location of the memory thermal sensor in relation to the first sensor is to allow utilization of temperature information from the first thermal sensor with temperature information from the memory thermal sensor.
3. The apparatus of claim 1, wherein a value of the thermal offset bit is to represent a temperature range for the thermal gradient.
4. The apparatus of claim 1, wherein the thermal offset bit is to control refresh behavior for a plurality of channels of the memory die.
5. The apparatus of claim 1, wherein the second die comprises a processor core or graphics processor.
6. The apparatus of claim 1, wherein the second die comprises a system on a chip (SoC).
7. The apparatus of claim 1, further comprising:
one or more processors communicatively coupled to the logic circuitry;
a network interface communicatively coupled with at least one of the one or more processors; and
a display communicatively coupled with at least one of the one or more processors.
8. A semiconductor die comprising:
a first thermal sensor and a second thermal sensor, the first and second thermal sensors to detect a thermal gradient; and
logic circuitry to provide a thermal offset bit to a storage location for the thermal offset bit of a mode register of a memory die responsive to detection of a change in the thermal gradient;
wherein the thermal offset bit is to direct a temperature compensated self-refresh (TCSR) logic of the memory die to modify a self-refresh rate of the DRAM;
wherein the first thermal sensor is to be aligned with or in close proximity with a memory thermal sensor of the memory die, and wherein the second thermal sensor of the semiconductor die is located at a hot spot of the semiconductor die.
9. The semiconductor die of claim 8, wherein a location of the memory thermal sensor in relation to the first thermal sensor is to allow utilization of temperature information from the first thermal sensor with temperature information from the memory thermal sensor.
10. The semiconductor die of claim 8, wherein the semiconductor die is to be thermally coupled with the memory die.
11. The semiconductor die of claim 8, wherein a value of the thermal offset bit is to represent a temperature range for the thermal gradient.
12. The semiconductor die of claim 8, wherein the thermal offset bit is to control refresh behavior for a plurality of channels of the memory die.
13. The semiconductor die of claim 8, wherein the semiconductor die comprises a processor core or graphics processor.
14. The semiconductor die of claim 8, wherein the semiconductor die comprises a system on a chip (SoC).
15. A memory die comprising:
dynamic random access memory (DRAM);
a mode register including a storage location for a thermal offset bit;
a memory thermal sensor; and
a temperature compensated self-refresh (TCSR) logic, the TCSR logic to modify a self-refresh rate of the DRAM responsive, at least in part, to the thermal offset bit; and
wherein the mode register is to receive the thermal offset bit from a second die responsive to a change in a thermal gradient between a first thermal sensor and a second thermal sensor of the second die,
wherein the memory thermal sensor is to be aligned with or in close proximity with the first thermal sensor, and wherein the second thermal sensor is located at a hot spot of the second die.
15. (canceled)
16. The memory die of claim 15, wherein the memory die is to be thermally coupled with the second die.
17. The memory die of claim 15, wherein a value of the thermal offset bit is to represent a temperature range for the thermal gradient.
18. The memory die of claim 15, further comprising a plurality of channels, wherein the thermal offset bit is to control refresh behavior for the plurality of channels.
19. The memory die of claim 15, wherein the second die comprises a processor core or graphics processor.
20. The memory die of claim 15, wherein the second die comprises a system on a chip (SoC).
21. A method comprising:
detecting a thermal gradient with a first thermal sensor and a second thermal sensor of a semiconductor die;
generating by logic circuitry of the semiconductor die a thermal offset bit responsive to detection of a change in the thermal gradient; and
transmitting the thermal offset bit for storage in a storage location of a mode register of a memory die, the memory die including dynamic random access memory (DRAM);
wherein the thermal offset bit is to direct a temperature compensated self-refresh (TCSR) logic of the memory die to modify a self-refresh rate of the DRAM;
wherein the first thermal sensor is to be aligned with or in close proximity with a memory thermal sensor of the memory die, and the second thermal sensor is located at a hot spot of the semiconductor die.
22. The method of claim 21, wherein a location of the memory thermal sensor in relation to the first thermal sensor is to allow utilization of temperature information from the first thermal sensor with temperature information from the memory thermal sensor.
23. The method of claim 21, wherein the semiconductor die is to be thermally coupled with the memory die.
24. The method of claim 21, wherein a value of the thermal offset bit is to represent a temperature range for the thermal gradient.
25. The method of claim 21, wherein the thermal offset bit is to control refresh behavior for a plurality of channels of the memory die.
26. At least one non-transitory computer-readable storage medium having stored thereon data representing sequences of instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising:
detecting a thermal gradient with a first thermal sensor and a second thermal sensor of a semiconductor die;
generating by logic circuitry of the semiconductor die a thermal offset bit responsive to detection of a change in the thermal gradient; and
transmitting the thermal offset bit for storage in a storage location of a mode register of a memory die, the memory die including dynamic random access memory (DRAM);
wherein the thermal offset bit is to direct a temperature compensated self-refresh (TCSR) logic of the memory die to modify a self-refresh rate of the DRAM;
wherein the first thermal sensor is to be aligned with or in close proximity with a memory thermal sensor of the memory die, and the second thermal sensor is located at a hot spot of the semiconductor die.
27. The medium of claim 26, wherein a location of the memory thermal sensor in relation to the first thermal sensor is to allow utilization of temperature information from the first thermal sensor with temperature information from the memory thermal sensor.
28. The medium of claim 26, wherein the semiconductor die is to be thermally coupled with the memory die.
29. The medium of claim 26, wherein a value of the thermal offset bit is to represent a temperature range for the thermal gradient.
30. The medium of claim 26, wherein the thermal offset bit is to control refresh behavior for a plurality of channels of the memory die.
31. The memory die of claim 15, wherein a location of the memory thermal sensor in relation to the first thermal sensor is to allow for utilization of temperature information from the first thermal sensor with temperature information from the memory thermal sensor.
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