US20150271504A1 - Adaptable video architectures - Google Patents
Adaptable video architectures Download PDFInfo
- Publication number
- US20150271504A1 US20150271504A1 US14/731,327 US201514731327A US2015271504A1 US 20150271504 A1 US20150271504 A1 US 20150271504A1 US 201514731327 A US201514731327 A US 201514731327A US 2015271504 A1 US2015271504 A1 US 2015271504A1
- Authority
- US
- United States
- Prior art keywords
- blocks
- sub
- pipeline
- processed
- video
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
- H04N19/127—Prioritisation of hardware or computational resources
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
- H04N19/182—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a pixel
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
- H04N19/156—Availability of hardware or computational resources, e.g. encoding based on power-saving criteria
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
- H04N19/187—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a scalable video layer
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
- H04N19/439—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using cascaded computational arrangements for performing a single operation, e.g. filtering
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
- G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Definitions
- FIG. 1 is a graphical representation of an example of a video device in accordance with various embodiments of the present disclosure.
- FIG. 2 is a flow chart illustrating an example of the real time adaptation of video processing in accordance with various embodiments of the present disclosure.
- FIG. 3 is a flow chart illustrating an example of scalable video pipeline processing in accordance with various embodiments of the present disclosure.
- FIG. 4 is a flow chart illustrating an example of pixel block size decomposition of video pixel blocks in accordance with various embodiments of the present disclosure.
- Image and multimedia processing may be provided through processing circuits implemented in individual chips or chip sets.
- the multimedia processing may be implemented with a single chip having flexible and low power architecture.
- the processor architecture may be configured in hardware and/or software executed by processing hardware (e.g., a processing unit).
- processing hardware e.g., a processing unit.
- Most conventional video coding architectures and designs are dedicated (hardware and/or software) to only one video coding standard and for servicing one video stream based thereon at a time.
- the adaptable video architecture is implemented in both hardware and software executed by hardware.
- An adaptable video (transcode-encode-decode) architecture is configured to fully and simultaneously support any number of video stream types, where each type is defined by one of a plurality of video coding standards.
- the hardware is time-shared between the multiple streams to provide nearly simultaneous processing of the streams. The net effect of the fine-grained time-sharing is that it appears to a user that the multiple streams are handled simultaneously by the video architecture.
- Video coding architectures are dedicated to a single video coding standard and for servicing one video stream at a time based upon that video coding standard.
- Software based architectures may be utilized for multiple standards but service only one stream at a time.
- the software based architectures face substantial limitations (especially for cutting edge standards) by not having access to dedicated hardware and for usurping general purpose processing resources.
- dedicated hardware places different power, space and cost demands on a design.
- each of the video coding standards (a) in software (without hardware acceleration); (b) in dedicated hardware; or (c) at an inferior performance level (e.g., at a reduced frame rate, resolution, quality, etc.) via a combination of (a) and (b); or not implement (or support) a video coding standard at all.
- an inferior performance level e.g., at a reduced frame rate, resolution, quality, etc.
- MPEG2 may not have been implemented with hardware acceleration.
- a user's device may be used 99% of the time viewing MPEG2 streams, all the while dedicated H.264 hardware sits idle.
- the adaptable transcode-encode-decode architecture uses two levels of architectural adaptability to overcome limitations.
- First, real time adaptation may be used to best support one or more simultaneous video streams.
- the streams may be of the same or differing video stream types.
- Second, a flexible architectural offering allows for design decision tailoring to fit a specific platform.
- For each coding standard (or type), several tiers of support (or stream pathways) may be offered to support multiple simultaneous video streams having the same or differing types.
- Such tiers involve transcode-encode-decode functional elements that may be carried out in software and/or with hardware acceleration. Serial, cyclic serial, parallel and combinations thereof may all be offered.
- This overall architectural offering with all underlying tiers may be fully integrated into a device or may be tailored to fit current design constraints by eliminating specific “element” tiers without requiring an underlying redesign.
- FIG. 1 shown is a graphical representation of a video device 100 including, e.g., a transcoder, encoder, or decoder that includes one or more hardware pipelines 103 or tiers for processing one or more streams of video data.
- Each pipeline 103 includes a plurality of elements 106 for processing the video stream data.
- the pipelines 103 are configured to allow the interconnections 109 between the pipeline elements 106 to be diverted based upon system conditions of the video device and/or video stream.
- the pipeline pathway may be reconfigured by diverting at least one of the interconnections allow processing by other pipeline elements 106 and/or by software modules 112 executed by shared general-purpose processing resources of the video device.
- All element tiers that make it into a device may function in a real time adaptive way to support shared processing resources for load balancing, multiple video stream conditions that arise during device use, and battery constraints.
- a pathway adaptation module executed by shared general-purpose processing resources of the video device monitors the conditions of the video device and controls rerouting the pipeline interconnections.
- FIG. 2 shown is a flow chart illustrating an example of the real time adaptation of a pipeline pathway 200 .
- a pipeline pathway 200 is defined for a first video stream.
- a decode pathway 200 may be defined wherein each pipeline element 106 is selected for the highest performance but with substantial power utilization to service a single video stream.
- the decode pathway 200 may be implemented in hardware or a combination of hardware and software executed by shared general-purpose processing resources such as, e.g., a processor, application specific chip, and/or other appropriate hardware.
- a change in one or more of the system conditions is detected. For example, during the visual presentation of a first video stream, battery conditions may change.
- An alternate pathway may be selected in box 209 based at least in part upon the condition changes.
- an alternative decoder pathway 200 a may be selected which offers better battery performance while delivering acceptable video quality.
- the alternate pipeline pathway 200 a may include, e.g., diverting the interconnections 109 between the pipeline elements 106 for processing by other pipeline elements 106 or by executed software modules 112 , bypassing pipeline elements 106 (which may be deactivated to reduce power usage), and/or rerouting to another pipeline pathway.
- Alternate pipeline pathways 200 a may be selected from a plurality of predefined pipeline pathways based upon a defined set of conditions or may be determined using an expert system (or other appropriate pattern recognition system) based upon the system conditions.
- the video stream transitions to the alternate pathway in box 212 (e.g., transition between the two pathways 200 and 200 a by synchronizing to a reference frame) and returns to box 206 to detect the next condition change. If an alternate pathway is not selected, then the video stream remains on the current pathway and returns to box 206 to detect the next condition change.
- Another change in conditions may then be detected such as, e.g., a user selecting a second video stream of the same or different type to be displayed in a shared screen arrangement.
- the decode architecture may adapt to best support the two streams by selecting various element tiers to form two pipeline pathways, one for processing each of the two streams.
- the video streams are transitioned and the sequence returns to box 206 to detect the next condition change.
- the sequence continues adapting to additional changes in the conditions. For example, a non-video stream task operating on the device may place a higher demand on shared general-purpose processing resources, which is detected in box 206 .
- the decode architecture may adapt to minimize its reliance on such shared resources by selecting other decoder pipeline elements 106 that are either less shared-resource consumptive or operate in dedicated hardware.
- the streams are transitioned before returning to box 206 .
- the adaptable video architecture may provide for a scalable video pipeline.
- Video processing predicts the current frame content utilizing previous content from previous video frames.
- H.264 uses this temporal coding for video processing.
- Other spatial and quality coding may also be used for video processing.
- Scalable video coding is an extension of H.264 that uses video information at different resolutions to predict current frame content.
- SVC defines a plurality of subset bitstreams, with each subset being independently decodable in a similar fashion as a single H.264 bitstream. Merely by dropping packets from the larger overall bitstream, a subset bitstream can be exposed.
- Each subset bitstream can represent one or more of scalable resolution, frame rate, and quality video signal.
- the subset bitstreams represent video layers within SVC with the base layer being fully compatible with H.264 (which is a single layer standard definition).
- H.264 which is a single layer standard definition.
- a receiving device can use the appropriate subset bitstream to perform the video processing.
- the additional subset bitstream layers can be discarded or used to for temporal, spatial and/or signal quality improvements.
- the adaptable video (transcode-encode-decode) architecture has at least two modes. First, the adaptable architecture is instantiated once for H.264 decode or other single layer standard. Second, the adaptable architecture is instantiated multiple times, each instance designed to accelerate the decoding of one SVC layer to improve the generated video image. For example, a lower resolution H.264 decode pipeline (M) may dump out internal aspects, which may then be read into next higher resolution layer (M+1). Information of values may be tapped out such as, e.g., motion vectors, transform coefficients, and/or image data prior to the application of the deblocking filter for use in the higher resolution pipeline. This may also be applied to multiple layers of progressively higher quality (and/or bitrate) at the same resolution or combined with different resolution layers.
- M lower resolution H.264 decode pipeline
- M+1 next higher resolution layer
- Information of values may be tapped out such as, e.g., motion vectors, transform coefficients, and/or image data prior to the application of the deblocking filter for
- a lower quality layer e.g., signal-to-noise ratio or fidelity
- the interlayer interpolations e.g., up sampling and/or filtering
- a decoder may include a plurality of decode pipelines 103 ( FIG. 1 ) with each decode pipeline 103 is associated with a different resolution.
- the decode pipelines 103 may be implemented in hardware and/or software modules executed by general-purpose processing resources. Information may be tapped out of a lower resolution decode pipeline (M), processed using an interlayer interpolation, and supplied to the next higher resolution decode pipeline (M+1) for use.
- a single decode pipeline may be used to perform the video processing at multiple resolutions.
- the decode pipeline 103 performs the video processing at a first resolution (M) with information being extracted as appropriate.
- the decode pipeline 103 may then performs the video processing at the next resolution (M+1) or at another higher resolution (e.g., M+2). Processing flow may be adjusted by sequencing the flow through the different decoding pipelines 103 as appropriate.
- encoder and transcoder pipelines may share some of the same functionality.
- a video stream is obtained by a video device.
- the video stream includes a plurality of subset bitstreams that may be processed by, e.g., a video decode pipeline of the video device.
- a first subset bitstream having a first resolution is processed in the video pipeline of the video device in box 306 .
- video information associated with the first subset bitstream is extracted (or tapped) from the video pipeline during processing of the first subset bitstream.
- interlayer interpolation is performed on at least a portion of the extracted video information.
- box 312 at least a portion of the extracted video data is provided to a video pipeline of the video device for processing in box 315 of a second subset bitstream having a second resolution higher than the first resolution.
- box 318 if another higher resolution subset bitstream is to be processed, then the flow returns to box 309 where interlayer interpolation is performed on at least a portion of the video information extracted during processing of the second subset bitstream. The flow continues until the processing of a higher subset bitstream ends at box 318 .
- the adaptable video architecture may provide for pixel block size decomposition of the standard pixel block sizes defined by a standard.
- FIG. 4 shown is a flowchart illustrating the decomposition/recomposition of the standard pixel blocks.
- an original pixel block may be decomposed into multiple sub-blocks which are fed through (decoding-encoding-transcoding) pipeline elements in box 406 before recomposing the results in box 409 to form a processed pixel block.
- Each sub-block may be processed by a different pipeline.
- Such multi-element pipelines may also be a single pipeline with multiple coding elements that happen to cycle on each sub-block before recomposition.
- single element decomposition and re-composition may be achieved. Improved performance and efficiencies may be realized through the parallel processing of the sub-blocks.
Abstract
Description
- This application claims priority to copending U.S. provisional application entitled “MULTIMEDIA PROCESSING” having Ser. No. 61/509,797, filed Jul. 20, 2011, the entirety of which is hereby incorporated by reference.
- Processing requirements are advancing as the world turns toward multimedia. The availability of internet multimedia content continues to improve with some sites supporting full high definition video sharing. The added use of video conferencing has also increased the demand for better quality and faster processing. In addition, cell phones are increasingly used as digital cameras and camcorders. The move to mobile equipment is increasing the demand for high resolution image processing with low power consumption.
- Many aspects of the present disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views.
-
FIG. 1 is a graphical representation of an example of a video device in accordance with various embodiments of the present disclosure. -
FIG. 2 is a flow chart illustrating an example of the real time adaptation of video processing in accordance with various embodiments of the present disclosure. -
FIG. 3 is a flow chart illustrating an example of scalable video pipeline processing in accordance with various embodiments of the present disclosure. -
FIG. 4 is a flow chart illustrating an example of pixel block size decomposition of video pixel blocks in accordance with various embodiments of the present disclosure. - Image and multimedia processing may be provided through processing circuits implemented in individual chips or chip sets. For example, the multimedia processing may be implemented with a single chip having flexible and low power architecture. The processor architecture may be configured in hardware and/or software executed by processing hardware (e.g., a processing unit). Most conventional video coding architectures and designs are dedicated (hardware and/or software) to only one video coding standard and for servicing one video stream based thereon at a time.
- The adaptable video architecture is implemented in both hardware and software executed by hardware. An adaptable video (transcode-encode-decode) architecture is configured to fully and simultaneously support any number of video stream types, where each type is defined by one of a plurality of video coding standards. The hardware is time-shared between the multiple streams to provide nearly simultaneous processing of the streams. The net effect of the fine-grained time-sharing is that it appears to a user that the multiple streams are handled simultaneously by the video architecture.
- Most conventional video coding architectures are dedicated to a single video coding standard and for servicing one video stream at a time based upon that video coding standard. Software based architectures may be utilized for multiple standards but service only one stream at a time. In addition, the software based architectures face substantial limitations (especially for cutting edge standards) by not having access to dedicated hardware and for usurping general purpose processing resources. On the other hand, dedicated hardware places different power, space and cost demands on a design. To support multiple video coding standards in the architecture, compromises are made to implement each of the video coding standards: (a) in software (without hardware acceleration); (b) in dedicated hardware; or (c) at an inferior performance level (e.g., at a reduced frame rate, resolution, quality, etc.) via a combination of (a) and (b); or not implement (or support) a video coding standard at all. Further, once such compromises have been made, they become fixed design constraints that may or may not provide adequate service or underutilize the resources in a device under particular streaming circumstances. For example, MPEG2 may not have been implemented with hardware acceleration. However, a user's device may be used 99% of the time viewing MPEG2 streams, all the while dedicated H.264 hardware sits idle.
- The adaptable transcode-encode-decode architecture uses two levels of architectural adaptability to overcome limitations. First, real time adaptation may be used to best support one or more simultaneous video streams. The streams may be of the same or differing video stream types. Second, a flexible architectural offering allows for design decision tailoring to fit a specific platform. For each coding standard (or type), several tiers of support (or stream pathways) may be offered to support multiple simultaneous video streams having the same or differing types. Such tiers involve transcode-encode-decode functional elements that may be carried out in software and/or with hardware acceleration. Serial, cyclic serial, parallel and combinations thereof may all be offered. This overall architectural offering with all underlying tiers may be fully integrated into a device or may be tailored to fit current design constraints by eliminating specific “element” tiers without requiring an underlying redesign.
- Referring to
FIG. 1 , shown is a graphical representation of avideo device 100 including, e.g., a transcoder, encoder, or decoder that includes one ormore hardware pipelines 103 or tiers for processing one or more streams of video data. Eachpipeline 103 includes a plurality ofelements 106 for processing the video stream data. Thepipelines 103 are configured to allow theinterconnections 109 between thepipeline elements 106 to be diverted based upon system conditions of the video device and/or video stream. The pipeline pathway may be reconfigured by diverting at least one of the interconnections allow processing byother pipeline elements 106 and/or bysoftware modules 112 executed by shared general-purpose processing resources of the video device. - All element tiers that make it into a device may function in a real time adaptive way to support shared processing resources for load balancing, multiple video stream conditions that arise during device use, and battery constraints. A pathway adaptation module executed by shared general-purpose processing resources of the video device monitors the conditions of the video device and controls rerouting the pipeline interconnections. Referring to
FIG. 2 , shown is a flow chart illustrating an example of the real time adaptation of apipeline pathway 200. Beginning withbox 203, apipeline pathway 200 is defined for a first video stream. For example, in a decoder, adecode pathway 200 may be defined wherein eachpipeline element 106 is selected for the highest performance but with substantial power utilization to service a single video stream. Thedecode pathway 200 may be implemented in hardware or a combination of hardware and software executed by shared general-purpose processing resources such as, e.g., a processor, application specific chip, and/or other appropriate hardware. Inbox 206, a change in one or more of the system conditions is detected. For example, during the visual presentation of a first video stream, battery conditions may change. - An alternate pathway may be selected in
box 209 based at least in part upon the condition changes. For example, analternative decoder pathway 200 a may be selected which offers better battery performance while delivering acceptable video quality. Thealternate pipeline pathway 200 a may include, e.g., diverting theinterconnections 109 between thepipeline elements 106 for processing byother pipeline elements 106 or by executedsoftware modules 112, bypassing pipeline elements 106 (which may be deactivated to reduce power usage), and/or rerouting to another pipeline pathway.Alternate pipeline pathways 200 a may be selected from a plurality of predefined pipeline pathways based upon a defined set of conditions or may be determined using an expert system (or other appropriate pattern recognition system) based upon the system conditions. If analternate pathway 200 a is selected, then the video stream transitions to the alternate pathway in box 212 (e.g., transition between the twopathways box 206 to detect the next condition change. If an alternate pathway is not selected, then the video stream remains on the current pathway and returns tobox 206 to detect the next condition change. - Another change in conditions may then be detected such as, e.g., a user selecting a second video stream of the same or different type to be displayed in a shared screen arrangement. Again, it is determined in
box 209 if an alternate pathway should be used. For example, the decode architecture may adapt to best support the two streams by selecting various element tiers to form two pipeline pathways, one for processing each of the two streams. Inbox 212, the video streams are transitioned and the sequence returns tobox 206 to detect the next condition change. The sequence continues adapting to additional changes in the conditions. For example, a non-video stream task operating on the device may place a higher demand on shared general-purpose processing resources, which is detected inbox 206. Inbox 209, the decode architecture may adapt to minimize its reliance on such shared resources by selecting otherdecoder pipeline elements 106 that are either less shared-resource consumptive or operate in dedicated hardware. Inbox 212, the streams are transitioned before returning tobox 206. These and other adaptation examples can apply equally to transcoder and encoder elements and tiers as well. - In another embodiment, the adaptable video architecture may provide for a scalable video pipeline. Video processing predicts the current frame content utilizing previous content from previous video frames. For example, H.264 uses this temporal coding for video processing. Other spatial and quality coding may also be used for video processing. Scalable video coding (SVC) is an extension of H.264 that uses video information at different resolutions to predict current frame content. SVC defines a plurality of subset bitstreams, with each subset being independently decodable in a similar fashion as a single H.264 bitstream. Merely by dropping packets from the larger overall bitstream, a subset bitstream can be exposed. Each subset bitstream can represent one or more of scalable resolution, frame rate, and quality video signal. More particularly, the subset bitstreams represent video layers within SVC with the base layer being fully compatible with H.264 (which is a single layer standard definition). When the overall bitstream is transmitted (e.g., by over air broadcast), a receiving device can use the appropriate subset bitstream to perform the video processing. The additional subset bitstream layers can be discarded or used to for temporal, spatial and/or signal quality improvements.
- The adaptable video (transcode-encode-decode) architecture has at least two modes. First, the adaptable architecture is instantiated once for H.264 decode or other single layer standard. Second, the adaptable architecture is instantiated multiple times, each instance designed to accelerate the decoding of one SVC layer to improve the generated video image. For example, a lower resolution H.264 decode pipeline (M) may dump out internal aspects, which may then be read into next higher resolution layer (M+1). Information of values may be tapped out such as, e.g., motion vectors, transform coefficients, and/or image data prior to the application of the deblocking filter for use in the higher resolution pipeline. This may also be applied to multiple layers of progressively higher quality (and/or bitrate) at the same resolution or combined with different resolution layers. For example, a lower quality layer (e.g., signal-to-noise ratio or fidelity) may dump out internal aspects, which may then be read into next higher quality layer. The interlayer interpolations (e.g., up sampling and/or filtering) may be performed externally by software modules executed by shared general-purpose processing resources of the video device, or by dedicated hardware.
- This may be extended to cover modalities to service multiple simultaneous streams, as well as (i) software only modes; (ii) sequential serial instantiation and use; (iii) cyclical serial flows; and (iv) a mix of (ii) and (iii). For example, in some implementations, a decoder may include a plurality of decode pipelines 103 (
FIG. 1 ) with eachdecode pipeline 103 is associated with a different resolution. Thedecode pipelines 103 may be implemented in hardware and/or software modules executed by general-purpose processing resources. Information may be tapped out of a lower resolution decode pipeline (M), processed using an interlayer interpolation, and supplied to the next higher resolution decode pipeline (M+1) for use. In other implementations, a single decode pipeline may be used to perform the video processing at multiple resolutions. In this case, thedecode pipeline 103 performs the video processing at a first resolution (M) with information being extracted as appropriate. Thedecode pipeline 103 may then performs the video processing at the next resolution (M+1) or at another higher resolution (e.g., M+2). Processing flow may be adjusted by sequencing the flow through thedifferent decoding pipelines 103 as appropriate. In addition, encoder and transcoder pipelines may share some of the same functionality. - Referring to
FIG. 3 , shown is a flow chart illustrating an example of scalable video pipeline processing. Beginning with box 303 a video stream is obtained by a video device. The video stream includes a plurality of subset bitstreams that may be processed by, e.g., a video decode pipeline of the video device. A first subset bitstream having a first resolution is processed in the video pipeline of the video device inbox 306. As discussed above, video information associated with the first subset bitstream is extracted (or tapped) from the video pipeline during processing of the first subset bitstream. Inbox 309, interlayer interpolation is performed on at least a portion of the extracted video information. - In
box 312, at least a portion of the extracted video data is provided to a video pipeline of the video device for processing inbox 315 of a second subset bitstream having a second resolution higher than the first resolution. Inbox 318, if another higher resolution subset bitstream is to be processed, then the flow returns tobox 309 where interlayer interpolation is performed on at least a portion of the video information extracted during processing of the second subset bitstream. The flow continues until the processing of a higher subset bitstream ends atbox 318. - In some embodiments, the adaptable video architecture may provide for pixel block size decomposition of the standard pixel block sizes defined by a standard. With reference to
FIG. 4 , shown is a flowchart illustrating the decomposition/recomposition of the standard pixel blocks. Beginning withbox 403, an original pixel block may be decomposed into multiple sub-blocks which are fed through (decoding-encoding-transcoding) pipeline elements inbox 406 before recomposing the results inbox 409 to form a processed pixel block. Each sub-block may be processed by a different pipeline. Such multi-element pipelines may also be a single pipeline with multiple coding elements that happen to cycle on each sub-block before recomposition. In some cases, single element decomposition and re-composition may be achieved. Improved performance and efficiencies may be realized through the parallel processing of the sub-blocks. - It should be emphasized that the above-described embodiments of the present disclosure are merely possible examples of implementations set forth for a clear understanding of the principles of the disclosure. Many variations and modifications may be made to the above-described embodiment(s) without departing substantially from the spirit and principles of the disclosure. All such modifications and variations are intended to be included herein within the scope of this disclosure.
Claims (21)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/731,327 US20150271504A1 (en) | 2011-07-20 | 2015-06-04 | Adaptable video architectures |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201161509797P | 2011-07-20 | 2011-07-20 | |
US13/250,518 US9083951B2 (en) | 2011-07-20 | 2011-09-30 | Adaptable video architectures |
US14/731,327 US20150271504A1 (en) | 2011-07-20 | 2015-06-04 | Adaptable video architectures |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/250,518 Continuation US9083951B2 (en) | 2011-07-20 | 2011-09-30 | Adaptable video architectures |
Publications (1)
Publication Number | Publication Date |
---|---|
US20150271504A1 true US20150271504A1 (en) | 2015-09-24 |
Family
ID=47555718
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/236,822 Active 2032-06-29 US8832412B2 (en) | 2011-07-20 | 2011-09-20 | Scalable processing unit |
US13/250,518 Active 2033-09-18 US9083951B2 (en) | 2011-07-20 | 2011-09-30 | Adaptable video architectures |
US14/731,327 Abandoned US20150271504A1 (en) | 2011-07-20 | 2015-06-04 | Adaptable video architectures |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/236,822 Active 2032-06-29 US8832412B2 (en) | 2011-07-20 | 2011-09-20 | Scalable processing unit |
US13/250,518 Active 2033-09-18 US9083951B2 (en) | 2011-07-20 | 2011-09-30 | Adaptable video architectures |
Country Status (1)
Country | Link |
---|---|
US (3) | US8832412B2 (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9392295B2 (en) | 2011-07-20 | 2016-07-12 | Broadcom Corporation | Adaptable media processing architectures |
GB2496862B (en) * | 2011-11-22 | 2016-06-01 | Canon Kk | Communication of data blocks over a communication system |
WO2015035338A1 (en) * | 2013-09-06 | 2015-03-12 | Futurewei Technologies, Inc. | Method and apparatus for asynchronous processor with a token ring based parallel processor scheduler |
KR102332523B1 (en) * | 2014-12-24 | 2021-11-29 | 삼성전자주식회사 | Apparatus and method for execution processing |
CN110494211A (en) * | 2016-12-12 | 2019-11-22 | 得克萨斯农业及机械体系综合大学 | High temperature insulating component |
US11232056B2 (en) | 2016-12-28 | 2022-01-25 | Intel Corporation | System and method for vector communication |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060059219A1 (en) * | 2004-09-16 | 2006-03-16 | Koshy Kamal J | Method and apparatus for performing modular exponentiations |
US20060126726A1 (en) * | 2004-12-10 | 2006-06-15 | Lin Teng C | Digital signal processing structure for decoding multiple video standards |
US20060188020A1 (en) * | 2005-02-24 | 2006-08-24 | Wang Zhicheng L | Statistical content block matching scheme for pre-processing in encoding and transcoding |
US20120294373A1 (en) * | 2010-01-19 | 2012-11-22 | Renesas Electronics Corporation | Moving image encoding method, moving image decoding method, moving image encoding device, and moving image decoding device |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6480541B1 (en) | 1996-11-27 | 2002-11-12 | Realnetworks, Inc. | Method and apparatus for providing scalable pre-compressed digital video with reduced quantization based artifacts |
GB2382673B (en) | 2001-10-31 | 2005-10-26 | Alphamosaic Ltd | A vector processing system |
GB2382672B (en) * | 2001-10-31 | 2005-10-05 | Alphamosaic Ltd | Repeated instruction execution |
GB2382886B (en) | 2001-10-31 | 2006-03-15 | Alphamosaic Ltd | Vector processing system |
US7036032B2 (en) * | 2002-01-04 | 2006-04-25 | Ati Technologies, Inc. | System for reduced power consumption by phase locked loop and method thereof |
US6976182B1 (en) * | 2002-02-01 | 2005-12-13 | Advanced Micro Devices, Inc. | Apparatus and method for decreasing power consumption in an integrated circuit |
US7944971B1 (en) * | 2002-07-14 | 2011-05-17 | Apple Inc. | Encoding video |
US8054880B2 (en) * | 2004-12-10 | 2011-11-08 | Tut Systems, Inc. | Parallel rate control for digital video encoder with multi-processor architecture and picture-based look-ahead window |
US7426577B2 (en) * | 2003-06-19 | 2008-09-16 | Avaya Technology Corp. | Detection of load balanced links in internet protocol netwoks |
US7441101B1 (en) * | 2003-12-10 | 2008-10-21 | Cisco Technology, Inc. | Thread-aware instruction fetching in a multithreaded embedded processor |
US20070094444A1 (en) * | 2004-06-10 | 2007-04-26 | Sehat Sutardja | System with high power and low power processors and thread transfer |
US8738891B1 (en) * | 2004-11-15 | 2014-05-27 | Nvidia Corporation | Methods and systems for command acceleration in a video processor via translation of scalar instructions into vector instructions |
EP1758426A1 (en) | 2005-08-24 | 2007-02-28 | Alcatel | Network device, interface device and method for exchanging packets |
JP2007318455A (en) * | 2006-05-25 | 2007-12-06 | Matsushita Electric Ind Co Ltd | Transcodec device |
WO2008041271A1 (en) | 2006-09-29 | 2008-04-10 | Fujitsu Microelectronics Limited | Transmitting/receiving system, node and communication method |
US7705880B2 (en) * | 2007-01-17 | 2010-04-27 | Nice Systems Ltd. | Device, system and method for encoding employing redundancy and switching capabilities |
US8848787B2 (en) * | 2007-10-15 | 2014-09-30 | Qualcomm Incorporated | Enhancement layer coding for scalable video coding |
DE102007061986A1 (en) | 2007-12-21 | 2009-06-25 | Bayerische Motoren Werke Aktiengesellschaft | communication system |
US20100268841A1 (en) | 2009-04-20 | 2010-10-21 | Texas Instruments Incorporated | Using higher layer information to facilitate coexistence in wireless networks |
WO2011153194A1 (en) * | 2010-06-02 | 2011-12-08 | Onmobile Global Limited | Method and apparatus for adapting media |
KR101355975B1 (en) | 2010-10-19 | 2014-01-29 | 한국전자통신연구원 | Adaptive multimedia decoding device and method for scalable satellite broadcasting |
US9392295B2 (en) | 2011-07-20 | 2016-07-12 | Broadcom Corporation | Adaptable media processing architectures |
-
2011
- 2011-09-20 US US13/236,822 patent/US8832412B2/en active Active
- 2011-09-30 US US13/250,518 patent/US9083951B2/en active Active
-
2015
- 2015-06-04 US US14/731,327 patent/US20150271504A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060059219A1 (en) * | 2004-09-16 | 2006-03-16 | Koshy Kamal J | Method and apparatus for performing modular exponentiations |
US20060126726A1 (en) * | 2004-12-10 | 2006-06-15 | Lin Teng C | Digital signal processing structure for decoding multiple video standards |
US20060188020A1 (en) * | 2005-02-24 | 2006-08-24 | Wang Zhicheng L | Statistical content block matching scheme for pre-processing in encoding and transcoding |
US20120294373A1 (en) * | 2010-01-19 | 2012-11-22 | Renesas Electronics Corporation | Moving image encoding method, moving image decoding method, moving image encoding device, and moving image decoding device |
Also Published As
Publication number | Publication date |
---|---|
US9083951B2 (en) | 2015-07-14 |
US20130024652A1 (en) | 2013-01-24 |
US20130022101A1 (en) | 2013-01-24 |
US8832412B2 (en) | 2014-09-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20150271504A1 (en) | Adaptable video architectures | |
US8861591B2 (en) | Software video encoder with GPU acceleration | |
RU2426267C2 (en) | Improved inter-layer prediction for extended spatial scalability in video coding | |
US9288497B2 (en) | Advanced video coding to multiview video coding transcoder | |
US9392295B2 (en) | Adaptable media processing architectures | |
US8780991B2 (en) | Motion estimation in enhancement layers in video encoding | |
EP3013065A1 (en) | Information processing device and method | |
CA2661771C (en) | Video multiviewer system with serial digital interface and related methods | |
JP2019092179A (en) | Bandwidth saving architecture of scalable video coding spatial mode | |
US8170121B2 (en) | H.264/AVC based approach to scalable video compression | |
IL230273A (en) | Transmission of reconstruction data in a tiered signal quality hierarchy | |
CA2661760C (en) | Video multiviewer system with switcher and distributed scaling and related methods | |
EP2850834A1 (en) | Unified fractional search and motion compensation architecture across multiple video standards | |
CA2661768C (en) | Video multiviewer system with distributed scaling and related methods | |
WO2014093175A2 (en) | Video coding including shared motion estimation between multiple independent coding streams | |
WO2002102049A2 (en) | System and method for multi-channel video and audio encoding on a single chip | |
WO2018089146A1 (en) | Conversion buffer to decouple normative and implementation data path interleaving of video coefficients | |
CN114650427A (en) | Load shifting video encoding process to hardware for better density quality tradeoff | |
KR20180116835A (en) | Method of providing video and apparatuses performing the same | |
Pescador et al. | A DSP based H. 264/SVCdecoder for a multimedia terminal | |
Nakamura et al. | Low delay 4K 120fps HEVC decoder with parallel processing architecture | |
US20080282304A1 (en) | Module and architecture for generating real-time, multiple-resolution video streams and the architecture thereof | |
Parois et al. | 4K real time software solution of scalable HEVC for broadcast video application | |
CN1070010C (en) | HDTV video-frequency decoder using SDTV to decode ASIC and its decoding method | |
Mizosoe et al. | A single chip H. 264/AVC HDTV encoder/decoder/transcoder system LSI |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: BROADCOM CORPORATION, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:UPTON, EBEN;VEITCH, GRAHAM;MORGAN, ALAN;AND OTHERS;SIGNING DATES FROM 20110922 TO 20111219;REEL/FRAME:035915/0813 |
|
AS | Assignment |
Owner name: BANK OF AMERICA, N.A., AS COLLATERAL AGENT, NORTH CAROLINA Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:BROADCOM CORPORATION;REEL/FRAME:037806/0001 Effective date: 20160201 Owner name: BANK OF AMERICA, N.A., AS COLLATERAL AGENT, NORTH Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:BROADCOM CORPORATION;REEL/FRAME:037806/0001 Effective date: 20160201 |
|
AS | Assignment |
Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD., SINGAPORE Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BROADCOM CORPORATION;REEL/FRAME:041706/0001 Effective date: 20170120 Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BROADCOM CORPORATION;REEL/FRAME:041706/0001 Effective date: 20170120 |
|
AS | Assignment |
Owner name: BROADCOM CORPORATION, CALIFORNIA Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS;ASSIGNOR:BANK OF AMERICA, N.A., AS COLLATERAL AGENT;REEL/FRAME:041712/0001 Effective date: 20170119 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |