US20150241385A1

US20150241385A1 - Solid state nanopore devices and methods of manufacture

Info

Publication number: US20150241385A1
Application number: US14/706,495
Authority: US
Inventors: Yann Astier; Jingwei Bai; Satyavolu Papa Rao; Kathleen Reuter; Joshua T. Smith
Original assignee: GlobalFoundries US 2 LLC
Current assignee: GlobalFoundries Inc
Priority date: 2013-08-26
Filing date: 2015-05-07
Publication date: 2015-08-27
Also published as: US20150056732A1; US9085120B2; US20150056407A1; US9168717B2

Abstract

Solid state nanopore devices for nanopore applications and methods of manufacture are disclosed herein. The method includes forming a membrane layer on an underlying substrate. The method further includes forming a hole in the membrane layer. The method further comprises plugging the hole with a sacrificial material. The method further includes forming a membrane over the sacrificial material. The method further includes removing the sacrificial material within the hole and portions of the underlying substrate. The method further includes drilling an opening in the membrane, aligned with the hole.

Description

FIELD OF THE INVENTION

The invention relates to solid state nanopore devices and methods of manufacture and, more particularly, to solid state nanopore devices for nanopore applications and methods of manufacture.

BACKGROUND

Solid state nanopore devices have been demonstrated for many potential applications in bio-sensing and other applications. For example, single molecular detection of DNA, RNA, and protein molecules has been realized in solid state nanopore devices. Also, bio-molecule binding affinity has been studied using solid state nanopore devices.
An important factor to improve the nanopore sensitivity to molecular translocation is to reduce the membrane thickness. A major challenge is that the thin membrane, especially when the membrane thickness is in the sub-10 nm regime, is mechanically fragile while suspending over a micron or tens of micron window size. The techniques typically used to generate thin membrane structures at these extremely-scaled sizes, such as reactive ion etch or ion milling to locally thin down a relative thicker membrane, are incapable to incorporate more functional structures on the top of the membrane such as field effect transistors (FETs) or tunneling junction electrodes.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.

SUMMARY

In a first aspect of the invention, a method comprises forming a membrane layer on an underlying substrate. The method further comprises forming a hole in the membrane layer. The method further comprises plugging the hole with a sacrificial material. The method further comprises forming a membrane over the sacrificial material. The method further comprises removing the sacrificial material within the hole. The method further comprises drilling an opening in the membrane, aligned with the hole.
In another aspect of the invention, a method comprises forming a dielectric layer on an underlying substrate. The method further comprises forming a hole in the dielectric layer by lithography and etching processes. The method further comprises plugging the hole with a sacrificial material to form a sacrificial plug. The plugging comprises blanket depositing of an oxide material to a thickness greater than the depth of the hole, and planarizing the oxide material to the surface of the dielectric layer. The method further comprises forming a membrane over the sacrificial plug. The method further comprises removing the sacrificial plug and portions of the underlying substrate. The method further comprises drilling an opening in the membrane, aligned with the hole.
In yet another aspect of the invention, a structure comprises: a dielectric layer on an underlying substrate; a hole in the dielectric layer and underlying substrate; and a membrane over the sacrificial plug having an opening suspended and aligned with the hole.
In another aspect of the invention, a design structure tangibly embodied in a machine readable storage medium for designing, manufacturing, or testing an integrated circuit is provided. The design structure comprises the structures of the present invention. In further embodiments, a hardware description language (HDL) design structure encoded on a machine-readable data storage medium comprises elements that when processed in a computer-aided design system generates a machine-executable representation of the ultrathin membranes for nanopore applications, which comprises the structures of the present invention. In still further embodiments, a method in a computer-aided design system is provided for generating a functional design model of the ultrathin membranes for nanopore applications. The method comprises generating a functional representation of the structural elements of the ultrathin membranes for nanopore applications.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The present invention is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present invention.

FIGS. 1 a-1 f show processes and respective structures in accordance with aspects of the present invention;

FIGS. 2 a-2 d show processes and respective structures in accordance with additional aspects of the present invention;

FIGS. 3 a-3 d show structures in accordance with aspects of the present invention;

FIGS. 4 a and 4 b show bio-sensing structures in accordance with aspects of the present invention; and

FIG. 5 is a flow diagram of a design process used in semiconductor design, manufacture, and/or test.

DETAILED DESCRIPTION

The invention relates to solid state nanopore devices and methods of manufacture and, more particularly, to solid state nanopore devices for nanopore applications and methods of manufacture. In more specific embodiments, the present invention is directed to methods of creating an ultra thin membrane suspended over a few hundred nanometer window supported by a thicker membrane which can span over a micron or tens of microns wide window on a Si wafer. In embodiments, this is achieved by forming a thin membrane film on top of a planarized thick membrane film with a sacrificial plug. After removal of the sacrificial plug, a small sized opening can be formed in the membrane file, aligned with the hole formed by the removal of the sacrificial plug.
Advantageously, fabrication flows of the present invention allow a thin membrane to span only over a small area, which makes it mechanically strong enough to undergo post process and test procedures. Additionally, the thickness of the membrane is dependent on a formation method (e.g., growth or deposition process), which is better controlled than etching methods currently used to form thin membranes. Moreover, the fabricated membrane of the present invention has a flat top surface, making it compatible with additional functional structures such as FET or tunneling junction electrodes.
FIG. 1 a shows a beginning structure and respective processing steps in accordance with aspects of the present invention. In particular, the structure 5 of FIG. 1 includes a substrate 10. The substrate 10 can be, for example, a Si wafer; although other materials are contemplated by the present invention. A thick membrane 12, e.g., dielectric layer, is deposited on the substrate 10. In embodiments, the dielectric layer 12 can be, for example, SiNx, with thickness of about 20 nm to 500 nm. The dielectric layer 12 can be deposited using any conventionally known deposition method, such as, for example, low-pressure chemical vapor deposition (LPCVD).
In embodiments, a hole 14 is formed within the dielectric layer 12. In embodiments, the hole 14 can be formed using standard lithography and etching processes. For example, a resist can be applied to the dielectric layer 12, which is patterned by local exposure to an energy source (e.g., an electron beam). A reactive ion etch (RIE) is performed through the patterned resist to form the hole 14 within the dielectric layer 12 while masking the rest of the dielectric layer 12. The resist can then be stripped or removed using conventional descum or stripping processes, such as oxygen plasma ashing. In embodiments, the hole can be about 200 nm or less in size; although other dimensions are also contemplated by the present invention. In embodiments, the hole can be any desired shape.
In FIG. 1 b, the hole 14 is filled with a sacrificial material 16. In embodiments, the sacrificial material 16 can be, for example, SiO₂, formed by a blanket CVD process or other conventional processes, e.g., plasma enhanced CVD (PECVD) or atomic layer deposition (ALD). In embodiments, the thickness of the sacrificial material 16 should be thicker than the depth of the hole 14.
In FIG. 1 c, the sacrificial material 16 undergoes a planarization process. For example, the sacrificial material 16 can be planarized using a chemical mechanical planarization (CMP) process to planarize the sacrificial material 16 to the surface of the dielectric layer 12. In this way, the sacrificial material 16 will plug the hole 14, resulting in a sacrificial plug 16 a. In embodiments, the CMP process should not cause any significant dishing in the sacrificial plug 16 a, depending on the size of the original hole 14.
In FIG. 1 d, an arbitrary thickness of membrane material 18 is deposited on top of the planarized substrate, e.g., sacrificial plug 16 a and dielectric layer 12. In this case, the membrane thickness 18 can be as thin as a few nanometers, depending on the size of the sacrificial plug 16 a. In embodiments, the membrane material 18 can be, for example, SiNx, with thickness of about 10 nm. The membrane material 18 can be blanket deposited using any conventionally known deposition method, e.g., LPCVD.
As shown in FIG. 1 e, the sacrificial plug 16 a and portions of the underlying substrate 10 are removed using conventional etching techniques, such as RIE or wet etch processes. In embodiments, the underlying substrate 10 and sacrificial plug 16 a can be removed using different etching steps, each of which is selective to the material being etched, e.g., Si material and oxide material. For example, oxide material can be etched using an HF₂dip or dilute buffered oxide etch (BOE) process. In embodiments, the removal of the sacrificial plug area will result in a hole 20.
In FIG. 1 f, the membrane material 18 undergoes a drilling process to open a hole (opening) 22 in the membrane material 18. In embodiments, the opening 22 is aligned with the hole 20 (resulting from the removal of the oxide material). More specifically, the opening 22 is suspended over the hole 20, formed in the dielectric layer 12. The opening 22 can be from 1 nm to about 30 nm in diameter. Functional electrodes with a very narrow gap may be used as a mask to achieve the smaller hole sizes of 1 nm to 5 nm. The opening 22 can be formed by a transmission electron microscopy (TEM) process or focused ion beam (FIB) process, from either the front side or back side of the structure (although formation from the back side is preferred). As should be understood by those of ordinary skill in the art, the TEM process is a microscopy technique whereby a beam of electrons is transmitted through a thin specimen, e.g., membrane material 18. The opening 22 can be drilled by either process within seconds of beam focus.
FIGS. 2 a-2 d show processes and respective structures in accordance with additional aspects of the present invention. More specifically, starting from the structure of FIG. 1 c, an option sacrificial material 16 b is formed over the planarized substrate, e.g., sacrificial plug 16 a and dielectric layer 12. In this case, the option sacrificial material 16 b can have a thickness of about a few nanometers. In embodiments, the option sacrificial material 16 b can be, for example, SiO₂or other dielectric material, and is preferably the same material as used for the sacrificial plug 16 a. In embodiments, the option sacrificial material 16 b can be grown and, if necessary, planarized using CMP processes. The option sacrificial material 16 b can be used to minimize edge erosion and possible dishing effect which may occurs to the sacrificial plug 16 a, thereby enabling a flatter surface to be achieved, such as might be necessary for the inclusion of thin function electrodes, for example.
In FIG. 2 b, an arbitrary thickness of membrane material 18 is deposited on top of the planarized substrate, e.g., option sacrificial material 16 b. In this case, the membrane thickness 18 can be as thin as a few nanometers. In embodiments, the membrane material 18 can be, for example, SiNx, with thickness of about 10 nm. The membrane material 18 can be blanket deposited using any conventionally known deposition method, e.g., LPCVD.
As shown in FIG. 2 c, the sacrificial plug 16 a and portions of the underlying substrate 10 are removed using conventional etching techniques. In embodiments, the underlying substrate 10 and sacrificial plug area 16 a can be removed using different etching steps, each of which is selective to the material being etched, e.g., Si material and oxide material. For example, oxide material can be etched using an HF₂dip or dilute (BOE). In embodiments, the removal of the sacrificial plug 16 a will result in a hole 20 and undercut (air gap) formation 24 between the membrane material 18 and the dielectric layer 12.
In FIG. 2 d, the membrane material 18 undergoes a drilling process to open a hole (opening) 22 in the membrane material 18. In embodiments, the opening 22 is aligned with the hole 20 (resulting from the removal of the oxide material), and can be about 1 nm to about 30 nm in diameter. Functional electrodes with a very narrow gap may be used as a mask to achieve the smaller hole sizes of 1 nm to 5 nm. As in the previous aspect of the present invention, the opening 22 is suspended over the hole 20, and is formed by a transmission electron microscopy (TEM) process or focused ion beam (FIB) process, from either the front side or back side of the structure (although formation from the back side is preferred).
FIGS. 3 a-3 d show various views of the structures fabricated in the processes described above. More specifically, FIGS. 3 a and 3 b show structures fabricated in accordance with the processes described with regard to FIGS. 2 a-2 d; whereas, FIGS. 3 c and 3 d show structures fabricated in accordance with the processes described with regard to FIGS. 1 a-1 f. In the embodiments shown in FIGS. 3 a-3 d, the dielectric material (dielectric material 12) is SiNx, deposited to a thickness of about 50 nm with a locally patterned hole array (holes 14), each having a width of about 200 nm. The holes are filled with TEOS oxide and then polished down. The membrane 18, e.g., nitride film, is deposited to a thickness of about 10 nm. FIG. 3 b shows the undercut 24; whereas, FIG. 3 d is devoid of the undercut (due to the fact that a second oxide layer (e.g., layer 16 b) is not used in the fabrication process).
FIG. 4 a shows a structure starting from the structure of FIG. 1 f; whereas, FIG. 4 b shows a structure starting from the structure of FIG. 2 d. In particular, FIGS. 4 a and 4 b show a structure 5′ and 5″, respectively, with electrodes 26 positioned on both sides of the opening 22. In embodiments, the electrodes 26 can be fabricated using any conventional metal deposition and patterning processes. For example, metal or metal alloy material, e.g., palladium, gold, or other metal, can be deposited using an electron-beam, sputter, or thermal deposition process. The metal can then be patterned by conventional RIE processes, known to those of skill in the art, to form the electrodes 26. In embodiments, the electrodes 26 can be representative of a FET or tunneling junction electrodes.
FIG. 5 is a flow diagram of a design process used in semiconductor design, manufacture, and/or test. FIG. 5 shows a block diagram of an exemplary design flow 900 used for example, in semiconductor IC logic design, simulation, test, layout, and manufacture. Design flow 900 includes processes, machines and/or mechanisms for processing design structures or devices to generate logically or otherwise functionally equivalent representations of the design structures and/or devices described above and shown in FIGS. 1 a-1 f, 2 a-2 d, 3 a-3 d, 4 a and 4 b. The design structures processed and/or generated by design flow 900 may be encoded on machine-readable transmission or storage media to include data and/or instructions that when executed or otherwise processed on a data processing system generate a logically, structurally, mechanically, or otherwise functionally equivalent representation of hardware components, circuits, devices, or systems. Machines include, but are not limited to, any machine used in an IC design process, such as designing, manufacturing, or simulating a circuit, component, device, or system. For example, machines may include: lithography machines, machines and/or equipment for generating masks (e.g. e-beam writers), computers or equipment for simulating design structures, any apparatus used in the manufacturing or test process, or any machines for programming functionally equivalent representations of the design structures into any medium (e.g. a machine for programming a programmable gate array).
Design flow 900 may vary depending on the type of representation being designed. For example, a design flow 900 for building an application specific IC (ASIC) may differ from a design flow 900 for designing a standard component or from a design flow 900 for instantiating the design into a programmable array, for example a programmable gate array (PGA) or a field programmable gate array (FPGA) offered by Altera® Inc. or Xilinx® Inc.
FIG. 5 illustrates multiple such design structures including an input design structure 920 that is preferably processed by a design process 910. Design structure 920 may be a logical simulation design structure generated and processed by design process 910 to produce a logically equivalent functional representation of a hardware device. Design structure 920 may also or alternatively comprise data and/or program instructions that when processed by design process 910, generate a functional representation of the physical structure of a hardware device. Whether representing functional and/or structural design features, design structure 920 may be generated using electronic computer-aided design (ECAD) such as implemented by a core developer/designer. When encoded on a machine-readable data transmission, gate array, or storage medium, design structure 920 may be accessed and processed by one or more hardware and/or software modules within design process 910 to simulate or otherwise functionally represent an electronic component, circuit, electronic or logic module, apparatus, device, or system such as those shown in FIGS. 1 a-1 f, 2 a-2 d, 3 a-3 d, 4 a and 4 b. As such, design structure 920 may comprise files or other data structures including human and/or machine-readable source code, compiled structures, and computer-executable code structures that when processed by a design or simulation data processing system, functionally simulate or otherwise represent circuits or other levels of hardware logic design. Such data structures may include hardware-description language (HDL) design entities or other data structures conforming to and/or compatible with lower-level HDL design languages such as Verilog and VHDL, and/or higher level design languages such as C or C++.
Design process 910 preferably employs and incorporates hardware and/or software modules for synthesizing, translating, or otherwise processing a design/simulation functional equivalent of the components, circuits, devices, or logic structures shown in FIGS. 1 a-1 f, 2 a-2 d, 3 a-3 d, 4 a and 4 b to generate a netlist 980 which may contain design structures such as design structure 920. Netlist 980 may comprise, for example, compiled or otherwise processed data structures representing a list of wires, discrete components, logic gates, control circuits, I/O devices, models, etc. that describes the connections to other elements and circuits in an integrated circuit design. Netlist 980 may be synthesized using an iterative process in which netlist 980 is resynthesized one or more times depending on design specifications and parameters for the device. As with other design structure types described herein, netlist 980 may be recorded on a machine-readable data storage medium or programmed into a programmable gate array. The medium may be a non-volatile storage medium such as a magnetic or optical disk drive, a programmable gate array, a compact flash, or other flash memory. Additionally, or in the alternative, the medium may be a system or cache memory, buffer space, or electrically or optically conductive devices and materials on which data packets may be transmitted and intermediately stored via the Internet, or other networking suitable means.
Design process 910 may include hardware and software modules for processing a variety of input data structure types including netlist 980. Such data structure types may reside, for example, within library elements 930 and include a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.). The data structure types may further include design specifications 940, characterization data 950, verification data 960, design rules 970, and test data files 985 which may include input test patterns, output test results, and other testing information. Design process 910 may further include, for example, standard mechanical design processes such as stress analysis, thermal analysis, mechanical event simulation, process simulation for operations such as casting, molding, and die press forming, etc. One of ordinary skill in the art of mechanical design can appreciate the extent of possible mechanical design tools and applications used in design process 910 without deviating from the scope and spirit of the invention. Design process 910 may also include modules for performing standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc.
Design process 910 employs and incorporates logic and physical design tools such as HDL compilers and simulation model build tools to process design structure 920 together with some or all of the depicted supporting data structures along with any additional mechanical design or data (if applicable), to generate a second design structure 990.
Design structure 990 resides on a storage medium or programmable gate array in a data format used for the exchange of data of mechanical devices and structures (e.g. information stored in a IGES, DXF, Parasolid XT, JT, DRG, or any other suitable format for storing or rendering such mechanical design structures). Similar to design structure 920, design structure 990 preferably comprises one or more files, data structures, or other computer-encoded data or instructions that reside on transmission or data storage media and that when processed by an ECAD system generate a logically or otherwise functionally equivalent form of one or more of the embodiments of the invention shown in FIGS. 1 a-1 f, 2 a-2 d, 3 a-3 d, 4 a and 4 b. In one embodiment, design structure 990 may comprise a compiled, executable HDL simulation model that functionally simulates the devices shown in FIGS. 1 a-1 f, 2 a-2 d, 3 a-3 d, 4 a and 4 b.
Design structure 990 may also employ a data format used for the exchange of layout data of integrated circuits and/or symbolic data format (e.g. information stored in a GDSII (GDS2), GL1, OASIS, map files, or any other suitable format for storing such design data structures). Design structure 990 may comprise information such as, for example, symbolic data, map files, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a manufacturer or other designer/developer to produce a device or structure as described above and shown in FIGS. 1 a-1 f, 2 a-2 d, 3 a-3 d, 4 a and 4 b. Design structure 990 may then proceed to a stage 995 where, for example, design structure 990: proceeds to tape-out, is released to manufacturing, is released to a mask house, is sent to another design house, is sent back to the customer, etc.
The method as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

What is claimed is:

1. A method, comprising:

forming a membrane layer on an underlying semiconductor substrate;

forming a hole in the membrane layer;

plugging the hole with a sacrificial plug;

forming a membrane over the sacrificial plug;

removing the sacrificial plug and portions of the underlying semiconductor substrate; and

drilling an opening in the membrane, aligned with the hole, after the sacrificial plug and portions of the underlying semiconductor substrate have been removed.

2. The method of claim 1, further comprising:

forming an optional sacrificial material over the sacrificial plug; and

forming the membrane directly over a top surface of the optional sacrificial material.

3. The method of claim 2, wherein the optional sacrificial material is a same material as used for the sacrificial plug.

4. The method of claim 2, further comprising:

removing portions of the optional sacrificial material,

wherein the membrane remains directly over remaining portions of the optional sacrificial material during the removing step.

5. The method of claim 4, wherein the removing of the portions of the optional sacrificial material forms an air gap between the membrane layer and the membrane.

6. The method of claim 1, wherein the membrane layer and the membrane are both SiNx, and

wherein the membrane layer is formed to a thickness of about 20 nm to 500 nm using low-pressure chemical vapor deposition (LPCVD) processes and the membrane has a thickness of about 10 nm.

7. The method of claim 1, wherein the opening is about 5 nm in diameter, suspended over the hole in the membrane layer.

8. The method of claim 1, wherein a sacrificial material is blanketed deposited to a thickness greater than a depth of the hole and is thereafter planarized to form the sacrificial plug.

9. A method, comprising:

forming a membrane layer on an underlying semiconductor substrate;

forming a hole in the membrane layer;

plugging the hole with a sacrificial material, wherein the sacrificial material is blanketed deposited to a thickness greater than a depth of the hole and is thereafter planarized to form a sacrificial plug;

forming a membrane over the sacrificial plug;

removing the sacrificial plug within the hole and portions of the underlying semiconductor substrate; and

10. The method of claim 9, further comprising:

forming an optional sacrificial material over the sacrificial plug; and

11. The method of claim 10, wherein the optional sacrificial material is a same material as used for the sacrificial plug.

12. The method of claim 10, further comprising:

removing portions of the optional sacrificial material,

13. The method of claim 12, wherein the removing of the portions of the optional sacrificial material forms an air gap between the membrane layer and the membrane.