US20150099339A1 - Non-volatile memory device and method for fabricating the same - Google Patents

Non-volatile memory device and method for fabricating the same Download PDF

Info

Publication number
US20150099339A1
US20150099339A1 US14/569,035 US201414569035A US2015099339A1 US 20150099339 A1 US20150099339 A1 US 20150099339A1 US 201414569035 A US201414569035 A US 201414569035A US 2015099339 A1 US2015099339 A1 US 2015099339A1
Authority
US
United States
Prior art keywords
layer
gate electrode
sacrificial
forming
inter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US14/569,035
Other versions
US9159570B2 (en
Inventor
Min-Soo Kim
Dong-Sun Sheen
Seung-Ho Pyi
Sung-Jin Whang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
SK Hynix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SK Hynix Inc filed Critical SK Hynix Inc
Priority to US14/569,035 priority Critical patent/US9159570B2/en
Assigned to SK Hynix Inc. reassignment SK Hynix Inc. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KIM, MIN-SOO, PYI, SEUNG-HO, SHEEN, DONG-SUN, WHANG, SUNG-JIN
Publication of US20150099339A1 publication Critical patent/US20150099339A1/en
Application granted granted Critical
Publication of US9159570B2 publication Critical patent/US9159570B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H01L21/28282—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H01L27/11582—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors

Definitions

  • Exemplary embodiments of the present invention relate to a non-volatile memory device and a fabrication method thereof, and more particularly, to a non-volatile memory device having a three-dimensional structure where a plurality of memory cells are stacked vertically from a substrate, and a method for fabricating the non-volatile memory device.
  • Non-volatile memory devices retain data although power is turned off.
  • various nonvolatile memory devices such as a flash memory, have been widely used.
  • non-volatile memory device having a two-dimensional structure where memory cells are formed in a single layer may reach a limit
  • a non-volatile memory device having a three-dimensional structure where a plurality of memory cells are formed along the channels that are extend vertically from a semiconductor substrate have been suggested. More specifically, non-volatile memory devices having a three-dimensional structure are divided into devices having a linear channel layers and devices having U-shaped channel layers.
  • a charge-trapping-type non-volatile memory device generally includes a memory layer between a channel layer and a gate electrode, and the memory layer includes a charge blocking layer, a charge storage layer, and a channel insulation layer.
  • erase operation characteristics of a charge-trapping-type non-volatile memory device are deteriorated due to back tunneling that occurs as the electrons are introduced to the charge storage layer through the charge blocking layer when a memory cell performs an erase operation.
  • a method of forming the charge blocking layer thick or a method of using a high dielectric layer is suggested.
  • preventing the charges from being introduced from the charge blocking layer to the charge storage layer may be difficult, and the size of the non-volatile memory device may be increased.
  • An embodiment of the present invention is directed to a non-volatile memory device that may improve erase operation characteristics by suppressing back tunneling of electrons by substituting a charge blocking layer interposed between a gate electrode and a charge storage layer with an air gap, and a method for fabricating the non-volatile memory device.
  • a non-volatile memory device includes: a channel layer vertically extending from a substrate; a plurality of inter-layer dielectric layers and a plurality of gate electrodes that are alternately stacked along the channel layer; and an air gap interposed between the channel layer and each of the plurality of gate electrodes.
  • a method for fabricating a non-volatile memory device includes: alternately stacking a plurality of inter-layer dielectric layers and a plurality of first and second sacrificial layers over a substrate;
  • channel holes that expose the substrate by selectively etching the inter-layer dielectric layers and the first and second sacrificial layers; sequentially forming a charge blocking layer, a charge storage layer, a tunnel insulation layer, and a channel layer along internal walls of the channel holes; forming slit holes through the first and second sacrificial layers and the inter-layer dielectric layers on both sides of each channel hole; removing the first sacrificial layers exposed through the slit holes; forming a first gate electrode layer pattern in a space created by removing the first sacrificial layers; removing the second sacrificial layers; and forming a second gate electrode layer for coupling a pair of the first gate electrode layer patterns with each other with the air gap formed between the pair of first gate electrode layer patterns, wherein the air gap is formed by removing the second sacrificial layers.
  • FIGS. 1A to 1G are cross-sectional views illustrating a non-volatile memory device and a fabrication method thereof in accordance with a first embodiment of the present invention.
  • FIGS. 2A to 2I are cross-sectional views illustrating a non-volatile memory device and a fabrication method thereof in accordance with a second embodiment of the present invention.
  • first layer is referred to as being “on” a second layer or “on” a substrate, it not only refers to a case where the first layer is formed directly on the second layer or the substrate but also a case where a third layer exists between the first layer and the second layer or the substrate.
  • FIGS. 1A to 1G are cross-sectional views illustrating a non-volatile memory device and a fabrication method thereof in accordance with a first embodiment of the present invention.
  • FIG. 1G is a cross-sectional view illustrating the non-volatile memory device in accordance with the first embodiment of the present invention.
  • FIGS. 1A to 1F are cross-sectional view illustrating a process for fabricating the non-volatile memory device show in FIG. 1G .
  • an inter-layer dielectric layer 120 , a first sacrificial layer 125 , a second sacrificial layer 130 , and a third sacrificial layer 135 are sequentially and repeatedly stacked over a substrate 100 .
  • the substrate 100 may be a semiconductor substrate such as a monocrystalline silicon substrate, and the substrate 100 may include an understructure (not shown).
  • the structure where the inter-layer dielectric layer 120 and the first to third sacrificial layers 125 , 130 , and 135 are sequentially and repeatedly stacked is referred to as a gate structure.
  • the inter-layer dielectric layer 120 may be disposed in the lowermost portion and the uppermost portion of the gate structure.
  • the inter-layer dielectric layer 120 may be formed of an oxide-based material such as silicon oxide (SiO 2 ).
  • SiO 2 silicon oxide
  • the drawings show that the first to third sacrificial layers 125 , 130 , and 135 are stacked four times, the present invention is not limited to four sets of the first to third sacrificial layers 125 , 130 , and 135 , and the first to third sacrificial layers 125 , 130 , and 135 may be stacked more than four times or less than four times.
  • the first sacrificial layer 125 and the third sacrificial layer 135 are removed in a subsequent process to provide a space where a first gate electrode layer is to be formed.
  • the first sacrificial layer 125 and the third sacrificial layer 135 may be formed of a material having an etch selectivity against the second sacrificial layer 130 and the inter-layer dielectric layer 120 .
  • the first sacrificial layer 125 and the third sacrificial layer 135 may be formed of a nitride.
  • the second sacrificial layer 130 is removed in a subsequent process to provide a path for forming an air gap, which is to be described later.
  • the second sacrificial layer 130 may be formed of a material having an etch selectivity against the first sacrificial layer 125 , the third sacrificial layer 135 , and the inter-layer dielectric layer 120 .
  • the first sacrificial layer 125 and the third sacrificial layer 135 may be formed of polysilicon.
  • channel holes H 1 are formed to expose the substrate 100 by selectively etching the gate structure.
  • the channel holes H 1 may have a round or oval shape when seen from above, and a plurality of channel holes H 1 may be arrayed in a matrix form.
  • a charge blocking layer 140 prevents charges in the charge storage layer 145 from transferring to a layer outside of the charge storage layer 145 .
  • the charge blocking layer 140 may be formed of an oxide layer.
  • the charge storage layer 145 stores data by trapping charges.
  • the charge storage layer 145 may be formed of a nitride layer.
  • the tunnel insulation layer 150 performs a charge tunneling, and it may be formed of an oxide layer.
  • a channel layer 155 is formed in the channel holes Hi.
  • the channel layer 155 may be formed of a semiconductor material, e.g., polysilicon. Although the channel layer 155 may be formed to completely fill the channel holes H 1 in the embodiment of the present invention, the scope of the present invention is not limited a channel layer that completely fills the channel holes HI. According to another embodiment, the channel layer 155 may not be formed to completely fill with the channel layer 155 .
  • a protective layer having an etch selectivity against the first sacrificial layer 125 , the second sacrificial layer 130 , and the third sacrificial layer 135 may be formed over the gate structure including the channel layer 155 to prevent the charge storage layer 145 or the channel layer 155 from being lost in the course of a subsequent process that removes the first sacrificial layer 125 , the second sacrificial layer 130 , and the third sacrificial layer 135 .
  • slit holes T formed through the inter-layer dielectric layer 120 and the first to third sacrificial layers 125 , 130 , and 135 are formed by selectively etching the gate structure on both sides of each channel hole H 1 .
  • the slit holes T may be arrayed in parallel to each other in a form of slit extending in a direction crossing the cross-sectional direction of the drawings.
  • the first sacrificial layer 125 and the third sacrificial layer 135 that are exposed by the slit holes T are removed.
  • a wet etch process using the etch selectivity against the inter-layer dielectric layer pattern 120 A and the second sacrificial layer pattern 130 A may be performed to remove the first sacrificial layer 125 and the third sacrificial layer 135 .
  • the inter-layer dielectric layer 120 and the second sacrificial layer 130 that are not etched or removed are referred to as an inter-layer dielectric layer pattern 120 A and a second sacrificial layer pattern 130 A, respectively.
  • the understructure of the substrate 100 may be protected from being damaged in the process of removing the second sacrificial layer pattern 130 A by implanting an impurity, such as boron (B), into the substrate 100 exposed through the slit holes T to give the exposed substrate 100 an etch selectivity against the second sacrificial layer pattern 130 A.
  • an impurity such as boron (B)
  • a barrier metal layer 160 is formed along walls a resultant structured formed by removing the first sacrificial layer 125 and the third sacrificial layer 135 .
  • the barrier metal layer 160 improves interface characteristics between a first gate electrode layer, which is to be described later, and the inter-layer dielectric layer pattern 120 A, the second sacrificial layer pattern 130 A, and the charge blocking layer 140 .
  • the barrier metal layer 160 may be formed by conformally depositing a titanium nitride (TiN).
  • a conductive layer 165 for forming a first gate electrode which is referred to as a first gate electrode-forming conductive layer 165 , is formed over the barrier metal layer 160 to fill a space created by removing the first sacrificial layer 125 and the third sacrificial layer 135 .
  • the first gate electrode-forming conductive layer 165 may be formed by depositing a conductive material, such as metal, through an Atomic Layer Deposition (ALD) process or a Chemical Vapor Deposition (CVD) process.
  • ALD Atomic Layer Deposition
  • CVD Chemical Vapor Deposition
  • the first gate electrode-forming conductive layer 165 may be formed by forming a tungsten (W) core first and subsequently depositing a bulk tungsten.
  • the first gate electrode-forming conductive layer 165 and the barrier metal layer 160 are etched until the sides of the second sacrificial layer pattern 130 A and the inter-layer dielectric layer pattern 120 A are exposed to isolate the barrier metal layer 160 and the first gate electrode-forming conductive layer 165 for each layer.
  • barrier metal layer 160 It is desirable to minimize the volume of the barrier metal layer 160 , which has a relatively high resistance value, and the barrier metal layer 160 may be etched deeper than the first gate electrode-forming conductive layer 165 as a result of the etch rate difference between the barrier metal layer 160 and the first gate electrode-forming conductive layer 165 .
  • the barrier metal layer 160 and the first gate electrode-forming conductive layer 165 that are not etched between the inter-layer dielectric layer pattern 120 A and the second sacrificial layer pattern 130 A are referred to as a barrier metal layer pattern 160 A and a first gate electrode layer 165 A, respectively.
  • the charge blocking layer 140 is exposed by removing the second sacrificial layer pattern 130 A.
  • the second sacrificial layer pattern 130 A may be removed through a wet etch process using the etch selectivity against the inter-layer dielectric layer pattern 120 A, the barrier metal layer pattern 160 A, and the first gate electrode layer 165 A.
  • the removed portion of the charge blocking layer 140 may be the portion of the charge blocking layer 140 that contacts the barrier metal layer pattern 160 A, and the charge blocking layer 140 that is not removed is referred to as a charge blocking layer pattern 140 A.
  • the portion of the charge blocking layer 140 may be removed through a wet etch process that is performed using the etch selectivity against the barrier metal layer pattern 160 A and the first gate electrode layer 165 A. Since a portion of the inter-layer dielectric layer pattern 120 A is removed and recessed during the wet etch process, the first gate electrode layer 165 A may extend further into the slit holes T than the inter-layer dielectric layer pattern 120 A.
  • a second gate electrode layer 170 that covers an air gap 175 , which is formed by removing the second sacrificial layer pattern 130 A and the portion of the charge blocking layer 140 , is formed.
  • the second gate electrode layer 170 couples a pair of adjacent first gate electrode layers 165 A, and the second gate electrode layer 170 may extend into the slit hole T from the inter-layer dielectric layer pattern 120 A.
  • a gate electrode formed of the first gate electrode layer 165 A and the second gate electrode layer 170 is formed.
  • the second gate electrode layer 170 may include a metal.
  • the second gate electrode layer 170 may be formed by selectively depositing a bulk tungsten without a nucleation tungsten.
  • the first gate electrode layer 165 A is formed of tungsten and the second gate electrode layer 170 is formed by depositing a bulk tungsten through a selective deposition process, the tungsten is deposited on the existing tungsten layer, which is the first gate electrode layer 165 A. Therefore, mask process and a gate electrode isolation process may not be further performed.
  • the second gate electrode layer 170 when the second gate electrode layer 170 is formed through the selective deposition process, an electrical bridge may be prevented from occurring between the second gate electrode layers 170 . Also, since the influence of a loading effect is minimized, tungsten may be uniformly deposited to the edge of a memory cell.
  • the non-volatile memory device in accordance with the first embodiment of the present invention may be fabricated through the fabrication method described above.
  • the non-volatile memory device in accordance with the first embodiment of the present invention includes the channel layer 155 that is extends vertically from the substrate 100 , the multiple inter-layer dielectric layer patterns 120 A and the multiple gate electrodes that are alternately stacked along the channel layer 155 , the charge storage layer 145 interposed between the channel layer 155 and each gate electrode, the air gap 175 interposed between the gate electrode and the charge storage layer 145 , the tunnel insulation layer 150 interposed between the charge storage layer 145 and the channel layer 155 , and the barrier metal layer pattern 160 A interposed between the inter-layer dielectric layer pattern 120 A and the gate electrode.
  • Each of the gate electrodes may be formed of the first gate electrode layer 165 A and the second gate electrode layer 170 that is coupled with the first gate electrode layer 165 A. Particularly, the gate electrode extends in one direction while surrounding the channel layer 155 , and the gate electrode may have a portion extending into the slit hole T from the inter-layer dielectric layer pattern 120 A.
  • FIGS. 2A to 2I are cross-sectional views illustrating a non-volatile memory device and a fabrication method thereof in accordance with a second embodiment of the present invention. While describing the second embodiment of the present invention, description of portions that are substantially the same as the first embodiment is omitted.
  • a first pass gate electrode layer 105 is formed over a substrate 100 .
  • the substrate 100 may be a semiconductor substrate such as a monocrystalline silicon substrate, and the first pass gate electrode layer 105 may be formed of a conductive material, such as doped polysilicon or metal.
  • the first pass gate electrode layer 105 is selectively etched to form a groove, and a sacrificial layer pattern 110 is formed in the groove.
  • the sacrificial layer pattern 110 is removed in a subsequent process to provide a space where sub-channel holes are to be formed.
  • the sacrificial layer pattern 110 may be formed of a material having an etch selectivity against the first pass gate electrode layer 105 , a second pass gate electrode layer 115 , and a gate structure. Also, the sacrificial layer pattern 110 is arrayed in a matrix form when seen from above, and the sacrificial layer pattern 110 may have a shape of island having a longitudinal axis in the cross-sectional direction shown in the drawing and a short axis of a direction crossing the cross-sectional direction shown in the drawing.
  • a second pass gate electrode layer 115 is formed over the first pass gate electrode layer 105 and the sacrificial layer pattern 110 .
  • the second pass gate electrode layer 115 may be formed of a conductive material, such as a doped polysilicon or metal.
  • the first pass gate electrode layer 105 and the second pass gate electrode layer 115 are gate electrodes of a pass transistor and may have a shape surrounding the sacrificial layer pattern 110 .
  • an inter-layer dielectric layer 120 , a first sacrificial layer 125 , a second sacrificial layer 130 , and a third sacrificial layer 135 are sequentially and repeatedly stacked over the second pass gate electrode layer 115 .
  • the inter-layer dielectric layer 120 may be formed of an oxide-based material
  • the first sacrificial layer 125 and the third sacrificial layer 135 are removed in a subsequent process to provide a space where a first gate electrode layer is to be formed.
  • the first sacrificial layer 125 and the third sacrificial layer 135 may be formed of a material having an etch selectivity against the second sacrificial layer 130 and the inter-layer dielectric layer 120 .
  • the second sacrificial layer 130 is a layer used to form an air gap, which is to be described later, and the second sacrificial layer 130 may be formed of a material having an etch selectivity against the first sacrificial layer 125 , the third sacrificial layer 135 , and the inter-layer dielectric layer 120 .
  • a pair of channel holes H 1 that exposes the sacrificial layer pattern 110 is formed by selectively etching the gate structure and the second pass gate electrode layer 115 .
  • the pair of the channel holes H 1 provides a space for forming a channel layer, which is to be described later, and a pair of channel holes H 1 may be disposed for each sacrificial layer pattern 110 .
  • the sacrificial layer pattern 110 exposed through the pair of the channel holes H 1 is removed.
  • the sacrificial layer pattern 110 may be removed through a wet etch process, which is performed using the etch selectivity against the first pass gate electrode layer 105 , the second pass gate electrode layer 115 , and the gate structure.
  • sub-channel holes H 2 for coupling the pair of the channel holes H 1 are formed in the space created by removing the sacrificial layer pattern 110 .
  • a charge blocking layer 140 , a charge storage layer 145 , and a tunnel insulation layer 150 are sequentially formed along internal walls of the pair of the channel holes H 1 and the sub-channel holes H 2 .
  • the charge blocking layer 140 , the charge storage layer 145 , and the tunnel insulation layer 150 are sequentially formed.
  • the charge blocking layer 140 , the charge storage layer 145 , and the tunnel insulation layer 150 may have a triple-layer structure of oxide-nitride-oxide (ONO).
  • a channel layer 155 is formed in the pair of the channel holes H 1 and the sub-channel holes H 2 .
  • the channel layer 155 may be divided into a main channel layer that is used as a channel for a selection transistor or a memory cell and a sub-channel layer that is used as a channel for a pass transistor.
  • the channel layer 155 may be formed of a semiconductor material, such as polysilicon.
  • slit holes T formed through the inter-layer dielectric layer 120 and the first to third sacrificial layers 125 , 130 and 135 are formed by selectively etching the gate structure on both sides of each channel hole Hi.
  • the slit holes T may be arrayed in parallel to each other in a form of slit extending in a direction crossing the cross-sectional direction of the drawings.
  • the first sacrificial layer 125 and the third sacrificial layer 135 that are exposed by the slit holes T are removed.
  • a wet etch process using the etch selectivity against the inter-layer dielectric layer pattern 120 A and the second sacrificial layer pattern 130 A may be performed to remove the first sacrificial layer 125 and the third sacrificial layer 135 .
  • the inter-layer dielectric layer 120 and the second sacrificial layer 130 that are not etched or removed are referred to as an inter-layer dielectric layer pattern 120 A and a second sacrificial layer pattern 130 A, respectively.
  • a barrier metal layer 160 is formed a resultant structure formed by removing first sacrificial layer 125 and the third sacrificial layer 135 .
  • the barrier metal layer 160 improves interface characteristics.
  • the barrier metal layer 160 may be formed by conformally depositing a titanium nitride (TiN).
  • a conductive layer 165 for forming a first gate electrode which is referred to as a first gate electrode-forming conductive layer 165 , is formed over the barrier metal layer 160 to fill a space created by removing the first sacrificial layer 125 and the third sacrificial layer 135 .
  • the first gate electrode-forming conductive layer 165 may be formed by depositing a conductive material, such as metal, through an Atomic Layer Deposition (ALD) process or a
  • the first gate electrode-forming conductive layer 165 and the barrier metal layer 160 are etched until the sides of the second sacrificial layer pattern 130 A and the inter-layer dielectric layer pattern 120 A are exposed to isolate the barrier metal layer 160 and the first gate electrode-forming conductive layer 165 for each layer.
  • the remaining barrier metal layer 160 and the remaining first gate electrode-forming conductive layer 165 that are not etched between the inter-layer dielectric layer pattern 120 A and the second sacrificial layer pattern 130 A are referred to as a barrier metal layer pattern 160 A and a first gate electrode layer 165 A, respectively.
  • the charge blocking layer 140 is exposed by removing the second sacrificial layer pattern 130 A.
  • the second sacrificial layer pattern 130 A may be removed through a wet etch process that is performed using the etch selectivity against the inter-layer dielectric layer pattern 120 A, the barrier metal layer pattern 160 A, and the first gate electrode layer 165 A.
  • the removed portion of the charge blocking layer 140 may be the portion of the charge blocking layer 140 that contacts the barrier metal layer pattern 160 A, and the charge blocking layer 140 that is not removed is referred to as a charge blocking layer pattern 140 A.
  • the portion of the charge blocking layer 140 may be removed through a wet etch process that is performed using the etch selectivity against the barrier metal layer pattern 160 A and the first gate electrode layer 165 A.
  • a second gate electrode layer 170 that covers an air gap 175 which is formed by removing the second sacrificial layer pattern 130 A and the portion of the charge blocking layer 140 , is formed.
  • a gate electrode formed of the first gate electrode layer 165 A and the second gate electrode layer 170 is formed.
  • the second gate electrode layer 170 may be formed by selectively depositing a conductive material such as metal.
  • the second gate electrode layer 170 couples a pair of adjacent first gate electrode layers 165 A, and the second gate electrode layer 170 may extend into the slit hole T from the inter-layer dielectric layer pattern 120 A.
  • a pass gate electrode that includes the first pass gate electrode layer 105 and the second pass gate electrode layer 115 is formed in the lower portion of the gate structure, and the pass gate electrode includes a sub-channel layer for coupling a pair of main channel layers with each other.
  • erase operation characteristics may be improved by suppressing back tunneling of electrons by substituting a charge blocking layer interposed between a gate electrode and a charge storage layer with an air gap, and a method for fabricating the non-volatile memory device.

Abstract

A non-volatile memory device includes a channel layer vertically extending from a substrate, a plurality of inter-layer dielectric layers and a plurality of gate electrodes that are alternately stacked along the channel layer, and an air gap interposed between the channel layer and each of the plurality of gate electrodes. The non-volatile memory device may improve erase operation characteristics by suppressing back tunneling of electrons by substituting a charge blocking layer interposed between a gate electrode and a charge storage layer with an air gap, and a method for fabricating the non-volatile memory device.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • The present application claims priority of Korean Patent Application No. 10-2011-0140533, filed on Dec. 22, 2011, which is incorporated herein by reference in its entirety.
    • BACKGROUND
  • 1. Field
  • Exemplary embodiments of the present invention relate to a non-volatile memory device and a fabrication method thereof, and more particularly, to a non-volatile memory device having a three-dimensional structure where a plurality of memory cells are stacked vertically from a substrate, and a method for fabricating the non-volatile memory device.
  • 2. Description of the Related Art
  • Non-volatile memory devices retain data although power is turned off. Currently, various nonvolatile memory devices, such as a flash memory, have been widely used.
  • As the integration degree of a non-volatile memory device having a two-dimensional structure where memory cells are formed in a single layer may reach a limit, a non-volatile memory device having a three-dimensional structure where a plurality of memory cells are formed along the channels that are extend vertically from a semiconductor substrate have been suggested. More specifically, non-volatile memory devices having a three-dimensional structure are divided into devices having a linear channel layers and devices having U-shaped channel layers.
  • A charge-trapping-type non-volatile memory device generally includes a memory layer between a channel layer and a gate electrode, and the memory layer includes a charge blocking layer, a charge storage layer, and a channel insulation layer. However, erase operation characteristics of a charge-trapping-type non-volatile memory device are deteriorated due to back tunneling that occurs as the electrons are introduced to the charge storage layer through the charge blocking layer when a memory cell performs an erase operation.
  • To address this back tunneling, a method of forming the charge blocking layer thick or a method of using a high dielectric layer is suggested. However, preventing the charges from being introduced from the charge blocking layer to the charge storage layer may be difficult, and the size of the non-volatile memory device may be increased.
    • SUMMARY
  • An embodiment of the present invention is directed to a non-volatile memory device that may improve erase operation characteristics by suppressing back tunneling of electrons by substituting a charge blocking layer interposed between a gate electrode and a charge storage layer with an air gap, and a method for fabricating the non-volatile memory device.
  • In accordance with an embodiment of the present invention, a non-volatile memory device includes: a channel layer vertically extending from a substrate; a plurality of inter-layer dielectric layers and a plurality of gate electrodes that are alternately stacked along the channel layer; and an air gap interposed between the channel layer and each of the plurality of gate electrodes.
  • In accordance with another embodiment of the present invention, a method for fabricating a non-volatile memory device includes: alternately stacking a plurality of inter-layer dielectric layers and a plurality of first and second sacrificial layers over a substrate;
  • forming channel holes that expose the substrate by selectively etching the inter-layer dielectric layers and the first and second sacrificial layers; sequentially forming a charge blocking layer, a charge storage layer, a tunnel insulation layer, and a channel layer along internal walls of the channel holes; forming slit holes through the first and second sacrificial layers and the inter-layer dielectric layers on both sides of each channel hole; removing the first sacrificial layers exposed through the slit holes; forming a first gate electrode layer pattern in a space created by removing the first sacrificial layers; removing the second sacrificial layers; and forming a second gate electrode layer for coupling a pair of the first gate electrode layer patterns with each other with the air gap formed between the pair of first gate electrode layer patterns, wherein the air gap is formed by removing the second sacrificial layers.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. 1A to 1G are cross-sectional views illustrating a non-volatile memory device and a fabrication method thereof in accordance with a first embodiment of the present invention.
  • FIGS. 2A to 2I are cross-sectional views illustrating a non-volatile memory device and a fabrication method thereof in accordance with a second embodiment of the present invention.
    •  DETAILED DESCRIPTION
  • Exemplary embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention.
  • The drawings are not necessarily to scale and in some instances, proportions may have been exaggerated in order to clearly illustrate features of the embodiments. When a first layer is referred to as being “on” a second layer or “on” a substrate, it not only refers to a case where the first layer is formed directly on the second layer or the substrate but also a case where a third layer exists between the first layer and the second layer or the substrate.
  • FIGS. 1A to 1G are cross-sectional views illustrating a non-volatile memory device and a fabrication method thereof in accordance with a first embodiment of the present invention. FIG. 1G is a cross-sectional view illustrating the non-volatile memory device in accordance with the first embodiment of the present invention. FIGS. 1A to 1F are cross-sectional view illustrating a process for fabricating the non-volatile memory device show in FIG. 1G.
  • Referring to FIG. 1A, an inter-layer dielectric layer 120, a first sacrificial layer 125, a second sacrificial layer 130, and a third sacrificial layer 135 are sequentially and repeatedly stacked over a substrate 100. The substrate 100 may be a semiconductor substrate such as a monocrystalline silicon substrate, and the substrate 100 may include an understructure (not shown). For illustration purposes, the structure where the inter-layer dielectric layer 120 and the first to third sacrificial layers 125, 130, and 135 are sequentially and repeatedly stacked is referred to as a gate structure.
  • The inter-layer dielectric layer 120 may be disposed in the lowermost portion and the uppermost portion of the gate structure. The inter-layer dielectric layer 120 may be formed of an oxide-based material such as silicon oxide (SiO2). Although the drawings show that the first to third sacrificial layers 125, 130, and 135 are stacked four times, the present invention is not limited to four sets of the first to third sacrificial layers 125, 130, and 135, and the first to third sacrificial layers 125, 130, and 135 may be stacked more than four times or less than four times.
  • Particularly, the first sacrificial layer 125 and the third sacrificial layer 135 are removed in a subsequent process to provide a space where a first gate electrode layer is to be formed. The first sacrificial layer 125 and the third sacrificial layer 135 may be formed of a material having an etch selectivity against the second sacrificial layer 130 and the inter-layer dielectric layer 120. For example, the first sacrificial layer 125 and the third sacrificial layer 135 may be formed of a nitride. Also, the second sacrificial layer 130 is removed in a subsequent process to provide a path for forming an air gap, which is to be described later. The second sacrificial layer 130 may be formed of a material having an etch selectivity against the first sacrificial layer 125, the third sacrificial layer 135, and the inter-layer dielectric layer 120. For example, the first sacrificial layer 125 and the third sacrificial layer 135 may be formed of polysilicon.
  • Referring to FIG. 1B, channel holes H1 are formed to expose the substrate 100 by selectively etching the gate structure. The channel holes H1 may have a round or oval shape when seen from above, and a plurality of channel holes H1 may be arrayed in a matrix form.
  • Subsequently, a charge blocking layer 140, a charge storage layer 145, and a tunnel insulation layer 150 are sequentially formed along sidewalls of the channel holes Hi. The charge blocking layer 140 prevents charges in the charge storage layer 145 from transferring to a layer outside of the charge storage layer 145. The charge blocking layer 140 may be formed of an oxide layer. The charge storage layer 145 stores data by trapping charges. The charge storage layer 145 may be formed of a nitride layer. The tunnel insulation layer 150 performs a charge tunneling, and it may be formed of an oxide layer.
  • Subsequently, a channel layer 155 is formed in the channel holes Hi. The channel layer 155 may be formed of a semiconductor material, e.g., polysilicon. Although the channel layer 155 may be formed to completely fill the channel holes H1 in the embodiment of the present invention, the scope of the present invention is not limited a channel layer that completely fills the channel holes HI. According to another embodiment, the channel layer 155 may not be formed to completely fill with the channel layer 155.
  • Although not illustrated in the drawings, a protective layer having an etch selectivity against the first sacrificial layer 125, the second sacrificial layer 130, and the third sacrificial layer 135 may be formed over the gate structure including the channel layer 155 to prevent the charge storage layer 145 or the channel layer 155 from being lost in the course of a subsequent process that removes the first sacrificial layer 125, the second sacrificial layer 130, and the third sacrificial layer 135.
  • Referring to FIG. 1C, slit holes T formed through the inter-layer dielectric layer 120 and the first to third sacrificial layers 125, 130, and 135 are formed by selectively etching the gate structure on both sides of each channel hole H1. The slit holes T may be arrayed in parallel to each other in a form of slit extending in a direction crossing the cross-sectional direction of the drawings.
  • Subsequently, the first sacrificial layer 125 and the third sacrificial layer 135 that are exposed by the slit holes T are removed. A wet etch process using the etch selectivity against the inter-layer dielectric layer pattern 120A and the second sacrificial layer pattern 130A may be performed to remove the first sacrificial layer 125 and the third sacrificial layer 135. The inter-layer dielectric layer 120 and the second sacrificial layer 130 that are not etched or removed are referred to as an inter-layer dielectric layer pattern 120A and a second sacrificial layer pattern 130A, respectively. Meanwhile, the understructure of the substrate 100 may be protected from being damaged in the process of removing the second sacrificial layer pattern 130A by implanting an impurity, such as boron (B), into the substrate 100 exposed through the slit holes T to give the exposed substrate 100 an etch selectivity against the second sacrificial layer pattern 130A.
  • Referring to FIG. 1D, a barrier metal layer 160 is formed along walls a resultant structured formed by removing the first sacrificial layer 125 and the third sacrificial layer 135. The barrier metal layer 160 improves interface characteristics between a first gate electrode layer, which is to be described later, and the inter-layer dielectric layer pattern 120A, the second sacrificial layer pattern 130A, and the charge blocking layer 140. For example, the barrier metal layer 160 may be formed by conformally depositing a titanium nitride (TiN).
  • Subsequently, a conductive layer 165 for forming a first gate electrode, which is referred to as a first gate electrode-forming conductive layer 165, is formed over the barrier metal layer 160 to fill a space created by removing the first sacrificial layer 125 and the third sacrificial layer 135. The first gate electrode-forming conductive layer 165 may be formed by depositing a conductive material, such as metal, through an Atomic Layer Deposition (ALD) process or a Chemical Vapor Deposition (CVD) process. For example, the first gate electrode-forming conductive layer 165 may be formed by forming a tungsten (W) core first and subsequently depositing a bulk tungsten.
  • Referring to FIG. 1E, the first gate electrode-forming conductive layer 165 and the barrier metal layer 160 are etched until the sides of the second sacrificial layer pattern 130A and the inter-layer dielectric layer pattern 120A are exposed to isolate the barrier metal layer 160 and the first gate electrode-forming conductive layer 165 for each layer.
  • It is desirable to minimize the volume of the barrier metal layer 160, which has a relatively high resistance value, and the barrier metal layer 160 may be etched deeper than the first gate electrode-forming conductive layer 165 as a result of the etch rate difference between the barrier metal layer 160 and the first gate electrode-forming conductive layer 165. The barrier metal layer 160 and the first gate electrode-forming conductive layer 165 that are not etched between the inter-layer dielectric layer pattern 120A and the second sacrificial layer pattern 130A are referred to as a barrier metal layer pattern 160A and a first gate electrode layer 165A, respectively.
  • Referring to FIG. 1F, the charge blocking layer 140 is exposed by removing the second sacrificial layer pattern 130A. The second sacrificial layer pattern 130A may be removed through a wet etch process using the etch selectivity against the inter-layer dielectric layer pattern 120A, the barrier metal layer pattern 160A, and the first gate electrode layer 165A.
  • Subsequently, a portion of the exposed charge blocking layer 140 is removed. The removed portion of the charge blocking layer 140 may be the portion of the charge blocking layer 140 that contacts the barrier metal layer pattern 160A, and the charge blocking layer 140 that is not removed is referred to as a charge blocking layer pattern 140A. The portion of the charge blocking layer 140 may be removed through a wet etch process that is performed using the etch selectivity against the barrier metal layer pattern 160A and the first gate electrode layer 165A. Since a portion of the inter-layer dielectric layer pattern 120A is removed and recessed during the wet etch process, the first gate electrode layer 165A may extend further into the slit holes T than the inter-layer dielectric layer pattern 120A.
  • Referring to FIG. 1G, a second gate electrode layer 170 that covers an air gap 175, which is formed by removing the second sacrificial layer pattern 130A and the portion of the charge blocking layer 140, is formed. The second gate electrode layer 170 couples a pair of adjacent first gate electrode layers 165A, and the second gate electrode layer 170 may extend into the slit hole T from the inter-layer dielectric layer pattern 120A. As a result of this process, a gate electrode formed of the first gate electrode layer 165A and the second gate electrode layer 170 is formed.
  • The second gate electrode layer 170 may include a metal. For example, the second gate electrode layer 170 may be formed by selectively depositing a bulk tungsten without a nucleation tungsten.
  • More specifically, when the first gate electrode layer 165A is formed of tungsten and the second gate electrode layer 170 is formed by depositing a bulk tungsten through a selective deposition process, the tungsten is deposited on the existing tungsten layer, which is the first gate electrode layer 165A. Therefore, mask process and a gate electrode isolation process may not be further performed.
  • Also, when the second gate electrode layer 170 is formed through the selective deposition process, an electrical bridge may be prevented from occurring between the second gate electrode layers 170. Also, since the influence of a loading effect is minimized, tungsten may be uniformly deposited to the edge of a memory cell.
  • The non-volatile memory device in accordance with the first embodiment of the present invention may be fabricated through the fabrication method described above.
  • Referring to FIG. 1G, the non-volatile memory device in accordance with the first embodiment of the present invention includes the channel layer 155 that is extends vertically from the substrate 100, the multiple inter-layer dielectric layer patterns 120A and the multiple gate electrodes that are alternately stacked along the channel layer 155, the charge storage layer 145 interposed between the channel layer 155 and each gate electrode, the air gap 175 interposed between the gate electrode and the charge storage layer 145, the tunnel insulation layer 150 interposed between the charge storage layer 145 and the channel layer 155, and the barrier metal layer pattern 160A interposed between the inter-layer dielectric layer pattern 120A and the gate electrode.
  • Each of the gate electrodes may be formed of the first gate electrode layer 165A and the second gate electrode layer 170 that is coupled with the first gate electrode layer 165A. Particularly, the gate electrode extends in one direction while surrounding the channel layer 155, and the gate electrode may have a portion extending into the slit hole T from the inter-layer dielectric layer pattern 120A.
  • FIGS. 2A to 2I are cross-sectional views illustrating a non-volatile memory device and a fabrication method thereof in accordance with a second embodiment of the present invention. While describing the second embodiment of the present invention, description of portions that are substantially the same as the first embodiment is omitted.
  • Referring to FIG. 2A, a first pass gate electrode layer 105 is formed over a substrate 100. The substrate 100 may be a semiconductor substrate such as a monocrystalline silicon substrate, and the first pass gate electrode layer 105 may be formed of a conductive material, such as doped polysilicon or metal.
  • Subsequently, the first pass gate electrode layer 105 is selectively etched to form a groove, and a sacrificial layer pattern 110 is formed in the groove.
  • The sacrificial layer pattern 110 is removed in a subsequent process to provide a space where sub-channel holes are to be formed.
  • The sacrificial layer pattern 110 may be formed of a material having an etch selectivity against the first pass gate electrode layer 105, a second pass gate electrode layer 115, and a gate structure. Also, the sacrificial layer pattern 110 is arrayed in a matrix form when seen from above, and the sacrificial layer pattern 110 may have a shape of island having a longitudinal axis in the cross-sectional direction shown in the drawing and a short axis of a direction crossing the cross-sectional direction shown in the drawing.
  • Subsequently, a second pass gate electrode layer 115 is formed over the first pass gate electrode layer 105 and the sacrificial layer pattern 110. The second pass gate electrode layer 115 may be formed of a conductive material, such as a doped polysilicon or metal. The first pass gate electrode layer 105 and the second pass gate electrode layer 115 are gate electrodes of a pass transistor and may have a shape surrounding the sacrificial layer pattern 110.
  • Referring to FIG. 2B, an inter-layer dielectric layer 120, a first sacrificial layer 125, a second sacrificial layer 130, and a third sacrificial layer 135 are sequentially and repeatedly stacked over the second pass gate electrode layer 115. The inter-layer dielectric layer 120 may be formed of an oxide-based material,
  • The first sacrificial layer 125 and the third sacrificial layer 135 are removed in a subsequent process to provide a space where a first gate electrode layer is to be formed. The first sacrificial layer 125 and the third sacrificial layer 135 may be formed of a material having an etch selectivity against the second sacrificial layer 130 and the inter-layer dielectric layer 120. Also, the second sacrificial layer 130 is a layer used to form an air gap, which is to be described later, and the second sacrificial layer 130 may be formed of a material having an etch selectivity against the first sacrificial layer 125, the third sacrificial layer 135, and the inter-layer dielectric layer 120.
  • Referring to FIG. 2C, a pair of channel holes H1 that exposes the sacrificial layer pattern 110 is formed by selectively etching the gate structure and the second pass gate electrode layer 115. The pair of the channel holes H1 provides a space for forming a channel layer, which is to be described later, and a pair of channel holes H1 may be disposed for each sacrificial layer pattern 110.
  • Subsequently, the sacrificial layer pattern 110 exposed through the pair of the channel holes H1 is removed. The sacrificial layer pattern 110 may be removed through a wet etch process, which is performed using the etch selectivity against the first pass gate electrode layer 105, the second pass gate electrode layer 115, and the gate structure. As a result of this process, sub-channel holes H2 for coupling the pair of the channel holes H1 are formed in the space created by removing the sacrificial layer pattern 110.
  • Referring to FIG. 2D, a charge blocking layer 140, a charge storage layer 145, and a tunnel insulation layer 150 are sequentially formed along internal walls of the pair of the channel holes H1 and the sub-channel holes H2. The charge blocking layer 140, the charge storage layer 145, and the tunnel insulation layer 150 are sequentially formed. The charge blocking layer 140, the charge storage layer 145, and the tunnel insulation layer 150 may have a triple-layer structure of oxide-nitride-oxide (ONO).
  • Subsequently, a channel layer 155 is formed in the pair of the channel holes H1 and the sub-channel holes H2. The channel layer 155 may be divided into a main channel layer that is used as a channel for a selection transistor or a memory cell and a sub-channel layer that is used as a channel for a pass transistor. The channel layer 155 may be formed of a semiconductor material, such as polysilicon.
  • Referring to FIG. 2E, slit holes T formed through the inter-layer dielectric layer 120 and the first to third sacrificial layers 125, 130 and 135 are formed by selectively etching the gate structure on both sides of each channel hole Hi. The slit holes T may be arrayed in parallel to each other in a form of slit extending in a direction crossing the cross-sectional direction of the drawings.
  • Subsequently, the first sacrificial layer 125 and the third sacrificial layer 135 that are exposed by the slit holes T are removed.
  • A wet etch process using the etch selectivity against the inter-layer dielectric layer pattern 120A and the second sacrificial layer pattern 130A may be performed to remove the first sacrificial layer 125 and the third sacrificial layer 135. The inter-layer dielectric layer 120 and the second sacrificial layer 130 that are not etched or removed are referred to as an inter-layer dielectric layer pattern 120A and a second sacrificial layer pattern 130A, respectively.
  • Referring to FIG. 2F, a barrier metal layer 160 is formed a resultant structure formed by removing first sacrificial layer 125 and the third sacrificial layer 135. The barrier metal layer 160 improves interface characteristics. For example, the barrier metal layer 160 may be formed by conformally depositing a titanium nitride (TiN).
  • Subsequently, a conductive layer 165 for forming a first gate electrode, which is referred to as a first gate electrode-forming conductive layer 165, is formed over the barrier metal layer 160 to fill a space created by removing the first sacrificial layer 125 and the third sacrificial layer 135. The first gate electrode-forming conductive layer 165 may be formed by depositing a conductive material, such as metal, through an Atomic Layer Deposition (ALD) process or a
  • Chemical Vapor Deposition (CVD) process.
  • Referring to FIG. 2G, the first gate electrode-forming conductive layer 165 and the barrier metal layer 160 are etched until the sides of the second sacrificial layer pattern 130A and the inter-layer dielectric layer pattern 120A are exposed to isolate the barrier metal layer 160 and the first gate electrode-forming conductive layer 165 for each layer.
  • The remaining barrier metal layer 160 and the remaining first gate electrode-forming conductive layer 165 that are not etched between the inter-layer dielectric layer pattern 120A and the second sacrificial layer pattern 130A are referred to as a barrier metal layer pattern 160A and a first gate electrode layer 165A, respectively.
  • Referring to FIG. 2H, the charge blocking layer 140 is exposed by removing the second sacrificial layer pattern 130A. The second sacrificial layer pattern 130A may be removed through a wet etch process that is performed using the etch selectivity against the inter-layer dielectric layer pattern 120A, the barrier metal layer pattern 160A, and the first gate electrode layer 165A.
  • Subsequently, a portion of the exposed charge blocking layer 140 is removed. The removed portion of the charge blocking layer 140 may be the portion of the charge blocking layer 140 that contacts the barrier metal layer pattern 160A, and the charge blocking layer 140 that is not removed is referred to as a charge blocking layer pattern 140A. The portion of the charge blocking layer 140 may be removed through a wet etch process that is performed using the etch selectivity against the barrier metal layer pattern 160A and the first gate electrode layer 165A.
  • Referring to FIG. 2I, a second gate electrode layer 170 that covers an air gap 175, which is formed by removing the second sacrificial layer pattern 130A and the portion of the charge blocking layer 140, is formed. As a result of this process, a gate electrode formed of the first gate electrode layer 165A and the second gate electrode layer 170 is formed.
  • The second gate electrode layer 170 may be formed by selectively depositing a conductive material such as metal. The second gate electrode layer 170 couples a pair of adjacent first gate electrode layers 165A, and the second gate electrode layer 170 may extend into the slit hole T from the inter-layer dielectric layer pattern 120A.
  • In the second embodiment of the present invention, a pass gate electrode that includes the first pass gate electrode layer 105 and the second pass gate electrode layer 115 is formed in the lower portion of the gate structure, and the pass gate electrode includes a sub-channel layer for coupling a pair of main channel layers with each other.
  • According to an embodiment of the present invention, erase operation characteristics may be improved by suppressing back tunneling of electrons by substituting a charge blocking layer interposed between a gate electrode and a charge storage layer with an air gap, and a method for fabricating the non-volatile memory device.
  • While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.

Claims (9)

1-9. (canceled)
10. A method for fabricating a non-volatile memory device, comprising:
alternately stacking a plurality of inter-layer dielectric layers and a plurality of first and second sacrificial layers over a substrate;
forming channel holes that expose the substrate by selectively etching the inter-layer dielectric layers and the first and second sacrificial layers;
sequentially forming a charge blocking layer, a charge storage layer, a tunnel insulation layer, and a channel layer along internal walls of the channel holes;
forming slit holes through the first and second sacrificial layers and the inter-layer dielectric layers on both sides of each channel hole;
removing the first sacrificial layers exposed through the slit holes;
forming a first gate electrode layer pattern in a space created by removing the first sacrificial layers;
removing the second sacrificial layers; and
forming a second gate electrode layer for coupling a pair of the first gate electrode layer patterns with each other with the air gap formed between the pair of first gate electrode layer patterns, wherein the air gap is formed by removing the second sacrificial layers.
11. The method of claim 10, further comprising:
forming a barrier metal layer on internal walls of removed resultant structure formed by removing the first sacrificial layers, before the forming of the first gate electrode layer pattern.
12. The method of claim 10, further comprising:
removing a portion of the charge blocking layer that is exposed through the air gap, before the forming of the second gate electrode layer.
13. The method of claim 10, further comprising:
forming a pass gate electrode over the substrate, before the stacking of the inter-layer dielectric layers and the first and second sacrificial layers.
14. The method of claim 10, wherein the second gate electrode layer extends from each inter-layer dielectric layer into the slit hole.
15. The method of claim 10, wherein the second gate electrode layer is formed by selectively depositing tungsten.
16. The method of claim 10, wherein the second sacrificial layer is formed of a material having an etch selectivity against the first sacrificial layer.
17. The method of claim 13, further comprising:
forming sub-channel holes that each couples a pair of channel holes with each other in the pass gate electrode, after the forming of the channel holes.
US14/569,035 2011-12-22 2014-12-12 Non-volatile memory device and method for fabricating the same Expired - Fee Related US9159570B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/569,035 US9159570B2 (en) 2011-12-22 2014-12-12 Non-volatile memory device and method for fabricating the same

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR10-2011-0140533 2011-12-22
KR1020110140533A KR20130072911A (en) 2011-12-22 2011-12-22 Nonvolatile memory device and method for fabricating the same
US13/618,182 US8928063B2 (en) 2011-12-22 2012-09-14 Non-volatile memory device and method for fabricating the same
US14/569,035 US9159570B2 (en) 2011-12-22 2014-12-12 Non-volatile memory device and method for fabricating the same

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US13/618,182 Division US8928063B2 (en) 2011-12-22 2012-09-14 Non-volatile memory device and method for fabricating the same

Publications (2)

Publication Number Publication Date
US20150099339A1 true US20150099339A1 (en) 2015-04-09
US9159570B2 US9159570B2 (en) 2015-10-13

Family

ID=48653681

Family Applications (2)

Application Number Title Priority Date Filing Date
US13/618,182 Expired - Fee Related US8928063B2 (en) 2011-12-22 2012-09-14 Non-volatile memory device and method for fabricating the same
US14/569,035 Expired - Fee Related US9159570B2 (en) 2011-12-22 2014-12-12 Non-volatile memory device and method for fabricating the same

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US13/618,182 Expired - Fee Related US8928063B2 (en) 2011-12-22 2012-09-14 Non-volatile memory device and method for fabricating the same

Country Status (2)

Country Link
US (2) US8928063B2 (en)
KR (1) KR20130072911A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9666525B2 (en) 2015-08-28 2017-05-30 Samsung Electronics Co., Ltd. Three-dimensional semiconductor memory device
US10079203B2 (en) 2015-09-23 2018-09-18 Samsung Electronics Co., Ltd. Vertical memory devices and methods of manufacturing the same
CN109003979A (en) * 2017-06-07 2018-12-14 力晶科技股份有限公司 Vertical memory and manufacturing method thereof
US11227870B2 (en) * 2019-06-13 2022-01-18 Samsung Electronics Co., Ltd. Semiconductor memory device and method for fabricating the same

Families Citing this family (132)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9324576B2 (en) 2010-05-27 2016-04-26 Applied Materials, Inc. Selective etch for silicon films
US10283321B2 (en) 2011-01-18 2019-05-07 Applied Materials, Inc. Semiconductor processing system and methods using capacitively coupled plasma
US8999856B2 (en) 2011-03-14 2015-04-07 Applied Materials, Inc. Methods for etch of sin films
US9064815B2 (en) 2011-03-14 2015-06-23 Applied Materials, Inc. Methods for etch of metal and metal-oxide films
JP5593283B2 (en) * 2011-08-04 2014-09-17 株式会社東芝 Semiconductor memory device and manufacturing method thereof
JP2013065636A (en) * 2011-09-15 2013-04-11 Toshiba Corp Nonvolatile semiconductor storage device and manufacturing method of the same
US9267739B2 (en) 2012-07-18 2016-02-23 Applied Materials, Inc. Pedestal with multi-zone temperature control and multiple purge capabilities
US9373517B2 (en) 2012-08-02 2016-06-21 Applied Materials, Inc. Semiconductor processing with DC assisted RF power for improved control
US9132436B2 (en) 2012-09-21 2015-09-15 Applied Materials, Inc. Chemical control features in wafer process equipment
US10256079B2 (en) 2013-02-08 2019-04-09 Applied Materials, Inc. Semiconductor processing systems having multiple plasma configurations
US9362130B2 (en) 2013-03-01 2016-06-07 Applied Materials, Inc. Enhanced etching processes using remote plasma sources
US9040422B2 (en) 2013-03-05 2015-05-26 Applied Materials, Inc. Selective titanium nitride removal
US20140271097A1 (en) 2013-03-15 2014-09-18 Applied Materials, Inc. Processing systems and methods for halide scavenging
KR20140117212A (en) * 2013-03-26 2014-10-07 에스케이하이닉스 주식회사 Semiconductor device
KR20140134178A (en) * 2013-05-13 2014-11-21 에스케이하이닉스 주식회사 Semiconductor device
US9252151B2 (en) 2013-07-08 2016-02-02 Sandisk Technologies Inc. Three dimensional NAND device with birds beak containing floating gates and method of making thereof
US9493879B2 (en) 2013-07-12 2016-11-15 Applied Materials, Inc. Selective sputtering for pattern transfer
US9773648B2 (en) 2013-08-30 2017-09-26 Applied Materials, Inc. Dual discharge modes operation for remote plasma
KR20150049146A (en) 2013-10-29 2015-05-08 에스케이하이닉스 주식회사 Semiconductor device
US9576809B2 (en) 2013-11-04 2017-02-21 Applied Materials, Inc. Etch suppression with germanium
US9520303B2 (en) 2013-11-12 2016-12-13 Applied Materials, Inc. Aluminum selective etch
US9245762B2 (en) 2013-12-02 2016-01-26 Applied Materials, Inc. Procedure for etch rate consistency
KR20150091895A (en) * 2014-02-04 2015-08-12 에스케이하이닉스 주식회사 Semiconductor device and method of operating the same
JP2015149381A (en) * 2014-02-06 2015-08-20 株式会社東芝 Semiconductor storage device
US9499898B2 (en) 2014-03-03 2016-11-22 Applied Materials, Inc. Layered thin film heater and method of fabrication
US9299537B2 (en) 2014-03-20 2016-03-29 Applied Materials, Inc. Radial waveguide systems and methods for post-match control of microwaves
US9903020B2 (en) 2014-03-31 2018-02-27 Applied Materials, Inc. Generation of compact alumina passivation layers on aluminum plasma equipment components
KR102175763B1 (en) 2014-04-09 2020-11-09 삼성전자주식회사 Semiconductor Memory Device And Method Of Fabricating The Same
US9309598B2 (en) 2014-05-28 2016-04-12 Applied Materials, Inc. Oxide and metal removal
KR20150146073A (en) * 2014-06-20 2015-12-31 에스케이하이닉스 주식회사 Semiconductor device and manufacturing method thereof
KR102248205B1 (en) * 2014-06-25 2021-05-04 삼성전자주식회사 Semiconductor device having vertical channel and air gap
US9496167B2 (en) 2014-07-31 2016-11-15 Applied Materials, Inc. Integrated bit-line airgap formation and gate stack post clean
US20160043099A1 (en) * 2014-08-05 2016-02-11 Applied Materials, Inc. Wordline 3d flash memory air gap
US9659753B2 (en) 2014-08-07 2017-05-23 Applied Materials, Inc. Grooved insulator to reduce leakage current
US9553102B2 (en) 2014-08-19 2017-01-24 Applied Materials, Inc. Tungsten separation
US9917096B2 (en) * 2014-09-10 2018-03-13 Toshiba Memory Corporation Semiconductor memory device and method for manufacturing same
US9355862B2 (en) 2014-09-24 2016-05-31 Applied Materials, Inc. Fluorine-based hardmask removal
US9613822B2 (en) 2014-09-25 2017-04-04 Applied Materials, Inc. Oxide etch selectivity enhancement
US9966240B2 (en) 2014-10-14 2018-05-08 Applied Materials, Inc. Systems and methods for internal surface conditioning assessment in plasma processing equipment
US9355922B2 (en) 2014-10-14 2016-05-31 Applied Materials, Inc. Systems and methods for internal surface conditioning in plasma processing equipment
US11637002B2 (en) 2014-11-26 2023-04-25 Applied Materials, Inc. Methods and systems to enhance process uniformity
US10224210B2 (en) 2014-12-09 2019-03-05 Applied Materials, Inc. Plasma processing system with direct outlet toroidal plasma source
US10573496B2 (en) 2014-12-09 2020-02-25 Applied Materials, Inc. Direct outlet toroidal plasma source
US9502258B2 (en) 2014-12-23 2016-11-22 Applied Materials, Inc. Anisotropic gap etch
US11257693B2 (en) 2015-01-09 2022-02-22 Applied Materials, Inc. Methods and systems to improve pedestal temperature control
US20160225652A1 (en) 2015-02-03 2016-08-04 Applied Materials, Inc. Low temperature chuck for plasma processing systems
US9728437B2 (en) 2015-02-03 2017-08-08 Applied Materials, Inc. High temperature chuck for plasma processing systems
US9881805B2 (en) 2015-03-02 2018-01-30 Applied Materials, Inc. Silicon selective removal
US9613896B2 (en) 2015-03-18 2017-04-04 Kabushiki Kaisha Toshiba Semiconductor memory device with conductive columnar body
US9691645B2 (en) 2015-08-06 2017-06-27 Applied Materials, Inc. Bolted wafer chuck thermal management systems and methods for wafer processing systems
US9741593B2 (en) 2015-08-06 2017-08-22 Applied Materials, Inc. Thermal management systems and methods for wafer processing systems
US9349605B1 (en) 2015-08-07 2016-05-24 Applied Materials, Inc. Oxide etch selectivity systems and methods
US10504700B2 (en) 2015-08-27 2019-12-10 Applied Materials, Inc. Plasma etching systems and methods with secondary plasma injection
KR102413766B1 (en) * 2015-09-08 2022-06-27 삼성전자주식회사 Non-volatile memory device and method for fabricating the same
US9711526B2 (en) * 2015-11-19 2017-07-18 Kabushiki Kaisha Toshiba Semiconductor memory device
KR102594494B1 (en) * 2016-02-17 2023-10-27 에스케이하이닉스 주식회사 Semiconductor device and manufacturing method thereof
US9711530B1 (en) 2016-03-25 2017-07-18 Sandisk Technologies Llc Locally-trap-characteristic-enhanced charge trap layer for three-dimensional memory structures
US9812463B2 (en) 2016-03-25 2017-11-07 Sandisk Technologies Llc Three-dimensional memory device containing vertically isolated charge storage regions and method of making thereof
US10504754B2 (en) 2016-05-19 2019-12-10 Applied Materials, Inc. Systems and methods for improved semiconductor etching and component protection
US10522371B2 (en) 2016-05-19 2019-12-31 Applied Materials, Inc. Systems and methods for improved semiconductor etching and component protection
US9865484B1 (en) 2016-06-29 2018-01-09 Applied Materials, Inc. Selective etch using material modification and RF pulsing
US10062575B2 (en) 2016-09-09 2018-08-28 Applied Materials, Inc. Poly directional etch by oxidation
US10629473B2 (en) 2016-09-09 2020-04-21 Applied Materials, Inc. Footing removal for nitride spacer
US9721789B1 (en) 2016-10-04 2017-08-01 Applied Materials, Inc. Saving ion-damaged spacers
US10062585B2 (en) 2016-10-04 2018-08-28 Applied Materials, Inc. Oxygen compatible plasma source
US9934942B1 (en) 2016-10-04 2018-04-03 Applied Materials, Inc. Chamber with flow-through source
US10546729B2 (en) 2016-10-04 2020-01-28 Applied Materials, Inc. Dual-channel showerhead with improved profile
US10062579B2 (en) 2016-10-07 2018-08-28 Applied Materials, Inc. Selective SiN lateral recess
US9947549B1 (en) 2016-10-10 2018-04-17 Applied Materials, Inc. Cobalt-containing material removal
US10163696B2 (en) 2016-11-11 2018-12-25 Applied Materials, Inc. Selective cobalt removal for bottom up gapfill
US9768034B1 (en) 2016-11-11 2017-09-19 Applied Materials, Inc. Removal methods for high aspect ratio structures
US10242908B2 (en) 2016-11-14 2019-03-26 Applied Materials, Inc. Airgap formation with damage-free copper
US10026621B2 (en) 2016-11-14 2018-07-17 Applied Materials, Inc. SiN spacer profile patterning
US9991277B1 (en) 2016-11-28 2018-06-05 Sandisk Technologies Llc Three-dimensional memory device with discrete self-aligned charge storage elements and method of making thereof
US10566206B2 (en) 2016-12-27 2020-02-18 Applied Materials, Inc. Systems and methods for anisotropic material breakthrough
US10431429B2 (en) 2017-02-03 2019-10-01 Applied Materials, Inc. Systems and methods for radial and azimuthal control of plasma uniformity
US10403507B2 (en) 2017-02-03 2019-09-03 Applied Materials, Inc. Shaped etch profile with oxidation
US10043684B1 (en) 2017-02-06 2018-08-07 Applied Materials, Inc. Self-limiting atomic thermal etching systems and methods
US10319739B2 (en) 2017-02-08 2019-06-11 Applied Materials, Inc. Accommodating imperfectly aligned memory holes
US10943834B2 (en) 2017-03-13 2021-03-09 Applied Materials, Inc. Replacement contact process
US9960180B1 (en) 2017-03-27 2018-05-01 Sandisk Technologies Llc Three-dimensional memory device with partially discrete charge storage regions and method of making thereof
US10319649B2 (en) 2017-04-11 2019-06-11 Applied Materials, Inc. Optical emission spectroscopy (OES) for remote plasma monitoring
US11276590B2 (en) 2017-05-17 2022-03-15 Applied Materials, Inc. Multi-zone semiconductor substrate supports
US11276559B2 (en) 2017-05-17 2022-03-15 Applied Materials, Inc. Semiconductor processing chamber for multiple precursor flow
US10497579B2 (en) 2017-05-31 2019-12-03 Applied Materials, Inc. Water-free etching methods
US10049891B1 (en) 2017-05-31 2018-08-14 Applied Materials, Inc. Selective in situ cobalt residue removal
US10920320B2 (en) 2017-06-16 2021-02-16 Applied Materials, Inc. Plasma health determination in semiconductor substrate processing reactors
US10541246B2 (en) 2017-06-26 2020-01-21 Applied Materials, Inc. 3D flash memory cells which discourage cross-cell electrical tunneling
US10727080B2 (en) 2017-07-07 2020-07-28 Applied Materials, Inc. Tantalum-containing material removal
US10541184B2 (en) 2017-07-11 2020-01-21 Applied Materials, Inc. Optical emission spectroscopic techniques for monitoring etching
US10354889B2 (en) 2017-07-17 2019-07-16 Applied Materials, Inc. Non-halogen etching of silicon-containing materials
US10170336B1 (en) 2017-08-04 2019-01-01 Applied Materials, Inc. Methods for anisotropic control of selective silicon removal
US10043674B1 (en) 2017-08-04 2018-08-07 Applied Materials, Inc. Germanium etching systems and methods
US10297458B2 (en) 2017-08-07 2019-05-21 Applied Materials, Inc. Process window widening using coated parts in plasma etch processes
US10283324B1 (en) 2017-10-24 2019-05-07 Applied Materials, Inc. Oxygen treatment for nitride etching
US10128086B1 (en) 2017-10-24 2018-11-13 Applied Materials, Inc. Silicon pretreatment for nitride removal
US10256112B1 (en) 2017-12-08 2019-04-09 Applied Materials, Inc. Selective tungsten removal
US10903054B2 (en) 2017-12-19 2021-01-26 Applied Materials, Inc. Multi-zone gas distribution systems and methods
US11328909B2 (en) 2017-12-22 2022-05-10 Applied Materials, Inc. Chamber conditioning and removal processes
US10854426B2 (en) 2018-01-08 2020-12-01 Applied Materials, Inc. Metal recess for semiconductor structures
US10964512B2 (en) 2018-02-15 2021-03-30 Applied Materials, Inc. Semiconductor processing chamber multistage mixing apparatus and methods
US10679870B2 (en) 2018-02-15 2020-06-09 Applied Materials, Inc. Semiconductor processing chamber multistage mixing apparatus
TWI716818B (en) 2018-02-28 2021-01-21 美商應用材料股份有限公司 Systems and methods to form airgaps
US10593560B2 (en) 2018-03-01 2020-03-17 Applied Materials, Inc. Magnetic induction plasma source for semiconductor processes and equipment
US10319600B1 (en) 2018-03-12 2019-06-11 Applied Materials, Inc. Thermal silicon etch
US10497573B2 (en) 2018-03-13 2019-12-03 Applied Materials, Inc. Selective atomic layer etching of semiconductor materials
US10573527B2 (en) 2018-04-06 2020-02-25 Applied Materials, Inc. Gas-phase selective etching systems and methods
US10490406B2 (en) 2018-04-10 2019-11-26 Appled Materials, Inc. Systems and methods for material breakthrough
US10699879B2 (en) 2018-04-17 2020-06-30 Applied Materials, Inc. Two piece electrode assembly with gap for plasma control
US10886137B2 (en) 2018-04-30 2021-01-05 Applied Materials, Inc. Selective nitride removal
KR102487371B1 (en) * 2018-06-22 2023-01-11 삼성전자주식회사 Vertical semiconductor devices
US10872778B2 (en) 2018-07-06 2020-12-22 Applied Materials, Inc. Systems and methods utilizing solid-phase etchants
US10755941B2 (en) 2018-07-06 2020-08-25 Applied Materials, Inc. Self-limiting selective etching systems and methods
US10672642B2 (en) 2018-07-24 2020-06-02 Applied Materials, Inc. Systems and methods for pedestal configuration
KR20200031442A (en) 2018-09-14 2020-03-24 삼성전자주식회사 Integrated circuit device and method of manufacturing the same
US11049755B2 (en) 2018-09-14 2021-06-29 Applied Materials, Inc. Semiconductor substrate supports with embedded RF shield
US10892198B2 (en) 2018-09-14 2021-01-12 Applied Materials, Inc. Systems and methods for improved performance in semiconductor processing
US11062887B2 (en) 2018-09-17 2021-07-13 Applied Materials, Inc. High temperature RF heater pedestals
US11417534B2 (en) 2018-09-21 2022-08-16 Applied Materials, Inc. Selective material removal
US11682560B2 (en) 2018-10-11 2023-06-20 Applied Materials, Inc. Systems and methods for hafnium-containing film removal
KR102476135B1 (en) 2018-10-19 2022-12-12 삼성전자주식회사 Semiconductor device and method of forming the same
US11121002B2 (en) 2018-10-24 2021-09-14 Applied Materials, Inc. Systems and methods for etching metals and metal derivatives
US11437242B2 (en) 2018-11-27 2022-09-06 Applied Materials, Inc. Selective removal of silicon-containing materials
US11721527B2 (en) 2019-01-07 2023-08-08 Applied Materials, Inc. Processing chamber mixing systems
US10920319B2 (en) 2019-01-11 2021-02-16 Applied Materials, Inc. Ceramic showerheads with conductive electrodes
KR20210000208A (en) 2019-06-24 2021-01-04 삼성전자주식회사 Semiconductor devices and manufacturing method for the same
KR20210103305A (en) * 2020-02-13 2021-08-23 에스케이하이닉스 주식회사 non volatile memory device having 3-dimensional structure
CN113314541B (en) * 2020-06-08 2022-12-02 长江存储科技有限责任公司 Memory device
KR20220118260A (en) * 2021-02-18 2022-08-25 에스케이하이닉스 주식회사 Semiconductor device and manufacturing method of semiconductor device
KR20220118261A (en) 2021-02-18 2022-08-25 에스케이하이닉스 주식회사 Semiconductor device and manufacturing method of semiconductor device
KR20220118258A (en) 2021-02-18 2022-08-25 에스케이하이닉스 주식회사 Semiconductor device and manufacturing method of semiconductor device
CN114361171A (en) * 2022-01-13 2022-04-15 长鑫存储技术有限公司 Manufacturing method of semiconductor structure and semiconductor structure

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090108333A1 (en) * 2007-10-29 2009-04-30 Kabushiki Kasiha Toshiba Non-volatile semiconductor storage device and method of manufacturing the same
US7847334B2 (en) * 2008-03-14 2010-12-07 Kabushiki Kaisha Toshiba Non-volatile semiconductor storage device and method of manufacturing the same
US20120001249A1 (en) * 2010-06-30 2012-01-05 Sandisk Corporation Ultrahigh density vertical nand memory device & method of making thereof
US20120012920A1 (en) * 2010-07-15 2012-01-19 Seung-Mok Shin Vertical non-volatile memory device
US20120049268A1 (en) * 2010-09-01 2012-03-01 Samsung Electronics Co., Ltd. Three dimensional semiconductor memory devices and methods of fabricating the same
US20120098051A1 (en) * 2010-10-26 2012-04-26 Byoungkeun Son Nonvolatile memory device and method of forming the same
US20120139027A1 (en) * 2010-12-02 2012-06-07 Samsung Electronics Co., Ltd. Vertical structure non-volatile memory devices including impurity providing layer
US20120146122A1 (en) * 2010-12-14 2012-06-14 Sung Jin Whang 3-d non-volatile memory device and method of manufacturing the same

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20080073579A (en) 2007-02-06 2008-08-11 삼성전자주식회사 Flash memory having bridge floating gates and method of fabricating the same

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090108333A1 (en) * 2007-10-29 2009-04-30 Kabushiki Kasiha Toshiba Non-volatile semiconductor storage device and method of manufacturing the same
US7847334B2 (en) * 2008-03-14 2010-12-07 Kabushiki Kaisha Toshiba Non-volatile semiconductor storage device and method of manufacturing the same
US20120001249A1 (en) * 2010-06-30 2012-01-05 Sandisk Corporation Ultrahigh density vertical nand memory device & method of making thereof
US20120012920A1 (en) * 2010-07-15 2012-01-19 Seung-Mok Shin Vertical non-volatile memory device
US20120049268A1 (en) * 2010-09-01 2012-03-01 Samsung Electronics Co., Ltd. Three dimensional semiconductor memory devices and methods of fabricating the same
US20120098051A1 (en) * 2010-10-26 2012-04-26 Byoungkeun Son Nonvolatile memory device and method of forming the same
US20120139027A1 (en) * 2010-12-02 2012-06-07 Samsung Electronics Co., Ltd. Vertical structure non-volatile memory devices including impurity providing layer
US20120146122A1 (en) * 2010-12-14 2012-06-14 Sung Jin Whang 3-d non-volatile memory device and method of manufacturing the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9666525B2 (en) 2015-08-28 2017-05-30 Samsung Electronics Co., Ltd. Three-dimensional semiconductor memory device
US10079203B2 (en) 2015-09-23 2018-09-18 Samsung Electronics Co., Ltd. Vertical memory devices and methods of manufacturing the same
CN109003979A (en) * 2017-06-07 2018-12-14 力晶科技股份有限公司 Vertical memory and manufacturing method thereof
US11227870B2 (en) * 2019-06-13 2022-01-18 Samsung Electronics Co., Ltd. Semiconductor memory device and method for fabricating the same

Also Published As

Publication number Publication date
US9159570B2 (en) 2015-10-13
US20130161726A1 (en) 2013-06-27
US8928063B2 (en) 2015-01-06
KR20130072911A (en) 2013-07-02

Similar Documents

Publication Publication Date Title
US9159570B2 (en) Non-volatile memory device and method for fabricating the same
US9023702B2 (en) Nonvolatile memory device and method for fabricating the same
US8860119B2 (en) Nonvolatile memory device and method for fabricating the same
US8735961B2 (en) 3D non-volatile memory device and method for fabricating the same
US9543313B2 (en) Nonvolatile memory device and method for fabricating the same
US8507976B2 (en) Nonvolatile memory device and method for fabricating the same
CN108735748B (en) Three-dimensional semiconductor device
US8921922B2 (en) Nonvolatile memory device and method for fabricating the same
US9640548B2 (en) Method for fabricating non-volatile memory device
US8865554B2 (en) Method for fabricating nonvolatile memory device
US20180277631A1 (en) Semiconductor device and method for manufacturing same
US9006089B2 (en) Nonvolatile memory device and method for fabricating the same
US9048139B2 (en) Method for fabricating non-volatile memory device
JP2011029576A (en) Nonvolatile semiconductor memory device and manufacturing method thereof
US20160118395A1 (en) Semiconductor device and method of fabricating the same
CN110473876B (en) Three-dimensional memory and preparation method thereof
KR20210083427A (en) Semiconductor device and method of manufacturing the semiconductor device
US10109578B2 (en) Semiconductor memory device

Legal Events

Date Code Title Description
AS Assignment

Owner name: SK HYNIX INC., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KIM, MIN-SOO;SHEEN, DONG-SUN;PYI, SEUNG-HO;AND OTHERS;REEL/FRAME:034628/0936

Effective date: 20141030

STCF Information on status: patent grant

Free format text: PATENTED CASE

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4

FEPP Fee payment procedure

Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

LAPS Lapse for failure to pay maintenance fees

Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20231013