Connect public, paid and private patent data with Google Patents Public Datasets

Semiconductor devices including silicide regions and methods of fabricating the same

Download PDF

Info

Publication number
US20150031183A1
US20150031183A1 US14485035 US201414485035A US2015031183A1 US 20150031183 A1 US20150031183 A1 US 20150031183A1 US 14485035 US14485035 US 14485035 US 201414485035 A US201414485035 A US 201414485035A US 2015031183 A1 US2015031183 A1 US 2015031183A1
Authority
US
Grant status
Application
Patent type
Prior art keywords
layer
epitaxial
formed
gate
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US14485035
Inventor
Sungkwan Kang
Keum Seok Park
Byeongchan Lee
Sangbom Kang
Nam-Kyu Kim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02441Group 14 semiconducting materials
    • H01L21/0245Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/02636Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639Preparation of substrate for selective deposition
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H01L29/4975Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 being a silicide layer, e.g. TiSi2
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/518Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H01L29/66507Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide providing different silicide thicknesses on the gate and on source or drain
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66613Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66636Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • [0001]
    This is a Divisional of U.S. application Ser. No. 13/155,483, filed Jun. 8, 2011, which makes a claim priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2010-0087618, filed on Sep. 7, 2010.
  • BACKGROUND
  • [0002]
    The inventive concept relates to a semiconductor device and to a method of fabricating the same. More particularly, the inventive concept relates to a semiconductor device including a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) having a silicide on its source/drain region and to a method of fabricating the same.
  • [0003]
    A semiconductor device may include an integrated circuit (IC) made up of a plurality of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs or MOS transistors for short). Reducing the size and design rule of such a semiconductor device, i.e., increasing the degree of integration of the device, may thus require a scaling-down of MOS transistors. However, scaled-down of MOS transistors may exhibit short channel effects which degrade the operational characteristics of the semiconductor device. Accordingly, research is being conducted on various techniques aimed at fabricating highly integrated semiconductor devices that offer better performance. In particular, research is being conducted on ways to increase the mobility of charge carriers (electrons or holes) in MOS transistors with the aim of developing high-performance semiconductor devices. Also, research is being conducted on ways to form low-resistivity silicide layers in MOS transistors, which can minimize contact resistance and sheet resistance of the gate, source and drain of MOS transistors, and thereby allow for the production of more highly integrated semiconductor devices.
  • SUMMARY
  • [0004]
    According to one aspect of the inventive concept, there is provided a semiconductor device having a silicided source/drain region constituted by an epitaxial layer. The semiconductor device includes a semiconductor substrate, a gate electrode structure comprising a gate electrode located on an active region of the semiconductor substrate, first and second epitaxial regions located in the active region at opposite sides of the gate electrode structure, respectively, and first and second silicide layers on upper surfaces of the first and second epitaxial regions, respectively. The first and second epitaxial regions both comprise Si—X, where X is one of germanium and carbon. Each of the first and second silicide layers is devoid of X, and both of the first and second silicide layers comprise Si—Y, where Y is a metal or metal alloy.
  • [0005]
    According to another aspect of the inventive concept, there is provided a semiconductor device including a PMOS transistor having a silicided source/drain region constituted by an epitaxial layer, and an NMOS transistor electrically connected to the PMOS. The semiconductor device also includes a substrate having a first region and a second region, and a device isolation layer in the substrate and which demarcates a first active region in the first region of the substrate and a second active region in the second region of the substrate. The PMOS transistor is disposed at the first region of the substrate and comprises a first gate electrode located on the first active region, first and second epitaxial regions located in the first active region at opposite sides of the first gate electrode, respectively, and first and second silicide layers on upper surfaces of the first and second epitaxial regions, respectively. The first and second epitaxial regions both comprise SiGe. Each of the first and second silicide layers is devoid of germanium, and both of the first and second silicide layers comprise Si—Y, where Y is a metal or metal alloy. The NMOS transistor is disposed at the second region of the substrate.
  • [0006]
    According to another aspect of the inventive concept, there is provided a method of fabricating a semiconductor device including forming a gate electrode structure comprising a gate electrode on an active region of a substrate, forming first and second epitaxial regions in the active region at opposite sides of the gate electrode structure, respectively, forming a silicon layer on the first and second epitaxial regions including by depositing silicon on each of the first and second epitaxial regions, and converting at least a portion of the silicon layer, on each of the first and second epitaxial regions, to a silicide.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0007]
    These and other aspects and features of the inventive concept will be better understood from the detailed description of preferred embodiments thereof made in conjunction with the accompanying drawings. In the drawings:
  • [0008]
    FIG. 1 is a flow chart of a first embodiment of a method of fabricating a semiconductor device according to the inventive concept;
  • [0009]
    FIG. 2 is a plan view of a semiconductor device according to the inventive concept;
  • [0010]
    FIGS. 3 to 10 are each sectional views in the directions of lines I-I′ and II-II′ of FIG. 2, respectively, and together illustrate the first embodiment of a method of fabricating a semiconductor device according to the inventive concept;
  • [0011]
    FIG. 11 is a graph illustrating a technique used to form a silicon epitaxial layer in a method of fabricating a semiconductor device according to the inventive concept;
  • [0012]
    FIG. 12 is a graph illustrating another technique used to form a silicon epitaxial layer in a method of fabricating a semiconductor device according to the inventive concept;
  • [0013]
    FIGS. 13A to 13D are sectional views illustrating a process of forming a silicon epitaxial layer according to the inventive concept;
  • [0014]
    FIGS. 14 to 16 are each a pair of sectional views taken along lines I-I′ and II-II′ of FIG. 2, and illustrate processes in a second embodiment of a method of fabricating a semiconductor device according to the inventive concept;
  • [0015]
    FIGS. 17 to 20 are each a pair of sectional views taken along lines I-I′ and II-II′ of FIG. 2, and illustrate processes in a third embodiment of a method of fabricating a semiconductor device according to the inventive concept;
  • [0016]
    FIG. 21 is a flow chart of a fourth embodiment of method of fabricating a semiconductor device according to the inventive concept;
  • [0017]
    FIGS. 22 to 27 are each a pair of sectional views taken along lines I-I′ and II-II′ of FIG. 2, and illustrate processes in the fourth embodiment of a method of fabricating a semiconductor device according to the inventive concept;
  • [0018]
    FIG. 28 is a flow chart of a fifth embodiment of a method of fabricating a semiconductor device according to the inventive concept;
  • [0019]
    FIG. 29 is a sectional view of a semiconductor device fabricated by the method illustrated in FIG. 28;
  • [0020]
    FIG. 30 is a flow chart of a sixth embodiment of a method of fabricating a semiconductor device according to the inventive concept;
  • [0021]
    FIGS. 31 to 34 are each a sectional view and illustrate processes in the sixth embodiment of a method of fabricating a semiconductor device according to the inventive concept;
  • [0022]
    FIG. 35 is a sectional view of a process in another version of the sixth embodiment of a method of fabricating a semiconductor device according to the inventive concept;
  • [0023]
    FIG. 36 is a circuit diagram of an inverter including a CMOS transistor according to the inventive concept; and
  • [0024]
    FIG. 37 is a circuit diagram of an SRAM device including a CMOS transistor according to exemplary embodiments of the inventive concept.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • [0025]
    Various embodiments and examples of embodiments of the inventive concept will be described more fully hereinafter with reference to the accompanying drawings. In the drawings, the sizes and relative sizes and shapes of elements, layers and regions, such as implanted or etched regions, shown in section may be exaggerated for clarity. In particular, the cross-sectional illustrations of the semiconductor devices and intermediate structures fabricated during the course of their manufacture are schematic. Also, when like numerals appear in the drawings, such numerals are used to designate like elements.
  • [0026]
    Furthermore, spatially relative terms, such as “upper”, “top”, “lower” and “bottom” are used to describe an element's and/or feature's relationship to another element(s) and/or feature(s) as illustrated in the figures. Thus, the spatially relative terms may apply to orientations in use which differ from the orientation depicted in the figures. Obviously, though, all such spatially relative terms refer to the orientation shown in the drawings for ease of description and are not necessarily limiting as embodiments according to the inventive concept can assume orientations different than those illustrated in the drawings when in use. In addition, a term such as “upper” or “bottom” as used to describe a surface generally refers not only to the orientation depicted in the drawings but may refer to the fact that the surface is the uppermost or bottommost surface in the orientation depicted, as would be clear from the drawings and context of the written description.
  • [0027]
    It will also be understood that when an element or layer is referred to as being “on” another element or layer, it can be directly on the other element or layer or intervening elements or layers may be present. In contrast, when an element or layer is referred to as being “directly on” another element or layer, there are no intervening elements or layers present.
  • [0028]
    Furthermore, the term “and/or” as used herein includes any and all practical combinations of one or more of the associated listed items. With respect to materials of a particular layer, the term “and/or” may be used to indicate that the particular layer is made up of one or more films of different materials.
  • [0029]
    It will also be understood that although the terms first, second, third, etc. are used herein to describe various elements, regions, layers, etc., these elements, regions, and/or layers are not limited by these terms. These terms are only used to distinguish one element, layer or region from another.
  • [0030]
    Other terminology used herein for the purpose of describing particular examples or embodiments of the inventive concept is to be taken in context. For example, the terms “comprises” or “comprising” when used in this specification specifies the presence of stated features or processes but does not preclude the presence or additional features or processes.
  • [0031]
    Also, in the description that follows, conventional notation known in the art of crystallography as Miller indices will be used. Miller indices, as is known in the art, indicate the arrangement of atoms in a crystalline solid. More specifically, Miller indices describe arrangements of atoms in a crystalline solid in terms of directions and planes in a crystal lattice.
  • [0032]
    Miller indices are sets of three integers h, k and l that describe a family of planes in a crystal lattice. The integers are written in their lowest terms, i.e., as their minimum integer ratio such that their greatest common divisor is 1. When the three integers are arranged in ( ) like (h k l), the index denotes the reciprocals of intercepts of the plane in a coordinate system of a unit cell of the crystal lattice. This plane could be any one of planes parallel to each other in the lattice. Furthermore, many planes in the lattice are equivalent to each other in a crystallographic sense. Therefore, the notation {h k l} is used to denote the set of planes that are equivalent to (h k l) by the symmetry of the lattice.
  • [0033]
    Also, a direction in a crystal lattice is described by a set of three integers representing a vector in that direction between two points in the unit cell of the crystal lattice. The vector is denoted by {h k l} with the integers being the intercepts of the vector when projected onto the crystallographic axes of a unit cell of the lattice (and again reduced to the simplest whole number ratio). Similar to planes in a crystal lattice, many directions in the lattice are crystallographically equivalent to each other due to symmetry of the lattice. Therefore, the notation <h k l> describes the set of directions that are equivalent to direction {h k l} by symmetry.
  • [0034]
    Finally, before the detailed description of the preferred embodiments proceeds, an aspect of a PMOS transistor to which the inventive concept applies will be described. A PMOS transistor formed on a semiconductor substrate includes a gate electrode disposed on the semiconductor substrate, a gate insulating layer interposed between the gate electrode and the substrate, and source/drain electrodes disposed in the semiconductor substrate at both sides of the gate electrode. When a predetermined bias voltage is applied to the PMOS transistor, a channel is formed in the semiconductor substrate under the gate electrode. Holes serving as major charge carriers in the PMOS transistor move through the channel. The mobility of holes in the channel is a factor in the speed of operation of the PMOS. Thus, operating characteristics of the PMOS transistor can be improved by increasing the mobility of the holes.
  • [0035]
    In general, the mobility of charge carriers can be improved by applying physical stress to the channel region beneath the gate electrode to thereby change the energy band structure of the channel region. In the case of a PMOS transistor having holes as major charge carriers, a compressive stress when applied to the channel region can improve the mobility of holes. Also, the mobility of the charge carriers is affected by the orientation of the crystal lattice of the semiconductor substrate. For example, holes serving as major charge carriers in a PMOS transistor have high mobility in the <110> directions of a silicon lattice. Therefore, a channel region of the PMOS transistor is formed so as to extend lengthwise in one of the <110> directions.
  • Embodiment 1
  • [0036]
    A first embodiment of a semiconductor device and a method of fabricating the same will now be described with reference to FIGS. 1-10
  • [0037]
    Referring first to FIGS. 1, 2 and 3, a semiconductor substrate 10 having an active region delimited by a device isolation layer 20 is provided (S10).
  • [0038]
    The semiconductor substrate 10 may be a monocrystalline silicon substrate. Alternatively, the semiconductor substrate 10 may be a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or an epitaxial layer substrate produced by a selective epitaxial growth (SEG) process. In the example of this embodiment that follows, the semiconductor substrate 10 is a silicon substrate.
  • [0039]
    The device isolation layer 20 is formed by forming a trench in the semiconductor substrate 10 and filling the trench with a dielectric material. In this process, the trench can be formed by forming a mask (not illustrated) exposing a field region of the semiconductor substrate 10 and anisotropic ally etching the substrate using the mask as an etch mask. As a result of the anisotropic etching, the top of the trench is generally wider than its bottom. The trench is preferably filled with a dielectric having good gap-filling characteristics. Examples of dielectric material having good gap-filling characteristics include boron-phosphor silicate glass (BPSG), high-density plasma oxides, undoped silicate glass (USG), and Tonen SilaZene (TOSZ).
  • [0040]
    Also, the semiconductor substrate 10 may include a doped region 101. In particular, the semiconductor substrate 10 may include a doped region forming an n-type well (hereinafter also referred to as an N-well).
  • [0041]
    Subsequently, a gate insulator 111 and a gate electrode 121 are formed on the active region with the gate insulator 111 interposed between the gate electrode 121 and the active region (S20).
  • [0042]
    The gate insulator 111 may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer and a high-k dielectric layer, or a combination of such layers. Here, high-k dielectric refers to those materials whose dielectric constant is greater than that of silicon oxide. Examples of high-k dielectrics include tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, aluminum oxide, yttrium oxide, niobium oxide, cesium oxide, indium oxide, iridium oxide, and barium strontium titanate (BST).
  • [0043]
    The gate electrode 121 can be formed by forming a gate conductive layer and a capping layer on the gate insulator 111, and patterning (etching) the resulting structure. That is, the gate electrode 121 may include a gate conductive pattern 121 and a capping pattern 123 on the gate conductive pattern 121. The gate electrode 121 may also extend longitudinally on the active region in one of the <110> directions or the <100> directions of the crystal lattice of the silicon substrate 10.
  • [0044]
    In one example of this embodiment, the gate electrode 121 is formed of doped polysilicon (poly-Si), i.e., polysilicon doped with an n-type or p-type dopant. Thus, in the case in which a PMOS transistor is formed, the gate electrode 121 may be formed of a polysilicon layer doped with a p-type dopant. In another example of this embodiment, the gate electrode 121 is formed of conductive material that has a lower resistivity and a higher work function than doped polysilicon. For example, the gate electrode 121 may be formed of a metal layer and/or a metal nitride layer. Examples of the metal layers include tungsten and molybdenum layers and examples of conductive metal nitride layers include titanium nitride, tantalum nitride, tungsten nitride, and titanium aluminum nitride layers.
  • [0045]
    Next, doped regions are formed in the active region at both sides of the gate electrode 121 (S30). In an example of this embodiment, each doped region includes a lightly-doped region 141 and a heavily-doped region 143 (described below with reference to FIG. 4). The lightly-doped regions 141 are formed in the semiconductor substrate 10 at both sides of the gate electrode 121 by implanting a p-type dopant (e.g., boron (B)) using the gate electrode 121 as an ion implantation mask. In this case, diffusion of the dopant causes the lightly-doped region 141 to extend to a location beneath the gate electrode 121.
  • [0046]
    Also, a channel doped region (not illustrated) may be formed by performing a halo ion implantation process after the p-type lightly-doped region 141 is formed. Such a channel doped region may be formed by ion-implanting an n-type dopant (e.g., arsenic (As)), i.e., a dopant of a conductivity type opposite to the conductivity type of the source/drain region. The n-type channel doped region increases the ion concentration of the active region under the gate electrode 121, thus preventing a punch-through phenomenon.
  • [0047]
    Referring to FIGS. 1, 2 and 4, a spacer 130 is formed on the sidewall of the gate electrode 121 (at both sides of the gate electrode as shown in the figure). In this respect, the spacer 130 may be formed by depositing dielectric material on the semiconductor substrate 10 and performing a blanket anisotropic etching process (e.g., an etch-back process) on the resulting structure.
  • [0048]
    In the illustrated example, the spacer 130 has a structure of stacked dielectric materials having an etch selectivity with respect to one another. More specifically, a silicon oxide layer and a silicon nitride layer are sequentially and conformally formed on the semiconductor substrate 10. The silicon oxide layer can be formed by a chemical vapor deposition (CVD) process or can be formed by thermally oxidizing the gate electrode 121 and the semiconductor substrate 10. The silicon oxide layer cures the sidewall of damage caused when the gate electrode 121 is formed by the aforementioned patterning (etching) process, and serves as a buffer layer between the semiconductor substrate 10 and the silicon nitride layer. The sequentially-formed silicon oxide layer and silicon nitride layer are then etched back to form a dual spacer 130 that includes an L-shaped lower spacer element 131 and an upper spacer element 133 on each side of the gate electrode 121. A dual spacer 130 hampers the creation of a short channel effect which tends to otherwise occur when the channel length (i.e., the distance between the source and drain regions) decreases with increases in the degree to which the semiconductor device is integrated.
  • [0049]
    The heavily-doped region 143 is formed on the semiconductor substrate 10 at both sides of the gate electrode 121 after the spacer 130 is formed. Also, the heavily-doped region 143 may be formed after a recess 105 (described below with reference to FIG. 5) has been formed. In any case, the heavily-doped region 143 may be formed by implanting a p-type dopant (e.g., boron (B)) using the gate electrode 121 and the spacer 130 as an ion implantation mask. In this case as well, the p-type heavily-doped region 143 may extend to a location under the spacer 130.
  • [0050]
    Referring to FIGS. 1, 2 and 5, after spacer 130 has been formed, the semiconductor substrate 10 is selectively etched to form a recess 105 at opposite sides of the gate electrode 121, respectively (S40). In the illustrated example of this embodiment, the bottom of the recess 105 is parallel to the upper surface of or plane of the semiconductor substrate 10. Also, the first and second sides of the recess 105, adjacent the opposite sides of the gate electrode 121, respectively, are inclined with respect to the upper surface of the semiconductor substrate 10. If the lattice of the semiconductor substrate 10 is oriented such that the upper surface or plane thereof is a (100) plane of the lattice, the bottom surface delimiting the bottom of the recess 105 is a (100) plane and first and second sides surfaces delimiting the first and second sides of the recess 105, respectively, may be constituted by a (110), a (111) or a (311) plane. More generally speaking, first and second side surfaces of the substrate that respectively delimit the sides of recess 105 adjacent to the gate electrode 121 each subtend an angle of greater than 90° and less than 180° with respect to the surface that delimits the bottom of the recess 105. Thus, the recess 105 may extend under the gate electrode 121. The recess 105 may also expose sidewalls of the device isolation layer 20.
  • [0051]
    The recess 105 is formed by etching the substrate 10 using the gate electrode 121, the spacer 130 and the device isolation layer 20 as an etch mask. By way of example, the recess 105 may be formed to a depth of about 300 Å to about 1000 Å from the upper surface of the semiconductor substrate 10. Note, in this respect, the heavily-doped region 143 is formed to a depth predetermined to be greater than that of the recess 105. Therefore, the recess 105 exposes the lightly-doped or heavily-doped regions 141 and 143 without exposing the N-well or the underlying portion of the semiconductor substrate 10.
  • [0052]
    An example of a specific process that can be used to form an illustrated recess 105 will now be described.
  • [0053]
    First, a shallow trench is formed adjacent the sides of the gate electrode 121 by dry etching the substrate 10 (isotropically or anisotropically) using the gate electrode 121, the spacer 130 and the device isolation layer 20 as an etch mask. In this process, HCl, Cl2 and H2 may be used as etch gas.
  • [0054]
    Subsequently, the trench is expanded by isotropically etching the substrate, to complete the recess 105. In this isotropic etching process, an organic alkali etchant (e.g., tetra-methyl ammonium-hydroxide (TMAH)) or ammonium hydroxide (NH4OH) is used as an etchant. As a result, the substrate 10 is etched not only in the vertical direction but also in the horizontal direction. Accordingly, a portion of the semiconductor substrate 10 under the spacer 130 is etched when the recess 105 is formed.
  • [0055]
    In particular, in the case in which the semiconductor substrate 10 is a silicon substrate and is wet etched using ammonium hydroxide (NH4OH) as an etchant, the etching rate of the silicon substrate 111 is lowest in a horizontal direction and is highest in a vertical direction normal to the (100) plane. Accordingly, a respective (111) plane defining each side of the recess 105 adjacent the gate electrode 121 will be left. As a result, a tapered structure is located beneath the gate electrode 121 between the sides of the recess each delimited by a respective (111) plane, i.e., the structure has a wedge-shaped cross-sectional area.
  • [0056]
    Also, in this case, the etching processes may create surface defects within the recess 105. Accordingly, after the recess 105 has been formed, the substrate may be cleaned with O3 and HF to remove any surface defects.
  • [0057]
    In another example, the recess adjacent the sides of the gate electrode 121 may be formed only by an anisotropic dry etching process. As a result, the bottom surface delimiting the bottom of the recess is parallel to the upper surface of the semiconductor substrate 10, and the first and second side surfaces delimiting the respective sides of the recess adjacent the gate electrode have an angle of a little more than 90° with respect to the bottom surface. More specifically, the bottom surface of the recess 105 may be a (100) plane and the first and second side surfaces may be constituted by a (110) plane or a (311) plane.
  • [0058]
    The recess adjacent the gate electrode 121 may also be formed by a chemical vapor etching (CVE) process. For example, the recess adjacent the gate electrode 121 may be formed by a CVE process using HCl and H2 as etch gas.
  • [0059]
    Referring to FIGS. 1, 2 and 6, a selective epitaxial growth (SEG) process is performed to form an SiGe epitaxial layer 150 in the recess 105 (S50). Note, at this time, the heavily-doped region 143, which surrounds the recess 105, isolates the epitaxial layer 150 with respect to the N-well of the semiconductor substrate 10.
  • [0060]
    The SEG process, as the name implies, allows for the SiGe epitaxial layer 150 to be selectively grown, in this case only on the surfaces of the semiconductor substrate 10 exposed by the recess 105, i.e., without being formed on the device isolation layer 20. The epitaxial layer formed in the recess 105 has the same crystalline structure as the semiconductor substrate 10 because the semiconductor substrate 10 serves as a seed layer in the SEG process.
  • [0061]
    According to the example of this embodiment in which the transistor being formed is a PMOS transistor, the silicon of the epitaxial layer is provided with germanium, through a doping process, to improve the performance of the PMOS transistor. Germanium has a lattice constant greater than that of the silicon of the semiconductor substrate 10. That is, in this embodiment, the layer formed in the recess 105 is of a semiconductor material that has a lattice constant greater than that of the semiconductor substrate 10 while having the same crystalline structure as the material of the semiconductor substrate 10. For example, the epitaxial layer may be formed of silicon germanium (Si1-xGex, x: 0.1˜0.9), wherein the lattice constant of the silicon germanium is greater than the lattice constant of Si and less than the lattice constant of Ge.
  • [0062]
    As the silicon is doped, the Si atoms in the silicon lattice are replaced with the Ge atoms. Hence, the lattice expands because the lattice constant of Ge is greater than the lattice constant of Si. Accordingly, the SiGe epitaxial layer 150 imparts a compressive stress in the channel region of the PMOS transistor. The stress imparted to the channel region is especially great because the segments of the SiGe epitaxial layer 150 having portions located beneath the spacer 130 have a wedge-shaped profile. Furthermore, the compressive stress is also applied to the gate electrode 121.
  • [0063]
    The SEG process for forming the SiGe epitaxial layer 150 a may be implemented using solid phase epitaxy (SPE), vapor phase epitaxy (VPE) and/or a liquid phase epitaxy (LPE). A chemical vapor deposition (CVD) process, a reduced pressure chemical vapor deposition (RPCVD) process or an ultra high vacuum chemical vapor deposition process may be used in the case in which the SEG process is carried out by VPE.
  • [0064]
    Also, in an example of the SEG process of this embodiment, the SiGe epitaxial layer 150 is formed by exposing the substrate 10 to silicon source gas, germanium source gas, and selective etch gas simultaneously. The silicon source gas may comprise monochlorosilane (SiH3Cl), dichlorosilane (DCS), trichlorosilane (TCS), hexachlorosilane (HCS), SiH4, Si2H6, or a combination thereof. The germanium source gas may comprise GeH4, Ge2H4, GeH3Cl, Ge2H2Cl2, Ge3HCl3, or a combination thereof. The selective etch gas may comprise HCl, Cl2, or a combination thereof. Also, carrier gas may be supplied together with the source gas to uniformly supply the source gas to the surface of the semiconductor substrate 10 during the selective epitaxial process. The carrier gas may include at least one of hydrogen, helium, nitrogen and argon. Also, the selective growth process may be performed at a temperature of at least about 550° C. or greater under a pressure of at least several mTorr.
  • [0065]
    In general, the growth rate of the SiGe epitaxial layer 150 depends on the ratio of the silicon source gas to the germanium source gas. Moreover, the rate at which the SiGe epitaxial layer 150 grows in a particular direction is dependent on the orientation of the underlying crystal plane of the Si seed layer. In this case, the SiGe epitaxial layer 150 grows significantly more quickly in the horizontal direction than in the vertical direction because the SiGe epitaxial layer 150 grows in the (100) direction of the lattice of the silicon substrate while hardly growing in the (110), (111) or (311) directions.
  • [0066]
    The compressive stress on the channel region is proportional to the thickness of the SiGe epitaxial layer 150. Thus, in this embodiment, as shown in FIG. 6, the SiGe epitaxial layer 150 is formed to project above the level of the upper surface of the active region of the semiconductor substrate 10. For example, the top surface 150 t of the SiGe epitaxial layer 150 may be disposed above the level of the upper surface of the gate insulating layer 111. In an example of this embodiment, the top surface 150 t of the SiGe epitaxial layer 150 is about 10 nm to about 40 nm above the upper surface of the active region of the semiconductor substrate 10. Thus, the SiGe epitaxial layer 150 imparts more compressive stress to the channel region than if it were formed flush with the upper surface of the active region.
  • [0067]
    Also, in an example of this embodiment, the upper portion of the SiGe epitaxial layer 150 has a higher concentration of Ge than its lower portion. The lower portion of the epitaxial layer 150, with its relatively low concentration of Ge, minimizes the lattice mismatch between the epitaxial layer 150 and the semiconductor substrate 10 formed of silicon. As an example of this, the lower portion of the epitaxial layer may have a thickness of about 20 nm to about 50 nm, and may have a Ge concentration of about 10% to about 30%, whereas the upper portion of the epitaxial layer may have a thickness of about 40 nm to about 60 nm, and may have a Ge concentration of about 20% to about 50%. In this way, a relatively great compressive stress can be applied to the channel region because the upper portion of the epitaxial layer 150 can have a high concentration of Ge.
  • [0068]
    The epitaxial layer 150 is also doped with a p-type dopant (e.g., boron (B)). The doping may be performed in situ, i.e., during the forming of the SiGe epitaxial layer 150. Alternatively, the p-type dopant may be ion-implanted after the SEG process has been performed. In any case, the p-type doped epitaxial layer constitutes a source/drain region of the PMOS transistor together with the lightly-doped and heavily-doped regions 141 and 143.
  • [0069]
    In the embodiment described above, the SiGe epitaxial layer 150 contacts the lightly-doped and heavily-doped regions 141 and 143. Accordingly, the p-type SiGe epitaxial layer 150, which has a small band gap, does not directly contact the N− well. Therefore, leakage current at the interface between the semiconductor substrate 10 and the SiGe epitaxial layer 150 is suppressed.
  • [0070]
    The resulting SiGe epitaxial layer 150 extends laterally toward the gate electrode 121. For example, the SiGe epitaxial layer 150 has a wedge-shaped portion that extends under the spacer 130. In particular, as described above, the growth rate of the SiGe epitaxial layer 150 differs amongst the directions in the SiGe lattice. Due to this characteristic of the SEG process, inclined surfaces 150 s are produced in the portion of the SiGe epitaxial layer 150 which is formed above the upper surface of the substrate in the upper region. More specifically, the SiGe epitaxial layer 150 may have a bottom surface, and an upper portion having a top surface 150 t and side surfaces 150 s inclined relative to the top surface 150 t.
  • [0071]
    In this case, the bottom surface and the top surface 150 t of the SiGe epitaxial layer 150 are parallel to the upper surface of the active region of the semiconductor substrate 10. That is, if the upper surface of the active region of the semiconductor substrate 10 is a (100) plane of the crystal lattice, the bottom surface and the top surface 150 t of the SiGe epitaxial layer 150 are planes parallel to the (100) plane. The inclined surfaces 150 s of the SiGe epitaxial layer 150 subtend predetermined obtuse angles with respect to the bottom surface or the top surface 150 t. For example, if the upper surface of the active region of the semiconductor substrate 10 is a (100) plane of the lattice, the inclined surfaces 150 s may be parallel to a (111) plane, a (110) plane or a (311) plane.
  • [0072]
    Furthermore, although the inclined surfaces 150 s are illustrated as being located entirely above the level of the upper surface of the active region of the semiconductor substrate 10, portions of the inclined surfaces 150 s of the SiGe epitaxial layer 150 may extend under the upper surface of the active region. In this case, a groove may be formed between the device isolation layer 20 and the recess 105 to accommodate the lower ends of the inclined surface 150 s of the SiGe epitaxial layer 150.
  • [0073]
    Referring still to FIGS. 1, 2 and 6, a selective epitaxial growth (SEG) process is performed to form an Si epitaxial layer 160 on the SiGe epitaxial layer 150 (S60).
  • [0074]
    The Si epitaxial layer 160 is grown only on the SiGe epitaxial layer 150, i.e., the Si epitaxial layer 160 is selectively grown, because it is formed using the SiGe epitaxial layer 150 as a seed layer. The Si epitaxial layer 160 may be formed in situ upon the completion of the process of forming the SiGe epitaxial layer 150.
  • [0075]
    Solid phase epitaxy (SPE), vapor phase epitaxy (VPE) and/or liquid phase epitaxy (LPE) may be used to form the Si epitaxial layer 160. In the case in which a VPE process is used as the SEG process for forming the Si epitaxial layer 160, the VPE process can be realized by means of a chemical vapor deposition (CVD) process, a reduced pressure chemical vapor deposition (RPCVD) process or an ultra high vacuum chemical vapor deposition process.
  • [0076]
    The growth and etching rates of the Si material during the SEG process of forming Si epitaxial layer 160 differ amongst the respective crystal planes and directions of the underlying lattice. When an SEG process is used to form the Si epitaxial layer 160, the growth and etching rates of the Si epitaxial layer 160 may differ amongst different crystal planes constituting the surface of the underlying lattice. Specifically, the growth rate of the Si epitaxial layer 160 is highest on the (100) plane and lowest on the (111) plane, whereas the etching rate of the Si epitaxial layer 160 is lowest on the (100) plane and highest on the (110) plane. Accordingly, if the silicon source gas and the etch gas are simultaneously supplied to form the Si epitaxial layer 160, the layer grows mainly in the vertical direction from the top surface 150 t of the SiGe epitaxial layer 150 (the (100) plane) and significantly less so from the inclined surface 150 s of the SiGe epitaxial layer 150. Therefore, as illustrated in the drawings, an Si epitaxial layer 160′ could very well be formed on only the top surface 150 t of the SiGe epitaxial layer 150 while the inclined surfaces 150 s of the SiGe epitaxial layer 150 remain exposed.
  • [0077]
    However, according to the first embodiment of the inventive concept, the Si epitaxial layer 160 completely caps the portion of the SiGe epitaxial layer 150 that projects above the level of the upper surface of the semiconductor substrate 10. For instance, the Si epitaxial layer 160 covers the top surface 150 t and the inclined surfaces 150 s of the SiGe epitaxial layer 150. The Si epitaxial layer 160 is, for example, about 10 nm to about 30 nm thick on the top surface 150 t of the SiGe epitaxial layer 150. Moreover, the Si epitaxial layer 160 is thicker on the top surface 150 t of the SiGe epitaxial layer 150 than on the inclined surfaces 150 s of the SiGe epitaxial layer 150. Also, the thickness of the Si epitaxial layer 160 may decrease toward the device isolation layer 20.
  • [0078]
    A technique of forming the Si epitaxial layer 160 so that it completely caps the exposed portion of the SiGe epitaxial layer 150 will be described later on in detail with reference to FIGS. 11 and 12 and FIGS. 13A to 13D.
  • [0079]
    Referring to FIGS. 1, 2, 7 and 8, silicide layers 171 and 173 are formed on the source/drain region and the gate electrode 121, respectively, after the Si epitaxial layer 160 has been formed (S70). In this example of the first embodiment, the gate electrode 121 is of doped polysilicon. Also, the proportion of the silicon and metal elements in the silicide layer 171 may be about 90% or more. Furthermore, as mentioned above, preferably, the Si epitaxial layer 160 completely caps the portion of the SiGe epitaxial layer 150 that projects above the level of the upper surface of the semiconductor substrate 10. In this case, it is possible to prevent the metal layer used for forming the silicide layer 171 from contacting the SiGe epitaxial layer 150. Also, it is possible to prevent the metal layer from infiltrating to the semiconductor substrate 10 along the interface between the device isolation layer 20 and the SiGe epitaxial layer 150 where the metal could react with the semiconductor substrate 10.
  • [0080]
    Referring to FIG. 7, first the capping pattern 123 on the gate electrode 121 is removed, and a metal layer 170 is conformally formed on the semiconductor substrate 10. Thus, the metal layer 170 covers the top surface of the gate electrode 121 and the surface of the Si epitaxial layer 160. The metal layer 170 may be formed of a refractory metal such as cobalt, titanium, nickel, tungsten or molybdenum.
  • [0081]
    Subsequently, a thermal treatment process is performed to cause the silicon of the Si epitaxial layer 160 and the gate electrode 121 to react with the metal of layer 170. In an exemplary embodiment, the thermal treatment process comprises heating the substrate at a temperature of about 250° C. to about 800° C. In this respect, a rapid thermal process (RTP) device or furnace may be used to execute the thermal treatment process.
  • [0082]
    As a result of the thermal treatment process, silicon of the gate electrode 121 and the Si epitaxial layer 160 is consumed and the silicide layers 171 and 173 are formed. That is, a portion or the entire Si epitaxial layer 160 may be converted into the silicide layer 171, and an upper portion of the gate electrode 173 is converted into the silicide layer 173. If the entire Si epitaxial layer 160 reacts with the metal layer 170, the silicide layer 171 contacts the top surface 150 t and the inclined surfaces 150 s of the SiGe epitaxial layer 150. Alternatively, if only a portion of the Si epitaxial layer 160 reacts with the metal layer 170, an Si epitaxial layer remains between the silicide layer 171 and the SiGe epitaxial layer 150. In any case, as illustrated in FIG. 8, silicide layer 171 is formed on the SiGe epitaxial layer 150 and silicide layer 173 is formed on the gate electrode 121.
  • [0083]
    Thus, as can be seen in FIG. 8, first and second epitaxial regions comprising germanium are located in a surface of the active region of the substrate 10 on respective opposite sides of the gate electrode structure, first and second silicide layers 171 are located on the first and second epitaxial regions, respectively, and at least a portion of each of the first and second silicide layers 171 is devoid of germanium, and comprises silicon and either a metal or metal alloy.
  • [0084]
    According to an example of this embodiment, the metal layer 170 is a nickel layer, formed of pure nickel or a nickel alloy. In the case of nickel alloy, the metal layer 170 may contain at least one material selected from the group consisting of tantalum (Ta), zirconium (Zr), titanium (Ti), hafnium (Hf), tungsten (W), cobalt (Co), platinum (Pt), molybdenum (Mo), palladium (Pd), vanadium (V) and niobium (Nb).
  • [0085]
    Now, if the Si epitaxial layer had been locally formed only on the top surface 150 t of the SiGe epitaxial layer 150 (as was described with reference to FIG. 6 vis-à-vis layer 160′), the metal layer 170 would directly cover the inclined surfaces 150 s of the SiGe epitaxial layer 150. If the metal layer were formed of nickel, the nickel would react with the silicon substrate 10 at the interface between the device isolation layer 20 and the SiGe epitaxial layer 150 during the thermal treatment process because the reaction rate of silicon and nickel is higher than the reaction rate of silicon germanium and nickel. Accordingly, the resulting nickel silicide layer would encroach upon the semiconductor substrate 10 adjacent to the SiGe epitaxial layer 150. The nickel silicide layer would thus facilitate junction leakage current and thereby degrade the breakdown voltage characteristics of the PMOS transistor.
  • [0086]
    However, according to an aspect of the inventive concept, the Si epitaxial layer 160 covers the top surface 150 t and the inclined surface 150 s of the SiGe epitaxial layer 150. Therefore, the metal layer 170 (i.e., the nickel layer) is spaced apart from the SiGe epitaxial layer 150 and the semiconductor substrate 10 as illustrated in FIG. 7. Accordingly, the nickel silicide layer 171 formed on the semiconductor substrate 10, as the end result of the thermal treatment process, does not encroach upon the semiconductor substrate 10. Also, because the metal layer 170 is prevented from reacting with the SiGe epitaxial layer 150 when the silicide layer 171 is formed, there is no increase in contact resistance in the source/drain region.
  • [0087]
    Finally, in the example in which the silicide layer 171 is a nickel silicide layer, the silicide layer 171 may be a layer of NiSi, NiSi2, Ni3Si2, Ni2Si or Ni31Si12. Also, the silicide layer 171 may have a composition of NixSi1-x (0<x<1). An advantage of forming the silicide layer 171 of nickel silicide is that nickel silicide has a lower resistivity than cobalt silicide and titanium silicide and is formed by reacting nickel with silicon at a lower temperature than the temperature necessary to cause cobalt or titanium to react with silicon.
  • [0088]
    After the thermal treatment process, a wet etching process is performed to remove any un-silicided un-reacted metal. The wet etching process may use a solution of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) as an etchant.
  • [0089]
    Referring to FIGS. 1, 2 and 9, a contact plug 190 connected to the silicide layer 171 is formed after the silicide layers 171 and 173 are formed.
  • [0090]
    More specifically, a conformal etch stop layer 180 may be formed on the semiconductor substrate 10. The etch stop layer 180 may comprise a silicon nitride layer or a silicon oxynitride layer. Next, an interlayer dielectric (ILD) 185 is formed on the semiconductor substrate 10. The interlayer dielectric 185 may be formed of O3-TEOS (O3-Tetra Ethyl OrthoSilicate), USG (Undoped Silicate Glass), PSG (PhosphoSilicate Glass), BSG (Borosilicate Glass), BPSG (BorophosphoSilicate Glass), FSG (Fluoride Silicate Glass), SOG (Spin On Glass), TOSZ (Tonen SilaZene), or a combination thereof. Also, the interlayer dielectric 185 may be formed by a CVD process or a spin coating process. The structure may be planarized after the interlayer dielectric 185 has been formed.
  • [0091]
    Contact holes exposing the silicide layer 171 are then formed in the interlayer dielectric 185. The contact holes can be formed by forming a mask on the interlayer dielectric 185, and anisotropically etching the interlayer dielectric 185 using the mask as an etch mask.
  • [0092]
    Subsequently, the contact holes are filled with a conductive material to form contact plugs 190. The contact plugs 190 are preferably formed of a low-resistivity metal material. For example, the contact plugs 190 may be formed of at least one metal layer (e.g., at least one of a cobalt layer, a titanium layer, a nickel layer, a tungsten layer and a molybdenum layer) and a conductive metal nitride layer (e.g., a titanium nitride layer, a tantalum nitride layer, a tungsten nitride layer or a titanium aluminum nitride layer). Furthermore, a metal barrier layer may be formed before the contact plugs 190 to prevent the diffusion of the metal material of the contact plugs 190. In this case, the metal barrier layer may comprise a conductive metal nitride layer such as a tungsten nitride (WN) layer, a tantalum nitride (TiN) layer or a titanium nitride (TaN) layer.
  • [0093]
    Note, although contact plugs 190 are shown as respectively connected to the gate silicide layer 173 and each silicide layer 171, a semiconductor device according to the inventive concept may have various other arrangements of the contact plugs 190.
  • [0094]
    Method of Forming Silicon Epitaxial Layer
  • [0095]
    Referring to FIG. 11, the forming of the Si epitaxial layer 160 includes: alternately supplying silicon source gas (S1) and selective etch gas (S2) into a processing chamber, in which the semiconductor substrate 10 is disposed, as a cycle of operations; and then repeating the cycle at least once. The silicon source gas may comprise monochlorosilane (SiH3Cl), dichlorosilane (DCS), trichlorosilane (TCS), hexachlorosilane (HCS), SiH4, Si2H6, or a combination thereof. The selective etch gas may comprise HCl, Cl2, or a combination thereof. Also, carrier gas may be supplied together with the silicon source gas so that the silicon source gas is uniformly dispersed over the semiconductor substrate 10. In this case, the carrier gas may comprise at least one of hydrogen, helium, nitrogen and argon. Also, the Si epitaxial layer 160 may be grown by conducting the process at a temperature of about 550° C. to about 700° C. under a pressure of several mTorr or less.
  • [0096]
    More specifically, and referring FIGS. 11 and 13A, the silicon source gas is supplied to the semiconductor substrate 10 on which the SiGe epitaxial layer 150 and the device isolation layer 20 have been formed (S1). In an example of this embodiment, a silane not including a chloride (e.g., SiH4 and Si2H6) is used as the silicon source gas. The silane dissolves at about 650° C. into silicon atoms. At this time, the epitaxial layer is not etched because the dissolution of the silane does not produce any by-product corrosive to the epitaxial layer, such as a hydrogen chloride (HCl).
  • [0097]
    The silicon atoms generated by dissolving the silicon source gas bond with the surfaces of the device isolation layer 20 and the SiGe epitaxial layer 150. Accordingly, silicon layers 31 and 32 are formed on the surfaces of the device isolation layer 20 and the SiGe epitaxial layer 150. Here, the bonding force between an Si atom and the SiGe epitaxial layer 150 is stronger than the bonding force between a dielectric layer and an Si atom. Thus, the silicon layer 31 formed on the SiGe epitaxial layer 150 is thicker than the silicon layer 32 formed on the device isolation layer 20. Also, the silicon atoms may bond to only parts of the surface of the device isolation layer 20 as shown in the figure.
  • [0098]
    Meanwhile, as described above, because the growth rate of the Si epitaxial layer 160 depends on the crystal plane of the underlying lattice, the thickness of the silicon layer 31 growing on the top surface 150 t of the SiGe epitaxial layer 150 becomes different from the thickness of the silicon layer 31 growing on an inclined surface 150 s of the SiGe epitaxial layer 150. Specifically, the silicon layer 31 is thinner on the inclined surface 150 s of the SiGe epitaxial layer 150 than on the top surface 150 t of the SiGe epitaxial layer 150 parallel to the upper surface of the semiconductor substrate 10.
  • [0099]
    Referring to FIGS. 11 and 13B, next, the supplying of the silicon source gas is stopped, and the selective etch gas is supplied (S2). The selective etch gas comprises a halogen that will react with the silicon atoms. More specifically, when the selective etch gas is supplied to the semiconductor substrate 10, chlorine atoms of the selective etch gas bond with the Si to separate the silicon atoms from the SiGe epitaxial layer 150 and the device isolation layer 20. However, the Si on the device isolation layer 20 is removed by the etch gas more rapidly than the Si on the SiGe epitaxial layer 150 because the bonding force between the device isolation layer 20 and the silicon atoms is weak. Thus, the silicon layer 32 is removed from the device isolation layer 20, and the structure is left with a silicon epitaxial layer 33 on the SiGe epitaxial layer 150. Furthermore, the flow rate and/or the supply time of the selective etch gas is regulated to be lower than that of the silicon source gas to ensure that the silicon layer 31 is not completely removed from the SiGe epitaxial layer 150 during the cycle. Subsequently, as illustrated in FIGS. 11 and 13C, the silicon source gas is again supplied, and new silicon atoms bond to the surfaces of the device isolation layer 20 and the silicon epitaxial layer 33. Accordingly, the thickness of the silicon layer on the SiGe epitaxial layer 150 increases. Then, as illustrated in FIGS. 11 and 13D, the selective etch gas is supplied to remove all of the new silicon atoms from the device isolation layer 20, leaving another thickness 37 of the silicon epitaxial layer on the SiGe epitaxial layer 150.
  • [0100]
    The cycle may be repeated until a silicon layer of a predetermined thickness remains on the SiGe epitaxial layer 150.
  • [0101]
    In another technique illustrated in FIG. 12, the forming of the Si epitaxial layer 160 includes: supplying the silicon source gas (S1), supplying purge gas in a first purge operation (P1), supplying the selective etch gas (S2), and supplying purge gas in a second purge operation (P2) in the foregoing sequence, into a process chamber in which the semiconductor substrate 10 is disposed, as a cycle of operations; and then repeating the cycle at least once.
  • [0102]
    According to this technique, the first purge operation P1 is performed to remove any silicon atoms that have not bonded to the surfaces of the device isolation layer 20 and the SiGe epitaxial layer 150 after the silicon source gas has been supplied. The purge gas may comprise hydrogen, helium, nitrogen or argon, and may be different from the carrier gas. On the other hand, the second purge operation P2 is performed to remove the by-products (e.g., SiCl4 and SiCl3) of the reaction between the silicon atoms and the chorine atoms of the selective etch gas. In this operation as well, the purge gas may comprise hydrogen, helium, nitrogen or argon, and may be different from the carrier gas.
  • [0103]
    These techniques may be carried out using batch-type high-vacuum CVD equipment. Thus, the selective Si epitaxial layer growth process may be performed on a plurality of semiconductor substrates 10 at a time.
  • Embodiment 2
  • [0104]
    Processes in a second embodiment of a method of fabricating a semiconductor device according to the inventive concept are illustrated in FIGS. 14 to 16. Aspects of this embodiment, other than those described below, are similar to those of the first embodiment and hence, will not be described in detail for the sake of brevity. Mainly, though, this embodiment differs from the first embodiment in that a dielectric spacer 165 is formed on the device isolation layer 20 to cover one side of the Si epitaxial layer 160 before a silicide process is performed.
  • [0105]
    Specifically, as illustrated in FIG. 14, after the Si epitaxial layer 160 is formed, a dielectric layer is conformally formed on the semiconductor substrate 10. The dielectric layer may comprise a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof.
  • [0106]
    Subsequently, a blanket anisotropic etching process (e.g., an etch-back process) is performed to etch the dielectric layer until the Si epitaxial layer 160 is exposed. Because the SiGe epitaxial layer 150 is elevated above the upper surface of the active region of the semiconductor substrate 10, a dielectric spacer 165 is formed over the inclined surface 150 s of the SiGe epitaxial layer 150 at one side of the Si epitaxial layer 160. Similarly, the dielectric spacer 165 is also formed on one side of the gate spacer 130.
  • [0107]
    Referring to FIG. 15, a metal layer 170 is conformally formed on the semiconductor substrate 10. Thus, the metal layer 170 covers the device isolation layer 20, the dielectric spacer 165, the Si epitaxial layer 160, and the gate electrode 121. Also, only the top surface of the Si epitaxial layer 160 parallel to the upper surface of the semiconductor substrate 10 contacts the metal layer 170 because the side of the Si epitaxial layer 160 is covered by the dielectric spacer 165.
  • [0108]
    Subsequently, a thermal treatment process is performed to cause the metal layer 170 to react with the Si epitaxial layer 160 as described with reference to FIG. 7, thereby forming a silicide layer 171 on the SiGe epitaxial layer 150 as illustrated in FIG. 16. In this case, the metal material of layer 170 is prevented from reacting with the semiconductor substrate 10 and the SiGe epitaxial layer 150 because the Si epitaxial layer 160 and the dielectric spacer 165 are disposed between the metal layer 170 and the inclined surface 150 s of the SiGe epitaxial layer 150. That is, it is possible to prevent an encroachment of the nickel silicide layer 171 upon the semiconductor substrate 10.
  • [0109]
    Furthermore, in this embodiment, the Si epitaxial layer 160 remains on the inclined surfaces 150 s of the SiGe epitaxial layer 150, i.e., does not react there with the metal layer 170 during the siliciding process, because the metal layer 170 locally contacts only the top surface 160 t of the Si epitaxial layer 160. That is, the silicide layer 171 may be locally formed on the top surface 150 t of the SiGe epitaxial layer 150.
  • Embodiment 3
  • [0110]
    A third embodiment of a method of fabricating a semiconductor device according to the inventive concept will now be described with reference to FIGS. 17 to 20. Aspects of this embodiment, other than those described below, are similar to those of the first embodiment and hence, will not be described in detail for the sake of brevity.
  • [0111]
    Referring first to FIG. 17, an etch stop layer 180 and an interlayer dielectric 185 are sequentially formed on the semiconductor substrate 10 after the Si epitaxial layer 160 has been formed. As was described with reference to FIG. 9, the etch stop layer 180 is conformally formed on the semiconductor substrate 10. Also, the interlayer dielectric 185 is formed of dielectric material having good step coverage. Then, the interlayer dielectric 185 is patterned to form contact holes exposing the Si epitaxial layer 160. At this time, a contact hole may also be formed to expose the gate electrode 121.
  • [0112]
    Referring to FIG. 18, a metal layer 170 is conformally formed on the interlayer dielectric 185 through which the contact holes have been formed, and a thermal treatment process is performed to form silicide layers 171 and 173.
  • [0113]
    In this embodiment, only that portion of the Si epitaxial layer 160 exposed by a contact hole reacts with the metal layer 170 to form the silicide layer 171. That is, the silicide layer 171 is locally formed on the top surface 150 t of the SiGe epitaxial layer 150, and an Si epitaxial layer 160 remains on the inclined surfaces 150 s of the SiGe epitaxial layer 150.
  • [0114]
    Next, the metal layer 170 not reacting with the Si epitaxial layer 160 on the interlayer dielectric 185 is removed, and the contact holes are filled with a conductive material to form contact plugs 190 contacting the silicide layer as illustrated in FIG. 19.
  • [0115]
    Meanwhile, as illustrated in FIG. 20, due to an alignment error in the process of forming the contact holes, the contact holes may expose the inclined surfaces 150 s of the SiGe epitaxial layer 150. If the Si epitaxial layer were selectively formed on the top surface 150 t of the SiGe epitaxial layer 150 (refer to an illustration of this case depicted by layer 160′ in FIG. 6), the inclined surface 150 s of the SiGe epitaxial layer 150 would be exposed by the contact hole. In this case, in the silicide process, the metal layer 170 would directly contact the SiGe epitaxial layer 150, the metal layer 170 would infiltrate between the SiGe epitaxial layer 150 and the device isolation layer 20, and hence the metal layer would react with the semiconductor substrate 10 during the siliciding process.
  • [0116]
    However, in this embodiment, as illustrated in FIG. 20, even in the case of an alignment error in which the contact holes are aligned with the inclined surface 150 s of the SiGe epitaxial layer 150, the metal layer 170 is prevented from reacting with the SiGe epitaxial layer 150 or the semiconductor substrate 10 because the inclined surface 150 s of the SiGe epitaxial layer 150 is covered by the Si epitaxial layer 160.
  • Embodiment 4
  • [0117]
    A fourth embodiment of a method of fabricating a semiconductor device according to the inventive concept will now be described with reference to FIG. 21 and FIGS. 22 to 27.
  • [0118]
    In this embodiment, a CMOS device constituted by NMOS and PMOS transistors is formed. As was described above, the operating characteristics of a PMOS transistor can be improved by improving the mobility of holes in the channel region. Also, as was described above, the operating characteristics of an NMOS transistor may be improved by improving the mobility of electrons in the channel region. When the channel region of the NMOS transistor is formed lengthwise in any of the <110> directions, tensile stress applied to the channel region of the NMOS transistor improves the mobility of electrons through the channel.
  • [0119]
    Referring now to FIGS. 21 and 22, a semiconductor substrate 10 including a first region 100 for accommodating PMOS transistors and a second region 200 for accommodating NMOS transistors is provided (S110).
  • [0120]
    As described with respect to Embodiment 1, the semiconductor substrate 10 may be a silicon substrate with a (100) plane. Furthermore, first and second active regions are respectively defined in the first and second regions 100 and 200 by the device isolation layer 20. The semiconductor substrate 10 also includes n-type and p-type doped wells 101 and 201. For example, the first active region includes an n-type well 101 for PMOS transistors, and the second active region includes a p-type well 201 for NMOS transistors.
  • [0121]
    Next, first gate electrodes 121 and second gate electrodes 221 are formed respectively on the first and second regions 100 and 200 (S120). For simplicity, reference may be made at times to only one of the first gate electrodes and only one of the second gate electrodes hereafter.
  • [0122]
    The first and second gate electrodes are formed by sequentially forming a gate insulating layer, a gate conductive layer and a capping layer on the first and second regions 100 and 200 and patterning the resulting stack of layers. Herein, the first and second gate insulating layers 111 and 211 may comprise a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a high-k dielectric layer, or a combination thereof. Thus, a first gate structure having a first gate insulating layer 111, the first gate electrode 121 and a first capping layer 123 is formed on the first region 100, and a second gate structure having a second gate insulating layer 211, the second gate electrode 221 and a second capping layer 223 is formed on the second region 200. The first and second gate electrodes 121 and 221 may each be of n-type or p-type doped polysilicon (poly-Si). Alternatively, the first and second gate electrodes 121 and 221 may each be of a metal material.
  • [0123]
    Subsequently, a first spacer 130 a is formed on opposite sidewalls of the first gate electrode 121, and a first spacer 230 a is formed on opposite sidewalls of the second gate electrode 221. Specifically, a dielectric layer is formed on the semiconductor substrate 10, and then a blanket anisotropic etching process (e.g., an etch-back process) is performed to form the first spacers 130 a and 230 a. The first spacers 130 a and 230 a may be formed by sequentially forming an oxide layer and a nitride layer and etching back the oxide layer and the nitride layer. In this case, each of the first spacers 130 a and 230 a includes L-shaped lower spacer elements and upper spacer elements. The oxide layer cures the sidewalls of the first and second gate electrodes 121 and 221 of any damage which may have occurred when the layers were patterned to form the first and second gate electrodes 121 and 221. In addition, the oxide layer can serve as a buffer between the nitride layer and the first and second gate electrodes 121 and 221.
  • [0124]
    Next, p-type doped regions are formed at both sides of the first gate electrode 121, and n-type doped regions are formed at both sides of the second gate electrode 221. In an example of this embodiment, the n-type and p-type doped regions each include lightly-doped and heavily-doped regions.
  • [0125]
    Specifically, the first region 100 is covered by a mask and an n-type dopant (e.g., As) is ion-implanted into the semiconductor substrate 10 at both sides of the second gate electrode 221 to form an n-type lightly-doped region 241. Subsequently, a p-type channel doped region may be formed under the second gate electrode 221 to prevent a punch-through phenomenon.
  • [0126]
    Then, the second region 200 is covered by a mask and a p-type dopant (e.g., B) is ion-implanted into the semiconductor substrate 10 at both sides of the first gate electrode 121 to form a p-type lightly-doped region 141. Thereafter, an n-type channel doped region may be formed under the first gate electrode 121 to prevent a punch-through phenomenon.
  • [0127]
    Referring to FIG. 23, a second spacer 130 b is formed on both sides of the first gate electrode 121, and a second spacer 230 b is formed on both sides of the second gate electrode 221. Specifically, a dielectric layer is deposited on the semiconductor substrate 10, and then a blanket anisotropic etching process (e.g., an etch-back process) is performed to form the second spacers 130 b and 230 b. Similar to the process of forming the first spacers 130 a and 230 a, the second spacers 130 b and 230 b may be formed by sequentially forming an oxide layer and a nitride layer and etching back the oxide layer and the nitride layer. Accordingly, the second spacers 130 b and 230 b may each include L-shaped lower spacer elements and upper spacer elements.
  • [0128]
    Next, n-type and p-type heavily-doped regions 143 and 243 are formed. The second spacers 130 b and 230 b serve to increase the distance between adjacent ones of the heavily-doped regions 143 and adjacent ones of the heavily-doped regions 243. Thus, the second spacers 130 b and 230 b act as a means to ensure that the resulting transistors are not prone to experiencing a short channel effect.
  • [0129]
    Similar to the processes of forming the lightly-doped regions 141 and 241, the respective processes of forming the heavily-doped regions 143 and 243 may be performed sequentially on the first and second regions 200. That is, the first region 100 is covered by a mask and an n-type dopant (e.g., As) is ion-implanted into the semiconductor substrate 10 at both sides of the second gate electrode 221 to form n-type heavily-doped regions 243. Then, the second region 200 is covered by a mask and a p-type dopant (e.g., B) is ion-implanted into the semiconductor substrate 10 at both sides of the first gate electrode 121 to form p-type heavily-doped regions 143.
  • [0130]
    Referring to FIGS. 21 and 24, a recess 105 is formed to a predetermined depth in the semiconductor substrate 10 at both sides of the gate electrode 121 (S140). Note, the depth to which the dopant is implanted in the forming of the p-type heavily-doped regions 143 is predetermined to be greater than the depth of the recess 105. Thus, as was described above, the p-type heavily-doped regions 143 prevent the recess 105 from exposing the N-well 101 and therefore serve to prevent leakage current through defects formed on the surfaces delimiting the recess 105.
  • [0131]
    The recess 105 is formed by covering the second region 200 with a mask 302 and then, as was described with reference to FIG. 5, the substrate 10 is etched using the first gate electrode 121, the first and second spacers 130 b and 230 b and the device isolation layer 20 as an etch mask.
  • [0132]
    In this embodiment, the recess 105 is formed between the device isolation layer 20 and an adjacent first gate electrode 121 and between adjacent ones of the first gate electrodes 121. Also, as is clear from the description of FIG. 5, the recess 105 may be defined by a bottom surface parallel to the upper surface of the active region of the substrate 10, and first and second side surfaces adjacent to a first gate electrode 121 and inclined (at an obtuse angle) relative to the bottom surface. Again reference may be made to the description of FIG. 5 for other aspects and features of the recess.
  • [0133]
    Referring to FIGS. 21 and 25, an SiGe epitaxial layer 150 is grown in the recess 105 (S150).
  • [0134]
    The SiGe epitaxial layer 150 is formed by a selective epitaxial growth process. For all aspects of this process and characteristics of the resulting SiGe epitaxial layer 150, reference may be had to the description of FIG. 6.
  • [0135]
    In this embodiment, the segment of the SiGe epitaxial layer 150 grown between adjacent ones of the first gate electrodes 121 is confined between the second spacers 130 b on the confronting sidewalls of the adjacent ones of the first gate electrodes 121. Thus, the segment of the SiGe epitaxial layer 150 grown between the adjacent first gate electrodes 121 contacts the second spacers 130 b. More specifically, inclined surfaces 150 s of the upper portion of the SiGe epitaxial layer 150, which projects above the level of the upper surface of the active region of the semiconductor substrate 10, contact the second spacers 130 b.
  • [0136]
    Subsequently, a selective epitaxial growth process is performed to form an Si epitaxial layer 160 on the SiGe epitaxial layer 150 (S160). This process is performed in any of the manners described above with reference to FIGS. 12 to 17.
  • [0137]
    Referring to FIGS. 21 and 26, silicide layers 171, 173, 271 and 273 are formed in the first and second regions 100 and 200 (S170).
  • [0138]
    Specifically, the mask 302 covering the second region 200 is removed. Also, in the case in which the first and second gate electrodes 121 and 221 are formed of doped polysilicon, the capping patterns 123 and 121 are removed. Subsequently, a metal layer is conformally formed over the entirety of the first and second regions 100 and 200, and a thermal treatment process is performed on the resulting structure. As was described above, the metal layer is preferably a nickel layer. As a result of the thermal treatment process, the metal layer reacts with the Si epitaxial layers 160 on the first region 100, the first and second gate electrodes 121 and 221, and the doped regions 243 of the second region 200. Accordingly, the silicide layers 171 and 271 are formed on the SiGe epitaxial layer 150 on the first region 100 and the doped regions 243 of the second region 200, and the gate silicide layers 173 and 273 are formed on the first and second gate electrodes 121 and 221. Also, any part of the metal layer which has not reacted with the silicon may be removed after the thermal treatment process.
  • [0139]
    Referring to FIGS. 21 and 27, contact plugs 190 and 290 connected to the silicide layers 171, 173, 271 and 273 are then formed.
  • [0140]
    Specifically, an etch stop layer 180 and an interlayer dielectric 185 are sequentially formed on the semiconductor substrate 10 as described with reference to FIG. 9. Furthermore, a stress-inducing layer, including internal stress, may be formed on the second region 200 of the semiconductor substrate 10 before the interlayer dielectric 185 is formed. The stress in the layer is “memorized” as compressive stress by the source and drain regions at opposite sides of the gate electrode 121 such that tensile stress is imparted to the channel region of the NMOS transistor.
  • [0141]
    In any case, the etch stop layer 180 and the interlayer dielectric 185 are patterned to form contact holes that expose the silicide layers 171, 173, 271 and 273. Ideally, respective ones of the contact holes expose those portions of the silicide layer 171 situated only on the top surface 150 t of the SiGe epitaxial layer 150. Next, the contact holes are filled with conductive material to form contact plugs 190 and 290. FIG. 27 illustrates an example in which a respective contact plug is connected to each silicide layer. However, other arrangements of the contact plugs are possible within the scope of the inventive concept.
  • [0142]
    However, the contact holes formed to expose the silicide layer 171 may instead be aligned with inclined surfaces 150 s of the SiGe epitaxial layer 150. Nonetheless, the contact plugs that fill these contact holes do not contact the SiGe epitaxial layer 150 because even the inclined surfaces 150 s of the SiGe epitaxial layer 150 are covered by the silicide layer 171. Therefore, an increase in contact resistance is prevented.
  • [0143]
    In another example of this embodiment, the silicide process may be performed after the interlayer dielectric 185 and contact holes have been formed, as described with reference to FIGS. 17 to 19. That is, in this example, contact holes are formed in the interlayer dielectric 185, and the metal layer 170 is conformally formed on the interlayer dielectric 185. Then, the silicide layers 171, 173, 271 and 273 are formed by thermally treating the structure. In this case, only those portions of the Si epitaxial layer 160 on the first region 100 and doped regions of the second region which were exposed by the contact holes react with the metal layer to form a silicide. That is, the silicide layers 171 and 271 are locally formed on the top surface 150 t of the SiGe epitaxial layer 150 and on the n-type heavily-doped region 243, and the Si epitaxial layer may remain on the inclined surfaces 150 s of the SiGe epitaxial layer 150.
  • Embodiment 5
  • [0144]
    A fifth embodiment of a method of fabricating a semiconductor device will now be described with reference to FIGS. 28 and 29. Aspects of this embodiment, other than those described below, are similar to those of the first and fourth embodiments and hence, will not be described in detail for the sake of brevity.
  • [0145]
    Basically, this method of fabricating a semiconductor device according to the inventive concept is the same as that of fourth embodiment with the exception of forming an SiC epitaxial layer 250 in the n-type source/drain region of the NMOS transistor.
  • [0146]
    Specifically, the forming of the SiC epitaxial layer 250 at both sides of the second gate electrode 221 includes: forming a trench in the semiconductor substrate 10 at both sides of the second gate electrode 221; and performing a selective epitaxial growth process to grow an SiC layer in the trench.
  • [0147]
    The trench may be formed by anisotropically etching the substrate 10 using the second gate electrode 221 and the spacers as an etch mask. At this time, the first region 100 is covered with a mask.
  • [0148]
    The selective epitaxial growth process for forming the SiC epitaxial layer 250 may be performed by simultaneously supplying silicon source gas, carbon source gas and selective etch gas to the substrate 10. The silicon source gas may comprise dichlorosilane (DCS), trichlorosilane (TCS), hexachlorosilane (HCS), SiH4, Si2H6, or a combination thereof. The carbon source gas may comprise SiH3CH3, CH4, C2H4, or a combination thereof. The selective etch gas may comprise HCl, Cl2, or a combination thereof.
  • [0149]
    The lattice constant of carbon is smaller than the lattice constant of silicon. Therefore, the lattice of the substrate 10 at both sides of the second gate electrode 221 contracts when the SiC epitaxial layer 250 is formed. As a result of the contraction of the lattice, tensile stress is induced in the channel region under the second gate electrode 221. Accordingly, the mobility of electrons in the channel under the second gate electrode 221 is improved.
  • [0150]
    Also, in an example of this embodiment, the mask 302 may be removed after the SiGe and SiC epitaxial layers 150 and 250 have been formed. The Si epitaxial layer 160 is then grown on not only the exposed of the SiGe epitaxial layer 150 but also on the exposed surface of the SiC epitaxial layer 250. Then, the siliciding process is performed so that the SiC epitaxial layer 250 is silicided as well. Thus, a semiconductor device according to the inventive concept may have first and second epitaxial regions comprising carbon located on respective opposite sides of a gate electrode structure (comprising gate electrode 221) in the active region in region 200 of the substrate 10, and first and second silicide layers located on the first and second epitaxial regions, respectively, wherein at least a portion of each of the first and second silicide layers is devoid of carbon and comprises silicon and either a metal or metal alloy.
  • Embodiment 6
  • [0151]
    A sixth embodiment of a method of fabricating a semiconductor device according to the inventive concept will now be described with reference to FIG. 30 and FIGS. 31 to 34. Aspects of this embodiment, other than those described below, are similar to those of the previous embodiments and hence, will not be described in detail for the sake of brevity. In particular, the sixth embodiment of the method of fabricating a semiconductor device is essentially the same as that of the first and fourth embodiments with the exception of the forming of the end gate electrodes. In this embodiment, metal gate electrodes are formed after the silicide layers 171 and 271 have been formed in source/drain regions.
  • [0152]
    Referring to FIGS. 30 and 31, a metal layer is conformally formed on the entirety of the first and second regions 100 and 200 of the substrate 10, and a thermal treatment process is performed on the resulting structure. As a result, the metal layer reacts with the Si epitaxial layer and the n-type doped regions. At this time, a silicide layer is not formed on the first and second gate electrodes 121 and 221 because the first and second capping patterns 123 and 223 are interposed between the metal layer and the first and second gate electrodes 121 and 221. Accordingly, silicide layers are formed only on the source/drain regions of the NMOS and PMOS transistors.
  • [0153]
    An etch stop layer 180 and an interlayer dielectric 185 are then sequentially formed as described with reference to FIG. 9. In this embodiment, the interlayer dielectric 185 may be formed to such a thickness as to cover the first and second gate electrodes 121 and 221, and then is planarized.
  • [0154]
    Referring to FIG. 32, the first and second capping patterns 123 and 223 and the first and second gate electrodes 121 and 221 are then removed to form openings 186 that expose first and second gate insulating layers 111 and 211. The first and second gate electrodes 121 and 221 can be removed by a wet etching process using an etchant having an etch selectivity with respect to first spacers 130 a and 230 a and the first and second gate electrodes 121 and 221.
  • [0155]
    Referring to FIG. 33, metal gate electrodes 187 and 287 are formed in the openings 186. The forming of the metal gate electrodes 187 and 287 may include: forming a metal layer on the interlayer dielectric 185 to such a thickness as to overfill the openings 186 using a deposition process having good step coverage; and planarizing the metal layer to expose the interlayer dielectric 185. In this respect, the metal gate electrodes 187 and 287 may be formed of a metal layer and/or a metal nitride layer. Examples of the metal layers include aluminum, tungsten and molybdenum layers and examples of conductive metal nitride layers include titanium nitride, tantalum nitride, tungsten nitride, and titanium aluminum nitride layers. Also, a metal barrier layer may be formed on the sides of the opening before the metal layer has been formed to prevent the diffusion of the metal material of the layer. For example, the metal barrier layer may comprise a conductive metal nitride layer such as a tungsten nitride (WN) layer, a tantalum nitride (TiN) layer or a titanium nitride (TaN) layer.
  • [0156]
    Contact plugs 190 and 290 connected to the silicide layers 171 and 271 are then formed as illustrated in FIG. 34.
  • [0157]
    In another example of this embodiment, the silicide process is performed after the contact holes have been formed. Accordingly, as illustrated in FIG. 35, only that portion of the Si epitaxial layer exposed by a contact hole reacts with the metal layer to form silicide layers 175 and 275. That is, the silicide layers 175 and 275 are locally formed on the top surface 150 t of the SiGe epitaxial layer 150 and on the n-type heavily-doped region 143, and an Si epitaxial layer remains on the inclined surfaces of the upper portion of the SiGe epitaxial layer 150.
  • [0158]
    PMOS transistors according to the inventive concept may be used in a logic circuit. For example, the PMOS transistors may constitute a CMOS inverter or an SRAM.
  • [0159]
    A CMOS inverter according to the inventive concept will now be described with reference to the circuit diagram of FIG. 36.
  • [0160]
    The CMOS inverter includes a PMOS transistor P1 and an NMOS transistor N1. The PMOS and NMOS transistors are connected in series between a driving voltage terminal Vdd and a ground voltage terminal, and a common input signal is inputted to the gates of the PMOS and NMOS transistors. A common output signal is outputted from the drains of the PMOS and NMOS transistors. Also, a driving voltage is applied to the source of the PMOS transistor, and a ground voltage is applied to the source of the NMOS transistor. The CMOS inverter inverts an input signal IN and outputs the resulting signal as an output signal OUT. In other words, when a logic level ‘1’ is inputted as the inverter input signal, a logic level ‘0’ is outputted as the output signal. On the other hand, when a logic level ‘0’ is inputted as the inverter input signal, a logic level ‘1’ is outputted as the output signal.
  • [0161]
    An SRAM including a CMOS device according to the inventive concept will now be described with reference to the circuit diagram of FIG. 37.
  • [0162]
    One cell in the SRAM includes first and second access transistors Q1 and Q2, first and second driving transistors Q3 and Q4, and first and second load transistors Q5 and Q6. The sources of the first and second driving (pull-up) transistors Q3 and Q4 are connected to a ground line VSS, and the sources of the first and second load (driver) transistors Q5 and Q6 are connected to a power line VDD.
  • [0163]
    The first driving transistor Q3 including an NMOS transistor and the first load transistor Q5 including a PMOS transistor constitute a first inverter. Likewise, the second driving transistor Q4 including an NMOS transistor and the second load transistor Q6 including a PMOS transistor constitute a second inverter.
  • [0164]
    The output terminals of the first and second inverters are connected to the sources of the first and second access transistors Q1 and Q2. Also, the input terminal of the first inverter and the output terminal of the second inverter are connected and conversely the input terminal of the second inverter and the output terminal of the first inverter are connected to constitute a latch circuit. The drains of the first and second access transistors Q1 and Q2 are connected, respectively, to first and second bit lines BL and /BL.
  • [0165]
    As described above, according to the inventive concept, an Si epitaxial layer is formed on both the top surface and inclined surface of the SiGe epitaxial layer despite the fact that the growth rate of silicon is dependent on the crystal plane of the underlying lattice on which the silicon is grown. Accordingly, the metal material of a metal layer used to form a silicide is prevented from reacting with the SiGe epitaxial layer. Also, the metal material is prevented from infiltrating along the boundary between the SiGe epitaxial layer and the device isolation layer in which case it would react with the semiconductor substrate.
  • [0166]
    The above-disclosed subject matter is to be considered illustrative and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the true spirit and scope of the inventive concept. Thus, to the maximum extent allowed by law, the scope of the inventive concept is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.

Claims (14)

What is claimed is:
1. A method of fabricating a semiconductor device, comprising:
forming a gate electrode structure comprising a gate electrode on an active region of a substrate;
forming first and second epitaxial regions in the active region at opposite sides of the gate electrode structure, respectively;
forming a silicon layer on the first and second epitaxial regions including by depositing silicon on each of the first and second epitaxial regions; and
converting at least a portion of the silicon layer, on each of the first and second epitaxial regions, to a silicide.
2. The method of claim 1, wherein the forming of the first and second epitaxial are formed to protrude above the upper surface of the active region.
3. The method of claim 1, wherein the substrate is a silicon substrate, and the forming of the first and second epitaxial regions comprises forming a recess in the substrate at both sides of the gate electrode, and epitaxially growing SiGe in the recess until the SiGe protrudes above an upper surface of the active region, whereby the first and second epitaxial regions each include a top upper surface which is parallel to the upper surface of the active region, and at least one inclined surface which extends downwardly from the upper surface at an inclination relative to the top surface such that the top and inclined surfaces subtend an obtuse angle.
4. The method of claim 3, wherein the silicon layer is formed to cover the top and inclined surfaces of each of the first and second epitaxial regions.
5. The method of claim 4, wherein the silicon layer is formed conformally with respect to the top and inclined surfaces of the epitaxial regions such that the silicon layer has a horizontal portion on the top surface of each of the epitaxial regions and inclined portions on the inclined surfaces of each of the first and second epitaxial regions, respectively.
6. The method of claim 4, wherein the converting of at least a portion of the silicon layer, on each of the first and second epitaxial regions, to a silicide comprises converting the entirety of the silicon layer to a silicide.
7. The method of claim 4, wherein the converting of at least a portion of the silicon layer, on each of the first and second epitaxial regions, to a silicide comprises converting only that portion of the silicon layer located over the top surface of each of the epitaxial regions to silicide.
8. The method of claim 4, wherein the converting of at least a portion of the silicon layer, on each of the first and second epitaxial regions, to a silicide comprises converting only an upper portion of the silicon layer to a silicide such that a portion of the silicon layer remains interposed between the epitaxial regions and the silicide.
9. The method of claim 1, wherein the forming of the first and second epitaxial layers comprises forming silicon-germanium.
10. The method of claim 1, wherein the forming of the first and second epitaxial layers comprises forming silicon-carbon.
11. The method of claim 1, wherein the forming of the silicon layer comprises a selective epitaxial growth process including alternately supplying silicon source gas and selective etch gas into a processing chamber, in which the semiconductor substrate is disposed, as a cycle of operations; and repeating the cycle at least once.
12. The method of claim 11, wherein the silicon source gas comprises at least one of monochlorosilane (SiH3Cl), dichlorosilane (DCS), trichlorosilane (TCS), hexachlorosilane (HCS), SiH4, and Si2H6, and the selective etch gas comprises at least one of HCl and Cl2.
13. The method of claim 1, wherein the forming of the silicon layer comprises a selective epitaxial growth process including supplying silicon source gas into a process chamber in which the semiconductor substrate is disposed, subsequently purging the process chamber, subsequently supplying selective etch gas into the process chamber, and subsequently purging the process chamber for a second time as a cycle of operations; and repeating the cycle at least once.
14. The method of claim 13, wherein the silicon source gas comprises at least one of monochlorosilane (SiH3Cl), dichlorosilane (DCS), trichlorosilane (TCS), hexachlorosilane (HCS), SiH4, and Si2H6, and the selective etch gas comprises at least one of HCl and Cl2.
US14485035 2010-09-07 2014-09-12 Semiconductor devices including silicide regions and methods of fabricating the same Abandoned US20150031183A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR10-2010-0087618 2010-09-07
KR20100087618A KR101776926B1 (en) 2010-09-07 2010-09-07 Semiconductor device and method for manufacturing the same
US13155483 US8835995B2 (en) 2010-09-07 2011-06-08 Semiconductor devices including silicide regions and methods of fabricating the same
US14485035 US20150031183A1 (en) 2010-09-07 2014-09-12 Semiconductor devices including silicide regions and methods of fabricating the same

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14485035 US20150031183A1 (en) 2010-09-07 2014-09-12 Semiconductor devices including silicide regions and methods of fabricating the same
US14995215 US20160133748A1 (en) 2010-09-07 2016-01-14 Semiconductor devices including silicide regions and methods of fabricating the same
US15619882 US20170278967A1 (en) 2010-09-07 2017-06-12 Semiconductor device including mos transistor having silicided source/drain region and method of fabricating the same

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US13155483 Division US8835995B2 (en) 2010-09-07 2011-06-08 Semiconductor devices including silicide regions and methods of fabricating the same

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US14995215 Continuation US20160133748A1 (en) 2010-09-07 2016-01-14 Semiconductor devices including silicide regions and methods of fabricating the same

Publications (1)

Publication Number Publication Date
US20150031183A1 true true US20150031183A1 (en) 2015-01-29

Family

ID=45770064

Family Applications (4)

Application Number Title Priority Date Filing Date
US13155483 Active 2032-12-27 US8835995B2 (en) 2010-09-07 2011-06-08 Semiconductor devices including silicide regions and methods of fabricating the same
US14485035 Abandoned US20150031183A1 (en) 2010-09-07 2014-09-12 Semiconductor devices including silicide regions and methods of fabricating the same
US14995215 Pending US20160133748A1 (en) 2010-09-07 2016-01-14 Semiconductor devices including silicide regions and methods of fabricating the same
US15619882 Pending US20170278967A1 (en) 2010-09-07 2017-06-12 Semiconductor device including mos transistor having silicided source/drain region and method of fabricating the same

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US13155483 Active 2032-12-27 US8835995B2 (en) 2010-09-07 2011-06-08 Semiconductor devices including silicide regions and methods of fabricating the same

Family Applications After (2)

Application Number Title Priority Date Filing Date
US14995215 Pending US20160133748A1 (en) 2010-09-07 2016-01-14 Semiconductor devices including silicide regions and methods of fabricating the same
US15619882 Pending US20170278967A1 (en) 2010-09-07 2017-06-12 Semiconductor device including mos transistor having silicided source/drain region and method of fabricating the same

Country Status (2)

Country Link
US (4) US8835995B2 (en)
KR (1) KR101776926B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150294865A1 (en) * 2014-04-14 2015-10-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods for manufacturing the same
US20170229578A1 (en) * 2016-02-09 2017-08-10 Globalfoundries Inc. Device with diffusion blocking layer in source/drain region

Families Citing this family (54)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8816409B2 (en) * 2010-07-15 2014-08-26 United Microelectronics Corp. Metal-oxide semiconductor transistor
KR101716113B1 (en) 2010-11-03 2017-03-15 삼성전자 주식회사 Semiconductor device and method of manufacturing thereof
US9537004B2 (en) 2011-05-24 2017-01-03 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain formation and structure
DE102011076695B4 (en) * 2011-05-30 2013-05-08 Globalfoundries Inc. Transistors with embedded strain-inducing material which is formed in generated by a Oxidationsätzprozess recesses
US20120315734A1 (en) * 2011-06-09 2012-12-13 Chan-Lon Yang Method for fabricating semiconductor device
US9847225B2 (en) * 2011-11-15 2017-12-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacturing the same
US8716765B2 (en) 2012-03-23 2014-05-06 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
CN102655081B (en) * 2012-04-16 2015-08-19 上海华力微电子有限公司 An amorphous carbon sacrificial preparation shallow junction and the sidewall of the gate structure
US20130270614A1 (en) * 2012-04-17 2013-10-17 Toshiba America Electronic Components, Inc. Formation of a trench silicide
US20130292774A1 (en) * 2012-05-07 2013-11-07 Globalfoundries Inc. Method for forming a semiconductor device having raised drain and source regions and corresponding semiconductor device
CN103390558B (en) * 2012-05-08 2016-09-07 中芯国际集成电路制造(上海)有限公司 The method of forming a transistor
US8936977B2 (en) * 2012-05-29 2015-01-20 Globalfoundries Singapore Pte. Ltd. Late in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations
US8759920B2 (en) * 2012-06-01 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of forming the same
US9012310B2 (en) * 2012-06-11 2015-04-21 Taiwan Semiconductor Manufacturing Company, Ltd. Epitaxial formation of source and drain regions
US9748338B2 (en) * 2012-06-29 2017-08-29 Intel Corporation Preventing isolation leakage in III-V devices
KR20140006370A (en) * 2012-07-04 2014-01-16 삼성전자주식회사 Semiconductor devices
US9281246B2 (en) * 2012-07-17 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Strain adjustment in the formation of MOS devices
US8969163B2 (en) * 2012-07-24 2015-03-03 International Business Machines Corporation Forming facet-less epitaxy with self-aligned isolation
KR20140038826A (en) 2012-09-21 2014-03-31 삼성전자주식회사 Semiconductor devices and methods of manufacturing the same
US9171762B2 (en) * 2012-11-01 2015-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and fabrication method thereof
US9054172B2 (en) * 2012-12-05 2015-06-09 United Microelectrnics Corp. Semiconductor structure having contact plug and method of making the same
US8900958B2 (en) 2012-12-19 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Epitaxial formation mechanisms of source and drain regions
US9252008B2 (en) 2013-01-11 2016-02-02 Taiwan Semiconductor Manufacturing Company, Ltd. Epitaxial formation mechanisms of source and drain regions
US8853039B2 (en) 2013-01-17 2014-10-07 Taiwan Semiconductor Manufacturing Company, Ltd. Defect reduction for formation of epitaxial layer in source and drain regions
US9029919B2 (en) * 2013-02-01 2015-05-12 Globalfoundries Inc. Methods of forming silicon/germanium protection layer above source/drain regions of a transistor and a device having such a protection layer
KR20140108960A (en) * 2013-03-04 2014-09-15 삼성전자주식회사 Semiconductor device having dual metal silicide layer and method of manufacturing the same
US9029226B2 (en) 2013-03-13 2015-05-12 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for doping lightly-doped-drain (LDD) regions of finFET devices
US9093468B2 (en) 2013-03-13 2015-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Asymmetric cyclic depositon and etch process for epitaxial formation mechanisms of source and drain regions
US8877592B2 (en) 2013-03-14 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Epitaxial growth of doped film for source and drain regions
US9076815B2 (en) * 2013-05-31 2015-07-07 Globalfoundries Inc. Spacer stress relaxation
US9093555B2 (en) * 2013-07-25 2015-07-28 Texas Instruments Incorporated Method of CMOS manufacturing utilizing multi-layer epitaxial hardmask films for improved EPI profile
US9012964B2 (en) 2013-08-09 2015-04-21 Taiwan Semiconductor Manufacturing Company, Ltd. Modulating germanium percentage in MOS devices
US9401365B2 (en) * 2013-12-19 2016-07-26 Texas Instruments Incorporated Epitaxial source/drain differential spacers
US9202916B2 (en) 2013-12-27 2015-12-01 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure
WO2015110527A1 (en) * 2014-01-22 2015-07-30 Mapper Lithography Ip B.V. Electrical charge regulation for a semiconductor substrate during charged particle beam processing
US20150255601A1 (en) * 2014-03-10 2015-09-10 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US9293534B2 (en) 2014-03-21 2016-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of dislocations in source and drain regions of FinFET devices
US9299587B2 (en) 2014-04-10 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Microwave anneal (MWA) for defect recovery
US9490365B2 (en) * 2014-06-12 2016-11-08 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of fin-like field effect transistor
KR20150144192A (en) * 2014-06-16 2015-12-24 삼성전자주식회사 Semiconductor devices and methods of manufacturing the same
US20150372108A1 (en) * 2014-06-19 2015-12-24 Globalfoundries Inc. Method and structure for protecting gates during epitaxial growth
US9837533B2 (en) 2014-07-01 2017-12-05 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US9299839B2 (en) * 2014-09-01 2016-03-29 United Microelectronics Corporation PFET and CMOS containing same
US9685364B2 (en) * 2014-09-05 2017-06-20 Globalfoundries Singapore Pte. Ltd. Silicon-on-insulator integrated circuit devices with body contact structures and methods for fabricating the same
US9748232B2 (en) * 2014-12-31 2017-08-29 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure and method for forming the same
US9496264B2 (en) * 2015-02-13 2016-11-15 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of FinFET device
US9812571B2 (en) * 2015-09-30 2017-11-07 International Business Machines Corporation Tensile strained high percentage silicon germanium alloy FinFETs
CN105261567A (en) * 2015-10-27 2016-01-20 上海华力微电子有限公司 Method for preparing cap layer of embedded epitaxial silicon-germanium layer
CN105374665A (en) * 2015-10-27 2016-03-02 上海华力微电子有限公司 Preparation method of cap layer of embedded epitaxial SiGe layer
US20170141228A1 (en) * 2015-11-16 2017-05-18 Taiwan Semiconductor Manufacturing Co., Ltd. Field effect transistor and manufacturing method thereof
CN107104051A (en) * 2016-02-22 2017-08-29 联华电子股份有限公司 Semiconductor element and manufacturing method thereof
CN107369615A (en) * 2016-05-12 2017-11-21 中芯国际集成电路制造(上海)有限公司 Forming a semiconductor structure
CN107369709A (en) * 2016-05-12 2017-11-21 中芯国际集成电路制造(上海)有限公司 Forming a semiconductor structure
US9847398B1 (en) * 2016-07-13 2017-12-19 United Microelectronics Corp. Semiconductor device with gate structure having dielectric layer on one side and contact plug on the other side

Citations (75)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5112439A (en) * 1988-11-30 1992-05-12 Mcnc Method for selectively depositing material on substrates
US5201995A (en) * 1992-03-16 1993-04-13 Mcnc Alternating cyclic pressure modulation process for selective area deposition
US6013319A (en) * 1998-04-28 2000-01-11 Dietze; Gerald R. Method and apparatus for increasing deposition quality of a chemical vapor deposition system
US20020008261A1 (en) * 2000-03-06 2002-01-24 Kabushiki Kaisha Toshiba Transistor, semiconductor device and manufacturing method of semiconductor device
US6489206B2 (en) * 2001-03-22 2002-12-03 United Microelectronics Corp. Method for forming self-aligned local-halo metal-oxide-semiconductor device
US20030087522A1 (en) * 2001-11-08 2003-05-08 Advanced Micro Devices, Inc. Method of forming reliable Cu interconnects
US6589887B1 (en) * 2001-10-11 2003-07-08 Novellus Systems, Inc. Forming metal-derived layers by simultaneous deposition and evaporation of metal
US6663787B1 (en) * 2001-02-06 2003-12-16 Advanced Micro Devices, Inc. Use of ta/tan for preventing copper contamination of low-k dielectric layers
US20040077184A1 (en) * 2002-10-17 2004-04-22 Applied Materials, Inc. Apparatuses and methods for depositing an oxide film
US6740977B2 (en) * 2002-04-24 2004-05-25 Samsung Electronics Co., Ltd. Insulating layers in semiconductor devices having a multi-layer nanolaminate structure of SiNx thin film and BN thin film and methods for forming the same
US20040126949A1 (en) * 2002-08-19 2004-07-01 Samsung Electronics Co., Ltd. Gate electrode of a semiconductor device and method of forming the same
US20040175893A1 (en) * 2003-03-07 2004-09-09 Applied Materials, Inc. Apparatuses and methods for forming a substantially facet-free epitaxial film
US6797652B1 (en) * 2002-03-15 2004-09-28 Advanced Micro Devices, Inc. Copper damascene with low-k capping layer and improved electromigration reliability
US20040188684A1 (en) * 2003-03-31 2004-09-30 Glass Glenn A. Selective deposition of smooth silicon, germanium, and silicon-germanium alloy epitaxial films
US6875694B1 (en) * 2004-02-10 2005-04-05 Advanced Micro Devices, Inc. Method of treating inlaid copper for improved capping layer adhesion without damaging porous low-k materials
US20050112817A1 (en) * 2003-11-25 2005-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having high drive current and method of manufacture thereof
US20050124105A1 (en) * 2003-12-09 2005-06-09 Kei Kanemoto Semiconductor device and method of manufacturing the same
US20050130454A1 (en) * 2003-12-08 2005-06-16 Anand Murthy Method for improving transistor performance through reducing the salicide interface resistance
US20060108320A1 (en) * 2004-11-22 2006-05-25 Lazovsky David E Molecular self-assembly in substrate processing
US7112528B2 (en) * 1996-12-30 2006-09-26 Applied Materials, Inc. Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug
US20060270133A1 (en) * 2005-05-26 2006-11-30 Kabushiki Kaisha Toshiba Semiconductor device and its manufacturing method
US20070122986A1 (en) * 2005-11-29 2007-05-31 Micron Technology, Inc. Carbon nanotube field effect transistor and methods for making same
US20070132038A1 (en) * 2005-12-08 2007-06-14 Chartered Semiconductor Mfg, LTD. Embedded stressor structure and process
US20070190730A1 (en) * 2006-02-13 2007-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Resolving pattern-loading issues of SiGe stressor
US20070266933A1 (en) * 2006-05-19 2007-11-22 Ryuta Tsuchiya Manufacturing method of semiconductor device
US20070281411A1 (en) * 2006-06-06 2007-12-06 Anand Murthy Formation of strain-inducing films
US20080026549A1 (en) * 2006-07-31 2008-01-31 Applied Materials, Inc. Methods of controlling morphology during epitaxial layer formation
US7355262B2 (en) * 2006-03-17 2008-04-08 Taiwan Semiconductor Manufacturing Company, Ltd. Diffusion topography engineering for high performance CMOS fabrication
US20080099846A1 (en) * 2006-10-26 2008-05-01 Fujitsu Limited Semiconductor device and its manufacture method
US20080105977A1 (en) * 2006-11-06 2008-05-08 Stephen Ellinwood Luce Interconnect layers without electromigration
US7390707B2 (en) * 2005-06-13 2008-06-24 Fujitsu Limited Semiconductor device fabrication method
US20080157224A1 (en) * 2006-12-29 2008-07-03 Fischer Kevin J Tuned tensile stress low resistivity slot contact structure for n-type transistor performance enhancement
US20080164491A1 (en) * 2007-01-04 2008-07-10 International Business Machines Corporation Structure and method for mobility enhanced mosfets with unalloyed silicide
US7405131B2 (en) * 2005-07-16 2008-07-29 Chartered Semiconductor Manufacturing, Ltd. Method and structure to prevent silicide strapping of source/drain to body in semiconductor devices with source/drain stressor
US20080245303A1 (en) * 2007-04-02 2008-10-09 Katsuhiko Yamamoto Manufacturing method of semiconductor apparatus
US20080251851A1 (en) * 2007-04-12 2008-10-16 Advanced Micro Devices, Inc. Strain enhanced semiconductor devices and methods for their fabrication
US20080265417A1 (en) * 2007-02-16 2008-10-30 Fujitsu Limited Semiconductor device and method of manufacturing the same
US20080303060A1 (en) * 2007-06-06 2008-12-11 Jin-Ping Han Semiconductor devices and methods of manufacturing thereof
US20090001420A1 (en) * 2007-06-27 2009-01-01 Sony Corporation Semiconductor device and method for manufacturing semiconductor device
US20090093094A1 (en) * 2007-10-05 2009-04-09 Zhiyuan Ye Selective Formation of Silicon Carbon Epitaxial Layer
US7524716B2 (en) * 2006-04-07 2009-04-28 United Microelectronics Corp. Fabricating method of semiconductor structure
US20090230480A1 (en) * 2006-03-31 2009-09-17 Lucian Shifren Epitaxial silicon germanium for reduced contact resistance in field-effect transistors
US20090236232A1 (en) * 2008-03-24 2009-09-24 Fujitsu Limited Electrolytic plating solution, electrolytic plating method, and method for manufacturing semiconductor device
US20090253265A1 (en) * 2007-05-27 2009-10-08 Hitachi Kokusai Electric, Inc. Method for fabricating semiconductor device and substrate processing apparatus
US20090280612A1 (en) * 2005-06-22 2009-11-12 Fujitsu Microelectronics Limited Semiconductor device and production method thereof
US20090283413A1 (en) * 2008-05-13 2009-11-19 Fujitsu Microelectronics Limited Electrolytic plating method and semiconductor device manufacturing method
US20100006539A1 (en) * 2008-07-08 2010-01-14 Jusung Engineering Co., Ltd Apparatus for manufacturing semiconductor
US7718500B2 (en) * 2005-12-16 2010-05-18 Chartered Semiconductor Manufacturing, Ltd Formation of raised source/drain structures in NFET with embedded SiGe in PFET
US20100197092A1 (en) * 2009-02-02 2010-08-05 Jin-Bum Kim Method of Manufacturing Semiconductor Device Having Stress Creating Layer
US20100207176A1 (en) * 2009-02-18 2010-08-19 Advanced Micro Devices, Inc. Metal oxide semiconductor devices having doped silicon-compromising capping layers and methods for fabricating the same
US20100311218A1 (en) * 2004-06-24 2010-12-09 Fujitsu Semiconductor Limited Semiconductor device, method of manufacturing the same, and method of evaluating semiconductor device
US20100327329A1 (en) * 2009-06-25 2010-12-30 Hiroshi Itokawa Semiconductor device and method of fabricating the same
US20110001170A1 (en) * 2009-07-03 2011-01-06 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing semiconductor device
US20110117679A1 (en) * 2009-11-19 2011-05-19 Taiwan Semiconductor Manufacturing Company, Ltd. Sacrificial offset protection film for a finfet device
US20110230027A1 (en) * 2010-03-19 2011-09-22 Kim Myung-Sun Methods of Forming Semiconductor Devices Having Faceted Semiconductor Patterns
US20110263092A1 (en) * 2010-04-22 2011-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating a semiconductor device
US20110312145A1 (en) * 2010-06-16 2011-12-22 Taiwan Semiconductor Manufacturing Company, Ltd. Source and drain feature profile for improving device performance and method of manufacturing same
US20120045878A1 (en) * 2007-05-14 2012-02-23 Fujitsu Semiconductor Limited Manufacture of semiconductor device with stress structure
US20120112290A1 (en) * 2010-11-09 2012-05-10 International Business Machines Corporation Controlled contact formation process
US20120241816A1 (en) * 2011-03-21 2012-09-27 GLOBALFOUNDRIES Dresden Module One Limited Liability Company & Co., KG Stabilization of Metal Silicides in PFET Transistors by Incorporation of Stabilizing Species in a Si/Ge Semiconductor Material
US20120292637A1 (en) * 2011-05-17 2012-11-22 Globalfoundries Inc. Dual Cavity Etch for Embedded Stressor Regions
US8344455B2 (en) * 2007-10-31 2013-01-01 Panasonic Corporation Semiconductor device and fabrication method for the same
US20130020612A1 (en) * 2011-07-22 2013-01-24 Taiwan Semiconductor Manufacturing Company, Ltd. Re-growing Source/Drain Regions from Un-Relaxed Silicon Layer
US20130045589A1 (en) * 2011-08-19 2013-02-21 Seokhoon Kim Semiconductor devices and methods of manufacturing the same
US8404546B2 (en) * 2008-04-30 2013-03-26 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain carbon implant and RTA anneal, pre-SiGe deposition
US20130248999A1 (en) * 1999-09-28 2013-09-26 Glenn A. Glass Contact resistance reduction employing germanium overlayer pre-contact metalization
US20130280897A1 (en) * 2009-06-19 2013-10-24 Fujitsu Semiconductor Limited Semiconductor device and method for manufacturing the same
US8586438B2 (en) * 2008-01-25 2013-11-19 Fujitsu Semiconductor Limited Semiconductor device and manufacturing method thereof
US20130316525A1 (en) * 2012-05-24 2013-11-28 Samsung Electronics Co., Ltd. Semiconductor device having selectively nitrided gate insulating layer and method of fabricating the same
US20130323899A1 (en) * 2005-01-21 2013-12-05 Taiwan Semiconductor Manufacturing Company, Ltd. High Performance CMOS Device Design
US20130334693A1 (en) * 2012-06-18 2013-12-19 International Business Machines Corporation Raised silicide contact
US20140035142A1 (en) * 2012-07-31 2014-02-06 International Business Machines Corporation Profile control in interconnect structures
US8653599B1 (en) * 2012-11-16 2014-02-18 International Business Machines Corporation Strained SiGe nanowire having (111)-oriented sidewalls
US8673724B2 (en) * 2011-11-04 2014-03-18 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices
US20150008520A1 (en) * 2013-07-02 2015-01-08 International Business Machines Corporation Dual channel hybrid semiconductor-on-insulator semiconductor devices

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6445016B1 (en) * 2001-02-28 2002-09-03 Advanced Micro Devices, Inc. Silicon-on-insulator (SOI) transistor having partial hetero source/drain junctions fabricated with high energy germanium implantation
US6657223B1 (en) * 2002-10-29 2003-12-02 Advanced Micro Devices, Inc. Strained silicon MOSFET having silicon source/drain regions and method for its fabrication
JP4369359B2 (en) * 2004-12-28 2009-11-18 富士通マイクロエレクトロニクス株式会社 Semiconductor device
US7195985B2 (en) * 2005-01-04 2007-03-27 Intel Corporation CMOS transistor junction regions formed by a CVD etching and deposition sequence
US7696537B2 (en) * 2005-04-18 2010-04-13 Toshiba America Electronic Components, Inc. Step-embedded SiGe structure for PFET mobility enhancement
JP4984665B2 (en) 2005-06-22 2012-07-25 富士通セミコンダクター株式会社 Semiconductor device and manufacturing method thereof
US7485524B2 (en) * 2006-06-21 2009-02-03 International Business Machines Corporation MOSFETs comprising source/drain regions with slanted upper surfaces, and method for fabricating the same
JP5076388B2 (en) * 2006-07-28 2012-11-21 富士通セミコンダクター株式会社 Semiconductor device and manufacturing method thereof
JP2008071890A (en) 2006-09-13 2008-03-27 Toshiba Corp Semiconductor device and its manufacturing method
US7759199B2 (en) * 2007-09-19 2010-07-20 Asm America, Inc. Stressor for engineered strain on channel
US20090152590A1 (en) * 2007-12-13 2009-06-18 International Business Machines Corporation Method and structure for semiconductor devices with silicon-germanium deposits
JP5120448B2 (en) * 2008-03-31 2013-01-16 富士通セミコンダクター株式会社 Semiconductor device and manufacturing method thereof
JP2009302317A (en) 2008-06-13 2009-12-24 Renesas Technology Corp Semiconductor device and method of manufacturing the same
US7736982B2 (en) * 2008-10-14 2010-06-15 United Microelectronics Corp. Method for forming a semiconductor device
US20100109044A1 (en) * 2008-10-30 2010-05-06 Tekleab Daniel G Optimized Compressive SiGe Channel PMOS Transistor with Engineered Ge Profile and Optimized Silicon Cap Layer
US20110031503A1 (en) * 2009-08-10 2011-02-10 International Business Machines Corporation Device with stressed channel
US7994062B2 (en) * 2009-10-30 2011-08-09 Sachem, Inc. Selective silicon etch process
US7989298B1 (en) * 2010-01-25 2011-08-02 International Business Machines Corporation Transistor having V-shaped embedded stressor
US8492234B2 (en) * 2010-06-29 2013-07-23 International Business Machines Corporation Field effect transistor device
US8216906B2 (en) * 2010-06-30 2012-07-10 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing integrated circuit device with well controlled surface proximity
US8679910B2 (en) * 2010-10-06 2014-03-25 Samsung Electronics Co., Ltd. Methods of fabricating devices including source/drain region with abrupt junction profile
CN102468326B (en) * 2010-10-29 2015-01-07 中国科学院微电子研究所 Contact electrode manufacture method and semiconductor device
US8835982B2 (en) * 2011-02-14 2014-09-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing strained source/drain structures
KR20130136328A (en) * 2012-06-04 2013-12-12 삼성전자주식회사 Semiconductor device having embedded strain-inducing pattern and method of forming the same
US20140054710A1 (en) * 2012-08-22 2014-02-27 Texas Instruments Incorporated Reduction of Proximity Effects in Field-Effect Transistors with Embedded Silicon-Germanium Source and Drain Regions
US8741759B2 (en) * 2012-11-08 2014-06-03 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating a semiconductor device
US9129952B2 (en) * 2012-11-22 2015-09-08 Samsung Electronics Co., Ltd. Semiconductor devices including a stressor in a recess and methods of forming the same
KR20160035650A (en) * 2014-09-23 2016-04-01 삼성전자주식회사 Semiconductor device and method of manufacturing the same
CN104821336B (en) * 2015-04-20 2017-12-12 上海华力微电子有限公司 Using conformal fill layer improves surface uniformity of the device and method of the system

Patent Citations (81)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5112439A (en) * 1988-11-30 1992-05-12 Mcnc Method for selectively depositing material on substrates
US5201995A (en) * 1992-03-16 1993-04-13 Mcnc Alternating cyclic pressure modulation process for selective area deposition
US7112528B2 (en) * 1996-12-30 2006-09-26 Applied Materials, Inc. Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug
US6013319A (en) * 1998-04-28 2000-01-11 Dietze; Gerald R. Method and apparatus for increasing deposition quality of a chemical vapor deposition system
US20130248999A1 (en) * 1999-09-28 2013-09-26 Glenn A. Glass Contact resistance reduction employing germanium overlayer pre-contact metalization
US20020008261A1 (en) * 2000-03-06 2002-01-24 Kabushiki Kaisha Toshiba Transistor, semiconductor device and manufacturing method of semiconductor device
US6663787B1 (en) * 2001-02-06 2003-12-16 Advanced Micro Devices, Inc. Use of ta/tan for preventing copper contamination of low-k dielectric layers
US6489206B2 (en) * 2001-03-22 2002-12-03 United Microelectronics Corp. Method for forming self-aligned local-halo metal-oxide-semiconductor device
US6589887B1 (en) * 2001-10-11 2003-07-08 Novellus Systems, Inc. Forming metal-derived layers by simultaneous deposition and evaporation of metal
US20030087522A1 (en) * 2001-11-08 2003-05-08 Advanced Micro Devices, Inc. Method of forming reliable Cu interconnects
US6797652B1 (en) * 2002-03-15 2004-09-28 Advanced Micro Devices, Inc. Copper damascene with low-k capping layer and improved electromigration reliability
US6740977B2 (en) * 2002-04-24 2004-05-25 Samsung Electronics Co., Ltd. Insulating layers in semiconductor devices having a multi-layer nanolaminate structure of SiNx thin film and BN thin film and methods for forming the same
US20040126949A1 (en) * 2002-08-19 2004-07-01 Samsung Electronics Co., Ltd. Gate electrode of a semiconductor device and method of forming the same
US20040077184A1 (en) * 2002-10-17 2004-04-22 Applied Materials, Inc. Apparatuses and methods for depositing an oxide film
US20040175893A1 (en) * 2003-03-07 2004-09-09 Applied Materials, Inc. Apparatuses and methods for forming a substantially facet-free epitaxial film
US20040188684A1 (en) * 2003-03-31 2004-09-30 Glass Glenn A. Selective deposition of smooth silicon, germanium, and silicon-germanium alloy epitaxial films
US20050112817A1 (en) * 2003-11-25 2005-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having high drive current and method of manufacture thereof
US20050130454A1 (en) * 2003-12-08 2005-06-16 Anand Murthy Method for improving transistor performance through reducing the salicide interface resistance
US20050253200A1 (en) * 2003-12-08 2005-11-17 Anand Murthy Method for improving transistor performance through reducing the salicide interface resistance
US20050124105A1 (en) * 2003-12-09 2005-06-09 Kei Kanemoto Semiconductor device and method of manufacturing the same
US6875694B1 (en) * 2004-02-10 2005-04-05 Advanced Micro Devices, Inc. Method of treating inlaid copper for improved capping layer adhesion without damaging porous low-k materials
US20100311218A1 (en) * 2004-06-24 2010-12-09 Fujitsu Semiconductor Limited Semiconductor device, method of manufacturing the same, and method of evaluating semiconductor device
US20060108320A1 (en) * 2004-11-22 2006-05-25 Lazovsky David E Molecular self-assembly in substrate processing
US20130323899A1 (en) * 2005-01-21 2013-12-05 Taiwan Semiconductor Manufacturing Company, Ltd. High Performance CMOS Device Design
US20060270133A1 (en) * 2005-05-26 2006-11-30 Kabushiki Kaisha Toshiba Semiconductor device and its manufacturing method
US7390707B2 (en) * 2005-06-13 2008-06-24 Fujitsu Limited Semiconductor device fabrication method
US20090280612A1 (en) * 2005-06-22 2009-11-12 Fujitsu Microelectronics Limited Semiconductor device and production method thereof
US7875521B2 (en) * 2005-06-22 2011-01-25 Fujitsu Semiconductor Limited Semiconductor device and production method thereof
US7405131B2 (en) * 2005-07-16 2008-07-29 Chartered Semiconductor Manufacturing, Ltd. Method and structure to prevent silicide strapping of source/drain to body in semiconductor devices with source/drain stressor
US20070122986A1 (en) * 2005-11-29 2007-05-31 Micron Technology, Inc. Carbon nanotube field effect transistor and methods for making same
US20070132038A1 (en) * 2005-12-08 2007-06-14 Chartered Semiconductor Mfg, LTD. Embedded stressor structure and process
US7939413B2 (en) * 2005-12-08 2011-05-10 Samsung Electronics Co., Ltd. Embedded stressor structure and process
US7718500B2 (en) * 2005-12-16 2010-05-18 Chartered Semiconductor Manufacturing, Ltd Formation of raised source/drain structures in NFET with embedded SiGe in PFET
US20070190730A1 (en) * 2006-02-13 2007-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Resolving pattern-loading issues of SiGe stressor
US7355262B2 (en) * 2006-03-17 2008-04-08 Taiwan Semiconductor Manufacturing Company, Ltd. Diffusion topography engineering for high performance CMOS fabrication
US20090230480A1 (en) * 2006-03-31 2009-09-17 Lucian Shifren Epitaxial silicon germanium for reduced contact resistance in field-effect transistors
US7524716B2 (en) * 2006-04-07 2009-04-28 United Microelectronics Corp. Fabricating method of semiconductor structure
US20070266933A1 (en) * 2006-05-19 2007-11-22 Ryuta Tsuchiya Manufacturing method of semiconductor device
US20070281411A1 (en) * 2006-06-06 2007-12-06 Anand Murthy Formation of strain-inducing films
US20080026549A1 (en) * 2006-07-31 2008-01-31 Applied Materials, Inc. Methods of controlling morphology during epitaxial layer formation
US20080099846A1 (en) * 2006-10-26 2008-05-01 Fujitsu Limited Semiconductor device and its manufacture method
US8258576B2 (en) * 2006-10-26 2012-09-04 Fujitsu Semiconductor Limited Method of manufacturing a semiconductor device including epitaxially growing semiconductor epitaxial layers on a surface of semiconductor substrate
US20080105977A1 (en) * 2006-11-06 2008-05-08 Stephen Ellinwood Luce Interconnect layers without electromigration
US20080157224A1 (en) * 2006-12-29 2008-07-03 Fischer Kevin J Tuned tensile stress low resistivity slot contact structure for n-type transistor performance enhancement
US20080164491A1 (en) * 2007-01-04 2008-07-10 International Business Machines Corporation Structure and method for mobility enhanced mosfets with unalloyed silicide
US8076239B2 (en) * 2007-02-16 2011-12-13 Fujitsu Semiconductor Limited Semiconductor device and method of manufacturing the same
US20080265417A1 (en) * 2007-02-16 2008-10-30 Fujitsu Limited Semiconductor device and method of manufacturing the same
US20080245303A1 (en) * 2007-04-02 2008-10-09 Katsuhiko Yamamoto Manufacturing method of semiconductor apparatus
US20080251851A1 (en) * 2007-04-12 2008-10-16 Advanced Micro Devices, Inc. Strain enhanced semiconductor devices and methods for their fabrication
US20120045878A1 (en) * 2007-05-14 2012-02-23 Fujitsu Semiconductor Limited Manufacture of semiconductor device with stress structure
US8247284B2 (en) * 2007-05-14 2012-08-21 Fujitsu Semiconductor Limited Manufacture of semiconductor device with stress structure
US20090253265A1 (en) * 2007-05-27 2009-10-08 Hitachi Kokusai Electric, Inc. Method for fabricating semiconductor device and substrate processing apparatus
US20080303060A1 (en) * 2007-06-06 2008-12-11 Jin-Ping Han Semiconductor devices and methods of manufacturing thereof
US20090001420A1 (en) * 2007-06-27 2009-01-01 Sony Corporation Semiconductor device and method for manufacturing semiconductor device
US20090093094A1 (en) * 2007-10-05 2009-04-09 Zhiyuan Ye Selective Formation of Silicon Carbon Epitaxial Layer
US8344455B2 (en) * 2007-10-31 2013-01-01 Panasonic Corporation Semiconductor device and fabrication method for the same
US8586438B2 (en) * 2008-01-25 2013-11-19 Fujitsu Semiconductor Limited Semiconductor device and manufacturing method thereof
US20090236232A1 (en) * 2008-03-24 2009-09-24 Fujitsu Limited Electrolytic plating solution, electrolytic plating method, and method for manufacturing semiconductor device
US8404546B2 (en) * 2008-04-30 2013-03-26 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain carbon implant and RTA anneal, pre-SiGe deposition
US20090283413A1 (en) * 2008-05-13 2009-11-19 Fujitsu Microelectronics Limited Electrolytic plating method and semiconductor device manufacturing method
US20100006539A1 (en) * 2008-07-08 2010-01-14 Jusung Engineering Co., Ltd Apparatus for manufacturing semiconductor
US20100197092A1 (en) * 2009-02-02 2010-08-05 Jin-Bum Kim Method of Manufacturing Semiconductor Device Having Stress Creating Layer
US20100207176A1 (en) * 2009-02-18 2010-08-19 Advanced Micro Devices, Inc. Metal oxide semiconductor devices having doped silicon-compromising capping layers and methods for fabricating the same
US20130280897A1 (en) * 2009-06-19 2013-10-24 Fujitsu Semiconductor Limited Semiconductor device and method for manufacturing the same
US20100327329A1 (en) * 2009-06-25 2010-12-30 Hiroshi Itokawa Semiconductor device and method of fabricating the same
US20110001170A1 (en) * 2009-07-03 2011-01-06 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing semiconductor device
US20110117679A1 (en) * 2009-11-19 2011-05-19 Taiwan Semiconductor Manufacturing Company, Ltd. Sacrificial offset protection film for a finfet device
US20110230027A1 (en) * 2010-03-19 2011-09-22 Kim Myung-Sun Methods of Forming Semiconductor Devices Having Faceted Semiconductor Patterns
US20110263092A1 (en) * 2010-04-22 2011-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating a semiconductor device
US20110312145A1 (en) * 2010-06-16 2011-12-22 Taiwan Semiconductor Manufacturing Company, Ltd. Source and drain feature profile for improving device performance and method of manufacturing same
US20120112290A1 (en) * 2010-11-09 2012-05-10 International Business Machines Corporation Controlled contact formation process
US20120241816A1 (en) * 2011-03-21 2012-09-27 GLOBALFOUNDRIES Dresden Module One Limited Liability Company & Co., KG Stabilization of Metal Silicides in PFET Transistors by Incorporation of Stabilizing Species in a Si/Ge Semiconductor Material
US20120292637A1 (en) * 2011-05-17 2012-11-22 Globalfoundries Inc. Dual Cavity Etch for Embedded Stressor Regions
US20130020612A1 (en) * 2011-07-22 2013-01-24 Taiwan Semiconductor Manufacturing Company, Ltd. Re-growing Source/Drain Regions from Un-Relaxed Silicon Layer
US20130045589A1 (en) * 2011-08-19 2013-02-21 Seokhoon Kim Semiconductor devices and methods of manufacturing the same
US8673724B2 (en) * 2011-11-04 2014-03-18 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices
US20130316525A1 (en) * 2012-05-24 2013-11-28 Samsung Electronics Co., Ltd. Semiconductor device having selectively nitrided gate insulating layer and method of fabricating the same
US20130334693A1 (en) * 2012-06-18 2013-12-19 International Business Machines Corporation Raised silicide contact
US20140035142A1 (en) * 2012-07-31 2014-02-06 International Business Machines Corporation Profile control in interconnect structures
US8653599B1 (en) * 2012-11-16 2014-02-18 International Business Machines Corporation Strained SiGe nanowire having (111)-oriented sidewalls
US20150008520A1 (en) * 2013-07-02 2015-01-08 International Business Machines Corporation Dual channel hybrid semiconductor-on-insulator semiconductor devices

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150294865A1 (en) * 2014-04-14 2015-10-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods for manufacturing the same
US9496149B2 (en) * 2014-04-14 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods for manufacturing the same
US20170229578A1 (en) * 2016-02-09 2017-08-10 Globalfoundries Inc. Device with diffusion blocking layer in source/drain region

Also Published As

Publication number Publication date Type
KR20120025314A (en) 2012-03-15 application
KR101776926B1 (en) 2017-09-08 grant
US20120056245A1 (en) 2012-03-08 application
US8835995B2 (en) 2014-09-16 grant
US20170278967A1 (en) 2017-09-28 application
US20160133748A1 (en) 2016-05-12 application

Similar Documents

Publication Publication Date Title
US6074919A (en) Method of forming an ultrathin gate dielectric
US20050156208A1 (en) Device having multiple silicide types and a method for its fabrication
US20040262683A1 (en) PMOS transistor strain optimization with raised junction regions
US7332439B2 (en) Metal gate transistors with epitaxial source and drain regions
US7176522B2 (en) Semiconductor device having high drive current and method of manufacturing thereof
US7888747B2 (en) Semiconductor device and method of fabricating the same
US6501135B1 (en) Germanium-on-insulator (GOI) device
US20120032275A1 (en) Metal semiconductor alloy structure for low contact resistance
US20090124056A1 (en) Method of fabricating semiconductor device
US20070018328A1 (en) Piezoelectric stress liner for bulk and SOI
US5698869A (en) Insulated-gate transistor having narrow-bandgap-source
US20050087806A1 (en) Semiconductor device having active regions connected together by interconnect layer and method of manufacture thereof
US6773995B2 (en) Double diffused MOS transistor and method for manufacturing same
US20060134844A1 (en) Method for fabricating dual work function metal gates
US20070007571A1 (en) Semiconductor device with a buried gate and method of forming the same
US20070190708A1 (en) Semiconductor device and method manufacturing semiconductor device
US20050110082A1 (en) Semiconductor device having high drive current and method of manufacture therefor
US7494884B2 (en) SiGe selective growth without a hard mask
US20110042729A1 (en) Method for improving selectivity of epi process
US20150303118A1 (en) Wrap-Around Contact
US20070196989A1 (en) Semiconductor device with strained transistors and its manufacture
US20130109144A1 (en) Semiconductor devices and methods of fabricating the same
JP2006173432A (en) Semiconductor device and its manufacturing method
US20110108894A1 (en) Method of forming strained structures in semiconductor devices
US20080169490A1 (en) Semiconductor device and manufacturing method thereof