US20140351470A1 - Methods and systems for an interposer board - Google Patents

Methods and systems for an interposer board Download PDF

Info

Publication number
US20140351470A1
US20140351470A1 US14459077 US201414459077A US2014351470A1 US 20140351470 A1 US20140351470 A1 US 20140351470A1 US 14459077 US14459077 US 14459077 US 201414459077 A US201414459077 A US 201414459077A US 2014351470 A1 US2014351470 A1 US 2014351470A1
Authority
US
Grant status
Application
Patent type
Prior art keywords
interposer
fan
pic
interposer board
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US14459077
Inventor
Darren Cepulis
Masud M. Reza
Michael Stearns
Chanh V. Hua
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Enterprise Development LP
Original Assignee
Hewlett-Packard Development Co LP
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/36Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 – G06F13/00 and G06F21/00
    • G06F1/16Constructional details or arrangements
    • G06F1/18Packaging or power distribution
    • G06F1/189Power distribution
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 – G06F13/00 and G06F21/00
    • G06F1/16Constructional details or arrangements
    • G06F1/20Cooling means
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 – G06F13/00 and G06F21/00
    • G06F1/16Constructional details or arrangements
    • G06F1/20Cooling means
    • G06F1/206Cooling means comprising thermal management
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 – G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof

Abstract

In accordance with at least some embodiments, a system includes an aggregator backplane coupled to a plurality of fans and power supplies and configured to consolidate control and monitoring for the plurality of fans and power supplies. The system also includes a plurality of compute nodes coupled to the aggregator backplane, wherein each compute node selectively communicates with the aggregator backplane via a corresponding interposer board. Each interposer board is configured to translate information passed between its corresponding compute node and the aggregator backplane.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This is a continuation of U.S. patent application Ser. No. 13/386,989, filed Jan. 25, 2012, which is the U.S. National Stage under 35 U.S.C. §371 of International Patent Application No. PCT/US2010/022563, filed Jan. 29, 2010, the disclosure of which is hereby incorporated herein by reference.
  • BACKGROUND
  • There are many types of computer architectures. Some computer architectures combine multiple compute nodes in a shared resource enclosure. Such architectures may require customizing the power, cooling and management of each compute node being implemented in the shared resource enclosure. As an example, such customization may involve significant changes to core firmware and hardware related to the baseboard management controller (BMC) in each compute node. Such customization may have one or more of the following problems: 1) high design costs; 2) long development cycles; 3) limited choices for compute nodes due to limited resources and schedule conflicts.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • For a detailed description of exemplary embodiments of the invention, reference will now be made to the accompanying drawings in which:
  • FIG. 1 illustrates a system in accordance with an embodiment of the disclosure;
  • FIG. 2 illustrates a server enclosure in accordance with an embodiment of the disclosure;
  • FIG. 3 shows a table of microcontroller registers for an interposer programmable interface controller (PIC) in accordance with an embodiment of the disclosure; and
  • FIG. 4 illustrates a method in accordance with an embodiment of the disclosure.
  • NOTATION AND NOMENCLATURE
  • Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, computer companies may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . ” Also, the term “couple” or “couples” is intended to mean either an indirect, direct, optical or wireless electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, through an indirect electrical connection via other devices and connections, through an optical electrical connection, or through a wireless electrical connection. Also, the term “server enclosure” means a server system chassis capable of hosting multiple compute nodes with common infrastructure (e.g., power supplies and fans). As used herein, a “server rack” may contain multiple of such server enclosures.
  • DETAILED DESCRIPTION
  • The following discussion is directed to various embodiments of the invention. Although one or more of these embodiments may be preferred, the embodiments disclosed should not be interpreted, or otherwise used, as limiting the scope of the disclosure, including the claims. In addition, one skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is meant only to be exemplary of that embodiment, and not intended to intimate that the scope of the disclosure, including the claims, is limited to that embodiment.
  • In accordance with embodiments of the disclosure, an interposer board is implemented for each of a plurality of compute nodes housed in an enclosure for a computing system (e.g., a server). Each interposer board interfaces its corresponding compute node to an aggregator backplane that manages the fans and power supplies for the server enclosure. Each interposer board provides predetermined functions that simplify the configuration of compute nodes in a server enclosure with an aggregator backplane. Without the interposer boards, each compute node would need to be designed or customized to communicate directly with the aggregator backplane. Such customization is possible, but is costly and/or results in undesirable latency in the release of new products (e.g., multi-node server enclosure and/or racks with multiple server enclosures).
  • FIG. 1 illustrates a system 100 in accordance with an embodiment of the disclosure. The system 100 may represent, for example, components found in a server enclosure. As shown in FIG. 1, the system 100 comprises a plurality of compute nodes 102A-102N. Each compute node 102A-102N comprises a motherboard or other printed circuit board (PCB) containing resources 104 such as any one or more of processing resources 106, memory resources 108 and input/output (I/O) resources 110. Further, each of the compute node 102A-102N may comprise a network interface 114 coupled to management logic 112. For example, the management logic 112 may monitor and/or log sensor data. In some embodiments, the management logic 112 is configured to transmit fan control signals and/or power supply control signals in response to detected temperature/electrical conditions. Further, the management logic 112 may handle remote computing requests received via the network interface 114. The management logic 122 may correspond to, for example, a baseboard management controller (BMC) known in the art.
  • In the system 100, a plurality of fans 120A-120N provide airflow/cooling for the plurality of compute nodes 102A-102N. FIG. 2 illustrates a server enclosure 200 in accordance with an embodiment of the disclosure. As shown in FIG. 2, the server enclosure 200 comprises eight compute nodes (nodes 1-8) that share a plurality of fans (e.g., fans 1-8). In general, nodes (e.g., nodes 1-8) are organized into zones, with each zone having at least one node and one fan assigned thereto. More specifically, the server enclosure 200 in the embodiment of FIG. 2 has four zones with two nodes and two fans in each zone. As shown, nodes 1 and 3 share two fans, nodes 2 and 4 share two fans, nodes 5 and 7 share two fans, and nodes 6 and 8 share two fans. Other zone configurations are possible and may vary depending on the size of the enclosure, the size of the compute nodes boards and components attached thereto, the heat generated by each compute node, the airflow provided by each fan and/or other characteristics.
  • Returning to FIG. 1, a plurality of power supplies 122A-122N provide power for the plurality of compute nodes 102A-102N. The fans 120A-120N and the power supplies 122A-122N are coupled to an aggregator backplane 124 that consolidates monitoring and control of the fans 120A-120N and the power supplies 122A-122N. In at least some embodiments, the aggregator backplane 124 comprises a backplane programmable interface controller (PIC) 126 (e.g., a microcontroller) coupled to interrupt handler logic 128 (e.g., a complex programmable logic device (CPLD)). The backplane PIC 126 consolidates fan status information received from the fans 120A-120N as well as power supply status information received from the power supplies 122A-122N. The backplane PIC 126 also responds to control signals or requests for information received from the compute nodes 102A-102N.
  • In accordance with at least some embodiments, information and/or control signals from the aggregator backplane 124 are selectively transmitted to each of the compute nodes 102A-102N via its corresponding interposer board 130A-130N. Similarly, information and/or control signals from each of the compute nodes 102A-102N are transmitted via its corresponding interposer board 130A-130N to the aggregator backplane 124. In accordance with at least some embodiments, the interrupt handler logic 128 facilitates communications between the backplane PIC 126 and each interposer board 130A-130N using interrupt protocols.
  • In FIG. 1, each of the interposer boards 130A-130N comprise the same or similar components. For convenience, only the components of the interposer board 130A are shown and discussed, but it should be understood that the discussion of interposer board 130A applies to the other interposer boards (130B-130N) as well. In FIG. 1, the interposer board 130A corresponds to a printed circuit board (PCB) with an interposer programmable interface controller (PIC) 132 mounted thereon and configured to perform various functions as will be described herein. The interposer board 130A also comprises at least one power connector 134 mounted on the PCB to provide a power interface from at least one of the power supplies 122A-122N to the corresponding compute node. The power interface provided by the power connector 134 also enables the aggregator backplane 126 to monitor the power consumption of the corresponding compute node. The interposer board 130A also comprises at least one fan connector 136 mounted on the PCB and coupled to the interposer PIC 132. The fan connector 136 provides an interface for the corresponding compute node to issue fan control signals (requests) and to receive responses to such requests. The interposer board 130A also comprises a serial bus connector (e.g., an I2C bus connector) 138 mounted to the PCB and coupled to the interposer PIC 132. The serial bus connector 128 provides a serial communication interface (e.g., a single-master I2C bus) between the interposer board 130A and its corresponding compute node.
  • In accordance with at least some embodiments, the interposer PIC 132 translates information passed between the aggregator backplane 126 and the compute node corresponding to interposer board 130A. For example, the interposer PIC 132 may translate fan control signals from pulse width modulation (PWM) to a serial bus protocol data packet (e.g., I2C data packets). More specifically, the interposer PIC 132 may receive fan control PWM information from its corresponding compute node and provide a translated version of the fan control PWM information to the backplane PIC 126 via an I2C bus. Further, the interposer PIC 132 may translate fan status signals from Fault to Tach fan emulation. More specifically, the interposer PIC 132 may provide a fan tachometer signal to its corresponding compute node based on a PWM duty cycle and the actual fan status.
  • In at least some embodiments, the interposer PIC 132 receives compute node fan PWM input and digitizes the input in terms of duty cycle. The digitized duty cycle is then passed to the backplane PIC 126 via a multi-master I2C bus. As an example, a fan PWM value of 0 will represent a 0% duty cycle and 100 will represent a 100% duty cycle. Optionally, a compute node BMC may write the fan PWM settings directly to registers of the interposer PIC 132. In some embodiments, digitization of the fan PWM signals may be accomplished based on direct current (DC) conversion. In DC conversion, the PWM signal is converted to an analog DC signal and is digitized via analog-to-digital conversion. Alternatively, digitization of PWM signals may be accomplished using a timer and a capture/compare (CCP) technique. In the timer and CCP technique, the interposer PIC analyzes the PWM signal as a digital input and calculates the duty cycle using internal timers and CCP.
  • The interposer PIC 132 also reads system fan status information from the backplane PIC 126 via an I2C bus. Once the fan status information has been read, the interposer PIC 132 is able to generate a fan tach signal to drive a fan tach signal of a compute node. If any of the system fans fail, a tach signal is not generated by the interposer PIC 132 for the failed fan. Otherwise, the interposer PIC 132 drives the fan tach signal at a frequency corresponding to the PWM of the fan using the equation FanTachCount per Sec=(PWM_DC/100)*(MaxFanRPM/60)*(FanTachPulse/Rev), where the value of FanTachPulse/Rev is normally 2 and MaxFanRPM is the Fan RPM at 100% fan PWM duty cycle.
  • In at least some embodiments, the interposer PIC 132 is configured to bridge a single-master serial bus topology (e.g., single-master I2C) for communications between the interposer board 130A and its corresponding compute node with a multi-master serial bus topology (e.g., multi-master I2C) for communications between the interposer board 130A and the aggregator backplane 126. For example, the interposer PIC 132 may provide I2C MUX arbitration based on request/grant (REQ/GNT) signals for an I2C bus. In other words, the interposer PIC 132 acts as an I2C pass thru between the BMC of a compute node and the backplane PIC 126 to avoid multi-master I2C issues.
  • In relation to the bridge function, the interposer PIC 132 may also manage a traffic level for the multi-master serial bus topology. For example, in at least some embodiments, the interposer PIC 132 is configured to manage consolidation and caching of data such as fan status information, power supply status information, and power consumption meter information. Using the cached information, the interposer PIC 132 is able to selectively respond to requests from a corresponding compute node without requesting updated information from the aggregator backplane 124. For example, the interposer PIC 132 may have a traffic control timing threshold (e.g., 2 seconds) during which all requests (e.g., fan control signals, requests for information) from the compute node corresponding to the interposer board 130A are responded to from cached information within the interposer PIC 132. Once the traffic control timing threshold is reached, the interposer PIC 132 may request updated information from the aggregator backplane 124. The request for updated information may be automated or may be in response to a related request from the compute node corresponding to the interposer board 102A. Further, in at least some embodiments, the aggregator backplane 124 is able to transmit updated information to the interposer PIC 132 without waiting for the interposer PIC 132 to issue or forward a request. The traffic control timing threshold described previously may vary according to predetermined criteria (e.g., the number of compute nodes in a given system) or ongoing traffic analysis.
  • In at least some embodiments, the interposer PIC 132 enables flashing firmware of the backplane PIC 126 via a single-master I2C bus. For example, during the flash process, the interposer PIC 132 receives each line of code from a compute node via a single-master I2C bus and stores the code internally. The interposer PIC 132 then obtains access to the multi-master I2C bus by generating a request (REQ) and receiving a grant (GNT) from the backplane PIC 126. Once the interposer PIC 132 has mastership of the multi-master I2C bus, the line of code is passed to the backplane PIC 126 via the multi-master I2C bus and so on.
  • During the flash process of the backplane PIC 126, the interposer PIC 132 has full functionality. In some embodiments, the backplane PIC 126 may set the system fans to full speed with 100% duty cycle to avoid any thermal events during flashing. During the flash, the interposer PIC 132 may return predetermined values (e.g., the last known power supply status, the last known fan status, a 100% duty cycle for current fan PWM value) in response to respective requests/commands received during the flash process.
  • In at least some embodiments, the firmware of the interposer PIC 132 may be flashed via the single-master I2C bus as well. To perform the flash, a compute node accesses the registers of the interposer PIC 132 by writing a value to the interposer PIC Mailbox register. The compute node also writes a firmware update key to a firmware update keyhole register to put the interposer PIC in bootloader mode. In at least some embodiments, the bootloader mode of the interposer PIC 132 has various attributes. For example, the interposer PIC 132 will limit access of its registers to flash-related functions. In other words, access to non-flash related registers will be NACK'd during the bootloader mode. Once the flash process completes (e.g., usually between 30 seconds to 3 minutes), the interposer PIC 132 automatically resets itself and bring itself back on-line. The reset process may be completed in less than a second and does not require the multi-node system or any of the compute nodes to cycle power or reset. In the bootloader mode, the computer node corresponding to the interposer PIC 132 will not have access to the registers of the backplane PIC 126. However, the interposer PIC 132 continues to generate the fan tach signals at 100% PWM duty cycle for both the fans. Once the flash process completes, the interposer PIC 132 resets itself and the compute node BMC will have access to all the registers of the backplane PIC 126 again. It is expected that the BMC of the corresponding compute node will recognize the flash process of the interposer PIC 132 and avoid logging errors. If a power loss occurs during the flash process (e.g., the interposer PIC 132 loses its VDD or the PIC reset pin is asserted low for a duration that causes a PIC reset), then the interposer PIC 132 returns to the bootloader mode once power is restored. The BMC of the corresponding compute node is then able to re-start the flash process.
  • In FIG. 1, the interrupt handler logic 128 of the aggregator backplane 124 manages communications between the backplane PIC 126 and each interposer board 130A-130N. As shown, an I2C bus (or other serial communication bus) is utilized for communications between the backplane PIC 126 and the interrupt handler logic 128. The timing of serial communications is controlled by a grant signal (GNT), a request signal (REQ) and an interrupt signal (INT). More specifically, the backplane PIC 126 may assert the REQ signal to request mastership of the I2C bus. The assertion of the REQ signal may be based on predetermined operations of the backplane PIC 126 or the INT signal being asserted by the interrupt handler logic 128 to the backplane PIC 126. In response to the REQ signal being asserted by the backplane PIC 126, the interrupt handler logic 128 selectively grants mastership of the I2C bus to the backplane PIC 126 and asserts the GNT signal to notify the backplane PIC 126 regarding the grant of mastership. In response to the GNT signal being asserted, the backplane PIC 126 is able to transmit information to the interrupt handler logic 128 via the I2C bus.
  • Similarly, an I2C bus (or other serial communication bus) is utilized for communications between the interrupt handler logic 128 and the interposer board 132. Again, the timing of serial communications is controlled by a grant signal (GNT), a request signal (REQ) and an interrupt signal (INT). More specifically, the interposer PIC 132 may assert the REQ signal to request mastership of the I2C bus. The assertion of the REQ signal may be based on predetermined operations of the interposer PIC 132 or the INT signal being asserted by the interrupt handler logic 128 to the interposer PIC 132. In response to the REQ signal being asserted by the backplane PIC 126, the interrupt handler logic 128 selectively grants mastership of the I2C bus to the interposer PIC 132 and asserts the GNT signal to notify the interposer PIC 132 regarding the grant of mastership. In response to the GNT signal being asserted, the interposer PIC 132 is able to transmit information to the interrupt handler logic 128 via the I2C bus. The interrupt handler logic 128 is thus able to route information from the backplane PIC 126 to each interposer board 130A-130N. Similarly, the interrupt handler logic 128 is able to route information from each interposer board 130A-130N to the backplane PIC 126.
  • The system 100 described for FIG. 1 may be understood as an abstraction architecture that reduces development time of a multi-node server enclosure by enabling use of available compute node boards with few, if any, modifications. Further, the fans 120A-120N of the system 100 may be, for example, Tach or Fault. Further, the power supplies 122A-122N may be industry standard or HP's “common slot” power supplies. In operation, the aggregator backplane 124 evaluates, monitors, and controls the power supplies 122A-122N and fans 120A-120N at the initial power-on of the system 100, obviating the need for any of the compute nodes 102A-102N of performing this task. The aggregator backplane 124 also performs power metering and limiting for the entire system 100 (e.g., enclosed in an enclosure) as well as for each of the compute nodes 102A-102N. The aggregator backplane 124 also steers relevant management data to and from each of the compute nodes 102A-102N via their corresponding interposer boards 130A-130N. In some embodiments, such steering of management data may be automatic and may be based on the location of each compute node 102A-102N within an enclosure. The backplane PIC 126 also controls the REQ/GNT arbitration for the multi-master I2C bus and thus is aware of which compute node is accessing its register set.
  • The abstraction architecture described herein greatly simplifies each compute node's BMC management support, which is normally handled through industry standard, Intelligent Platform Management Interface (IPMI) compatible Sensor Data Records (SDRs) in the BMC firmware. In accordance with at least some embodiments, each of the compute nodes 102A-102N contain an identical set of SDRs and do not have to carry multiple sets of SDRs depending on each compute node's location in the server enclosure, or in which fan zone (or power zone) a particular compute node is participating. In this manner, the complexity of designing the system 100 or another abstraction architecture system is reduced.
  • In the abstraction architecture of the system 100, the purpose of each interposer board 130A-130N is to simplify and adapt the power, cooling, and management signals for a single compute node into a multi-node, shared-resource architecture. For example, fan PWM outputs from a compute node are captured either as PWM signals or simple I2C bus writes by its corresponding interposer board and then converted (by an interposer PIC) to multi-master I2C bus transactions passed down to the backplane PIC 126 as fan speed requests. Further, each interposer board may retrieve and cache server management data such as power supply status (e.g., AC OK, DC OK, and redundancy status), fan status, actual fan speed, compute node power consumption, and overall chassis power consumption from the backplane PIC 126 on a periodic basis. The server management data is then quickly accessible to the BMC of the compute node corresponding to the interposer board with cached server management data. In some embodiments, sets of compute nodes (e.g., 8, 16 or more) are supported in a single enclosure. As the number of compute nodes increases in a multi-node shared resource architecture, the advantage of enabling each interposer PIC to control/minimize the traffic on the multi-master I2C bus increases as well.
  • In accordance with various industry standards, BMCs usually poll the status of sensors (driven by SDRs) as if the sensors were dedicated to a particular compute node. In the multi-node architecture described herein, the interposer PICs are able to limit the amount of traffic on the shared multi-master I2C bus. For example, a compute node's BMC may be configured to read fan status once per second. Meanwhile, the interposer PIC 132 is able to read fan status information from the backplane PIC 126 at a fixed slower rate (e.g., every 2 seconds). By having an interposer PIC return a locally cached copy of the fan status to the compute node's BMC, the amount of traffic to the backplane PIC 126 can be reduced without any design changes being required to the compute nodes.
  • FIG. 3 shows a table of microcontroller registers for an interposer PIC (e.g., interposer PIC 132) in accordance with an embodiment of the disclosure. As shown, the table comprises an actual fan PWM duty cycle register, a fan 1 tachometer count register, a fan 2 tachometer count register, a fan fault register, a power supply status register (“PS status register”), a firmware update keyhole register, a fan 1 speed request register, a fan 2 speed request register, a mailbox register, and reserved registers. In at least some embodiments, only the mailbox register is directly accessible. The remaining registers are accessible only after the mailbox register has been written to with the correct access key. The reserved registers are read-only registers that are not used at this time.
  • FIG. 4 illustrates a method 400 in accordance with an embodiment of the disclosure. The method 400 is for interfacing a compute node with an aggregator backplane of a multi-node server. As shown, the method 400 comprises receiving, by an interposer board separate from the compute node, a fan control signal from the compute node via a single-master serial bus (block 402). At block 404, the interposer board translates the received fan control signal. In at least some embodiments, translating fan control signals comprises accessing registers of a programmable interface controller (PIC) such as an actual fan pulse width modulation (PWM) duty cycle register, a fan tachometer count register, and a fan fault register. If a traffic control timer has expired (determination block 406), the interposer board routes the translated fan control signal to an aggregator backplane via a multi-master serial bus (block 408). The routing step of block 408 comprises, for example, bridging a single-master I2C bus topology to a multi-master I2C bus topology while managing a traffic level for the multi-master I2C bus topology. The interposer board then caches and routes a response to the fan control signal from the aggregator backplane to the compute node (block 410). If the traffic control timer has not expired (determination block 408), the interposer board responds to the translated fan control signal with previously cached information received from the aggregator board (block 412).
  • The above discussion is meant to be illustrative of the principles and various embodiments of the present invention. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.

Claims (9)

    What is claimed is:
  1. 1. An interposer board for interfacing a compute node with an aggregator backplane of a server enclosure, the interposer board comprising:
    a printed circuit board (PCB); and
    an interposer programmable interface controller (PIC) mounted on the PCB, the interposer PIC being configured to bridge a single-master serial bus topology for communications between the compute node and the interposer board with a multi-master serial bus topology for communications between the interposer board and the aggregator backplane.
  2. 2. The interposer board as in claim 1, wherein the interposer PIC is configured to translate fan control signals from pulse width modulation (PWM) to serial bus topology data packets and to translate fan status signals from Fault to Tach fan emulation.
  3. 3. The interposer board as in claim 1, wherein the interposer PIC is configured to manage traffic to the multi-master serial bus topology by caching fan status information, power supply status information, and power consumption meter information.
  4. 4. The interposer board as in claim 1, wherein the interposer PIC comprises a plurality of control registers including an actual fan pulse width modulation (PWM) duty cycle register, a fan tachometer count register, and a fan fault register, and a power supply status register.
  5. 5. The interposer board as in claim 1, further comprising a fan connector mounted on the PCB and coupled to the interposer PIC, and a single-master serial bus connector mounted to the PCB and coupled to the interposer PIC.
  6. 6. A method for interfacing a plurality of compute nodes with an aggregator backplane of a multi-node server enclosure, the method comprising:
    receiving, at each of a plurality of interposer boards and via a single-master serial bus, a fan control signal from a corresponding compute node separate from the interposer board;
    translating, by each such interposer board, the fan control signal received from the corresponding compute node;
    selectively routing, by the interposer board, translated fan control signals to the aggregator backplane via a multi-master serial bus;
    consolidating the translated fan control signals at the interposer board; and
    controlling a fan based on the consolidated translated fan control signals.
  7. 7. The method as in claim 6 further comprising caching, by the interposer board, server management data from the aggregator backplane for access by the compute node.
  8. 8. The method as in claim 6, further comprising managing a traffic level for the multi-master bus.
  9. 9. The method as in claim 6, further comprising selectively accessing registers of an interposer board programmable interface controller (PIC) including an actual fan pulse width modulation (PWM) duty cycle register, a fan tachometer count register, and a fan fault register.
US14459077 2010-01-29 2014-08-13 Methods and systems for an interposer board Abandoned US20140351470A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/US2010/022563 WO2011093877A1 (en) 2010-01-29 2010-01-29 Methods and systems for an interposer board
US201213386989 true 2012-01-25 2012-01-25
US14459077 US20140351470A1 (en) 2010-01-29 2014-08-13 Methods and systems for an interposer board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14459077 US20140351470A1 (en) 2010-01-29 2014-08-13 Methods and systems for an interposer board

Related Parent Applications (2)

Application Number Title Priority Date Filing Date
PCT/US2010/022563 Continuation WO2011093877A1 (en) 2010-01-29 2010-01-29 Methods and systems for an interposer board
US201213386989 Continuation 2012-01-25 2012-01-25

Publications (1)

Publication Number Publication Date
US20140351470A1 true true US20140351470A1 (en) 2014-11-27

Family

ID=44319628

Family Applications (2)

Application Number Title Priority Date Filing Date
US13386989 Active 2030-07-13 US8832348B2 (en) 2010-01-29 2010-01-29 Methods and systems for an interposer board
US14459077 Abandoned US20140351470A1 (en) 2010-01-29 2014-08-13 Methods and systems for an interposer board

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US13386989 Active 2030-07-13 US8832348B2 (en) 2010-01-29 2010-01-29 Methods and systems for an interposer board

Country Status (5)

Country Link
US (2) US8832348B2 (en)
EP (1) EP2529313A4 (en)
CN (1) CN102713885A (en)
DE (1) DE112010003136T5 (en)
WO (1) WO2011093877A1 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2271992B1 (en) * 2008-04-28 2013-04-03 Hewlett-Packard Development Company, L. P. Method and system for generating and delivering inter-processor interrupts in a multi-core processor and in certain shared-memory multi-processor systems
CN102996482B (en) * 2011-09-08 2015-09-30 上海微电子装备有限公司 A multi-state detecting method and apparatus of the fan
US9047068B2 (en) * 2011-10-31 2015-06-02 Dell Products L.P. Information handling system storage device management information access
US8994425B2 (en) 2012-08-03 2015-03-31 Altera Corporation Techniques for aligning and reducing skew in serial data signals
CN103970639A (en) * 2013-01-31 2014-08-06 鸿富锦精密电子(天津)有限公司 Heat dissipation system and server system with same
WO2014209277A1 (en) * 2013-06-25 2014-12-31 Hewlett-Packard Development Company, L.P. Powering nodes
CN105630094A (en) * 2014-10-30 2016-06-01 阿里巴巴集团控股有限公司 Server chassis and hot plug control method of fan
US10078610B2 (en) 2015-05-04 2018-09-18 Dell Products, L.P. System and method for optimized thermal control for management controller offline
EP3217240A1 (en) * 2016-03-07 2017-09-13 Aldebaran Robotics Data communication bus for a robot

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6260093B1 (en) * 1998-03-31 2001-07-10 Lsi Logic Corporation Method and apparatus for arbitrating access to multiple buses in a data processing system
US6368064B1 (en) * 2000-12-01 2002-04-09 3Com Corporation Apparatus and method of providing redundant power and redundant fan speed control to a plurality of fans
US20040027799A1 (en) * 2002-08-09 2004-02-12 King James Edward Computer system
US20060139854A1 (en) * 2004-12-29 2006-06-29 Beyers Timothy M Tapped interposer for connecting disk drive to chassis
US20070133955A1 (en) * 2005-12-09 2007-06-14 Wen Fuang Hsu Fan Speed Control Circuit Simultaneously Controlled By Temperature And PWM
US20080126597A1 (en) * 2006-08-15 2008-05-29 Tyan Computer Corporation Alternative Local Card, Central Management Module and System Management Architecture For Multi-Mainboard System
US20080165490A1 (en) * 2007-01-09 2008-07-10 Buckland Patrick A Technique to support multiple forms of sas dasd
US20090265045A1 (en) * 2008-04-21 2009-10-22 Dell Products, Lp Information handling system including cooling devices and methods of use thereof
US20090312874A1 (en) * 2008-06-11 2009-12-17 Advanced Micro Devices Inc. Apparatus and Method for Providing Cooling to Multiple Components
US20100281199A1 (en) * 2009-04-30 2010-11-04 Dell Products L.P. Data storage device carrier system

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0341872A3 (en) * 1988-05-09 1990-08-08 AT&T Corp. High density connectors
US5130636A (en) * 1991-02-12 1992-07-14 Raynet Corp. Protective circuit for providing a reference voltage at a backplane
WO1993000638A1 (en) * 1991-06-26 1993-01-07 Ast Research, Inc. Automatic distribution of interrupts controller for a multiple processor computer system
US6275864B1 (en) * 1991-08-13 2001-08-14 Storage Technology Corporation Matrix switch for a network management system
US5473757A (en) * 1992-12-11 1995-12-05 Ge Fanuc Automation North America, Inc. I/O controller using single data lines for slot enable/interrupt signals and specific circuit for distinguishing between the signals thereof
US6115814A (en) * 1997-11-14 2000-09-05 Compaq Computer Corporation Memory paging scheme for 8051 class microcontrollers
US6434167B1 (en) * 1998-01-20 2002-08-13 Texas Instruments Incorporated Communications device with extended filter and line monitoring function
US6069576A (en) * 1998-04-02 2000-05-30 The United States Of America As Represented By The Secretary Of The Navy Synchro-to-digital converter
US6105088A (en) * 1998-07-10 2000-08-15 Northrop Grumman Corporation Backplane assembly for electronic circuit modules providing electronic reconfigurable connectivity of digital signals and manual reconfigurable connectivity power, optical and RF signals
US6392372B1 (en) * 2000-03-31 2002-05-21 Ljm Products, Inc. Brushless DC fan module incorporating integral fan control circuit with a communication port for receiving digital commands to control fan
US6320771B1 (en) * 2000-04-10 2001-11-20 International Business Machines Corporation Fault tolerant active current sharing
US6862644B1 (en) * 2001-05-07 2005-03-01 General Bandwidth Inc. Backplane architecture for a telecommunications system chassis
KR200302002Y1 (en) 2002-10-02 2003-01-24 김미애 fan motor having a one-chip device for fan seed control
US7281076B2 (en) * 2003-04-30 2007-10-09 Hewlett-Packard Development Company, L.P. Form factor converter and tester in an open architecture modular computing system
US7512830B2 (en) * 2004-05-14 2009-03-31 International Business Machines Corporation Management module failover across multiple blade center chassis
US7310738B2 (en) * 2005-02-09 2007-12-18 Hewlett-Packard Development Company, L.P. Multifunctional control of cooling systems for computers
US7141950B1 (en) * 2006-02-28 2006-11-28 Cypress Semiconductor Corp. Fan control utilizing bi-directional communication
US20070230148A1 (en) * 2006-03-31 2007-10-04 Edoardo Campini System and method for interconnecting node boards and switch boards in a computer system chassis
US20080281475A1 (en) * 2007-05-09 2008-11-13 Tyan Computer Corporation Fan control scheme
US7817051B2 (en) * 2007-09-14 2010-10-19 Astec International Limited Power converter with degraded component alarm
US8107256B1 (en) * 2007-10-26 2012-01-31 Solace Systems, Inc. Serviceable networking appliance chassis
US20090299544A1 (en) 2008-05-30 2009-12-03 Minebea Co., Ltd. System and method for fan tray control and monitoring system
US7988063B1 (en) * 2008-06-30 2011-08-02 Emc Corporation Method for controlling cooling in a data storage system
US9354678B2 (en) * 2009-08-11 2016-05-31 Hewlett Packard Enterprise Development Lp Enclosure airflow controller
CN202563431U (en) * 2012-05-18 2012-11-28 浪潮电子信息产业股份有限公司 Universal power supply backplane device

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6260093B1 (en) * 1998-03-31 2001-07-10 Lsi Logic Corporation Method and apparatus for arbitrating access to multiple buses in a data processing system
US6368064B1 (en) * 2000-12-01 2002-04-09 3Com Corporation Apparatus and method of providing redundant power and redundant fan speed control to a plurality of fans
US20040027799A1 (en) * 2002-08-09 2004-02-12 King James Edward Computer system
US20060139854A1 (en) * 2004-12-29 2006-06-29 Beyers Timothy M Tapped interposer for connecting disk drive to chassis
US20070133955A1 (en) * 2005-12-09 2007-06-14 Wen Fuang Hsu Fan Speed Control Circuit Simultaneously Controlled By Temperature And PWM
US20080126597A1 (en) * 2006-08-15 2008-05-29 Tyan Computer Corporation Alternative Local Card, Central Management Module and System Management Architecture For Multi-Mainboard System
US20080165490A1 (en) * 2007-01-09 2008-07-10 Buckland Patrick A Technique to support multiple forms of sas dasd
US20090265045A1 (en) * 2008-04-21 2009-10-22 Dell Products, Lp Information handling system including cooling devices and methods of use thereof
US20090312874A1 (en) * 2008-06-11 2009-12-17 Advanced Micro Devices Inc. Apparatus and Method for Providing Cooling to Multiple Components
US20100281199A1 (en) * 2009-04-30 2010-11-04 Dell Products L.P. Data storage device carrier system

Also Published As

Publication number Publication date Type
EP2529313A1 (en) 2012-12-05 application
US20120131249A1 (en) 2012-05-24 application
DE112010003136T5 (en) 2012-06-21 application
CN102713885A (en) 2012-10-03 application
US8832348B2 (en) 2014-09-09 grant
WO2011093877A1 (en) 2011-08-04 application
EP2529313A4 (en) 2016-03-16 application

Similar Documents

Publication Publication Date Title
US6275864B1 (en) Matrix switch for a network management system
US5822512A (en) Switching control in a fault tolerant system
US20130010639A1 (en) Switch fabric management
US6763415B1 (en) Speculative bus arbitrator and method of operation
EP0343770A2 (en) Multi-bus microcomputer system with bus arbitration
US20090024764A1 (en) Tracking The Physical Location Of A Server In A Data Center
US20040083356A1 (en) Virtual communication interfaces for a micro-controller
US20050066106A1 (en) Input/output unit access switching system and method
US7062595B2 (en) Integrated gigabit ethernet PCI-X controller
US20020029358A1 (en) Method and apparatus for delivering error interrupts to a processor of a modular, multiprocessor system
US7039918B2 (en) Service processor and system and method using a service processor
US20050015632A1 (en) Rack-level power management of computer systems
US20090055157A1 (en) Server Having Remotely Manageable Emulated Functions
US20080043769A1 (en) Clustering system and system management architecture thereof
US20100250914A1 (en) Wake on lan for blade server
US20040228063A1 (en) IPMI dual-domain controller
US20130013957A1 (en) Reducing impact of a switch failure in a switch fabric via switch cards
US20110179211A1 (en) Bios architecture
CN101212345A (en) Blade server management system
US6697254B1 (en) Computer system
US7685325B2 (en) Synchronous bus controller system
US20120023210A1 (en) Server system and operation method thereof
US20090031051A1 (en) Centralized server rack management using usb
US20140289570A1 (en) Virtual baseboard management controller
US20120151475A1 (en) Virtualizing Baseboard Management Controller Operation

Legal Events

Date Code Title Description
AS Assignment

Owner name: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP, TEXAS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.;REEL/FRAME:037079/0001

Effective date: 20151027

AS Assignment

Owner name: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P., TEXAS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CEPULIS, DARREN J;REZA, MASUD M;STEARNS, MICHAEL;AND OTHERS;SIGNING DATES FROM 20100128 TO 20100129;REEL/FRAME:039191/0196