US20140217592A1 - Interconnect structure and method of making same - Google Patents

Interconnect structure and method of making same Download PDF

Info

Publication number
US20140217592A1
US20140217592A1 US14/251,728 US201414251728A US2014217592A1 US 20140217592 A1 US20140217592 A1 US 20140217592A1 US 201414251728 A US201414251728 A US 201414251728A US 2014217592 A1 US2014217592 A1 US 2014217592A1
Authority
US
United States
Prior art keywords
layer
dielectric layer
trench
structure
lower
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US14/251,728
Inventor
Ya Ou
Shom Ponoth
Terry A. Spooner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US11/954,812 priority Critical patent/US8772933B2/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to US14/251,728 priority patent/US20140217592A1/en
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: OU, YA, PONOTH, SHOM, SPOONER, TERRY A.
Publication of US20140217592A1 publication Critical patent/US20140217592A1/en
Assigned to GLOBALFOUNDRIES U.S. 2 LLC reassignment GLOBALFOUNDRIES U.S. 2 LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INTERNATIONAL BUSINESS MACHINES CORPORATION
Assigned to GLOBALFOUNDRIES INC. reassignment GLOBALFOUNDRIES INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GLOBALFOUNDRIES U.S. 2 LLC, GLOBALFOUNDRIES U.S. INC.
Application status is Abandoned legal-status Critical

Links

Images

Classifications

    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23FNON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F4/00Processes for removing metallic material from surfaces, not provided for in group C23F1/00 or C23F3/00
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226Via connections in a multilevel interconnection structure
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329Insulating materials
    • H01L23/53295Stacked insulating layers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An interconnect structure and method of fabricating the same is provided. More specifically, the interconnect structure is a defect free capped interconnect structure. The structure includes a conductive material formed in a trench of a planarized dielectric layer which is devoid of cap material. The structure further includes the cap material formed on the conductive material to prevent migration. The method of forming a structure includes selectively depositing a sacrificial material over a dielectric material and providing a metal capping layer over a conductive layer within a trench of the dielectric material. The method further includes removing the sacrificial material with any unwanted deposited or nucleated metal capping layer thereon.

Description

    FIELD OF THE INVENTION
  • The present invention relates generally to an interconnect structure and method of fabricating the same and, more particularly, to a defect free capped interconnect structure and method of fabricating the same.
  • BACKGROUND OF THE INVENTION
  • Electromigration is the transport of material caused by the gradual movement of ions in a conductor due to the momentum transfer between conducting electrons and diffusing metal atoms. The effect of electromigration is an important consideration to take into account in applications where high direct current densities are used, such as in microelectronics and related structures. In fact, electromigration is known to decrease the reliability of integrated circuits (ICs) and hence lead to a malfunction of the circuit. In the worst case, for example, electromigration leads to the eventual loss of one or more connections and intermittent failure of the entire circuit.
  • The current density in interconnect structures increases due to scaling of the structures. This increased current density degrades EM (electromigration) related reliability. As such, as the structure size in ICs decreases, the practical significance of the EM effect increases. Thus, with increasing miniaturization the probability of failure due to electromigration increases in VLSI and ULSI circuits because both the power density and the current density increase. Also, it is know that in advanced semiconductor manufacturing processes, copper is used as the interconnect material which is subject to EM. Basically, copper is preferred for its superior conductivity.
  • In conventional structures, a metal cap is formed over the copper in an attempt to minimize copper migration, i.e., increase EM lifetime. The metal cap is formed by a selective electroless metal cap deposition process using, for example, CoWP. Although the selective electroless metal cap deposition process is selective to copper, unwanted deposition and/or rogue nucleation of the CoWP still results on the surface of the interlevel dielectric of the structure. That is, although the process is selective to copper, there is still a low deposition rate of the CoWP on the surface of the interlevel dielectric. This, in turn, results in high leakage and poor time dependent dielectric breakdown. In fact, the unwanted deposition and/or rogue nucleation can cause device failure due to shorting between adjacent copper lines.
  • Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.
  • SUMMARY OF THE INVENTION
  • In a first aspect of the invention, a structure comprises a conductive material formed in a trench of a planarized dielectric layer which is devoid of cap material. The structure further includes the cap material formed on the conductive material to prevent migration.
  • In embodiments, the cap material is one of CoWB and CoWP. A liner extends about portions of the conductive material within the trench. The liner is tantalum, tantalum nitride, titanium, titanium nitride, Ruthenium or a combination thereof or doped variations of these (such as with Iridium). The planarized dielectric layer is silicon oxide, carbon doped oxide, SiCxOyHz or a porous dielectric material. The conductive material is precleaned copper.
  • In further embodiments, a sacrificial material selective to the dielectric layer is deposited on the dielectric layer. The sacrificial material is etched back over the conductive material such that the conductive material is free of the sacrificial material. The sacrificial material has a ratio of deposition rate on the dielectric layer to a deposition rate on copper of about 2 or greater. The sacrificial material is hydrophobic. The sacrificial material is a variety of polyxylylene polymers or a variety of silylating agents. The sacrificial material prevents unwanted deposition and/or rogue nucleation of the cap material on the dielectric layer.
  • In another aspect of the invention, an intermediate structure comprises a first dielectric layer having a trench filled with conductive material and a second dielectric layer formed over the first dielectric layer. The second dielectric layer has a via and trench filled with the conductive material and lined with a liner and devoid of unwanted deposition or nucleation of capping material. The capping material is on the conductive material. A cap layer separates the first dielectric layer and the second dielectric layer. A sacrificial layer is placed on the second dielectric layer which prevents the capping material from depositing on the second dielectric layer.
  • In embodiments, the liner is tantalum, tantalum nitride, titanium, titanium nitride, Ruthenium or a combination thereof or doped variations of these (such as with Iridium). The conductive material is precleaned copper. The sacrificial material has a ratio of deposition rate on the second dielectric layer to a deposition rate on the conductive material of about 2 or greater. The sacrificial material is at least one of: hydrophobic and has silylating agents, and a variety of polyxylylene polymers. The sacrificial material prevents unwanted deposition and/or rogue nucleation of the capping material on the second dielectric layer.
  • In another aspect of the invention, a method of forming a structure comprises selectively depositing a sacrificial material over a dielectric material and providing a metal capping layer over a conductive layer within a trench of the dielectric material. The method further includes removing the sacrificial material with any unwanted deposited or nucleated metal capping layer thereon.
  • In embodiments, the removing of the sacrificial material is one of: a UV assisted thermal composition process, followed by a solvent or water rinse; a thermal decomposition process followed by a solvent or water rinse; and a reducing plasma etch followed by a solvent or water rinse. The removing of the sacrificial layer does not significantly chemically damage the dielectric material, the conductive layer or a liner. The depositing of the sacrificial material is selective to the dielectric material.
  • In another aspect of the invention, a method of manufacturing a structure comprises forming a layered structure of a first dielectric material with a first metal wire and a second dielectric material with a second metal wire and extending to the first metal wire. The method includes selectively depositing a sacrificial material over the second dielectric material and depositing a metal capping layer over the second metal wire which causes unwanted depositing and/or nucleation of the metal capping layer on the sacrificial material. The method further includes undercutting the unwanted deposited and/or nucleated metal capping layer from the sacrificial material.
  • In embodiments, the undercutting includes removing at least a portion of the sacrificial material. The removing is performed by one of: a UV assisted thermal composition process, followed by a solvent or water rinse; a thermal decomposition process followed by a solvent or water rinse; and a reducing plasma etch followed by a solvent or water rinse.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The present invention is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present invention, in which:
  • FIG. 1 shows a beginning structure and respective fabrication processes in accordance with the invention;
  • FIGS. 2-6 show intermediate structures and respective fabrication processes in accordance with the invention;
  • FIG. 7 shows a final structure and respective fabrication processes in accordance with the invention;
  • FIG. 8 shows a known thickness of Parlyene as a function of temperature, indicating thermal decomposition and UV-assisted thermal decomposition;
  • FIG. 9 shows known etch rates of Parylene as a function of temperature; and
  • FIG. 10 shows a topography mapping of the structures of FIG. 4 and FIG. 5.
  • DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION
  • The present invention relates generally to an interconnect structure and method of fabricating the same and, more particularly, to a defect free capped interconnect structure and method of fabricating the same. By implementing the fabrication processes and structure in accordance with the invention, the copper interconnect is more reliable than conventional structures and hence is not prone to failure due to shorting, e.g., shorting between copper wires as a result of nucleation.
  • For example, advantageously, by implementing the fabrication processes and structure in accordance with the invention, the surface of the interlevel dielectric is free of capping material such as, for example, CoWP or CoWB. That is, by implementing the fabrication processes of the invention, the resultant structure is free of unwanted deposition and/or rogue nucleation of the CoWP (or other capping material) on the surface of the interlevel dielectric. This, in turn, results in low leakage and increased time dependent dielectric breakdown lifetime.
  • FIG. 1 shows a beginning structure and respective fabrication processes in accordance with the invention. More specifically, FIG. 1 shows a structure having a dielectric layer 10. The dielectric layer 10 can be, for example, any low k or ultra low k material such as, for example, silicon oxide, carbon doped oxide, SiCxOyHz or a porous ILD. In embodiments, the dielectric layer 10 may have a thickness ranging from, for example, about 500 Å to 10000 Å.
  • A metal (e.g., copper) wire 12 is formed in a trench of the dielectric layer 10 using a conventional processes. For example, in a conventional process, a photoresist layer (not shown) is formed over the dielectric layer 10 and exposed to form a pattern (using a hard mask). The photoresist layer may be, for example, an organic spin on layer. A reactive ion etching (RIE) process is performed to form the trench in the dielectric layer 10. A metal (e.g., copper) material is deposited into the trench to form the conductive wire 12 (e.g., copper wire). The structure is then planarized using a conventional process such as a chemical mechanical processing (CMP).
  • FIG. 2 shows an intermediate structure and respective fabrication processes in accordance with the invention. More specifically, FIG. 2 shows a cap layer 14 formed over the planarized dielectric layer 10 and the conductive wire 12. The cap layer 14 may be made from any conventional capping material such as, for example, silicon nitride or silicon carbide. The cap layer 14 can have a thickness that ranges from about 50 Å to 1000 Å.
  • An upper dielectric layer 16 is deposited over the lower cap layer 14, in a conventional process. In embodiments, the upper dielectric layer 16 may have a thickness ranging from, for example, about 500 Å to 10000 Å. The upper dielectric layer 16, much like the dielectric layer 10, can be, for example, any low k or ultra low k material such as, for example, silicon oxide, carbon doped oxide, SiCxOyHz or a porous ILD.
  • A via 18 and a via 19 are formed in the upper dielectric layer 16 using a conventional lithographic and etching process. For example, a photoresist (not shown) is formed over the upper dielectric layer 16 and exposed to form a pattern (using a hard mask). The photoresist layer may be, for example, an organic spin on layer. A reactive ion etching (RIE) process is performed to form the via 18 and the via 19 in the upper dielectric layer 16, which reaches to the cap layer 14.
  • A similar lithographic and RIE process is used to form a trench 20 in the upper dielectric layer 16. The trench 20 can range from about 250 Å to 5000 Å in thickness, and preferably about half way into the upper dielectric layer 16.
  • Referring to FIG. 3, a RIE is formed to open the cap layer 14 to the conductive wire 12. A sputter etch can be performed to etch into the conductive material (e.g., copper) of the conductive wire 12. This etching can also increase the depth of the trench 20. A liner material is deposited in the via 18, the via 19, and the trench 20 to form a liner 22. The liner material is deposited over and in contact with the conductive wire 12. The liner material can be, for example, tantalum, tantalum nitride, titanium, titanium nitride or Ruthenium. The liner material can be deposited using a conventional PVD (physical vapor deposition), CVD (chemical vapor deposition) or ALD (atomic layer deposition) process. The liner 22 can range in thickness from about 2 nm to 20 nm.
  • In FIG. 4, a copper seed layer is deposited over the liner 22. A copper plating may be performed over the copper seed layer to form a thicker copper layer 24, e.g., conductive wire. The copper layer 24 is planarized using a conventional process such as a chemical mechanical processing (CMP). In embodiments, the copper seed layer (or combination of the seed layer and plating) may range from about 25 Å to 700 Å.
  • In optional embodiments, a surface treatment of the structure of FIG. 4 can be provided to preclean the copper layer 24 (or conductive wire, hereinafter referred to as copper). For example, an ammonia preclean or high temperature treatment can be provided to remove any polymer residue on the copper. This precleaning process can increase the selectivity of a sacrificial material to the upper dielectric layer 16 that is deposited in subsequent processing steps.
  • FIG. 5 shows a cross sectional view of the structure of FIG. 4 and further fabrication processes in accordance with the invention. In this view, several trenches filled with copper are shown in the upper dielectric layer 16. As further fabrication processes, a sacrificial material 26 selective to the upper dielectric layer 16 is deposited on the structure via a chemical deposition process at ambient temperature. In embodiments, a non-selective short etch back of the sacrificial material 26 is performed to ensure that the copper layer 24 is free of the sacrificial material 26. The non-selective etch back process can be a gas based chemical RIE. The sacrificial material 26 is about 1 Å to 500 Å in thickness.
  • In embodiments, the sacrificial material 26 has selective deposition properties to the dielectric material. In one contemplated example, the sacrificial material 26 has a ratio of deposition rate on the dielectric material to the deposition rate on copper is about 2 or greater.
  • A preferred sacrificial material 26 is hydrophobic. Examples of the sacrificial material are silylating agents such as Trimethylchlorosilane and Hexamethyldisilazane. In another example, the sacrificial material can be a variety of polyxylylene polymers such as, for example, Parylene™. Parylene is a polymer manufactured from di-p-xylene, a dimer of p-xylene. Di-p-xylene, more properly known as [2.2]paracyclophane, is made from p-xylene in several steps involving bromination, amination and elimination.
  • FIG. 6 shows an intermediate structure and respective fabrication processes in accordance with the invention. In FIG. 6, a selective electroless metal cap deposition process forms a cap layer 28 over the copper layer 24. The cap layer 28 may be, for example, CoWP or CoWB or other appropriate capping materials designed to prevent copper migration. In embodiments, any capping material that can be selectively deposited on copper is contemplated.
  • As shown in FIG. 6, during this deposition process unwanted deposition and/or rogue nucleation of CoWP or CoWB or other capping materials (generally represented at reference numeral 30) results on the surface of the sacrificial material 26. In embodiments, a decrease in the unwanted deposition and/or rogue nucleation, compared to conventional structures, is possible as the sacrificial material 26 is hydrophobic. However, as shown in FIG. 6, unwanted deposition and/or rogue nucleation does not form on the upper dielectric layer 16.
  • FIG. 7 shows a final structure and respective fabrication processes in accordance with the invention. In FIG. 7, the sacrificial layer 26 is removed using various types of processes. In embodiments, it may only be necessary to remove a portion (e.g., an upper most layer) of the sacrificial layer 26, depending on the material properties of the sacrificial layer 26. These material properties may be, for example, compatibility with back of the line material processes, dielectric constant, thermal stability and mechanical properties, to name a few. In any scenario described herein, the removal of the sacrificial layer 26 or a portion thereof, will also result in the removal or undercutting of the unwanted metal or rogue nucleation of the CoWP, CoWB, etc., on the surface of the sacrificial material 26 (and hence the structure).
  • In embodiments, the sacrificial layer 26 may be removed using any process that is selective to the sacrificial layer 26, while maintaining the integrity of the dielectric, liner and copper materials of the structure. Thus, the removal process should not significantly chemically damage the dielectric, liner and copper materials of the structure. For example, the removal process may be a UV assisted thermal composition process, followed by a solvent or water rinse. Alternatively, a thermal decomposition process followed by a solvent or water rinse may be used to remove the sacrificial layer 26. Depending on the properties of the sacrificial layer 26, the thermal decomposition process can occur at temperatures of greater than 400° C. In alternative methods, the sacrificial layer 26 may be removed by a reducing plasma etch followed by a solvent or water rinse.
  • FIG. 8 shows a known thickness of Parlyene as a function of temperature, indicating thermal decomposition and UV-assisted thermal decomposition. (See, Chemical Vapor Deposition Polymerization: The Growth and Properties of Parylene Thin Films, by Jeffrey B. Fortin and Toh-Ming Lu.) As shown graphically, the thickness of Parylene changes due to degradation from annealing. That is, the thickness of Parylene decreases over time and increased temperature. This same or similar process is also applicable for other sacrificial materials, i.e., decrease of thickness over time and temperature.
  • FIG. 9 shows known etch rates of Parylene as a function of temperature. (See, Atomic Layer Deposition of Metals on Dielectric Substrates, by Gregory A Ten Eyck.) As shown in this graph, using 1.5:1 N2:H2 plasma etching at 55 W, the etch rate increases as temperature increases. The data of this graph and the graph of FIG. 8 can be used by those of skill in the art to determine appropriate removal rates of Parylene, when practicing the invention.
  • FIG. 10 shows a topography mapping of the structures of FIG. 4 and FIG. 5. It should be realized that after CMP processing, the dielectric layer 16 may be recessed in comparison to the liner 22 and copper 24. As shown experimentally, the sacrificial material 26 is selective to the dielectric layer 16. That is, as shown in FIG. 10 there is a profile change of the structures between the processing steps of FIG. 4 and FIG. 5. This profile change is experimental evidence that the sacrificial material 26 is deposited at a sufficient thickness on the dielectric layer 16 in a quantity thicker than that on the copper material 24. This sacrificial material 26 will protect the structure from unwanted deposition and/or nucleation of the cap material on the surface of the dielectric material. This, in turn, will increase the EM lifetime and reduce the risk of shorting between copper wires and early time dependent dielectric breakdown failure, especially as the structure is scaled.
  • The methods and structures as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with the structures of the invention) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
  • While the invention has been described in terms of embodiments, those skilled in the art will recognize that the invention can be practiced with modifications and in the spirit and scope of the appended claims.

Claims (17)

What is claimed is:
1. A structure, comprising:
a conductive layer formed in a trench of a planarized dielectric layer, a top surface of the conductive layer being at a coplanar level as a top surface of the dielectric layer;
a liner completely lining sidewalls and a bottom of the trench;
a sacrificial layer formed selective to an exposed surface of the planarized dielectric layer;
a cap layer formed on the conductive layer to prevent migration, the planarized dielectric layer being devoid of the cap layer, and the cap layer being in physical contact with the conductive layer; and
unwanted deposition and/or rogue nucleation material formed on the sacrificial layer, wherein the unwanted deposition and/or rogue nucleation is a same material as the cap layer.
2. The structure of claim 1, wherein the cap layer is one of CoWB and CoWP of different compositions.
3. The structure of claim 1, wherein the liner extends below portions of the conductive layer within the trench.
4. The structure of claim 3, wherein the liner is tantalum, tantalum nitride, titanium, titanium nitride or Ruthenium.
5. The structure of claim 1, wherein the planarized dielectric layer is silicon oxide, carbon doped oxide, SiCxOyHz or a porous dielectric material.
6. The structure of claim 1, wherein the sacrificial layer has a ratio of deposition rate on the planarized dielectric layer to a deposition rate on copper of about 2 or greater.
7. The structure of claim 1, wherein the sacrificial layer is one of hydrophobic, a variety of silylating agents, and a variety of polyxylylene polymers.
8. The structure of claim 1, wherein the sacrificial layer prevents the unwanted deposition and/or rogue nucleation of the cap layer on the planarized dielectric layer.
9. The structure of claim 1, further comprising:
a lower dielectric layer having a lower trench;
a lower cap layer formed on the lower dielectric layer, the planarized dielectric layer formed on the lower cap layer;
a planarized dielectric layer, formed on the lower cap layer, having an upper trench; and
a via aligned with the lower trench and structured to connect the trench with the lower trench, the via being formed through the planarized dielectric layer and the lower cap layer into the lower conductive layer,
wherein the liner extends through the lower cap layer, and a bottom surface of a bottom portion of the liner is non-planar and below a top surface of the lower dielectric layer.
10. An intermediate structure, comprising:
a first dielectric layer having a first trench filled with a first conductive layer;
a second dielectric layer formed over the first dielectric layer, the second dielectric layer having a via and a second trench, wherein the via and the second trench are lined with a liner and filled with a second conductive layer on the liner, a top surface of the second conductive layer being at a coplanar level as a top surface of the second dielectric layer, the second dielectric layer being devoid of unwanted deposition or nucleation of a capping layer, and the capping layer being on the second conductive layer;
a sacrificial layer placed on an entire exposed surface of the second dielectric layer, which prevents the capping layer from depositing on the second dielectric layer, the capping layer being devoid of the sacrificial layer; and
a plurality of isolated deposits of a nucleated cap material formed on the sacrificial material,
wherein the nucleated cap material comprises a same material as the capping layer.
11. The intermediate structure of claim 10, wherein the liner is tantalum, tantalum nitride, titanium, titanium nitride or Ruthenium.
12. The intermediate structure of claim 10, wherein the first conductive layer and the second conductive material are copper.
13. The intermediate structure of claim 10, wherein the sacrificial layer has a ratio of deposition rate on the second dielectric layer to a deposition rate on the second conductive layer of about 2 or greater.
14. The intermediate structure of claim 10, wherein the sacrificial layer is at least one of:
hydrophobic and has silylating agents, and a variety of polyxylylene polymers.
15. The intermediate structure of claim 10, wherein the sacrificial layer prevents unwanted deposition and/or rogue nucleation of the capping layer on the second dielectric layer.
16. The intermediate structure of claim 10, wherein:
the capping layer is one of CoWB and CoWP of different compositions; and
the capping layer is in physical contact with the second conductive layer.
17. The intermediate structure of claim 10, further comprising a lower capping layer formed on the first dielectric layer, wherein:
the second dielectric layer is formed on the lower capping layer;
the via aligns with the first trench and connects with the second trench, extends from the second dielectric layer through the lower capping layer and into the first trench;
the liner extends below portions of the second conductive layer within the via and the second trench, extends through the lower capping layer, and extends into and in physical contact with the first conductive layer; and
the second conductive layer extends through the lower capping layer and into the first trench.
US14/251,728 2007-12-12 2014-04-14 Interconnect structure and method of making same Abandoned US20140217592A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US11/954,812 US8772933B2 (en) 2007-12-12 2007-12-12 Interconnect structure and method of making same
US14/251,728 US20140217592A1 (en) 2007-12-12 2014-04-14 Interconnect structure and method of making same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/251,728 US20140217592A1 (en) 2007-12-12 2014-04-14 Interconnect structure and method of making same
US14/276,360 US9334572B2 (en) 2007-12-12 2014-05-13 Interconnect structure and method of making same

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US11/954,812 Continuation US8772933B2 (en) 2007-12-12 2007-12-12 Interconnect structure and method of making same

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US14/276,360 Continuation US9334572B2 (en) 2007-12-12 2014-05-13 Interconnect structure and method of making same

Publications (1)

Publication Number Publication Date
US20140217592A1 true US20140217592A1 (en) 2014-08-07

Family

ID=40752130

Family Applications (4)

Application Number Title Priority Date Filing Date
US11/954,812 Active 2029-11-04 US8772933B2 (en) 2007-12-12 2007-12-12 Interconnect structure and method of making same
US13/415,159 Active US8772180B2 (en) 2007-12-12 2012-03-08 Interconnect structure and method of making same
US14/251,728 Abandoned US20140217592A1 (en) 2007-12-12 2014-04-14 Interconnect structure and method of making same
US14/276,360 Active US9334572B2 (en) 2007-12-12 2014-05-13 Interconnect structure and method of making same

Family Applications Before (2)

Application Number Title Priority Date Filing Date
US11/954,812 Active 2029-11-04 US8772933B2 (en) 2007-12-12 2007-12-12 Interconnect structure and method of making same
US13/415,159 Active US8772180B2 (en) 2007-12-12 2012-03-08 Interconnect structure and method of making same

Family Applications After (1)

Application Number Title Priority Date Filing Date
US14/276,360 Active US9334572B2 (en) 2007-12-12 2014-05-13 Interconnect structure and method of making same

Country Status (2)

Country Link
US (4) US8772933B2 (en)
TW (1) TW200933743A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019055508A1 (en) * 2017-09-12 2019-03-21 Applied Materials, Inc. Selective deposition defects removal by chemical etch

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8772933B2 (en) * 2007-12-12 2014-07-08 International Business Machines Corporation Interconnect structure and method of making same
US8598031B2 (en) * 2009-09-28 2013-12-03 Globalfoundries Singapore Pte. Ltd. Reliable interconnect for semiconductor device
US8227339B2 (en) * 2009-11-02 2012-07-24 International Business Machines Corporation Creation of vias and trenches with different depths
US8399350B2 (en) * 2010-02-05 2013-03-19 International Business Machines Corporation Formation of air gap with protection of metal lines
US8906799B1 (en) * 2013-07-29 2014-12-09 International Business Machines Corporation Random local metal cap layer formation for improved integrated circuit reliability
US9142456B2 (en) * 2013-07-30 2015-09-22 Lam Research Corporation Method for capping copper interconnect lines
US9293365B2 (en) * 2014-03-27 2016-03-22 Globalfoundries Inc. Hardmask removal for copper interconnects with tungsten contacts by chemical mechanical polishing
US10269697B2 (en) * 2015-12-28 2019-04-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5695810A (en) * 1996-11-20 1997-12-09 Cornell Research Foundation, Inc. Use of cobalt tungsten phosphide as a barrier material for copper metallization
US6144099A (en) * 1999-03-30 2000-11-07 Advanced Micro Devices, Inc. Semiconductor metalization barrier
US6577011B1 (en) * 1997-07-10 2003-06-10 International Business Machines Corporation Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same
US20080108219A1 (en) * 2006-11-03 2008-05-08 Frank Huebinger Semiconductor interconnect and method of making same
US20080197500A1 (en) * 2007-02-16 2008-08-21 International Business Machines Corporation Interconnect structure with bi-layer metal cap
US8772933B2 (en) * 2007-12-12 2014-07-08 International Business Machines Corporation Interconnect structure and method of making same

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5612254A (en) 1992-06-29 1997-03-18 Intel Corporation Methods of forming an interconnect on a semiconductor substrate
US5767687A (en) 1996-11-29 1998-06-16 Geist; Jon Surface-capacitor type condensable-vapor sensor
US6245690B1 (en) * 1998-11-04 2001-06-12 Applied Materials, Inc. Method of improving moisture resistance of low dielectric constant films
US6387822B1 (en) * 1999-11-12 2002-05-14 Texas Instruments Incorporated Application of an ozonated DI water spray to resist residue removal processes
JP2002110644A (en) 2000-09-28 2002-04-12 Nec Corp Etching method
US6595006B2 (en) * 2001-02-13 2003-07-22 Technology Applications, Inc. Miniature reciprocating heat pumps and engines
US6951823B2 (en) 2001-05-14 2005-10-04 Axcelis Technologies, Inc. Plasma ashing process
US6878615B2 (en) * 2001-05-24 2005-04-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method to solve via poisoning for porous low-k dielectric
JP2003282698A (en) * 2002-03-22 2003-10-03 Sony Corp Method for fabricating semiconductor and the same
US7060619B2 (en) * 2003-03-04 2006-06-13 Infineon Technologies Ag Reduction of the shear stress in copper via's in organic interlayer dielectric material
US7026714B2 (en) * 2003-03-18 2006-04-11 Cunningham James A Copper interconnect systems which use conductive, metal-based cap layers
US6958524B2 (en) * 2003-11-06 2005-10-25 Taiwan Semiconductor Manufacturing Company, Ltd. Insulating layer having graded densification
CN100455178C (en) * 2004-02-24 2009-01-21 信越聚合物株式会社 Electromagnetic wave noise suppressor, structural body with electromagnetic wave noise suppressing function, and process for producing them
US7129159B2 (en) * 2004-08-17 2006-10-31 International Business Machines Corporation Integrated dual damascene RIE process with organic patterning layer
US7544574B2 (en) * 2005-10-11 2009-06-09 Intermolecular, Inc. Methods for discretized processing of regions of a substrate
US7772702B2 (en) * 2006-09-21 2010-08-10 Intel Corporation Dielectric spacers for metal interconnects and method to form the same
US20080197499A1 (en) 2007-02-15 2008-08-21 International Business Machines Corporation Structure for metal cap applications

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5695810A (en) * 1996-11-20 1997-12-09 Cornell Research Foundation, Inc. Use of cobalt tungsten phosphide as a barrier material for copper metallization
US6577011B1 (en) * 1997-07-10 2003-06-10 International Business Machines Corporation Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same
US6144099A (en) * 1999-03-30 2000-11-07 Advanced Micro Devices, Inc. Semiconductor metalization barrier
US20080108219A1 (en) * 2006-11-03 2008-05-08 Frank Huebinger Semiconductor interconnect and method of making same
US20080197500A1 (en) * 2007-02-16 2008-08-21 International Business Machines Corporation Interconnect structure with bi-layer metal cap
US8772933B2 (en) * 2007-12-12 2014-07-08 International Business Machines Corporation Interconnect structure and method of making same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019055508A1 (en) * 2017-09-12 2019-03-21 Applied Materials, Inc. Selective deposition defects removal by chemical etch

Also Published As

Publication number Publication date
US8772933B2 (en) 2014-07-08
US20090152723A1 (en) 2009-06-18
US20140326698A1 (en) 2014-11-06
US20120171862A1 (en) 2012-07-05
US8772180B2 (en) 2014-07-08
TW200933743A (en) 2009-08-01
US9334572B2 (en) 2016-05-10

Similar Documents

Publication Publication Date Title
JP4516640B2 (en) Method for forming interconnect structure in semiconductor device
US6258710B1 (en) Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity
US7902581B2 (en) Semiconductor device comprising a contact structure based on copper and tungsten
US5063175A (en) Method for manufacturing a planar electrical interconnection utilizing isotropic deposition of conductive material
US7341946B2 (en) Methods for the electrochemical deposition of copper onto a barrier layer of a work piece
US6919266B2 (en) Copper technology for ULSI metallization
US7262505B2 (en) Selective electroless-plated copper metallization
US6242349B1 (en) Method of forming copper/copper alloy interconnection with reduced electromigration
US6287954B1 (en) Method of forming copper interconnections with enhanced electromigration resistance and reduced defect sensitivity
US7413991B2 (en) Damascene process at semiconductor substrate level
EP0982771B1 (en) Process for semiconductor device fabrication having copper interconnects
US7259463B2 (en) Damascene interconnect structure with cap layer
US20020132468A1 (en) Structural reinforcement of highly porous low k dielectric films by Cu diffusion barrier structures
US6660634B1 (en) Method of forming reliable capped copper interconnects
US6368967B1 (en) Method to control mechanical stress of copper interconnect line using post-plating copper anneal
US6350687B1 (en) Method of fabricating improved copper metallization including forming and removing passivation layer before forming capping film
US7071562B2 (en) Interconnects with improved barrier layer adhesion
US6303505B1 (en) Copper interconnect with improved electromigration resistance
US8030777B1 (en) Protection of Cu damascene interconnects by formation of a self-aligned buffer layer
US6509267B1 (en) Method of forming low resistance barrier on low k interconnect with electrolessly plated copper seed layer
US7446032B2 (en) Methods of providing an adhesion layer for adhesion of barrier and/or seed layers to dielectric films
US6972253B2 (en) Method for forming dielectric barrier layer in damascene structure
US20010051420A1 (en) Dielectric formation to seal porosity of low dielectic constant (low k) materials after etch
US6153523A (en) Method of forming high density capping layers for copper interconnects with improved adhesion
KR100892403B1 (en) Method of forming reliable cu interconnects

Legal Events

Date Code Title Description
AS Assignment

Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:OU, YA;PONOTH, SHOM;SPOONER, TERRY A.;SIGNING DATES FROM 20140327 TO 20140328;REEL/FRAME:032664/0909

AS Assignment

Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001

Effective date: 20150629

AS Assignment

Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001

Effective date: 20150910

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION