US20140210051A1 - Method for implementing deep trench enabled high current capable bipolar transistor for current switching and output driver applications - Google Patents

Method for implementing deep trench enabled high current capable bipolar transistor for current switching and output driver applications Download PDF

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US20140210051A1
US20140210051A1 US13/750,374 US201313750374A US2014210051A1 US 20140210051 A1 US20140210051 A1 US 20140210051A1 US 201313750374 A US201313750374 A US 201313750374A US 2014210051 A1 US2014210051 A1 US 2014210051A1
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deep trench
providing
collector
recited
deep
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US8809156B1 (en
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David H. Allen
Douglas M. Dewanz
David P. Paulsen
II John E. Sheets
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International Business Machines Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41708—Emitter or collector electrodes for bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/6625—Lateral transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/735—Lateral transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout

Definitions

  • the present invention relates generally to the data processing field, and more particularly, relates to a method and structures for implementing deep trench enabled high current capable bipolar transistor for current switching and output driver applications.
  • this invention targets power gating applications where extremely large area field effect transistors (FETs) are generally used to enable/disable power delivery and similarly extremely large area FETs are generally used in off chip output driver applications.
  • FETs field effect transistors
  • Electrostatic discharge circuits are taking ever larger subsets of the semiconductor die area.
  • the power gating structures are area intensive, generally occupying 2% of the total area of the functional unit being power gated.
  • the power gating FETs also have significant IR drop implications on the power rail supporting the function being power gated, typically on the order of 2% IR drop when one spends 2% of the total area on power gating.
  • a deep oxygen implant is provided in a selected region of substrate.
  • a first deep trench and second deep trench are formed above the deep oxygen implant.
  • the first deep trench is a generally large rectangular box deep trench of minimum width and the second deep trench is a second small area deep trench centered within the first rectangular box deep trench.
  • Ion implantation at relatively high ion pressure is utilized to incorporate N+ dopants or P+ dopants on the exposed surfaces of each of the first deep trench and second deep trench.
  • Subsequent annealing renders highly doped N+ regions or P+ regions both inside and outside the outside the first deep trench and around the outside the second deep trench region. These N+ regions or P+ regions provide the collector and emitter respectively, and the existing substrate region provides the base region between the collector and emitter regions.
  • the bipolar transistor is current density optimized rather than being beta or gain optimized.
  • forming a base contact, a collector contact, and an emitter contact includes high concentration implants for providing low resistance contacts.
  • the deep oxygen implant forms an implanted silicon dioxide layer, which provides an etch stop for the deep trench etches.
  • the deep oxygen implant includes a depth in a range of approximately 2-5 micrometers ( ⁇ m).
  • the first deep trench is a generally large rectangular box deep trench, for example, on the order of 1.0 ⁇ m on a side.
  • collector current density is provided by using a base region width optimized for current density.
  • FIG. 1 is a schematic side plan view not to scale illustrating example processing steps for implementing a deep trench enabled high current capable bipolar transistor for current switching and output driver applications in accordance with the preferred embodiment
  • FIG. 2 is a schematic top plan view not to scale illustrating example processing steps for implementing the deep trench enabled high current capable bipolar transistor for current switching and output driver applications in accordance with the preferred embodiment
  • FIG. 3 is a schematic side plan view not to scale illustrating example processing steps for implementing a deep trench enabled high current capable bipolar transistor for current switching and output driver applications in accordance with the preferred embodiment
  • FIG. 4 is a schematic top plan view not to scale illustrating example processing steps for implementing the deep trench enabled high current capable bipolar transistor for current switching and output driver applications in accordance with the preferred embodiment
  • FIG. 5 is a schematic side plan view not to scale illustrating the deep trench enabled high current capable bipolar transistor for current switching and output driver applications with a final device schematic overlay in accordance with the preferred embodiment
  • FIG. 6 is a flow chart illustrating exemplary processing steps for fabricating a deep trench enabled high current capable bipolar transistor for current switching and output driver applications in accordance with the preferred embodiment.
  • a method and structures are provided for implementing deep trench enabled high current capable NPN or PNP bipolar transistor for current switching and output driver applications.
  • FIG. 1 there is schematically shown example processing steps generally designated by the reference character 100 for implementing a deep trench enabled high current capable bipolar transistor for current switching and output driver applications in accordance with the preferred embodiment.
  • the deep trench enabled high current capable bipolar transistor is current density optimized rather than being beta or gain optimized.
  • a semiconductor substrate 102 formed of a suitable material such as a silicon substrate 102 includes suitable doping, such as P-doped substrate 102 provided for fabricating a deep trench enabled high current capable NPN bipolar transistor.
  • suitable doping such as P-doped substrate 102 provided for fabricating a deep trench enabled high current capable NPN bipolar transistor.
  • a substrate that is N-doped is provided for the substrate 102 for fabricating a deep trench enabled high current capable PNP bipolar transistor.
  • an oxygen implant or O2 implant 104 through an O2 blocking layer or photo-resist 106 providing a deep oxygen implant 108 in a selected region of substrate 102 at a desired depth.
  • a high O2 implant dose is assumed thereby creating a definitive SiO2 layer 108 , for example, as deep as possible, such as ⁇ 2-5 ⁇ m, with considerations including silicon damage, implant dose, and the like.
  • FIG. 2 illustrates example processing steps generally designated by the reference character 200 for implementing the deep trench enabled high current capable bipolar transistor for current switching and output driver applications in accordance with the preferred embodiment.
  • the processing steps 200 include patterning and etching steps 202 providing a first deep trench 204 and a second deep trench 206 formed above the deep oxygen implant 108 in FIG. 1 .
  • the implanted silicon dioxide layer 108 provides an etch stop for the deep trench etches 204 , 206 .
  • the first deep trench 204 is a generally large, for example, on the order of 1.0 ⁇ m on a side, rectangular box deep trench of minimum width.
  • the second deep trench 206 is a second small area deep trench centered within the first rectangular box deep trench 204 .
  • This structure of trenches 204 , 206 as a large picture frame surrounding a dot in the center of the framed image.
  • N+ ion implant and anneal steps 302 for fabricating a deep trench enabled high current capable NPN bipolar transistor include ion implantation at relatively high ion pressure that is utilized to incorporate N+ dopants on the exposed surfaces of each of the first deep trench and second deep trench through a patterned implant blocking layer or photo-resist 304 . Subsequent annealing renders highly doped N+ regions 306 both inside and outside the first deep trench 204 and around the outside the second deep trench region 206 .
  • P+ ion implant and anneal steps 302 form highly doped P+ regions 306 both inside and outside the first deep trench 204 and around the outside the second deep trench region 206 for fabricating a deep trench enabled high current capable PNP bipolar transistor.
  • N+ regions 306 or P+ regions 306 provide the collector and emitter respectively, and the existing substrate region provides the base region between the collector and emitter regions, as illustrated in FIGS. 4 and 5 .
  • the existing substrate region provides the base region between the collector and emitter regions, as illustrated in FIGS. 4 and 5 .
  • current densities around 100 mA per ⁇ m 2 of collector are enabled.
  • the deep trench enabled high current capable bipolar transistor of the invention provides improvements over conventional FETs for high current applications.
  • a FET on the order of 1 mm of device width is required to source 800 mA of current.
  • Drawing gates on a contacted pitch the planar FET would requires hundreds of square microns of surface to support that potential 800 mA power gated circuit load.
  • Processing steps 402 include filling trenches 204 , 206 with polysilicon or other suitable conductive fill 404 , performing high concentration implants for low-resistance (low-R) contacts, and making a base contact 410 , a collector contact 412 , and an emitter contact 414 .
  • desired concentrations include ⁇ 1e21/cm 3 for the emitter, 1e17 3 base and 1e15/cm 3 for the collector to base junction, 1e19/cm 3 for the collector contact region.
  • FIG. 5 illustrates a final device schematic overlay for the example deep trench enabled high current capable bipolar transistor generally designated by the reference character 500 for current switching and output driver applications in accordance with the preferred embodiment.
  • the collector contact 412 , and the emitter contact 414 are shown with respective N+ regions 306 and conductive fill 404 and the base contact 410 is provided by the substrate P region between the collector and emitter N+ regions 306 .
  • FIG. 6 a flowchart illustrates exemplary processing steps generally designated by the reference character 600 for fabricating a deep trench enabled high current capable bipolar transistor for current switching and output driver applications in accordance with the preferred embodiment.
  • a base substrate is provided with p-doping for fabricating a deep trench NPN bipolar transistor for current switching and output driver applications.
  • the base substrate is provided with n-doping for fabricating a deep trench PNP bipolar transistor for current switching and output driver applications at block 602 .
  • a deep oxygen implant is performed in a selected region of substrate, creating a definitive SiO2 layer 108 .
  • Patterning and etching define a first deep trench 204 and a second deep trench 206 that are formed above the deep oxygen implant 108 with the first deep trench being a generally large rectangular box deep trench of minimum width and the second deep trench being a second small area deep trench centered within the first rectangular box deep trench as indicated in a block 606 .
  • an ion implant at relatively high ion pressure is utilized to incorporate N+ dopants or P+ dopants on the exposed surfaces of each of the first deep trench and second deep trench and subsequent annealing renders highly doped N+ regions or highly doped P+ regions both inside and outside the outside the first deep trench 204 and around the outside the second deep trench region 206 .
  • the N+ regions or P+ regions formed at block 608 provide the collector and emitter respectively, and the existing substrate region provides the base region between the collector and emitter regions.
  • the trenches 204 , 206 are filled with polysilicon or other conductive fill, high concentration implants are provided for low resistance contacts, with a P+ implantation to allow a low resistance base contact for the NPN bipolar transistor or an N+ implantation to allow a low resistance base contact for the PNP bipolar transistor, and a base contact 410 , a collector contact 412 , and an emitter contact 414 are formed.

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Abstract

A method and structures are provided for implementing deep trench enabled high current capable bipolar transistor for current switching and output driver applications. A deep oxygen implant is provided in a selected region of substrate. A first deep trench and second deep trench are formed above the deep oxygen implant. The first deep trench is a generally large rectangular box deep trench of minimum width and the second deep trench is a second small area deep trench centered within the first rectangular box deep trench. Ion implantation at relatively high ion pressure and annealing is utilized to form highly doped N+ regions or P+ regions both inside and outside the outside the first deep trench and around the outside the second deep trench region. These regions provide the collector and emitter respectively, and the existing substrate region provides the base region between the collector and emitter regions.

Description

    FIELD OF THE INVENTION
  • The present invention relates generally to the data processing field, and more particularly, relates to a method and structures for implementing deep trench enabled high current capable bipolar transistor for current switching and output driver applications.
    • DESCRIPTION OF THE RELATED ART
  • As integrated circuit logic circuit geometries continue to shrink, unfortunately a few structures continue to require a large area. Specifically, this invention targets power gating applications where extremely large area field effect transistors (FETs) are generally used to enable/disable power delivery and similarly extremely large area FETs are generally used in off chip output driver applications.
  • Electrostatic discharge circuits are taking ever larger subsets of the semiconductor die area. The power gating structures are area intensive, generally occupying 2% of the total area of the functional unit being power gated. The power gating FETs also have significant IR drop implications on the power rail supporting the function being power gated, typically on the order of 2% IR drop when one spends 2% of the total area on power gating.
  • A need exists for an effective mechanism and method of fabricating an enhanced transistor for current switching and output driver applications.
    • SUMMARY OF THE INVENTION
  • Principal aspects of the present invention are to provide a method and structures for implementing deep trench enabled high current capable bipolar transistor for current switching and output driver applications. Other important aspects of the present invention are to provide such method and structures substantially without negative effects and that overcome many of the disadvantages of prior art arrangements.
  • In brief, a method and structures are provided for implementing deep trench enabled high current capable bipolar transistor for current switching and output driver applications. A deep oxygen implant is provided in a selected region of substrate. A first deep trench and second deep trench are formed above the deep oxygen implant. The first deep trench is a generally large rectangular box deep trench of minimum width and the second deep trench is a second small area deep trench centered within the first rectangular box deep trench. Ion implantation at relatively high ion pressure is utilized to incorporate N+ dopants or P+ dopants on the exposed surfaces of each of the first deep trench and second deep trench. Subsequent annealing renders highly doped N+ regions or P+ regions both inside and outside the outside the first deep trench and around the outside the second deep trench region. These N+ regions or P+ regions provide the collector and emitter respectively, and the existing substrate region provides the base region between the collector and emitter regions.
  • In accordance with features of the invention, the bipolar transistor is current density optimized rather than being beta or gain optimized.
  • In accordance with features of the invention, forming a base contact, a collector contact, and an emitter contact includes high concentration implants for providing low resistance contacts.
  • In accordance with features of the invention, the deep oxygen implant forms an implanted silicon dioxide layer, which provides an etch stop for the deep trench etches.
  • In accordance with features of the invention, the deep oxygen implant includes a depth in a range of approximately 2-5 micrometers (μm).
  • In accordance with features of the invention, the first deep trench is a generally large rectangular box deep trench, for example, on the order of 1.0 μm on a side.
  • In accordance with features of the invention, collector current density is provided by using a base region width optimized for current density.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The present invention together with the above and other objects and advantages may best be understood from the following detailed description of the preferred embodiments of the invention illustrated in the drawings, wherein:
  • FIG. 1 is a schematic side plan view not to scale illustrating example processing steps for implementing a deep trench enabled high current capable bipolar transistor for current switching and output driver applications in accordance with the preferred embodiment;
  • FIG. 2 is a schematic top plan view not to scale illustrating example processing steps for implementing the deep trench enabled high current capable bipolar transistor for current switching and output driver applications in accordance with the preferred embodiment;
  • FIG. 3 is a schematic side plan view not to scale illustrating example processing steps for implementing a deep trench enabled high current capable bipolar transistor for current switching and output driver applications in accordance with the preferred embodiment;
  • FIG. 4 is a schematic top plan view not to scale illustrating example processing steps for implementing the deep trench enabled high current capable bipolar transistor for current switching and output driver applications in accordance with the preferred embodiment;
  • FIG. 5 is a schematic side plan view not to scale illustrating the deep trench enabled high current capable bipolar transistor for current switching and output driver applications with a final device schematic overlay in accordance with the preferred embodiment; and
  • FIG. 6 is a flow chart illustrating exemplary processing steps for fabricating a deep trench enabled high current capable bipolar transistor for current switching and output driver applications in accordance with the preferred embodiment.
    •  DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings, which illustrate example embodiments by which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the invention.
  • The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
  • In accordance with features of the invention, a method and structures are provided for implementing deep trench enabled high current capable NPN or PNP bipolar transistor for current switching and output driver applications.
  • Referring now to FIG. 1, there is schematically shown example processing steps generally designated by the reference character 100 for implementing a deep trench enabled high current capable bipolar transistor for current switching and output driver applications in accordance with the preferred embodiment. The deep trench enabled high current capable bipolar transistor is current density optimized rather than being beta or gain optimized.
  • In FIG. 1, in first processing steps 100, a semiconductor substrate 102 formed of a suitable material such as a silicon substrate 102 includes suitable doping, such as P-doped substrate 102 provided for fabricating a deep trench enabled high current capable NPN bipolar transistor. Alternatively, a substrate that is N-doped is provided for the substrate 102 for fabricating a deep trench enabled high current capable PNP bipolar transistor.
  • As shown in FIG. 1, an oxygen implant or O2 implant 104 through an O2 blocking layer or photo-resist 106 providing a deep oxygen implant 108 in a selected region of substrate 102 at a desired depth. A high O2 implant dose is assumed thereby creating a definitive SiO2 layer 108, for example, as deep as possible, such as ˜2-5 μm, with considerations including silicon damage, implant dose, and the like.
  • FIG. 2 illustrates example processing steps generally designated by the reference character 200 for implementing the deep trench enabled high current capable bipolar transistor for current switching and output driver applications in accordance with the preferred embodiment. The processing steps 200 include patterning and etching steps 202 providing a first deep trench 204 and a second deep trench 206 formed above the deep oxygen implant 108 in FIG. 1. The implanted silicon dioxide layer 108 provides an etch stop for the deep trench etches 204, 206. The first deep trench 204 is a generally large, for example, on the order of 1.0 μm on a side, rectangular box deep trench of minimum width. The second deep trench 206 is a second small area deep trench centered within the first rectangular box deep trench 204. One can visualize this structure of trenches 204, 206 as a large picture frame surrounding a dot in the center of the framed image.
  • Referring now to FIG. 3, there are shown example next processing steps generally designated by the reference character 300 for implementing a deep trench enabled high current capable bipolar transistor for current switching and output driver applications in accordance with the preferred embodiment. N+ ion implant and anneal steps 302 for fabricating a deep trench enabled high current capable NPN bipolar transistor include ion implantation at relatively high ion pressure that is utilized to incorporate N+ dopants on the exposed surfaces of each of the first deep trench and second deep trench through a patterned implant blocking layer or photo-resist 304. Subsequent annealing renders highly doped N+ regions 306 both inside and outside the first deep trench 204 and around the outside the second deep trench region 206. Alternatively for PNP bipolar transistor, P+ ion implant and anneal steps 302 form highly doped P+ regions 306 both inside and outside the first deep trench 204 and around the outside the second deep trench region 206 for fabricating a deep trench enabled high current capable PNP bipolar transistor.
  • These N+ regions 306 or P+ regions 306 provide the collector and emitter respectively, and the existing substrate region provides the base region between the collector and emitter regions, as illustrated in FIGS. 4 and 5. For example, assuming a fairly wide base region, with a beta of around 20, current densities around 100 mA per μm2 of collector are enabled. With 0.9 μm on each of the 3 sides of the collector at the collector-base interface and a collector/emitter depth of 3 μm one has 2.7 μm*3 μm of collector surface or 8.1 μm2, or conservatively 800 mA of current sourcing capability.
  • In accordance with features of the invention, the deep trench enabled high current capable bipolar transistor of the invention provides improvements over conventional FETs for high current applications. A FET on the order of 1 mm of device width is required to source 800 mA of current. Drawing gates on a contacted pitch the planar FET would requires hundreds of square microns of surface to support that potential 800 mA power gated circuit load.
  • Referring now to FIG. 4, there are shown example next processing steps generally designated by the reference character 400 for implementing the deep trench enabled high current capable bipolar transistor for current switching and output driver applications in accordance with the preferred embodiment. Processing steps 402 include filling trenches 204, 206 with polysilicon or other suitable conductive fill 404, performing high concentration implants for low-resistance (low-R) contacts, and making a base contact 410, a collector contact 412, and an emitter contact 414. For example, desired concentrations include ˜1e21/cm3 for the emitter, 1e173 base and 1e15/cm3 for the collector to base junction, 1e19/cm3 for the collector contact region.
  • FIG. 5 illustrates a final device schematic overlay for the example deep trench enabled high current capable bipolar transistor generally designated by the reference character 500 for current switching and output driver applications in accordance with the preferred embodiment. The collector contact 412, and the emitter contact 414 are shown with respective N+ regions 306 and conductive fill 404 and the base contact 410 is provided by the substrate P region between the collector and emitter N+ regions 306.
  • Referring now to FIG. 6, a flowchart illustrates exemplary processing steps generally designated by the reference character 600 for fabricating a deep trench enabled high current capable bipolar transistor for current switching and output driver applications in accordance with the preferred embodiment.
  • As indicated in a block 602, a base substrate is provided with p-doping for fabricating a deep trench NPN bipolar transistor for current switching and output driver applications. Alternatively, the base substrate is provided with n-doping for fabricating a deep trench PNP bipolar transistor for current switching and output driver applications at block 602. As indicated in a block 604, a deep oxygen implant is performed in a selected region of substrate, creating a definitive SiO2 layer 108. Patterning and etching define a first deep trench 204 and a second deep trench 206 that are formed above the deep oxygen implant 108 with the first deep trench being a generally large rectangular box deep trench of minimum width and the second deep trench being a second small area deep trench centered within the first rectangular box deep trench as indicated in a block 606.
  • Next as indicated in a block 608, an ion implant at relatively high ion pressure is utilized to incorporate N+ dopants or P+ dopants on the exposed surfaces of each of the first deep trench and second deep trench and subsequent annealing renders highly doped N+ regions or highly doped P+ regions both inside and outside the outside the first deep trench 204 and around the outside the second deep trench region 206. The N+ regions or P+ regions formed at block 608, provide the collector and emitter respectively, and the existing substrate region provides the base region between the collector and emitter regions.
  • As indicated in a block 610, the trenches 204, 206 are filled with polysilicon or other conductive fill, high concentration implants are provided for low resistance contacts, with a P+ implantation to allow a low resistance base contact for the NPN bipolar transistor or an N+ implantation to allow a low resistance base contact for the PNP bipolar transistor, and a base contact 410, a collector contact 412, and an emitter contact 414 are formed.
  • While the present invention has been described with reference to the details of the embodiments of the invention shown in the drawing, these details are not intended to limit the scope of the invention as claimed in the appended claims.

Claims (20)

What is claimed is:
1. A method for implementing a deep trench enabled high current capable bipolar transistor comprising:
providing a deep oxygen implant in a selected region of a substrate;
forming a first deep trench and a second deep trench above the deep oxygen implant; said first deep trench being a generally large rectangular box deep trench of minimum width and said second deep trench being a second small area deep trench centered within the first rectangular box deep trench;
providing highly doped regions both inside and outside of the first deep trench and around an outside of the second deep trench;
providing a collector and an emitter respectively with said highly doped regions, and provides a base region with a substrate region between said collector and said emitter regions.
2. The method as recited in claim 1 wherein providing a deep oxygen implant in a selected region of a substrate includes providing a blocking photo-resist layer and providing said deep oxygen implant.
3. The method as recited in claim 2 includes creating a SiO2 layer at a depth in a range of approximately 2-5 micrometers (μm).
4. The method as recited in claim 1 wherein providing a deep oxygen implant includes creating an etch stop for said first deep trench and said second deep trench.
5. The method as recited in claim 1 includes creating a current density optimized bipolar transistor, and selectively providing current sourcing capability for the deep trench enabled high current capable bipolar transistor.
6. The method as recited in claim 1 includes providing a P-doped substrate and providing highly doped N+ regions for creating an NPN current density optimized bipolar transistor.
7. The method as recited in claim 6 includes selectively providing a base region width providing a collector-base interface area and selectively providing a deep trench depth providing a collector-emitter depth for a predefined collector current sourcing capability.
8. The method as recited in claim 1 includes providing a N-doped substrate and providing highly doped P+ regions for creating an PNP current density optimized bipolar transistor.
9. The method as recited in claim 8 includes selectively providing a base region width providing a collector-base interface area and selectively providing a deep trench depth providing a collector-emitter depth for a predefined collector current sourcing capability.
10. The method as recited in claim 1 wherein providing said highly doped regions includes patterning a blocking photo-resist layer and providing an ion implantation at relatively high ion pressure to incorporate dopants on exposed surfaces of the first deep trench and the second deep trench.
11. The method as recited in claim 10 includes annealing the dopants to render highly doped regions both inside and outside the outside the first deep trench and around the outside the second deep trench.
12. The method as recited in claim 11 further includes filling the first deep trench and the second deep trench with a selected conductive fill.
13. The method as recited in claim 13 includes forming a base contact, a collector contact, and an emitter contact.
14. The method as recited in claim 13 includes performing high concentration implants for providing low resistance contacts.
15. A structure for implementing a deep trench enabled high current capable bipolar transistor comprising:
a deep oxygen implant in a selected region of a substrate;
a first deep trench and a second deep trench above the deep oxygen implant; said first deep trench being a generally large rectangular box deep trench of minimum width and said second deep trench being a second small area deep trench centered within the first rectangular box deep trench;
highly doped regions both inside and outside of said first deep trench and around an outside of said second deep trench and said first deep trench and said second deep trench including a selected conductive fill respectively defining a collector region and an emitter region, and a base region defined by a substrate region between said collector and said emitter regions.
16. The structure as recited in claim 15 wherein said deep oxygen implant includes a SiO2 layer at a depth in a range of approximately 2-5 micrometers (μm); and wherein said collector region and said emitter region include a depth in a range of approximately 2-5 micrometers (μm).
17. The structure as recited in claim 15 includes a base contact, a collector contact, and an emitter contact, each contact including a respective high concentration implant for providing low resistance contacts.
18. The structure as recited in claim 15 wherein the deep trench enabled high current capable bipolar transistor includes a current density optimized bipolar transistor, including a selected collector-base interface area and a selected collector/emitter depth to provide a predefined collector current sourcing capability.
19. The structure as recited in claim 15 wherein said substrate includes a P-doped substrate and said highly doped regions include highly doped N+ regions for creating an NPN current density optimized bipolar transistor.
20. The structure as recited in claim 15 wherein said substrate includes a N-doped substrate and said highly doped regions include highly doped P+ regions for creating a PNP current density optimized bipolar transistor.
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