US20140183747A1 - Multi-die, high current wafer level package - Google Patents
Multi-die, high current wafer level package Download PDFInfo
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- US20140183747A1 US20140183747A1 US13/732,664 US201313732664A US2014183747A1 US 20140183747 A1 US20140183747 A1 US 20140183747A1 US 201313732664 A US201313732664 A US 201313732664A US 2014183747 A1 US2014183747 A1 US 2014183747A1
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- integrated circuit
- circuit chip
- pillar
- wafer
- level package
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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Definitions
- Flat no-lead packaging technologies such as quad-flat no-leads (QFN) packaging technologies, physically and electrically connect integrated circuit chips to printed circuit boards.
- Flat no-lead packaging technologies typically employ a lead-frame that includes an integrated circuit chip (die) mounted thereon. The die may be electrically interconnected with the lead-frame through wire-bonding technology or flip-chip technology. An encapsulation structure is then formed over the lead-frame to encapsulate the integrated circuit chip.
- the wafer-level package devices include an integrated circuit chip (e.g., die) having at least one pillar (e.g., a copper pillar) formed over the integrated circuit chip.
- the pillar is configured to provide electrical interconnectivity to the integrated circuit chip.
- An encapsulation structure configured to support the pillar is formed over the surface of the integrated circuit chip.
- an integrated circuit chip device e.g., flip-chip die
- the integrated circuit chip device is at least partially encapsulated by the encapsulation structure.
- one or more solder contacts are formed upon a top surface (e.g., exposed end) of the copper pillar for serving as a connection between the wafer-level package device and corresponding pads of a printed circuit board, for facilitating connection between the device and the printed circuit board.
- the height of the integrated circuit chip device is less than the height of the pillar and/or less than the combined height of the pillar and the one or more solder contacts.
- FIG. 1 is a diagrammatic perspective elevation view illustrating a wafer-level package device in accordance with an example implementation of the present disclosure.
- FIG. 2 is a diagrammatic partial-cross-sectional end view of a section of a wafer-level package device shown in accordance with an exemplary implementation of the present disclosure.
- FIG. 3 is a top plan view of a portion of the wafer-level package device shown in FIG. 2 .
- FIG. 4 is a diagrammatic partial-cross-sectional end view of a section of the wafer-level package device shown in FIG. 1 .
- FIG. 5 is a top plan view of a portion of the wafer-level package device shown in FIG. 4 .
- FIG. 6 is a diagrammatic perspective elevation view illustrating a printed circuit board configured for being connected to the wafer-level package device shown in FIG. 1 .
- FIG. 7 is a longitudinal cross-sectional view depicting the printed circuit board shown in FIG. 6 being connected to the wafer-level package device shown in FIG. 1 .
- FIGS. 8A through 8J are diagrammatic partial cross-sectional views illustrating the fabrication of a wafer-level package device, such as shown in FIGS. 1 , 4 and 7 , in accordance with the process shown in FIGS. 9A and 9B .
- FIGS. 9A and 9B depict a flow diagram illustrating a process in an example implementation for fabricating wafer-level package devices, such as the wafer-level package devices shown in FIGS. 1 through 5 and FIG. 7 .
- QFN packaging technologies provide good mechanical protection to the integrated circuit chips (dies) contained within the device packages by fully encapsulating the integrated circuit chips within the package.
- flat no-lead (e.g., QFN) package devices are expensive to produce and typically provide relatively low pin counts (e.g., the pins of a QFN are typically located along the die edge).
- Wafer-level packaging is a chip-scale packaging technology that encompasses a variety of techniques whereby integrated circuit chips are packaged at wafer level, prior to segmentation. Wafer-level packaging extends the wafer fabrication processes to include device interconnection and device protection processes. Consequently, wafer-level packaging streamlines the manufacturing process by allowing for the integration of wafer fabrication, packaging, testing, and burn-in processes at the wafer level. Compared to flat no-lead (QFN) packaging techniques, wafer-level packaging is generally less costly to implement since packaging occurs at wafer level, while flat no-lead packaging is performed at strip level. Moreover, the footprint of a comparable wafer-level packaged device is typically less than that of a QFN packaged device since wafer-level packages can be nearly equal to the size of the integrated circuit chip.
- QFN flat no-lead
- the wafer-level package devices may thus provide mechanical protection of the integrated circuit chips (dies) contained within the device packages that is similar to that provided by flat no-lead (QFN) devices, while maintaining the benefits inherent in wafer-level packaging (e.g., lower cost, smaller package size, high pin count, etc.).
- the wafer-level package devices include an integrated circuit chip (e.g., die) having pillars that provide electrical interconnectivity to the devices.
- the pillars may be copper pillars having a solder layer formed over the exposed end of the pillar.
- An encapsulation structure configured to support the pillar is formed over the surface of the integrated circuit chip at wafer level.
- the encapsulation structure may be fabricated from epoxy, or a like substance.
- an integrated circuit chip device may be mounted to the integrated circuit chip so that the integrated circuit chip device is in electrical communication with the integrated circuit chip.
- the integrated circuit chip device is at least partially encapsulated by the encapsulation structure. Once singulated from the wafer, the devices may be mounted to a printed circuit board, and the pillars provide electrical interconnectivity through the backside of the device that interface with the pads of the printed circuit board.
- FIGS. 1 through 5 illustrate wafer-level package devices 100 in accordance with example implementations of the present disclosure.
- each device 100 includes an integrated circuit chip 102 comprised of a semiconductor substrate 104 (e.g., wafer) having one or more integrated circuits 106 formed therein.
- the semiconductor substrate 104 is formed of silicon.
- the integrated circuit chip 102 includes all front-end-of-line (FEOL) and necessary interconnect circuitry.
- the integrated circuits 106 may comprise digital integrated circuits, analog integrated circuits, mixed signal integrated circuits, combinations thereof, and so forth.
- the integrated circuits 106 may be formed through suitable FEOL fabrication techniques.
- the device 100 further includes pillars 108 extending from (e.g. formed upon) a surface 111 of the semiconductor substrate 104 .
- the pillars 108 include multiple, stacked layers, such as a first (e.g., a bottom) pillar layer (P 1 ) and a second (e.g., a top) pillar layer formed (e.g., stacked) upon the first pillar layer (P 2 ) (as shown in FIG. 7 ).
- the pillars 108 are copper pillars.
- the pillars 108 may be formed of other metals (e.g., gold or tin) or metal alloys.
- the pillars 108 may be fabricated via suitable manufacturing processes, such as the lamination/deposition process described herein.
- photo-imageable liquid dielectric materials for small copper thickness values e.g., up to approximately 20 micrometers (20 um) or dry film for larger copper thickness values can be used to plate the copper.
- the pillars 108 may have an aspect ratio (ratio of the width of the pillar to the height of the pillar) ranging from one to one (1:1) to about twenty to one (20:1).
- the pillars 108 serve to provide electrical interconnections between the integrated circuit chip 102 and a printed circuit board 600 (shown in FIG. 6 ) that is configured to receive the device 100 . In embodiments, such as shown in FIGS.
- each pillar 108 can include a single solder contact 110 disposed upon an exposed end 112 (e.g., the end distal from the substrate 104 ) of the pillar 108 .
- the single solder contact 110 can cover most of (e.g., almost all) of the exposed end 112 of the pillar 108 .
- FIG. 1 illustrates an exemplary embodiment of a single solder contact 110 disposed upon an exposed end 112 (e.g., the end distal from the substrate 104 ) of the pillar 108 .
- the single solder contact 110 can cover most of (e.g., almost all) of the exposed end 112 of the pillar 108 .
- a solder mask opening 113 can be defined upon the exposed end 112 of the pillar 108 using a photo-imageable dielectric material (e.g., Polyimide (PI), Polybenzoxazole (PBO), Benzocyclobuten (BCB)) to form a pad (e.g., solder pad) for the individual solder area, such that the single solder contact 110 may be disposed through the solder mask opening 113 .
- PI Polyimide
- PBO Polybenzoxazole
- BCB Benzocyclobuten
- each pillar 108 can include multiple solder contacts 110 disposed upon an exposed end 112 of the pillar 108 .
- the multiple solder contacts 110 may be disposed through multiple solder mask openings 113 (e.g., which form multiple solder areas), as shown in FIG. 5 .
- one or more solder contacts (e.g., solder bumps) 110 can be formed on the pillar 108 which can have a substantially greater height compared to the solder contacts 110 shown in FIG. 2 . This increased height can promote improved solder joint fatigue life.
- the pads (e.g., solder pads, solder areas) formed by the solder mask openings 113 may be rectangular (for maximizing the use of the surface area of the pillars), with rounded corners (for minimizing stress).
- the solder contacts 110 serve as a connection between the device 100 (e.g., the pillars 108 ) and corresponding pads (e.g., formed by solder mask openings 606 ) disposed over the printed circuit board 600 (shown in FIG. 6 ).
- the solder contacts 110 may be fabricated of a lead-free solder composition such as a Tin-Silver-Copper (Sn—Ag—Cu) alloy solder (i.e., SAC), a Tin-Silver (Sn—Ag) alloy solder, a Tin-Copper (Sn—Cu) allow solder, and so on.
- a Tin-Silver-Copper alloy solder i.e., SAC
- Sn—Ag Tin-Silver
- Sn—Cu Tin-Copper
- the device 100 may be optimized for users wanting a QFN-style package or a land grid array (LGA)-style package. In other embodiments, such as shown in FIGS. 4 and 5 , the device 100 may be optimized for users wanting a wafer-level packaging (WLP)-style package.
- WLP wafer-level packaging
- the device 100 may include an integrated circuit chip device 114 disposed over and connected to (e.g., mounted to) the surface 111 of the integrated circuit chip 102 (e.g., wafer).
- the integrated circuit chip device 114 may be in electrical communication with the integrated circuits 106 of the integrated circuit chip 102 .
- integrated circuit chip device 114 includes solder bumps 116 that allow the device 114 to be in electrical contact with the device 100 .
- the solder bumps 116 may, for example, be positioned over (e.g., connected to, disposed upon) a redistribution structure, such as a redistribution layer (RDL) 118 , of the wafer-level chip-scale device 100 to allow electrical communication between the integrated circuit chip device 114 and device 100 (e.g., the integrated circuits 106 , etc.).
- the RDL 118 may be formed from a conductive material, such as polysilicon, aluminum, copper, and so on.
- the integrated circuit chip device 114 extends additional functionality to device 100 by enabling system-in-a-package capabilities.
- integrated circuit chip device 114 may be a digital integrated circuit device, an analog integrated circuit device, a mixed-signal integrated circuit device, and so forth.
- the solder bumps 116 may be fabricated of a lead-free solder composition such as a Tin-Silver-Copper (Sn—Ag—Cu) alloy solder (i.e., SAC), a Tin-Silver (Sn—Ag) alloy solder, a Tin-Copper (Sn—Cu) alloy solder, and so on.
- a Tin-Silver-Copper (Sn—Ag—Cu) alloy solder i.e., SAC
- Tin-Silver (Sn—Ag) alloy solder Tin-Copper (Sn—Cu) alloy solder
- PbSn Tin-Lead solder compositions may be used.
- an underfill e.g., a capillary underfill
- the pillar 108 extends a first distance from the integrated circuit chip 102 (e.g., the distal end 112 of the pillar 108 is located a first distance (e.g., first height) above the surface 111 of the integrated circuit chip 102 ), while the integrated circuit chip device 114 has an end distal to the surface 111 , the distal end of the integrated circuit chip device 114 extending (e.g., being located) a second distance (e.g., second height) from (e.g., above) the surface 111 of the integrated circuit chip 102 .
- a second distance e.g., second height
- the solder contact(s) 110 are located at a third distance (e.g., third height) above the surface 111 of the integrated circuit chip 102 .
- the second distance/height may be less than the first distance/height and/or less than the third distance/height (e.g., the height of the integrated circuit chip device 114 is less than the height of the pillar 108 and/or less than the combined height of the pillar 108 and solder contact(s) 110 ).
- the pillars 108 are of an appropriate height to accommodate the integrated circuit chip device (e.g., flip-chip (FC) die) 114 and to carry high currents.
- FC flip-chip
- the device 100 also includes an encapsulation structure 120 disposed over the surface 111 of the integrated circuit chip 102 . As shown in FIGS. 2 and 4 , the encapsulation structure 120 at least substantially encapsulates the pillars 108 . Thus, the encapsulation structure 120 provides support and insulation to the pillars 108 (and the integrated circuit chip device 114 when the device 100 employs an integrated circuit chip device 114 ). The pillars 108 have a length that at least substantially extends to the depth of the encapsulation structure 120 . As shown in FIGS.
- the solder contacts 110 extend beyond a plane defined by the surface 122 of the encapsulation structure 120 to allow the solder contacts 110 to connect to the corresponding pads (e.g., formed by the solder mask openings 606 ) of the printed circuit board 600 (shown in FIG. 6 ).
- the encapsulation structure 120 may be a polymer material, such as epoxy, or the like, deposited over the surface 111 of the wafer-level chip-scale package device 100 .
- the device 100 may be configured for being connected to a printed circuit board 600 .
- the printed circuit board 600 includes a first trace (e.g., a first copper trace) 608 and a second trace (e.g., a second copper trace) 610 .
- the printed circuit board 600 includes: a first surface 612 , a second surface 614 being disposed opposite the first surface 612 , a first side 602 , the first side and a second side 604 , the second side 604 disposed opposite the first side 602 .
- FIG. 7 depicts device 100 being connected to printed circuit board 600 and further depicts the flow of electricity within device 100 . For example, as shown in FIG.
- electrical current is injected from the first copper trace 608 of the printed circuit board 600 into the solder contacts 110 of device 100 .
- the electrical current is then directed into the device 100 , via the solder contacts 110 , and flows within the device 100 in a direction which is away from a first side 115 of the device 100 and towards a second side 117 of the device 100 and is routed within the device 100 through vias 119 formed within the device 100 .
- the printed circuit board 600 may be aligned over the device 100 such that, the first copper trace 608 is oriented over pillars 108 which are proximal to the first side 115 of the device 100 , while the second copper trace 610 is oriented over pillars 108 which are proximal to the second side 117 of the device 100 .
- the size of the solder mask openings 113 of the device 100 and the size of the solder mask openings 606 of the printed circuit board 600 may be chosen such that a uniform solder height is provided across the whole device 100 (e.g., die) for avoiding any die tilt when connecting the die to (e.g., mounting the die upon) the printed circuit board 600 .
- FIGS. 9A and 9B illustrate an example process 900 that employs wafer-level packaging techniques to fabricate semiconductor devices having pillars, such as the devices 100 shown in FIGS. 1 through 5 and FIG. 7 .
- one or more pillars are initially formed over a semiconductor wafer.
- a lamination/deposition process may be employed to form the pillars.
- a blanket seed layer is deposited on the semiconductor wafer 300 (Block 901 ).
- the blanket seed layer may be doped silicon or the like.
- a first photoresist layer is formed over (e.g., formed upon) a semiconductor wafer (e.g., the seed layer of the semiconductor wafer (Block 902 ) prior to segmentation of the wafer into individual circuit chips (die).
- FIG. 8A illustrates a portion of the wafer 300 , which, when processed through suitable FEOL fabrication techniques, includes a semiconductor substrate 302 that comprises an integrated circuit chip 304 .
- the integrated circuit chip 304 includes one or more integrated circuits 306 formed therein.
- the substrate 302 may include a redistribution structure, such as a redistribution layer (RDL) 308 , formed over the surface 310 of the substrate 302 .
- RDL redistribution layer
- a dielectric layer 312 may also be formed over the surface 310 of the substrate 302 .
- the dielectric layer 312 may be benzocyclobutene polymer (BCB), silicon dioxide (SiO 2 ), or the like.
- the lamination step includes applying a first photoresist layer 314 over the wafer 300 (e.g., over the RDL 308 and the dielectric layer 312 ).
- the first photoresist layer 314 may be a composition of photopolymer and polyester film that may be patterned and etched through one or more suitable dry film lamination processes.
- the first photoresist layer 314 is then patterned and etched to form an etched area (Block 904 ).
- FIG. 8B illustrates the first photoresist layer 314 which is shown patterned and etched to form etched area 316 .
- the etched area 316 extends at least through the photoresist layer 314 to pads of the RDL layer 308 .
- FIG. 8C illustrates the conductive material 318 deposited in the etched area 316 to form a first layer (P 1 ) of the pillar 324 .
- a suitable electroplating process may be utilized to deposit a conductive material 318 in the etched area 316 of the first photoresist layer 314 .
- the conductive material 318 may comprise copper, aluminum, or a like conducting metal, or other conducting material.
- FIG. 8D illustrates removal of the photoresist layer 314 through suitable stripping processes.
- a second photoresist layer is formed over the semiconductor wafer (e.g., and over the first layer (P 1 ) of the pillar 324 ) (Block 909 ).
- FIG. 8E shows the second photoresist layer 315 placed over the wafer 300 .
- the second photoresist layer 315 is then patterned and etched to form an etched area (Block 910 ).
- FIG. 8F illustrates the second photoresist layer 315 which is shown patterned and etched to form etched area 317 .
- the etched area 317 extends to the first layer (P 1 ) of the pillar 324 .
- Conductive material 318 is then deposited in the etched area 317 to form the pillar(s) (e.g., the second layer (P 2 ) of the pillar 324 ) (Block 911 ).
- FIG. 8G illustrates the conductive material 318 deposited in the etched area 317 to form the second (e.g., upper) layer (P 2 ) on top of the first layer (P 1 ) of the pillar 324 .
- a suitable electroplating process may be utilized to deposit conductive material (e.g., copper) 318 in the etched area 317 of the second photoresist layer 315 .
- conductive material e.g., copper
- the second photoresist layer 315 is removed (Block 912 ).
- FIG. 8H illustrates removal of the second photoresist layer 315 through suitable stripping processes.
- the blanket seed layer is etched (Block 913 ).
- the pillar(s) 324 may be subjected to a suitable seed etch process.
- an integrated circuit chip device 114 as shown in FIGS.
- the integrated circuit chip device 114 may be connected to substrate 302 via a flip-chip process.
- An integrated circuit chip device 114 may extend system-in-a-package capabilities to the integrated circuit chip 304 .
- an encapsulation structure (e.g., dielectric compound) is formed over the wafer to at least substantially encapsulate the pillars.
- FIG. 8I illustrates the encapsulation structure 326 formed over the surface 310 of the wafer 300 to provide support and insulation to the integrated circuits 306 and the pillar(s) 324 .
- multiple polymer layers e.g., epoxy, etc.
- a top surface of the encapsulation structure 326 may be formed at or extend beyond a top surface of an exposed end 332 of the pillar 324 .
- an epoxy material may also be deposited on the backside (e.g., over the surface 329 ) of the wafer 300 .
- the encapsulation structure 326 may be subjected to a grinding process to expose pillars 324 (e.g., expose the end 332 of the pillar 324 distal from the substrate 302 ) (Block 917 ).
- the encapsulation structure 326 and the exposed end 332 of the pillar 324 may be subjected to a face grinding process for surface planarization.
- the encapsulation structure 326 extends at least substantially the length (e.g., depth) of the pillars 324 .
- an underfill e.g., a capillary underfill
- the encapsulation structure (e.g., overmold) 326 may be chosen to provide a reliable package solution (e.g., mechanical and environmental protection) without creating processing issues, especially with excessive wafer warpage.
- solder contacts 328 may be formed upon (e.g., applied to) the exposed end 332 of the pillar 324 (e.g., the end of the pillar 324 distal to the wafer 300 ). In embodiments, formation of the solder contacts 328 upon the pillars 324 may be done using solder ball drop, solder plating, or solder printing. Once the step of forming the solder contacts 328 upon the pillars 324 is complete, suitable processes may be employed to segment the individual integrated circuit chips 304 into individual packages.
- the step of applying the solder contacts to the pillar can be performed before the step of applying the encapsulation structure (Block 916 ).
- the step of connecting the integrated circuit chip device to the substrate can be performed either before or after the solder contacts are applied to the pillar(s) (Block 918 ), but prior to application of the encapsulation structure (Block 916 ).
- a packaging structure containing multiple die, which is configured for carrying high current is described herein.
- a low cost, high-reliability method for chip-to-wafer (e.g., wafer level) packaging of two or more die e.g., a method for fabricating the packaging structure containing multiple die
- the device 100 described herein promotes improved reliability performance (e.g., board-level reliability) due to higher solder standoff and/or higher printed circuit board standoff.
- the device 100 described herein by using a smaller amount of copper than some currently implemented devices, may promote improved reliability performance, reduced warpage typically caused by thermal mismatch between thick copper and the silicon die and reduction in required copper plating tool capacity to support a given wafer volume. Further, the device 100 described herein promotes improved manufacturability (e.g., with reduced plating time and reduced wafer warpage) and lower capital expense. Further, the method described herein allows a designer to: a.) design a power-field-effect transistor (power FET) in a fabrication (FAB) technology optimized for power; and b.) to design a separate, smaller controller die. The two die may then be combined into a low cost wafer-level package capable of carrying the high currents of the power-FET.
- power FET power-field-effect transistor
Abstract
Description
- Flat no-lead packaging technologies, such as quad-flat no-leads (QFN) packaging technologies, physically and electrically connect integrated circuit chips to printed circuit boards. Flat no-lead packaging technologies typically employ a lead-frame that includes an integrated circuit chip (die) mounted thereon. The die may be electrically interconnected with the lead-frame through wire-bonding technology or flip-chip technology. An encapsulation structure is then formed over the lead-frame to encapsulate the integrated circuit chip.
- Techniques are described for fabricating wafer-level package semiconductor devices for high-current applications. In one or more implementations, the wafer-level package devices include an integrated circuit chip (e.g., die) having at least one pillar (e.g., a copper pillar) formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity to the integrated circuit chip. An encapsulation structure configured to support the pillar is formed over the surface of the integrated circuit chip. In one or more implementations, an integrated circuit chip device (e.g., flip-chip die) may be mounted to the integrated circuit chip so that the integrated circuit chip device is in electrical communication with the integrated circuit chip. The integrated circuit chip device is at least partially encapsulated by the encapsulation structure. Further, one or more solder contacts are formed upon a top surface (e.g., exposed end) of the copper pillar for serving as a connection between the wafer-level package device and corresponding pads of a printed circuit board, for facilitating connection between the device and the printed circuit board. In the wafer-level package device, the height of the integrated circuit chip device is less than the height of the pillar and/or less than the combined height of the pillar and the one or more solder contacts.
- This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
- The detailed description is described with reference to the accompanying figures. The use of the same reference numbers in different instances in the description and the figures may indicate similar or identical items.
-
FIG. 1 is a diagrammatic perspective elevation view illustrating a wafer-level package device in accordance with an example implementation of the present disclosure. -
FIG. 2 is a diagrammatic partial-cross-sectional end view of a section of a wafer-level package device shown in accordance with an exemplary implementation of the present disclosure. -
FIG. 3 is a top plan view of a portion of the wafer-level package device shown inFIG. 2 . -
FIG. 4 is a diagrammatic partial-cross-sectional end view of a section of the wafer-level package device shown inFIG. 1 . -
FIG. 5 is a top plan view of a portion of the wafer-level package device shown inFIG. 4 . -
FIG. 6 is a diagrammatic perspective elevation view illustrating a printed circuit board configured for being connected to the wafer-level package device shown inFIG. 1 . -
FIG. 7 is a longitudinal cross-sectional view depicting the printed circuit board shown inFIG. 6 being connected to the wafer-level package device shown inFIG. 1 . -
FIGS. 8A through 8J are diagrammatic partial cross-sectional views illustrating the fabrication of a wafer-level package device, such as shown inFIGS. 1 , 4 and 7, in accordance with the process shown inFIGS. 9A and 9B . -
FIGS. 9A and 9B depict a flow diagram illustrating a process in an example implementation for fabricating wafer-level package devices, such as the wafer-level package devices shown inFIGS. 1 through 5 andFIG. 7 . - Devices that employ flat no-lead packaging technologies, such as QFN packaging technologies, provide good mechanical protection to the integrated circuit chips (dies) contained within the device packages by fully encapsulating the integrated circuit chips within the package. However, flat no-lead (e.g., QFN) package devices are expensive to produce and typically provide relatively low pin counts (e.g., the pins of a QFN are typically located along the die edge).
- Wafer-level packaging is a chip-scale packaging technology that encompasses a variety of techniques whereby integrated circuit chips are packaged at wafer level, prior to segmentation. Wafer-level packaging extends the wafer fabrication processes to include device interconnection and device protection processes. Consequently, wafer-level packaging streamlines the manufacturing process by allowing for the integration of wafer fabrication, packaging, testing, and burn-in processes at the wafer level. Compared to flat no-lead (QFN) packaging techniques, wafer-level packaging is generally less costly to implement since packaging occurs at wafer level, while flat no-lead packaging is performed at strip level. Moreover, the footprint of a comparable wafer-level packaged device is typically less than that of a QFN packaged device since wafer-level packages can be nearly equal to the size of the integrated circuit chip.
- Accordingly, techniques are described that employ wafer-level packaging techniques to fabricate semiconductor devices that have form factors similar to those of devices that employ flat no-lead (QFN) packaging technologies. The wafer-level package devices may thus provide mechanical protection of the integrated circuit chips (dies) contained within the device packages that is similar to that provided by flat no-lead (QFN) devices, while maintaining the benefits inherent in wafer-level packaging (e.g., lower cost, smaller package size, high pin count, etc.). The wafer-level package devices include an integrated circuit chip (e.g., die) having pillars that provide electrical interconnectivity to the devices. In specific implementations, the pillars may be copper pillars having a solder layer formed over the exposed end of the pillar. An encapsulation structure configured to support the pillar is formed over the surface of the integrated circuit chip at wafer level. In embodiments, the encapsulation structure may be fabricated from epoxy, or a like substance. In one or more implementations, an integrated circuit chip device may be mounted to the integrated circuit chip so that the integrated circuit chip device is in electrical communication with the integrated circuit chip. The integrated circuit chip device is at least partially encapsulated by the encapsulation structure. Once singulated from the wafer, the devices may be mounted to a printed circuit board, and the pillars provide electrical interconnectivity through the backside of the device that interface with the pads of the printed circuit board.
-
FIGS. 1 through 5 illustrate wafer-level package devices 100 in accordance with example implementations of the present disclosure. As shown, eachdevice 100 includes anintegrated circuit chip 102 comprised of a semiconductor substrate 104 (e.g., wafer) having one or more integratedcircuits 106 formed therein. In embodiments, thesemiconductor substrate 104 is formed of silicon. Further, theintegrated circuit chip 102 includes all front-end-of-line (FEOL) and necessary interconnect circuitry. In various implementations, theintegrated circuits 106 may comprise digital integrated circuits, analog integrated circuits, mixed signal integrated circuits, combinations thereof, and so forth. The integratedcircuits 106 may be formed through suitable FEOL fabrication techniques. - The
device 100 further includespillars 108 extending from (e.g. formed upon) asurface 111 of thesemiconductor substrate 104. In embodiments, thepillars 108 include multiple, stacked layers, such as a first (e.g., a bottom) pillar layer (P1) and a second (e.g., a top) pillar layer formed (e.g., stacked) upon the first pillar layer (P2) (as shown inFIG. 7 ). In an implementation, thepillars 108 are copper pillars. In other embodiments, thepillars 108 may be formed of other metals (e.g., gold or tin) or metal alloys. Thepillars 108 may be fabricated via suitable manufacturing processes, such as the lamination/deposition process described herein. In embodiments, photo-imageable liquid dielectric materials for small copper thickness values (e.g., up to approximately 20 micrometers (20 um) or dry film for larger copper thickness values can be used to plate the copper. Thepillars 108 may have an aspect ratio (ratio of the width of the pillar to the height of the pillar) ranging from one to one (1:1) to about twenty to one (20:1). Thepillars 108 serve to provide electrical interconnections between the integratedcircuit chip 102 and a printed circuit board 600 (shown inFIG. 6 ) that is configured to receive thedevice 100. In embodiments, such as shown inFIGS. 2 and 3 , eachpillar 108 can include asingle solder contact 110 disposed upon an exposed end 112 (e.g., the end distal from the substrate 104) of thepillar 108. In embodiments, thesingle solder contact 110 can cover most of (e.g., almost all) of the exposedend 112 of thepillar 108. In alternative embodiments, such as shown inFIG. 3 , asolder mask opening 113 can be defined upon theexposed end 112 of thepillar 108 using a photo-imageable dielectric material (e.g., Polyimide (PI), Polybenzoxazole (PBO), Benzocyclobuten (BCB)) to form a pad (e.g., solder pad) for the individual solder area, such that thesingle solder contact 110 may be disposed through thesolder mask opening 113. In further embodiments, such as shown inFIGS. 4 and 5 , eachpillar 108 can includemultiple solder contacts 110 disposed upon anexposed end 112 of thepillar 108. Themultiple solder contacts 110 may be disposed through multiple solder mask openings 113 (e.g., which form multiple solder areas), as shown inFIG. 5 . In embodiments, by restricting the solderable area on the pillar surface, one or more solder contacts (e.g., solder bumps) 110 can be formed on thepillar 108 which can have a substantially greater height compared to thesolder contacts 110 shown inFIG. 2 . This increased height can promote improved solder joint fatigue life. In an embodiment, the pads (e.g., solder pads, solder areas) formed by thesolder mask openings 113 may be rectangular (for maximizing the use of the surface area of the pillars), with rounded corners (for minimizing stress). In embodiments, thesolder contacts 110 serve as a connection between the device 100 (e.g., the pillars 108) and corresponding pads (e.g., formed by solder mask openings 606) disposed over the printed circuit board 600 (shown inFIG. 6 ). In implementations, thesolder contacts 110 may be fabricated of a lead-free solder composition such as a Tin-Silver-Copper (Sn—Ag—Cu) alloy solder (i.e., SAC), a Tin-Silver (Sn—Ag) alloy solder, a Tin-Copper (Sn—Cu) allow solder, and so on. In embodiments, such as shown inFIGS. 2 and 3 , thedevice 100 may be optimized for users wanting a QFN-style package or a land grid array (LGA)-style package. In other embodiments, such as shown inFIGS. 4 and 5 , thedevice 100 may be optimized for users wanting a wafer-level packaging (WLP)-style package. - In some implementations, the
device 100 may include an integratedcircuit chip device 114 disposed over and connected to (e.g., mounted to) thesurface 111 of the integrated circuit chip 102 (e.g., wafer). In embodiments, the integratedcircuit chip device 114 may be in electrical communication with theintegrated circuits 106 of theintegrated circuit chip 102. For instance, as shown inFIGS. 2 and 4 , integratedcircuit chip device 114 includes solder bumps 116 that allow thedevice 114 to be in electrical contact with thedevice 100. The solder bumps 116 may, for example, be positioned over (e.g., connected to, disposed upon) a redistribution structure, such as a redistribution layer (RDL) 118, of the wafer-level chip-scale device 100 to allow electrical communication between the integratedcircuit chip device 114 and device 100 (e.g., theintegrated circuits 106, etc.). TheRDL 118 may be formed from a conductive material, such as polysilicon, aluminum, copper, and so on. Thus, the integratedcircuit chip device 114 extends additional functionality todevice 100 by enabling system-in-a-package capabilities. In implementations, integratedcircuit chip device 114 may be a digital integrated circuit device, an analog integrated circuit device, a mixed-signal integrated circuit device, and so forth. As with thesolder contacts 110 described above, the solder bumps 116 may be fabricated of a lead-free solder composition such as a Tin-Silver-Copper (Sn—Ag—Cu) alloy solder (i.e., SAC), a Tin-Silver (Sn—Ag) alloy solder, a Tin-Copper (Sn—Cu) alloy solder, and so on. However, it is contemplated that Tin-Lead (PbSn) solder compositions may be used. In embodiments, an underfill (e.g., a capillary underfill) can be applied to integratedcircuit chip device 114. In embodiments, in theintegrated device 100, thepillar 108 extends a first distance from the integrated circuit chip 102 (e.g., thedistal end 112 of thepillar 108 is located a first distance (e.g., first height) above thesurface 111 of the integrated circuit chip 102), while the integratedcircuit chip device 114 has an end distal to thesurface 111, the distal end of the integratedcircuit chip device 114 extending (e.g., being located) a second distance (e.g., second height) from (e.g., above) thesurface 111 of theintegrated circuit chip 102. Further, the solder contact(s) 110 are located at a third distance (e.g., third height) above thesurface 111 of theintegrated circuit chip 102. In embodiments, the second distance/height may be less than the first distance/height and/or less than the third distance/height (e.g., the height of the integratedcircuit chip device 114 is less than the height of thepillar 108 and/or less than the combined height of thepillar 108 and solder contact(s) 110). Thus, thepillars 108 are of an appropriate height to accommodate the integrated circuit chip device (e.g., flip-chip (FC) die) 114 and to carry high currents. - The
device 100 also includes anencapsulation structure 120 disposed over thesurface 111 of theintegrated circuit chip 102. As shown inFIGS. 2 and 4 , theencapsulation structure 120 at least substantially encapsulates thepillars 108. Thus, theencapsulation structure 120 provides support and insulation to the pillars 108 (and the integratedcircuit chip device 114 when thedevice 100 employs an integrated circuit chip device 114). Thepillars 108 have a length that at least substantially extends to the depth of theencapsulation structure 120. As shown inFIGS. 2 and 4 , thesolder contacts 110 extend beyond a plane defined by thesurface 122 of theencapsulation structure 120 to allow thesolder contacts 110 to connect to the corresponding pads (e.g., formed by the solder mask openings 606) of the printed circuit board 600 (shown inFIG. 6 ). In an implementation, theencapsulation structure 120 may be a polymer material, such as epoxy, or the like, deposited over thesurface 111 of the wafer-level chip-scale package device 100. - Referring to
FIGS. 6 and 7 , in embodiments, thedevice 100 may be configured for being connected to a printedcircuit board 600. In embodiments, the printedcircuit board 600 includes a first trace (e.g., a first copper trace) 608 and a second trace (e.g., a second copper trace) 610. Further, the printedcircuit board 600 includes: afirst surface 612, asecond surface 614 being disposed opposite thefirst surface 612, afirst side 602, the first side and asecond side 604, thesecond side 604 disposed opposite thefirst side 602.FIG. 7 depictsdevice 100 being connected to printedcircuit board 600 and further depicts the flow of electricity withindevice 100. For example, as shown inFIG. 7 , electrical current is injected from thefirst copper trace 608 of the printedcircuit board 600 into thesolder contacts 110 ofdevice 100. The electrical current is then directed into thedevice 100, via thesolder contacts 110, and flows within thedevice 100 in a direction which is away from afirst side 115 of thedevice 100 and towards asecond side 117 of thedevice 100 and is routed within thedevice 100 throughvias 119 formed within thedevice 100. In embodiments, the printedcircuit board 600 may be aligned over thedevice 100 such that, thefirst copper trace 608 is oriented overpillars 108 which are proximal to thefirst side 115 of thedevice 100, while thesecond copper trace 610 is oriented overpillars 108 which are proximal to thesecond side 117 of thedevice 100. In embodiments, the size of thesolder mask openings 113 of thedevice 100 and the size of thesolder mask openings 606 of the printedcircuit board 600 may be chosen such that a uniform solder height is provided across the whole device 100 (e.g., die) for avoiding any die tilt when connecting the die to (e.g., mounting the die upon) the printedcircuit board 600. -
FIGS. 9A and 9B illustrate anexample process 900 that employs wafer-level packaging techniques to fabricate semiconductor devices having pillars, such as thedevices 100 shown inFIGS. 1 through 5 andFIG. 7 . In theprocess 900 illustrated, one or more pillars are initially formed over a semiconductor wafer. As described herein, a lamination/deposition process may be employed to form the pillars. Accordingly, a blanket seed layer is deposited on the semiconductor wafer 300 (Block 901). For example, the blanket seed layer may be doped silicon or the like. In embodiments, a first photoresist layer is formed over (e.g., formed upon) a semiconductor wafer (e.g., the seed layer of the semiconductor wafer (Block 902) prior to segmentation of the wafer into individual circuit chips (die).FIG. 8A illustrates a portion of thewafer 300, which, when processed through suitable FEOL fabrication techniques, includes asemiconductor substrate 302 that comprises anintegrated circuit chip 304. Theintegrated circuit chip 304 includes one or moreintegrated circuits 306 formed therein. Thesubstrate 302 may include a redistribution structure, such as a redistribution layer (RDL) 308, formed over thesurface 310 of thesubstrate 302. As shown, adielectric layer 312 may also be formed over thesurface 310 of thesubstrate 302. Thedielectric layer 312 may be benzocyclobutene polymer (BCB), silicon dioxide (SiO2), or the like. The lamination step includes applying afirst photoresist layer 314 over the wafer 300 (e.g., over theRDL 308 and the dielectric layer 312). Thefirst photoresist layer 314 may be a composition of photopolymer and polyester film that may be patterned and etched through one or more suitable dry film lamination processes. - The
first photoresist layer 314 is then patterned and etched to form an etched area (Block 904).FIG. 8B illustrates thefirst photoresist layer 314 which is shown patterned and etched to form etchedarea 316. The etchedarea 316 extends at least through thephotoresist layer 314 to pads of theRDL layer 308. - A conductive material is then deposited in the etched area to form the pillar(s) (Block 906).
FIG. 8C illustrates theconductive material 318 deposited in the etchedarea 316 to form a first layer (P1) of thepillar 324. In one or more implementations, a suitable electroplating process may be utilized to deposit aconductive material 318 in the etchedarea 316 of thefirst photoresist layer 314. Theconductive material 318 may comprise copper, aluminum, or a like conducting metal, or other conducting material. - Once the pillar (e.g., the first layer (P1) of the pillar 324) has been formed, the photoresist layer is removed (Block 908).
FIG. 8D illustrates removal of thephotoresist layer 314 through suitable stripping processes. In embodiments, a second photoresist layer is formed over the semiconductor wafer (e.g., and over the first layer (P1) of the pillar 324) (Block 909).FIG. 8E shows thesecond photoresist layer 315 placed over thewafer 300. In embodiments, thesecond photoresist layer 315 is then patterned and etched to form an etched area (Block 910).FIG. 8F illustrates thesecond photoresist layer 315 which is shown patterned and etched to form etchedarea 317. In embodiments, the etchedarea 317 extends to the first layer (P1) of thepillar 324.Conductive material 318 is then deposited in the etchedarea 317 to form the pillar(s) (e.g., the second layer (P2) of the pillar 324) (Block 911).FIG. 8G illustrates theconductive material 318 deposited in the etchedarea 317 to form the second (e.g., upper) layer (P2) on top of the first layer (P1) of thepillar 324. In one or more implementations, a suitable electroplating process may be utilized to deposit conductive material (e.g., copper) 318 in the etchedarea 317 of thesecond photoresist layer 315. In embodiments, once the pillar (e.g., the second layer (P2) of the pillar 324) has been formed, thesecond photoresist layer 315 is removed (Block 912).FIG. 8H illustrates removal of thesecond photoresist layer 315 through suitable stripping processes. In embodiments, the blanket seed layer is etched (Block 913). In addition, the pillar(s) 324 may be subjected to a suitable seed etch process. As described above, in embodiments, an integrated circuit chip device 114 (as shown inFIGS. 2 and 4 ) may be positioned over and connected to the substrate 302 (Block 914). For example, the integratedcircuit chip device 114 may be connected tosubstrate 302 via a flip-chip process. An integratedcircuit chip device 114 may extend system-in-a-package capabilities to theintegrated circuit chip 304. - Once the pillar(s) 324 are formed, an encapsulation structure (e.g., dielectric compound) is formed over the wafer to at least substantially encapsulate the pillars. (Block 916).
FIG. 8I illustrates theencapsulation structure 326 formed over thesurface 310 of thewafer 300 to provide support and insulation to theintegrated circuits 306 and the pillar(s) 324. In embodiments, multiple polymer layers (e.g., epoxy, etc.) may be deposited over thesurface 310 to form theencapsulation structure 326. In embodiments, a top surface of theencapsulation structure 326 may be formed at or extend beyond a top surface of anexposed end 332 of thepillar 324. It is contemplated that an epoxy material may also be deposited on the backside (e.g., over the surface 329) of thewafer 300. In embodiments where the top surface of theencapsulation structure 326 extends past/above theexposed end 332 of thepillar 324, theencapsulation structure 326 may be subjected to a grinding process to expose pillars 324 (e.g., expose theend 332 of thepillar 324 distal from the substrate 302) (Block 917). For example, theencapsulation structure 326 and theexposed end 332 of the pillar 324 (e.g., a top surface of layer (P2) of the pillar 324) may be subjected to a face grinding process for surface planarization. As shown, theencapsulation structure 326 extends at least substantially the length (e.g., depth) of thepillars 324. In embodiments, prior to application of the encapsulation structure (Block 916), as part of the flip-chip process step (Block 914), an underfill (e.g., a capillary underfill) can be applied to integratedcircuit chip device 114 for promoting reliability, especially for temperature cycling (Block 915). In alternative embodiments, rather than applying an underfill to the integratedcircuit chip device 114, the encapsulation structure (e.g., overmold) 326 may be chosen to provide a reliable package solution (e.g., mechanical and environmental protection) without creating processing issues, especially with excessive wafer warpage. - One or more solder contacts are then applied to the pillar. (Block 918). For example,
solder contacts 328 may be formed upon (e.g., applied to) the exposedend 332 of the pillar 324 (e.g., the end of thepillar 324 distal to the wafer 300). In embodiments, formation of thesolder contacts 328 upon thepillars 324 may be done using solder ball drop, solder plating, or solder printing. Once the step of forming thesolder contacts 328 upon thepillars 324 is complete, suitable processes may be employed to segment the individualintegrated circuit chips 304 into individual packages. - In other embodiments, the step of applying the solder contacts to the pillar (Block 918) can be performed before the step of applying the encapsulation structure (Block 916). In such embodiments, the step of connecting the integrated circuit chip device to the substrate (Block 914) can be performed either before or after the solder contacts are applied to the pillar(s) (Block 918), but prior to application of the encapsulation structure (Block 916).
- A packaging structure containing multiple die, which is configured for carrying high current is described herein. Further, a low cost, high-reliability method for chip-to-wafer (e.g., wafer level) packaging of two or more die (e.g., a method for fabricating the packaging structure containing multiple die) to provide a structure configured for use in high current applications is described herein. The
device 100 described herein promotes improved reliability performance (e.g., board-level reliability) due to higher solder standoff and/or higher printed circuit board standoff. Further, thedevice 100 described herein, by using a smaller amount of copper than some currently implemented devices, may promote improved reliability performance, reduced warpage typically caused by thermal mismatch between thick copper and the silicon die and reduction in required copper plating tool capacity to support a given wafer volume. Further, thedevice 100 described herein promotes improved manufacturability (e.g., with reduced plating time and reduced wafer warpage) and lower capital expense. Further, the method described herein allows a designer to: a.) design a power-field-effect transistor (power FET) in a fabrication (FAB) technology optimized for power; and b.) to design a separate, smaller controller die. The two die may then be combined into a low cost wafer-level package capable of carrying the high currents of the power-FET. - Although the subject matter has been described in language specific to structural features and/or process operations, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.
Claims (20)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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US13/732,664 US9087779B2 (en) | 2013-01-02 | 2013-01-02 | Multi-die, high current wafer level package |
CN201410001440.9A CN103915397B (en) | 2013-01-02 | 2014-01-02 | More bare crystallines, high current wafer-level packaging |
US14/803,612 US9230903B2 (en) | 2013-01-02 | 2015-07-20 | Multi-die, high current wafer level package |
Applications Claiming Priority (1)
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US13/732,664 US9087779B2 (en) | 2013-01-02 | 2013-01-02 | Multi-die, high current wafer level package |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20150303156A1 (en) * | 2014-04-17 | 2015-10-22 | Nxp B.V. | Single inline no-lead semiconductor package |
US9668340B1 (en) | 2016-04-26 | 2017-05-30 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Methods and devices for preventing overhangs in a finishing layer of metal formed on electrical contact surfaces when fabricating multi-layer printed circuit boards |
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US9087779B2 (en) | 2013-01-02 | 2015-07-21 | Maxim Integrated Products, Inc. | Multi-die, high current wafer level package |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060180936A1 (en) * | 2004-03-31 | 2006-08-17 | Endicott Interconnect Technologies, Inc. | Fluoropolymer dielectric composition for use in circuitized substrates and circuitized substrate including same |
US20080265434A1 (en) * | 2004-06-30 | 2008-10-30 | Nec Electronics Corporation | Semiconductor device having a sealing resin and method of manufacturing the same |
US20100320599A1 (en) * | 2007-08-01 | 2010-12-23 | Vincent Chan | Die stacking apparatus and method |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
SG99939A1 (en) * | 2000-08-11 | 2003-11-27 | Casio Computer Co Ltd | Semiconductor device |
US7335986B1 (en) * | 2005-09-14 | 2008-02-26 | Amkor Technology, Inc. | Wafer level chip scale package |
JP5179787B2 (en) * | 2007-06-22 | 2013-04-10 | ラピスセミコンダクタ株式会社 | Semiconductor device and manufacturing method thereof |
US8980694B2 (en) * | 2011-09-21 | 2015-03-17 | Powertech Technology, Inc. | Fabricating method of MPS-C2 package utilized form a flip-chip carrier |
US9087779B2 (en) | 2013-01-02 | 2015-07-21 | Maxim Integrated Products, Inc. | Multi-die, high current wafer level package |
-
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060180936A1 (en) * | 2004-03-31 | 2006-08-17 | Endicott Interconnect Technologies, Inc. | Fluoropolymer dielectric composition for use in circuitized substrates and circuitized substrate including same |
US20080265434A1 (en) * | 2004-06-30 | 2008-10-30 | Nec Electronics Corporation | Semiconductor device having a sealing resin and method of manufacturing the same |
US20100320599A1 (en) * | 2007-08-01 | 2010-12-23 | Vincent Chan | Die stacking apparatus and method |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20150303156A1 (en) * | 2014-04-17 | 2015-10-22 | Nxp B.V. | Single inline no-lead semiconductor package |
US9379071B2 (en) * | 2014-04-17 | 2016-06-28 | Nxp B.V. | Single inline no-lead semiconductor package |
US9668340B1 (en) | 2016-04-26 | 2017-05-30 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Methods and devices for preventing overhangs in a finishing layer of metal formed on electrical contact surfaces when fabricating multi-layer printed circuit boards |
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US20150325512A1 (en) | 2015-11-12 |
CN103915397B (en) | 2018-10-02 |
US9087779B2 (en) | 2015-07-21 |
US9230903B2 (en) | 2016-01-05 |
CN103915397A (en) | 2014-07-09 |
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