US20140070233A1 - Silicon carbide semiconductor device - Google Patents

Silicon carbide semiconductor device Download PDF

Info

Publication number
US20140070233A1
US20140070233A1 US13/958,073 US201313958073A US2014070233A1 US 20140070233 A1 US20140070233 A1 US 20140070233A1 US 201313958073 A US201313958073 A US 201313958073A US 2014070233 A1 US2014070233 A1 US 2014070233A1
Authority
US
United States
Prior art keywords
insulating film
trench
silicon carbide
semiconductor device
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US13/958,073
Inventor
Takeyoshi Masuda
Yu Saitoh
Hideki Hayashi
Toru Hiyoshi
Keiji Wada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to US13/958,073 priority Critical patent/US20140070233A1/en
Assigned to SUMITOMO ELECTRIC INDUSTRIES, LTD. reassignment SUMITOMO ELECTRIC INDUSTRIES, LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HAYASHI, HIDEKI, HIYOSHI, TORU, SAITOH, YU, MASUDA, TAKEYOSHI, WADA, KEIJI
Publication of US20140070233A1 publication Critical patent/US20140070233A1/en
Priority to US14/957,267 priority patent/US9679986B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/511Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/0445Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/048Making electrodes
    • H01L21/049Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608Silicon carbide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/511Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/512Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being parallel to the channel plane
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/517Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66053Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356Disposition, e.g. buried gate electrode
    • H01L29/4236Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode

Definitions

  • the present invention relates to a silicon carbide semiconductor device, in particular, a silicon carbide semiconductor device having a trench.
  • Japanese Patent Laying-Open No. 7-326755 discloses a trench gate type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) employing a silicon carbide substrate.
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • This patent publication describes that a gate thermal oxidation film has a thicker film thickness on a bottom surface of a trench than the film thickness thereof on a side surface of the trench, so that a threshold voltage becomes low and breakdown voltage between the gate and the drain becomes high.
  • the bottom surface of the trench corresponds to a carbon plane, which allows for fast oxidation rate, of hexagonal single-crystal silicon carbide, whereas the side surface of the trench corresponds to a plane perpendicular to this carbon plane and allowing for slow oxidation rate.
  • a thermal oxidation film can be formed such that the thickness of the thermal oxidation film on the side surface of the trench is greatly different from the thickness of the thermal oxidation film on the bottom surface of the trench.
  • the gate insulating film on the trench is entirely formed by the thermal oxidation on the trench of the silicon carbide substrate.
  • the silicon carbide substrate used here normally has a high crystallinity, so that a thin and flat gate insulating film can be formed. In this way, low threshold voltage can be attained.
  • carbon atoms which have existed in the silicon carbide, remains to an extent that cannot be disregarded. According to a study conducted by the present inventors, the carbon atoms remaining in the gate oxide film decrease dielectric breakdown resistance of the gate insulating film. Accordingly, it is considered that there is room for further improvement for the dielectric breakdown resistance in the above-described conventional technique. Namely, it is considered that there is room for further increasing the breakdown voltage of the silicon carbide semiconductor device.
  • the present invention has been made to solve the foregoing problem and has its object to provide a silicon carbide semiconductor device having a low threshold voltage and a large breakdown voltage.
  • a silicon carbide semiconductor device of the present invention includes: a silicon carbide substrate, a gate insulating film, and a gate electrode.
  • the silicon carbide substrate includes first to third layers.
  • the first layer has first conductivity type.
  • the second layer is provided on the first layer and has second conductivity type.
  • the third layer is provided on the second layer, is separated from the first layer by the second layer, and has the first conductivity type.
  • the silicon carbide substrate is provided with a trench.
  • the trench includes a side wall and a bottom portion, the side wall extending through the third layer and the second layer and reaching the first layer, the bottom portion being formed of the first layer.
  • the gate insulating film is provided on the trench.
  • the gate insulating film includes a trench insulating film and a bottom insulating film.
  • the trench insulating film covers each of the side wall and the bottom portion.
  • the bottom insulating film is provided on the bottom portion with the trench insulating film being interposed therebetween.
  • the bottom insulating film has a carbon atom concentration lower than that of the trench insulating film.
  • the gate electrode is provided in the trench. The gate electrode is in contact with a portion of the trench insulating film on the side wall.
  • the bottom insulating film has a high dielectric breakdown resistance. Accordingly, the silicon carbide semiconductor device has a large breakdown voltage.
  • the gate electrode is in contact with the portion of the trench insulating film on the side wall. Namely, the gate electrode faces the side wall that forms a channel, without the bottom insulating film being interposed therebetween.
  • the bottom insulating film is disposed so as not to increase the threshold voltage. Accordingly, a low threshold voltage is attained without influence of the bottom insulating film.
  • a total of a thickness of the trench insulating film on the bottom portion and a thickness of the bottom insulating film is larger than a thickness of the trench insulating film on the side wall. Accordingly, the thickness of the gate insulating film can be made small on the side wall whereas the thickness thereof can be made large on the bottom portion. Accordingly, the breakdown voltage of the silicon carbide semiconductor device can be made larger while making the threshold voltage small.
  • a thickness of the bottom insulating film is larger than that of the trench insulating film. Accordingly, a ratio of the portion formed of the bottom insulating film of the gate insulating film is made large on the bottom portion. This leads to a larger breakdown voltage of the silicon carbide semiconductor device.
  • a thickness of the trench insulating film on the bottom portion is smaller than a thickness of the trench insulating film on the side wall. Accordingly, a region for providing the bottom insulating film is further secured on the bottom portion. This leads to a larger breakdown voltage of the silicon carbide semiconductor device.
  • the carbon atom concentration of the trench insulating film is more than 1 ⁇ 10 15 cm ⁇ 3
  • the carbon atom concentration of the bottom insulating film is less than 1 ⁇ 10 15 cm ⁇ 3 . Accordingly, the carbon atom concentration in the bottom insulating film is sufficiently made low. This leads to a larger breakdown voltage of the silicon carbide semiconductor device.
  • the bottom insulating film has a thickness of more than 100 nm. This leads to a larger breakdown voltage of the silicon carbide semiconductor device.
  • the trench insulating film is a thermal oxidation film of silicon carbide. This makes the trench insulating film thin and smooth. This leads to a larger breakdown voltage of the silicon carbide semiconductor device.
  • the bottom insulating film is formed of at least any one of silicon oxide, silicon nitride, and phosphorus silicate glass. This leads to a larger breakdown voltage of the silicon carbide semiconductor device.
  • the bottom insulating film is a thermal oxidation film of a film containing silicon and containing no carbon. This leads to a larger breakdown voltage of the silicon carbide semiconductor device.
  • FIG. 1 is a partial cross sectional view schematically showing a configuration of a silicon carbide semiconductor device in a first embodiment of the present invention.
  • FIG. 2 is a perspective view schematically showing a shape of a silicon carbide substrate included in the silicon carbide semiconductor device of FIG. 1 .
  • FIG. 3 shows the configuration of FIG. 2 more in detail with a region of second conductivity type being provided with hatching for viewability of the figure.
  • FIG. 4 is an enlarged view of FIG. 1 .
  • FIG. 5 is a graph showing a profile of a carbon atom concentration along an arrow Z in FIG. 4 .
  • FIG. 6 is a partial cross sectional view schematically showing a first step of a method for manufacturing the silicon carbide semiconductor device of FIG. 1 .
  • FIG. 7 is a partial cross sectional view schematically showing a second step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1 .
  • FIG. 8 is a partial cross sectional view schematically showing a third step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1 .
  • FIG. 9 is a partial cross sectional view schematically showing a fourth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1 .
  • FIG. 10 is a partial cross sectional view schematically showing a fifth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1 .
  • FIG. 11 is a partial cross sectional view schematically showing a sixth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1 .
  • FIG. 12 is a partial cross sectional view schematically showing a seventh step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1 .
  • FIG. 13 is a partial cross sectional view schematically showing an eighth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1 .
  • FIG. 14 is a partial cross sectional view schematically showing a ninth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1 .
  • FIG. 15 is a partial cross sectional view schematically showing a tenth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1 .
  • FIG. 16 is a partial cross sectional view schematically showing an eleventh step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1 .
  • FIG. 17 is a partial cross sectional view schematically showing a twelfth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1 .
  • FIG. 18 is a partial cross sectional view schematically showing a thirteenth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1 .
  • FIG. 19 is a partial cross sectional view schematically showing one step of a method for manufacturing a silicon carbide semiconductor device of a comparative example.
  • FIG. 20 is a partial cross sectional view schematically showing a configuration of a silicon carbide semiconductor device in a second embodiment of the present invention.
  • FIG. 21 is a partial cross sectional view schematically showing a fine structure in a surface of a silicon carbide substrate included in the silicon carbide semiconductor device.
  • FIG. 22 shows a crystal structure of a (000-1) plane in a hexagonal crystal of polytype 4H.
  • FIG. 23 shows a crystal structure of a (11-20) plane along a line XXIII-XXIII in FIG. 22 .
  • FIG. 24 shows a crystal structure of a combined plane of FIG. 21 in the vicinity of the surface within the (11-20) plane.
  • FIG. 25 shows the combined plane of FIG. 21 when viewed from a (01-10) plane.
  • FIG. 26 is a graph showing an exemplary relation between channel mobility and an angle between a channel surface and the (000-1) plane when macroscopically viewed, in each of a case where thermal etching is performed and a case where no thermal etching is performed.
  • FIG. 27 is a graph showing an exemplary relation between the channel mobility and an angle between a channel direction and a ⁇ 0-11-2> direction.
  • FIG. 28 shows a modification of FIG. 21 .
  • a vertical type MOSFET 500 (silicon carbide semiconductor device) of the present embodiment includes an epitaxial substrate 100 (silicon carbide substrate), gate insulating films 201 , gate electrodes 202 , interlayer insulating films 203 , source electrodes 221 , a drain electrode 211 , a source interconnection 222 , and a protecting electrode 212 .
  • Epitaxial substrate 100 is made of silicon carbide, and has a single-crystal substrate 110 and an epitaxial layer provided thereon.
  • the epitaxial layer includes an n ⁇ layer 121 (first layer), p type body layers 122 (second layer), n regions 123 (third layer), and contact regions 124 .
  • the silicon carbide of epitaxial substrate 100 preferably has a hexagonal crystal structure, more preferably, has a polytype of 4H.
  • Single-crystal substrate 110 has n type (first conductivity type) conductivity.
  • the plane orientation (hklm) of one main surface (upper surface in FIG. 1 ) of single-crystal substrate 110 preferably has m of negative value, more preferably, corresponds to approximately a (000-1) plane.
  • N ⁇ layer 121 has a donor added therein and therefore has n type conductivity.
  • the donor is preferably added to n ⁇ layer 121 by adding an impurity during epitaxial growth of n ⁇ layer 121 , rather than ion implantation.
  • N ⁇ layer 121 preferably has a donor concentration lower than that of single-crystal substrate 110 .
  • N ⁇ layer 121 preferably has a donor concentration of not less than 1 ⁇ 10 15 cm ⁇ 3 and not more than 5 ⁇ 10 16 cm ⁇ 3 , for example, has a donor concentration of 8 ⁇ 10 15 cm ⁇ 3 .
  • Each of p type body layers 122 is provided on n ⁇ layer 121 , has an acceptor added therein, and therefore has p type conductivity (second conductivity type).
  • P type body layer 122 has an acceptor concentration of, for example, 1 ⁇ 10 18 cm ⁇ 3 .
  • Each of n regions 123 has n type conductivity.
  • N region 123 is provided on p type body layer 122 , and is separated from n layer 121 by p type body layer 122 .
  • Contact region 124 has p type conductivity. Contact region 124 is formed on a portion of p type body layer 122 so as to be connected to p type body layer 122 .
  • epitaxial substrate 100 is provided with a trench TR.
  • Trench TR has side walls SW and a bottom portion BT.
  • Each of side walls SW extends through n region 123 and p type body layer 122 and reaches n layer 121 .
  • Bottom portion BT is formed of n layer 121 .
  • Side wall SW has a channel surface CH on p type body layer 122 ( FIG. 3 ).
  • Bottom portion BT is a flat surface substantially parallel to the main surface of epitaxial substrate 100 .
  • side wall SW has a predetermined crystal plane (also referred to as “special plane”) particularly on p type body layer 122 . Details of the special plane will be described later.
  • epitaxial substrate 100 has trench TR corresponds to such a fact that the epitaxial layer is partially removed above the upper surface of single-crystal substrate 110 .
  • a multiplicity of mesa structures are formed on the upper surface of single-crystal substrate 110 .
  • each of the mesa structures has upper surface and bottom portion both having a hexagonal shape, and has side walls inclined relative to the main surface of single-crystal substrate 110 .
  • trench TR expands toward the opening in a tapering manner.
  • Gate insulating film 201 is provided on trench TR. Gate insulating film 201 separates epitaxial substrate 100 and gate electrode 202 from each other in trench TR. Gate insulating film 201 has a trench insulating film 201 A and a bottom insulating film 201 B. Trench insulating film 201 A covers each of side walls SW and bottom portion BT. Bottom insulating film 201 B is provided on bottom portion BT with trench insulating film 201 A being interposed therebetween. Bottom insulating film 201 B has a portion located at a corner portion formed by bottom portion BT and each side wall SW.
  • Bottom insulating film 201 B has a carbon atom concentration lower than that of trench insulating film 201 A.
  • trench insulating film 201 A is a thermal oxidation film of silicon carbide.
  • trench insulating film 201 A is made of silicon oxide containing carbon atoms as an impurity.
  • bottom insulating film 201 B is a thermal oxidation film of a film containing silicon and containing no carbon.
  • bottom insulating film 201 B is a thermal oxidation film of a silicon film, and is made of silicon oxide.
  • trench insulating film 201 A has a thickness t 1 on side wall SW and has a thickness t 2 on bottom portion BT.
  • Bottom insulating film 201 B has a thickness t 3 on bottom portion BT.
  • a total of thickness t 2 and thickness t 3 is larger than thickness t 1 .
  • thickness t 3 is larger than thickness t 2 .
  • thickness t 2 is smaller than thickness t 1 .
  • thickness t 3 is larger than 100 nm.
  • Trench insulating film 201 A may have a carbon atom concentration of more than 1 ⁇ 10 15 cm ⁇ 3 .
  • Bottom insulating film 201 B preferably has a carbon atom concentration of less than 1 ⁇ 10 15 cm ⁇ 3 . It should be noted that in the case where the carbon atom concentrations are not uniform, an average value may be calculated.
  • a solid line of FIG. 5 illustrates a profile of a carbon atom concentration NC in the thickness direction (arrow Z in FIG. 4 ) from the bottom portion BT toward the trench.
  • trench insulating film 201 A typically has a carbon atom concentration NC of more than approximately 1 ⁇ 10 17 cm ⁇ 3 and less than approximately 1 ⁇ 10 20 cm ⁇ 3 , for example, has a carbon atom concentration NC of approximately 1 ⁇ 10 18 cm ⁇ 3 .
  • Gate electrode 202 is provided in trench TR. Specifically, gate electrode 202 is buried in trench TR with gate insulating film 201 interposed therebetween. Gate electrode 202 is in contact with trench insulating film 201 A at a portion located on side wall SW. On side wall SW, gate electrode 202 faces the surface of p type body layer 122 with only trench insulating film 201 A being interposed therebetween. In other words, bottom insulating film 201 B is not provided between the portion of trench insulating film 201 A on side wall SW and gate electrode 202 . Gate electrode 202 has an upper surface substantially as high as the upper surface of a portion of gate insulating film 201 on the upper surface of n region 123 . Interlayer insulating film 203 is provided to cover gate electrode 202 as well as the extended portion of gate insulating film 201 on the upper surface of n region 123 .
  • Source electrode 221 extends through interlayer insulating film 203 and makes contact with each of n regions 123 and contact region 124 .
  • Source interconnection 222 is provided on source electrode 221 and interlayer insulating film 203 in contact with source electrode 221 .
  • Drain electrode 211 is provided on an opposite surface of epitaxial substrate 100 to its surface in which trench TR is provided.
  • Protecting electrode 212 covers drain electrode 211 .
  • MOSFET 500 FIG. 1
  • n ⁇ layer 121 is formed by means of epitaxial growth.
  • This epitaxial growth can be performed by means of, for example, a CVD (Chemical Vapor Deposition) method in which a mixed gas of silane (SiH 4 ) and propane (C 3 H 8 ) is used as a source material gas and hydrogen gas (H 2 ) is used as a carrier gas, for example.
  • a CVD Chemical Vapor Deposition
  • SiH 4 silane
  • propane C 3 H 8
  • H 2 hydrogen gas
  • N nitrogen
  • P phosphorus
  • p type body layer 122 is formed on n′ layer 121
  • n region 123 is formed on p type body layer 122 .
  • ion implantation is performed into the upper surface of n ⁇ layer 121 .
  • ions of an acceptor such as aluminum (Al) are implanted.
  • ions of a donor such as phosphorus (P) are implanted, for example.
  • epitaxial substrate 100 is formed which has n ⁇ layer 121 , p type body layer 122 , and n region 123 . It should be noted that instead of the ion implantation, epitaxial growth involving addition of impurities may be employed.
  • contact regions 124 are formed.
  • activation heating treatment is performed to activate the impurities added by the ion implantation.
  • This heat treatment is preferably performed at a temperature of not less than 1500° C. and not more than 1900° C., for example, a temperature of approximately 1700° C.
  • the heat treatment is performed for approximately 30 minutes, for example.
  • the atmosphere of the heat treatment is preferably an inert gas atmosphere, such as Ar atmosphere.
  • a mask 247 ( FIG. 9 ) having an opening through which n region 123 is partially exposed is formed on epitaxial substrate 100 .
  • the opening is formed to correspond to the location of trench TR ( FIG. 1 ).
  • a silicon oxide film formed through thermal oxidation can be used, for example.
  • n region 123 , p type body layer 122 , and a portion of n ⁇ layer 121 are removed by etching.
  • An exemplary, usable etching method is reactive ion etching (RIB), in particular, inductively coupled plasma (ICP) RIE.
  • ICP-RIE can be employed in which SF 6 or a mixed gas of SF 6 and O 2 is used as the reactive gas, for example.
  • epitaxial substrate 100 is etched. Specifically, inner surface SV of recess TQ of epitaxial substrate 100 is thermally etched.
  • the thermal etching can be performed by, for example, heating epitaxial substrate 100 in an atmosphere including a reactive gas containing at least one or more types of halogen atom.
  • the at least one or more types of halogen atom include at least one of chlorine (Cl) atom and fluorine (F) atom.
  • This atmosphere is, for example, Cl 2 , BCL 3 , SF 6 , or CF 4 .
  • the thermal etching is performed using a mixed gas of chlorine gas and oxygen gas as a reactive gas, at a heat treatment temperature of, for example, not less than 700° C. and not more than 1000° C.
  • trench TR is formed as shown in FIG. 11 .
  • epitaxial substrate 100 is etched in a side etching manner from the opening of mask 247 as indicated by an arrow SE. Further, during this thermal etching, a special plane is spontaneously formed in side wall SW of trench TR, in particular, its portion formed of p type body layer 122 .
  • the reactive gas may contain a carrier gas in addition to the chlorine gas and the oxygen gas.
  • An exemplary, usable carrier gas is nitrogen (N 2 ) gas, argon gas, helium gas, or the like.
  • a silicon film 90 is formed on epitaxial substrate 100 having mask 247 provided thereon.
  • silicon film 90 is formed while using mask 247 .
  • Silicon film 90 is formed on bottom portion BT of trench TR. This formation can be performed by means of, for example, the CVD method.
  • mask 247 is removed by means of an appropriate method such as etching ( FIG. 13 ). In doing so, the portion of silicon film 90 on mask 247 is also removed.
  • silicon film 90 ( FIG. 13 ) is thermally oxidized. Accordingly, an silicon oxide film is formed ( FIG. 14 ) which serves as bottom insulating film 201 B that forms a portion of gate insulating film 201 ( FIG. 1 ). Silicon film 90 is thermally oxidized at, for example, not less than 800° C. and not more than 950° C.
  • epitaxial substrate 100 made of silicon carbide is thermally oxidized, thereby forming an silicon oxide film serving as trench insulating film 201 A of gate insulating film 201 .
  • Epitaxial substrate 100 is preferably thermally oxidized at a temperature higher than the temperature at which silicon film 90 is thermally oxidized, for example, is thermally oxidized at 1300° C. or more.
  • gate electrode 202 is formed on gate insulating film 201 .
  • Gate electrode 202 is formed in direct contact with trench insulating film 201 A on p type body layer 122 .
  • a method for forming gate electrode 202 can be performed by, for example, forming a film of conductor or doped polysilicon and performing CMP (Chemical Mechanical Polishing).
  • interlayer insulating film 203 is formed on gate electrode 202 and gate insulating film 201 so as to cover the exposed surface of gate electrode 202 .
  • etching is performed to form openings in interlayer insulating film 203 and gate insulating film 201 .
  • each of n region 123 and contact region 124 is exposed on the upper surface of the mesa structure.
  • source electrode 221 is formed in contact with each of n region 123 and contact region 124 .
  • source interconnection 222 , drain electrode 211 , and protecting electrode 212 are formed. In this way, MOSFET 500 is obtained.
  • MOSFET 500 ( FIG. 4 ) of the present embodiment, electric insulation between gate electrode 202 and bottom portion BT of trench TR is secured by bottom insulating film 201 B in addition to trench insulating film 201 A.
  • Bottom insulating film 201 B has a low carbon atom concentration, and therefore has a high dielectric breakdown resistance. Accordingly, MOSFET 500 has a large breakdown voltage.
  • gate electrode 202 is in contact with the portion of trench insulating film 201 A on side wall SW. Namely, gate electrode 202 faces side wall SW that forms a channel, without bottom insulating film 201 B being interposed therebetween.
  • bottom insulating film 201 B is disposed so as not to increase the threshold voltage. Accordingly, a low threshold voltage is attained without influence of bottom insulating film 201 B.
  • trench insulating film 201 A is a thermal oxidation film of silicon carbide of epitaxial substrate 100 (see FIG. 14 and FIG. 15 ). This makes the trench insulating film thin and smooth. Accordingly, the breakdown voltage of MOSFET 500 can be made larger.
  • bottom insulating film 201 B is made of silicon oxide. In this way, the breakdown voltage of MOSFET 500 can be made larger. Further, bottom insulating film 201 B is silicon film 90 , i.e., a thermal oxidation film of a film containing silicon and containing no carbon. In this way, the breakdown voltage of MOSFET 500 can be made larger.
  • the thickness of gate insulating film 201 can be made small on side wall SW whereas the thickness thereof can be made large on bottom portion BT. Accordingly, the breakdown voltage of MOSFET 500 can be made larger while making the threshold voltage small.
  • the breakdown voltage of MOSFET 500 can be made larger.
  • bottom insulating film 201 B has a carbon atom concentration of less than 1 ⁇ 10 15 cm ⁇ 3 , the carbon atom concentration of bottom insulating film 201 B is sufficiently low. Accordingly, the breakdown voltage of MOSFET 500 can be made larger.
  • the decrease of carbon atom concentration NC in gate insulating film 201 just above bottom portion BT of trench TR is relatively gradual as indicated by arrow d 1 ( FIG. 5 ). Accordingly, generation of stress due to the composition change in gate insulating film 201 can be suppressed.
  • a gate insulating film 201 Z is formed by means of thermal oxidation of epitaxial substrate 100 without bottom insulating film 201 B ( FIG. 15 ) as shown in FIG. 19 , carbon atom concentration NC is drastically decreased in gate insulating film 201 Z just above bottom portion BT of trench TR as indicated by arrow d 2 ( FIG. 5 ). As a result, stress is likely to be applied to gate insulating film 201 Z.
  • the silicon oxide film serving as bottom insulating film 201 B is a silicon oxide film formed through the thermal oxidation of silicon film 90 ( FIG. 13 ), but the silicon oxide film may be formed through, for example, the CVD method instead of forming silicon film 90 .
  • the material of the bottom insulating film is not limited to silicon oxide, and may be phosphorus silicate glass or silicon nitride, for example.
  • a film made of silicon nitride can be formed by means of, for example, the CVD method.
  • first conductivity type corresponds to n type conductivity
  • second conductivity type corresponds to p type conductivity
  • these conductivity types may be replaced with each other.
  • the donor and acceptor in the foregoing description are also replaced with each other.
  • the “first conductivity type” corresponds to n type conductivity.
  • the silicon carbide semiconductor device is not limited to the MOSFET, and may be a trench type IGBT (Insulated Gate Bipolar Transistor), for example.
  • a MOSFET 500 v silicon carbide semiconductor device of the present embodiment has a trench TRv having a V shape instead of trench TR ( FIG. 4 ).
  • Trench TRv has a bottom portion BTv, instead of bottom portion BT ( FIG. 4 ).
  • bottom portion BTv is a portion in which side walls SW facing each other make contact with each other so as to form a V shape.
  • the configuration of the present embodiment is substantially the same as the configuration of the first embodiment. Hence, the same or corresponding elements are given the same reference characters and are not described repeatedly.
  • side wall SW ( FIG. 1 ) of trench TR preferably has a predetermined crystal plane (also referred to as “special plane”) on, in particular, p type body layer 122 .
  • a side wall SW includes a plane S 1 (first plane) having a plane orientation of ⁇ 0-33-8 ⁇ as shown in FIG. 21 .
  • Plane S 1 preferably has a plane orientation of (0-33-8).
  • side wall SW microscopically includes plane S 1
  • side wall SW microscopically further includes a plane S 2 (second plane) having a plane orientation of ⁇ 0-11-1 ⁇ .
  • plane S 2 second plane
  • the term “microscopically” refers to “minutely to such an extent that at least the size about twice as large as an interatomic spacing is considered”.
  • a TEM Transmission Electron Microscope
  • plane S 2 has a plane orientation of (0-11-1).
  • plane S 1 and plane S 2 of side wall SW forms a combined plane SR having a plane orientation of ⁇ 0-11-2 ⁇ .
  • combined plane SR is formed of periodically repeated planes S 1 and S 2 .
  • Such a periodic structure can be observed by, for example, TEM or AFM (Atomic Force Microscopy).
  • combined plane SR has an off angle of 62° relative to the ⁇ 000-1 ⁇ plane, macroscopically.
  • the term “macroscopically” refers to “disregarding a fine structure having a size of approximately interatomic spacing”.
  • a method employing general X-ray diffraction can be used, for example.
  • combined plane SR has a plane orientation of (0-11-2).
  • combined plane SR has an off angle of 62° relative to the (000-1) plane, macroscopically.
  • channels in which the above-described periodic repetition is done.
  • Si atoms when viewing a silicon carbide single-crystal of polytype 4H from the (000-1) plane, atoms in a layer A (solid line in the figure), atoms in a layer B (broken line in the figure) disposed therebelow, and atoms in a layer C (chain line in the figure) disposed therebelow, and atoms in a layer B (not shown in the figure) disposed therebelow are repeatedly provided as shown in FIG. 22 .
  • a periodic stacking structure such as ABCBABCBABCB . . . is provided.
  • combined plane SR is constructed by alternately providing planes S 1 having a plane orientation of (0-33-8) and planes S 2 connected to planes S 1 and having a plane orientation different from that of each of planes S 1 .
  • Each of planes S 1 and S 2 has a length twice as large as the interatomic spacing of the Si atoms (or C atoms). It should be noted that a plane with plane S 1 and plane S 2 being averaged corresponds to the (0-11-2) plane ( FIG. 23 ).
  • the single-crystal structure has a portion periodically including a structure (plane S 1 portion) equivalent to a cubic structure.
  • combined plane SR is constructed by alternately providing planes S 1 having a plane orientation of (001) in the above-described structure equivalent to the cubic structure and planes S 2 connected to planes S 1 and having a plane orientation different from that of each of planes S 1 .
  • the surface can be formed of the planes (planes S 1 in FIG. 25 ) having a plane orientation of (001) in the structure equivalent to the cubic structure and the planes (planes S 2 in FIG. 25 ) connected to the foregoing planes and having a plane orientation different from that of each of the foregoing planes.
  • the polytype may be, for example, 6H or 15R.
  • the horizontal axis represents an angle D 1 formed by the (000-1) plane and the macroscopic plane orientation of side wall SW having the channel surface
  • the vertical axis represents mobility MB.
  • a group of plots CM correspond to a case where side wall SW is finished to correspond to a special plane by thermal etching
  • a group of plots MC correspond to a case where side wall SW is not thermally etched.
  • mobility MB is at maximum when the surface of the channel surface has a macroscopic plane orientation of (0-33-8). This is presumably due to the following reason. That is, in the case where the thermal etching is not performed, i.e., in the case where the microscopic structure of the channel surface is not particularly controlled, the macroscopic plane orientation thereof corresponds to (0-33-8), with the result that a ratio of the microscopic plane orientation of (0-33-8), i.e., the plane orientation of (0-33-8) in consideration of that in atomic level becomes statistically high.
  • channel direction CD ( FIG. 21 ) preferably has an angle D 2 of not less than 0° and not more than 60°, more preferably, substantially 0°.
  • side wall SW may further include plane S 3 (third plane) in addition to combined plane SR. More specifically, side wall SW may include a combined plane SQ formed of periodically repeated plane S 3 and combined plane SR.
  • the off angle of side wall SW relative to the ⁇ 000-1 ⁇ plane is deviated from the ideal off angle of combined plane SR, i.e., 62°.
  • this deviation is small, preferably, in a range of ⁇ 10°. Examples of a surface included in such an angle range include a surface having a macroscopic plane orientation of the ⁇ 0-33-8 ⁇ plane.
  • the off angle of side wall SW relative to the (000-1) plane is deviated from the ideal off angle of combined plane SR, i.e., 62°.
  • this deviation is small, preferably, in a range of ⁇ 10°.
  • Examples of a surface included in such an angle range include a surface having a macroscopic plane orientation of the (0-33-8) plane.

Abstract

A gate insulating film is provided on a trench. The gate insulating film has a trench insulating film and a bottom insulating film. The trench insulating film covers each of a side wall and a bottom portion. The bottom insulating film is provided on the bottom portion with a trench insulating film being interposed therebetween. The bottom insulating film has a carbon atom concentration lower than that of the trench insulating film. The gate electrode is in contact with a portion of the trench insulating film on the side wall. Accordingly, a low threshold voltage and a large breakdown voltage can be attained.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a silicon carbide semiconductor device, in particular, a silicon carbide semiconductor device having a trench.
  • 2. Description of the Background Art
  • Japanese Patent Laying-Open No. 7-326755 discloses a trench gate type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) employing a silicon carbide substrate. This patent publication describes that a gate thermal oxidation film has a thicker film thickness on a bottom surface of a trench than the film thickness thereof on a side surface of the trench, so that a threshold voltage becomes low and breakdown voltage between the gate and the drain becomes high. It is also described that the bottom surface of the trench corresponds to a carbon plane, which allows for fast oxidation rate, of hexagonal single-crystal silicon carbide, whereas the side surface of the trench corresponds to a plane perpendicular to this carbon plane and allowing for slow oxidation rate. Hence, by performing a thermal oxidation process once, a thermal oxidation film can be formed such that the thickness of the thermal oxidation film on the side surface of the trench is greatly different from the thickness of the thermal oxidation film on the bottom surface of the trench.
  • According to the technique of the above-described patent publication, the gate insulating film on the trench is entirely formed by the thermal oxidation on the trench of the silicon carbide substrate. The silicon carbide substrate used here normally has a high crystallinity, so that a thin and flat gate insulating film can be formed. In this way, low threshold voltage can be attained. However, in the insulating film thus formed by the thermal oxidation of silicon carbide, carbon atoms, which have existed in the silicon carbide, remains to an extent that cannot be disregarded. According to a study conducted by the present inventors, the carbon atoms remaining in the gate oxide film decrease dielectric breakdown resistance of the gate insulating film. Accordingly, it is considered that there is room for further improvement for the dielectric breakdown resistance in the above-described conventional technique. Namely, it is considered that there is room for further increasing the breakdown voltage of the silicon carbide semiconductor device.
  • SUMMARY OF THE INVENTION
  • The present invention has been made to solve the foregoing problem and has its object to provide a silicon carbide semiconductor device having a low threshold voltage and a large breakdown voltage.
  • A silicon carbide semiconductor device of the present invention includes: a silicon carbide substrate, a gate insulating film, and a gate electrode. The silicon carbide substrate includes first to third layers. The first layer has first conductivity type. The second layer is provided on the first layer and has second conductivity type. The third layer is provided on the second layer, is separated from the first layer by the second layer, and has the first conductivity type. The silicon carbide substrate is provided with a trench. The trench includes a side wall and a bottom portion, the side wall extending through the third layer and the second layer and reaching the first layer, the bottom portion being formed of the first layer. The gate insulating film is provided on the trench. The gate insulating film includes a trench insulating film and a bottom insulating film. The trench insulating film covers each of the side wall and the bottom portion. The bottom insulating film is provided on the bottom portion with the trench insulating film being interposed therebetween. The bottom insulating film has a carbon atom concentration lower than that of the trench insulating film. The gate electrode is provided in the trench. The gate electrode is in contact with a portion of the trench insulating film on the side wall.
  • According to this silicon carbide semiconductor device, electric insulation between the gate electrode and the bottom portion of the trench is secured by the bottom insulating film in addition to the trench insulating film. With the low carbon atom concentration, the bottom insulating film has a high dielectric breakdown resistance. Accordingly, the silicon carbide semiconductor device has a large breakdown voltage. Further, according to the silicon carbide semiconductor device, the gate electrode is in contact with the portion of the trench insulating film on the side wall. Namely, the gate electrode faces the side wall that forms a channel, without the bottom insulating film being interposed therebetween. Thus, the bottom insulating film is disposed so as not to increase the threshold voltage. Accordingly, a low threshold voltage is attained without influence of the bottom insulating film.
  • Preferably, a total of a thickness of the trench insulating film on the bottom portion and a thickness of the bottom insulating film is larger than a thickness of the trench insulating film on the side wall. Accordingly, the thickness of the gate insulating film can be made small on the side wall whereas the thickness thereof can be made large on the bottom portion. Accordingly, the breakdown voltage of the silicon carbide semiconductor device can be made larger while making the threshold voltage small.
  • Preferably, on the bottom portion, a thickness of the bottom insulating film is larger than that of the trench insulating film. Accordingly, a ratio of the portion formed of the bottom insulating film of the gate insulating film is made large on the bottom portion. This leads to a larger breakdown voltage of the silicon carbide semiconductor device.
  • Preferably, a thickness of the trench insulating film on the bottom portion is smaller than a thickness of the trench insulating film on the side wall. Accordingly, a region for providing the bottom insulating film is further secured on the bottom portion. This leads to a larger breakdown voltage of the silicon carbide semiconductor device.
  • Preferably, the carbon atom concentration of the trench insulating film is more than 1×1015 cm−3, and the carbon atom concentration of the bottom insulating film is less than 1×1015 cm−3. Accordingly, the carbon atom concentration in the bottom insulating film is sufficiently made low. This leads to a larger breakdown voltage of the silicon carbide semiconductor device.
  • Preferably, the bottom insulating film has a thickness of more than 100 nm. This leads to a larger breakdown voltage of the silicon carbide semiconductor device.
  • Preferably, the trench insulating film is a thermal oxidation film of silicon carbide. This makes the trench insulating film thin and smooth. This leads to a larger breakdown voltage of the silicon carbide semiconductor device.
  • Preferably, the bottom insulating film is formed of at least any one of silicon oxide, silicon nitride, and phosphorus silicate glass. This leads to a larger breakdown voltage of the silicon carbide semiconductor device.
  • Preferably, the bottom insulating film is a thermal oxidation film of a film containing silicon and containing no carbon. This leads to a larger breakdown voltage of the silicon carbide semiconductor device.
  • As described above, according to the present invention, a low threshold voltage and a large breakdown voltage are attained.
  • The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a partial cross sectional view schematically showing a configuration of a silicon carbide semiconductor device in a first embodiment of the present invention.
  • FIG. 2 is a perspective view schematically showing a shape of a silicon carbide substrate included in the silicon carbide semiconductor device of FIG. 1.
  • FIG. 3 shows the configuration of FIG. 2 more in detail with a region of second conductivity type being provided with hatching for viewability of the figure.
  • FIG. 4 is an enlarged view of FIG. 1.
  • FIG. 5 is a graph showing a profile of a carbon atom concentration along an arrow Z in FIG. 4.
  • FIG. 6 is a partial cross sectional view schematically showing a first step of a method for manufacturing the silicon carbide semiconductor device of FIG. 1.
  • FIG. 7 is a partial cross sectional view schematically showing a second step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1.
  • FIG. 8 is a partial cross sectional view schematically showing a third step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1.
  • FIG. 9 is a partial cross sectional view schematically showing a fourth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1.
  • FIG. 10 is a partial cross sectional view schematically showing a fifth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1.
  • FIG. 11 is a partial cross sectional view schematically showing a sixth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1.
  • FIG. 12 is a partial cross sectional view schematically showing a seventh step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1.
  • FIG. 13 is a partial cross sectional view schematically showing an eighth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1.
  • FIG. 14 is a partial cross sectional view schematically showing a ninth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1.
  • FIG. 15 is a partial cross sectional view schematically showing a tenth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1.
  • FIG. 16 is a partial cross sectional view schematically showing an eleventh step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1.
  • FIG. 17 is a partial cross sectional view schematically showing a twelfth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1.
  • FIG. 18 is a partial cross sectional view schematically showing a thirteenth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1.
  • FIG. 19 is a partial cross sectional view schematically showing one step of a method for manufacturing a silicon carbide semiconductor device of a comparative example.
  • FIG. 20 is a partial cross sectional view schematically showing a configuration of a silicon carbide semiconductor device in a second embodiment of the present invention.
  • FIG. 21 is a partial cross sectional view schematically showing a fine structure in a surface of a silicon carbide substrate included in the silicon carbide semiconductor device.
  • FIG. 22 shows a crystal structure of a (000-1) plane in a hexagonal crystal of polytype 4H.
  • FIG. 23 shows a crystal structure of a (11-20) plane along a line XXIII-XXIII in FIG. 22.
  • FIG. 24 shows a crystal structure of a combined plane of FIG. 21 in the vicinity of the surface within the (11-20) plane.
  • FIG. 25 shows the combined plane of FIG. 21 when viewed from a (01-10) plane.
  • FIG. 26 is a graph showing an exemplary relation between channel mobility and an angle between a channel surface and the (000-1) plane when macroscopically viewed, in each of a case where thermal etching is performed and a case where no thermal etching is performed.
  • FIG. 27 is a graph showing an exemplary relation between the channel mobility and an angle between a channel direction and a <0-11-2> direction.
  • FIG. 28 shows a modification of FIG. 21.
  • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • The following describes embodiments of the present invention based on figures. It should be noted that in the below-mentioned figures, the same or corresponding portions are given the same reference characters and are not described repeatedly. Regarding crystallographic indications in the present specification, an individual orientation is represented by [ ], a group orientation is represented by < >, and an individual plane is represented by ( ) and a group plane is represented by { }. In addition, a negative crystallographic index is normally expressed by putting “-” (bar) above a numeral, but is expressed by putting the negative sign before the numeral in the present specification.
  • First Embodiment
  • As shown in FIG. 1, a vertical type MOSFET 500 (silicon carbide semiconductor device) of the present embodiment includes an epitaxial substrate 100 (silicon carbide substrate), gate insulating films 201, gate electrodes 202, interlayer insulating films 203, source electrodes 221, a drain electrode 211, a source interconnection 222, and a protecting electrode 212.
  • Epitaxial substrate 100 is made of silicon carbide, and has a single-crystal substrate 110 and an epitaxial layer provided thereon. The epitaxial layer includes an nlayer 121 (first layer), p type body layers 122 (second layer), n regions 123 (third layer), and contact regions 124. The silicon carbide of epitaxial substrate 100 preferably has a hexagonal crystal structure, more preferably, has a polytype of 4H.
  • Single-crystal substrate 110 has n type (first conductivity type) conductivity. The plane orientation (hklm) of one main surface (upper surface in FIG. 1) of single-crystal substrate 110 preferably has m of negative value, more preferably, corresponds to approximately a (000-1) plane.
  • Nlayer 121 has a donor added therein and therefore has n type conductivity. The donor is preferably added to nlayer 121 by adding an impurity during epitaxial growth of nlayer 121, rather than ion implantation. Nlayer 121 preferably has a donor concentration lower than that of single-crystal substrate 110. Nlayer 121 preferably has a donor concentration of not less than 1×1015 cm−3 and not more than 5×1016 cm−3, for example, has a donor concentration of 8×1015 cm−3.
  • Each of p type body layers 122 is provided on nlayer 121, has an acceptor added therein, and therefore has p type conductivity (second conductivity type). P type body layer 122 has an acceptor concentration of, for example, 1×1018 cm−3.
  • Each of n regions 123 has n type conductivity. N region 123 is provided on p type body layer 122, and is separated from n layer 121 by p type body layer 122. Contact region 124 has p type conductivity. Contact region 124 is formed on a portion of p type body layer 122 so as to be connected to p type body layer 122.
  • Further, referring to FIG. 2 and FIG. 3, epitaxial substrate 100 is provided with a trench TR. Trench TR has side walls SW and a bottom portion BT. Each of side walls SW extends through n region 123 and p type body layer 122 and reaches n layer 121. Bottom portion BT is formed of n layer 121. Side wall SW has a channel surface CH on p type body layer 122 (FIG. 3). Bottom portion BT is a flat surface substantially parallel to the main surface of epitaxial substrate 100. Preferably, side wall SW has a predetermined crystal plane (also referred to as “special plane”) particularly on p type body layer 122. Details of the special plane will be described later.
  • The fact that epitaxial substrate 100 has trench TR corresponds to such a fact that the epitaxial layer is partially removed above the upper surface of single-crystal substrate 110. In the present embodiment, a multiplicity of mesa structures are formed on the upper surface of single-crystal substrate 110. Specifically, each of the mesa structures has upper surface and bottom portion both having a hexagonal shape, and has side walls inclined relative to the main surface of single-crystal substrate 110. Thus, trench TR expands toward the opening in a tapering manner.
  • Gate insulating film 201 is provided on trench TR. Gate insulating film 201 separates epitaxial substrate 100 and gate electrode 202 from each other in trench TR. Gate insulating film 201 has a trench insulating film 201A and a bottom insulating film 201B. Trench insulating film 201A covers each of side walls SW and bottom portion BT. Bottom insulating film 201B is provided on bottom portion BT with trench insulating film 201A being interposed therebetween. Bottom insulating film 201B has a portion located at a corner portion formed by bottom portion BT and each side wall SW.
  • Bottom insulating film 201B has a carbon atom concentration lower than that of trench insulating film 201A. Preferably, trench insulating film 201A is a thermal oxidation film of silicon carbide. In this case, trench insulating film 201A is made of silicon oxide containing carbon atoms as an impurity. Preferably, bottom insulating film 201B is a thermal oxidation film of a film containing silicon and containing no carbon. In the present embodiment, bottom insulating film 201B is a thermal oxidation film of a silicon film, and is made of silicon oxide.
  • As shown in FIG. 4, trench insulating film 201A has a thickness t1 on side wall SW and has a thickness t2 on bottom portion BT. Bottom insulating film 201B has a thickness t3 on bottom portion BT. Preferably, a total of thickness t2 and thickness t3 is larger than thickness t1. Preferably, thickness t3 is larger than thickness t2. Preferably, thickness t2 is smaller than thickness t1. Preferably, thickness t3 is larger than 100 nm.
  • Trench insulating film 201A may have a carbon atom concentration of more than 1×1015 cm−3. Bottom insulating film 201B preferably has a carbon atom concentration of less than 1×1015 cm−3. It should be noted that in the case where the carbon atom concentrations are not uniform, an average value may be calculated.
  • Further, referring to FIG. 5, a solid line of FIG. 5 illustrates a profile of a carbon atom concentration NC in the thickness direction (arrow Z in FIG. 4) from the bottom portion BT toward the trench. A location Z=0 corresponds to an interface between bottom portion BT and trench insulating film 201A. A location Z=t2 corresponds to an interface between trench insulating film 201A and bottom insulating film 201B. A location Z=t2+t3 corresponds to an interface between bottom insulating film 201B and gate electrode 202. When 0≦z≦t2, carbon atom concentration NC becomes smaller as Z increases. In the vicinity of Z=0 (arrow d1 in the figure), the decrease of carbon atom concentration NC is relatively gradual. When Z>t2, carbon atom concentration NC substantially reaches or falls below the detection limit. In the vicinity of location Z=0, trench insulating film 201A typically has a carbon atom concentration NC of more than approximately 1×1017 cm−3 and less than approximately 1×1020 cm−3, for example, has a carbon atom concentration NC of approximately 1×1018 cm−3.
  • Gate electrode 202 is provided in trench TR. Specifically, gate electrode 202 is buried in trench TR with gate insulating film 201 interposed therebetween. Gate electrode 202 is in contact with trench insulating film 201A at a portion located on side wall SW. On side wall SW, gate electrode 202 faces the surface of p type body layer 122 with only trench insulating film 201A being interposed therebetween. In other words, bottom insulating film 201B is not provided between the portion of trench insulating film 201A on side wall SW and gate electrode 202. Gate electrode 202 has an upper surface substantially as high as the upper surface of a portion of gate insulating film 201 on the upper surface of n region 123. Interlayer insulating film 203 is provided to cover gate electrode 202 as well as the extended portion of gate insulating film 201 on the upper surface of n region 123.
  • Source electrode 221 extends through interlayer insulating film 203 and makes contact with each of n regions 123 and contact region 124. Source interconnection 222 is provided on source electrode 221 and interlayer insulating film 203 in contact with source electrode 221. Drain electrode 211 is provided on an opposite surface of epitaxial substrate 100 to its surface in which trench TR is provided. Protecting electrode 212 covers drain electrode 211.
  • The following describes a method for manufacturing MOSFET 500 (FIG. 1).
  • As shown in FIG. 6, on single-crystal substrate 110, nlayer 121 is formed by means of epitaxial growth. This epitaxial growth can be performed by means of, for example, a CVD (Chemical Vapor Deposition) method in which a mixed gas of silane (SiH4) and propane (C3H8) is used as a source material gas and hydrogen gas (H2) is used as a carrier gas, for example. In doing so, it is preferable to introduce nitrogen (N) or phosphorus (P) as a donor, for example.
  • As shown in FIG. 7, p type body layer 122 is formed on n′ layer 121, and n region 123 is formed on p type body layer 122. Specifically, ion implantation is performed into the upper surface of nlayer 121. In the ion implantation for forming p type body layer 122, ions of an acceptor such as aluminum (Al) are implanted. Meanwhile, in the ion implantation for forming n region 123, ions of a donor such as phosphorus (P) are implanted, for example. Accordingly, epitaxial substrate 100 is formed which has nlayer 121, p type body layer 122, and n region 123. It should be noted that instead of the ion implantation, epitaxial growth involving addition of impurities may be employed.
  • As shown in FIG. 8, by means of the ion implantation, contact regions 124 are formed. Next, activation heating treatment is performed to activate the impurities added by the ion implantation. This heat treatment is preferably performed at a temperature of not less than 1500° C. and not more than 1900° C., for example, a temperature of approximately 1700° C. The heat treatment is performed for approximately 30 minutes, for example. The atmosphere of the heat treatment is preferably an inert gas atmosphere, such as Ar atmosphere.
  • Next, a mask 247 (FIG. 9) having an opening through which n region 123 is partially exposed is formed on epitaxial substrate 100. The opening is formed to correspond to the location of trench TR (FIG. 1). As mask 247, a silicon oxide film formed through thermal oxidation can be used, for example.
  • As shown in FIG. 10, in the opening of mask 247, n region 123, p type body layer 122, and a portion of nlayer 121 are removed by etching. An exemplary, usable etching method is reactive ion etching (RIB), in particular, inductively coupled plasma (ICP) RIE. Specifically, ICP-RIE can be employed in which SF6 or a mixed gas of SF6 and O2 is used as the reactive gas, for example. By means of such etching, in the region where trench TR (FIG. 1) is to be formed, a recess TQ can be formed which has a side wall having an inner surface SV substantially perpendicular to the main surface of single-crystal substrate 110.
  • Next, using mask 247, epitaxial substrate 100 is etched. Specifically, inner surface SV of recess TQ of epitaxial substrate 100 is thermally etched. The thermal etching can be performed by, for example, heating epitaxial substrate 100 in an atmosphere including a reactive gas containing at least one or more types of halogen atom. The at least one or more types of halogen atom include at least one of chlorine (Cl) atom and fluorine (F) atom. This atmosphere is, for example, Cl2, BCL3, SF6, or CF4. For example, the thermal etching is performed using a mixed gas of chlorine gas and oxygen gas as a reactive gas, at a heat treatment temperature of, for example, not less than 700° C. and not more than 1000° C.
  • As a result of the thermal etching, trench TR is formed as shown in FIG. 11. During the formation of trench TR, epitaxial substrate 100 is etched in a side etching manner from the opening of mask 247 as indicated by an arrow SE. Further, during this thermal etching, a special plane is spontaneously formed in side wall SW of trench TR, in particular, its portion formed of p type body layer 122.
  • It should be noted that the reactive gas may contain a carrier gas in addition to the chlorine gas and the oxygen gas. An exemplary, usable carrier gas is nitrogen (N2) gas, argon gas, helium gas, or the like. When the heat treatment temperature is set at not less than 700° C. and not more than 1000° C. as described above, a rate of etching SiC is approximately, for example, 70 μm/hour. In addition, in this case, mask 247, which is formed of silicon oxide and therefore has a very large selection ratio relative to SiC, is not substantially etched during the etching of SiC.
  • As shown in FIG. 12, a silicon film 90 is formed on epitaxial substrate 100 having mask 247 provided thereon. In other words, silicon film 90 is formed while using mask 247. Silicon film 90 is formed on bottom portion BT of trench TR. This formation can be performed by means of, for example, the CVD method. Next, mask 247 is removed by means of an appropriate method such as etching (FIG. 13). In doing so, the portion of silicon film 90 on mask 247 is also removed.
  • Next, oxidation is performed in trench TR, thereby forming gate insulating film 201 (FIG. 1) on trench TR. Specifically, the following steps are performed. First, silicon film 90 (FIG. 13) is thermally oxidized. Accordingly, an silicon oxide film is formed (FIG. 14) which serves as bottom insulating film 201B that forms a portion of gate insulating film 201 (FIG. 1). Silicon film 90 is thermally oxidized at, for example, not less than 800° C. and not more than 950° C. Next, as shown in FIG. 15, epitaxial substrate 100 made of silicon carbide is thermally oxidized, thereby forming an silicon oxide film serving as trench insulating film 201A of gate insulating film 201. Epitaxial substrate 100 is preferably thermally oxidized at a temperature higher than the temperature at which silicon film 90 is thermally oxidized, for example, is thermally oxidized at 1300° C. or more.
  • As shown in FIG. 16, gate electrode 202 is formed on gate insulating film 201. Gate electrode 202 is formed in direct contact with trench insulating film 201A on p type body layer 122. A method for forming gate electrode 202 can be performed by, for example, forming a film of conductor or doped polysilicon and performing CMP (Chemical Mechanical Polishing).
  • As shown in FIG. 17, interlayer insulating film 203 is formed on gate electrode 202 and gate insulating film 201 so as to cover the exposed surface of gate electrode 202. Referring to FIG. 18, etching is performed to form openings in interlayer insulating film 203 and gate insulating film 201. Through the opening, each of n region 123 and contact region 124 is exposed on the upper surface of the mesa structure. Next, on the upper surface of the mesa structure, source electrode 221 is formed in contact with each of n region 123 and contact region 124. Referring to FIG. 1 again, source interconnection 222, drain electrode 211, and protecting electrode 212 are formed. In this way, MOSFET 500 is obtained.
  • According to MOSFET 500 (FIG. 4) of the present embodiment, electric insulation between gate electrode 202 and bottom portion BT of trench TR is secured by bottom insulating film 201B in addition to trench insulating film 201A. Bottom insulating film 201B has a low carbon atom concentration, and therefore has a high dielectric breakdown resistance. Accordingly, MOSFET 500 has a large breakdown voltage. Further, according to this MOSFET 500, gate electrode 202 is in contact with the portion of trench insulating film 201A on side wall SW. Namely, gate electrode 202 faces side wall SW that forms a channel, without bottom insulating film 201B being interposed therebetween. Thus, bottom insulating film 201B is disposed so as not to increase the threshold voltage. Accordingly, a low threshold voltage is attained without influence of bottom insulating film 201B.
  • Further, trench insulating film 201A is a thermal oxidation film of silicon carbide of epitaxial substrate 100 (see FIG. 14 and FIG. 15). This makes the trench insulating film thin and smooth. Accordingly, the breakdown voltage of MOSFET 500 can be made larger.
  • Further, bottom insulating film 201B is made of silicon oxide. In this way, the breakdown voltage of MOSFET 500 can be made larger. Further, bottom insulating film 201B is silicon film 90, i.e., a thermal oxidation film of a film containing silicon and containing no carbon. In this way, the breakdown voltage of MOSFET 500 can be made larger.
  • When t2+t3>t1, the thickness of gate insulating film 201 can be made small on side wall SW whereas the thickness thereof can be made large on bottom portion BT. Accordingly, the breakdown voltage of MOSFET 500 can be made larger while making the threshold voltage small.
  • When t3>t2, a ratio of the portion formed of bottom insulating film 201B of gate insulating film 201 becomes large on bottom portion BT. Accordingly, the breakdown voltage of MOSFET 500 can be made larger.
  • When t2<t1, a region for providing bottom insulating film 201B is further secured on bottom portion BT. Accordingly, the breakdown voltage of MOSFET 500 can be made larger.
  • When t3>100 nm, the breakdown voltage of MOSFET 500 can be made larger.
  • When bottom insulating film 201B has a carbon atom concentration of less than 1×1015 cm−3, the carbon atom concentration of bottom insulating film 201B is sufficiently low. Accordingly, the breakdown voltage of MOSFET 500 can be made larger.
  • Further, according to the present embodiment, the decrease of carbon atom concentration NC in gate insulating film 201 just above bottom portion BT of trench TR (FIG. 5) is relatively gradual as indicated by arrow d1 (FIG. 5). Accordingly, generation of stress due to the composition change in gate insulating film 201 can be suppressed. In contrast, if a gate insulating film 201Z is formed by means of thermal oxidation of epitaxial substrate 100 without bottom insulating film 201B (FIG. 15) as shown in FIG. 19, carbon atom concentration NC is drastically decreased in gate insulating film 201Z just above bottom portion BT of trench TR as indicated by arrow d2 (FIG. 5). As a result, stress is likely to be applied to gate insulating film 201Z.
  • It should be noted that in the present embodiment, the silicon oxide film serving as bottom insulating film 201B (FIG. 14) is a silicon oxide film formed through the thermal oxidation of silicon film 90 (FIG. 13), but the silicon oxide film may be formed through, for example, the CVD method instead of forming silicon film 90. Further, the material of the bottom insulating film is not limited to silicon oxide, and may be phosphorus silicate glass or silicon nitride, for example. A film made of silicon nitride can be formed by means of, for example, the CVD method.
  • Further, the “first conductivity type” corresponds to n type conductivity, and the “second conductivity type” corresponds to p type conductivity, but these conductivity types may be replaced with each other. In this case, the donor and acceptor in the foregoing description are also replaced with each other. It should be noted that in order to attain higher channel mobility, it is preferable that the “first conductivity type” corresponds to n type conductivity. Further, the silicon carbide semiconductor device is not limited to the MOSFET, and may be a trench type IGBT (Insulated Gate Bipolar Transistor), for example.
  • Second Embodiment
  • As shown in FIG. 20, a MOSFET 500 v (silicon carbide semiconductor device) of the present embodiment has a trench TRv having a V shape instead of trench TR (FIG. 4). Trench TRv has a bottom portion BTv, instead of bottom portion BT (FIG. 4). When viewed in cross section (FIG. 20), bottom portion BTv is a portion in which side walls SW facing each other make contact with each other so as to form a V shape. Apart from the configuration described above, the configuration of the present embodiment is substantially the same as the configuration of the first embodiment. Hence, the same or corresponding elements are given the same reference characters and are not described repeatedly.
  • (Surface Having Special Plane)
  • As described above, side wall SW (FIG. 1) of trench TR preferably has a predetermined crystal plane (also referred to as “special plane”) on, in particular, p type body layer 122. Such a side wall SW includes a plane S1 (first plane) having a plane orientation of {0-33-8} as shown in FIG. 21. Plane S1 preferably has a plane orientation of (0-33-8).
  • More preferably, side wall SW microscopically includes plane S1, and side wall SW microscopically further includes a plane S2 (second plane) having a plane orientation of {0-11-1}. Here, the term “microscopically” refers to “minutely to such an extent that at least the size about twice as large as an interatomic spacing is considered”. As a method for observing such a microscopic structure, for example, a TEM (Transmission Electron Microscope) can be used. Preferably, plane S2 has a plane orientation of (0-11-1).
  • Preferably, plane S1 and plane S2 of side wall SW forms a combined plane SR having a plane orientation of {0-11-2}. Specifically, combined plane SR is formed of periodically repeated planes S1 and S2. Such a periodic structure can be observed by, for example, TEM or AFM (Atomic Force Microscopy). In this case, combined plane SR has an off angle of 62° relative to the {000-1} plane, macroscopically. Here, the term “macroscopically” refers to “disregarding a fine structure having a size of approximately interatomic spacing”. For the measurement of such a macroscopic off angle, a method employing general X-ray diffraction can be used, for example. Preferably, combined plane SR has a plane orientation of (0-11-2). In this case, combined plane SR has an off angle of 62° relative to the (000-1) plane, macroscopically.
  • Preferably, in the channel surface, carriers flow in a channel direction CD, in which the above-described periodic repetition is done.
  • The following describes detailed structure of combined plane SR.
  • Generally, regarding Si atoms (or C atoms), when viewing a silicon carbide single-crystal of polytype 4H from the (000-1) plane, atoms in a layer A (solid line in the figure), atoms in a layer B (broken line in the figure) disposed therebelow, and atoms in a layer C (chain line in the figure) disposed therebelow, and atoms in a layer B (not shown in the figure) disposed therebelow are repeatedly provided as shown in FIG. 22. In other words, with four layers ABCB being regarded as one period, a periodic stacking structure such as ABCBABCBABCB . . . is provided.
  • As shown in FIG. 23, in the (11-20) plane (cross section taken along a line XXIII-XXIII of FIG. 22), atoms in each of four layers ABCB constituting the above-described one period are not aligned completely along the (0-11-2) plane. In FIG. 23, the (0-11-2) plane is illustrated to pass through the locations of the atoms in layers B. In this case, it is understood that each of atoms in layers A and C is deviated from the (0-11-2) plane. Hence, even when the macroscopic plane orientation of the surface of the silicon carbide single-crystal, i.e., the plane orientation thereof with its atomic level structure being ignored is limited to (0-11-2), this surface can have various structures microscopically.
  • As shown in FIG. 24, combined plane SR is constructed by alternately providing planes S1 having a plane orientation of (0-33-8) and planes S2 connected to planes S1 and having a plane orientation different from that of each of planes S1. Each of planes S1 and S2 has a length twice as large as the interatomic spacing of the Si atoms (or C atoms). It should be noted that a plane with plane S1 and plane S2 being averaged corresponds to the (0-11-2) plane (FIG. 23).
  • As shown in FIG. 25, when viewing combined plane SR from the (01-10) plane, the single-crystal structure has a portion periodically including a structure (plane S1 portion) equivalent to a cubic structure. Specifically, combined plane SR is constructed by alternately providing planes S1 having a plane orientation of (001) in the above-described structure equivalent to the cubic structure and planes S2 connected to planes S1 and having a plane orientation different from that of each of planes S1. Also in a polytype other than 4H, the surface can be formed of the planes (planes S1 in FIG. 25) having a plane orientation of (001) in the structure equivalent to the cubic structure and the planes (planes S2 in FIG. 25) connected to the foregoing planes and having a plane orientation different from that of each of the foregoing planes. The polytype may be, for example, 6H or 15R.
  • Referring to FIG. 26, the following describes a relation between the crystal plane of side wall SW and mobility MB of the channel surface. In the graph of FIG. 26, the horizontal axis represents an angle D1 formed by the (000-1) plane and the macroscopic plane orientation of side wall SW having the channel surface, whereas the vertical axis represents mobility MB. A group of plots CM correspond to a case where side wall SW is finished to correspond to a special plane by thermal etching, whereas a group of plots MC correspond to a case where side wall SW is not thermally etched.
  • In group of plots MC, mobility MB is at maximum when the surface of the channel surface has a macroscopic plane orientation of (0-33-8). This is presumably due to the following reason. That is, in the case where the thermal etching is not performed, i.e., in the case where the microscopic structure of the channel surface is not particularly controlled, the macroscopic plane orientation thereof corresponds to (0-33-8), with the result that a ratio of the microscopic plane orientation of (0-33-8), i.e., the plane orientation of (0-33-8) in consideration of that in atomic level becomes statistically high.
  • On the other hand, mobility MB in group of plots CM is at maximum when the macroscopic plane orientation of the channel surface is (0-11-2) (arrow EX). This is presumably due to the following reason. That is, as shown in FIG. 24 and FIG. 25, the multiplicity of planes S1 each having a plane orientation of (0-33-8) are densely and regularly arranged with planes S2 interposed therebetween, whereby a ratio of the microscopic plane orientation of (0-33-8) becomes high in the surface of the channel surface.
  • It should be noted that mobility MB has orientation dependency on combined plane SR. In a graph shown in FIG. 27, the horizontal axis represents an angle D2 between the channel direction and the <0-11-2> direction, whereas the vertical axis represents mobility MB (in any unit) in the channel surface. A broken line is supplementarily provided therein for viewability of the graph. From this graph, it has been found that in order to increase channel mobility MB, channel direction CD (FIG. 21) preferably has an angle D2 of not less than 0° and not more than 60°, more preferably, substantially 0°.
  • As shown in FIG. 28, side wall SW may further include plane S3 (third plane) in addition to combined plane SR. More specifically, side wall SW may include a combined plane SQ formed of periodically repeated plane S3 and combined plane SR. In this case, the off angle of side wall SW relative to the {000-1} plane is deviated from the ideal off angle of combined plane SR, i.e., 62°. Preferably, this deviation is small, preferably, in a range of ±10°. Examples of a surface included in such an angle range include a surface having a macroscopic plane orientation of the {0-33-8} plane. More preferably, the off angle of side wall SW relative to the (000-1) plane is deviated from the ideal off angle of combined plane SR, i.e., 62°. Preferably, this deviation is small, preferably, in a range of ±10°. Examples of a surface included in such an angle range include a surface having a macroscopic plane orientation of the (0-33-8) plane.
  • Such a periodic structure can be observed by, for example, TEM or AFM. Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the scope of the present invention being interpreted by the terms of the appended claims.

Claims (9)

What is claimed is:
1. A silicon carbide semiconductor device comprising:
a silicon carbide substrate including a first layer having first conductivity type, a second layer provided on said first layer and having second conductivity type, and a third layer provided on said second layer, separated from said first layer by said second layer, and having said first conductivity type, said silicon carbide substrate being provided with a trench having a side wall and a bottom portion, said side wall extending through said third layer and said second layer and reaching said first layer, said bottom portion being formed of said first layer;
a gate insulating film provided on said trench, said gate insulating film including a trench insulating film and a bottom insulating film, said trench insulating film covering each of said side wall and said bottom portion, said bottom insulating film being provided on said bottom portion with said trench insulating film being interposed therebetween, said bottom insulating film having a carbon atom concentration lower than that of said trench insulating film; and
a gate electrode provided in said trench, said gate electrode being in contact with a portion of said trench insulating film on said side wall.
2. The silicon carbide semiconductor device according to claim 1, wherein a total of a thickness of said trench insulating film on said bottom portion and a thickness of said bottom insulating film is larger than a thickness of said trench insulating film on said side wall.
3. The silicon carbide semiconductor device according to claim 1, wherein on said bottom portion, a thickness of said bottom insulating film is larger than that of said trench insulating film.
4. The silicon carbide semiconductor device according to claim 1, wherein a thickness of said trench insulating film on said bottom portion is smaller than a thickness of said trench insulating film on said side wall.
5. The silicon carbide semiconductor device according to claim 1, wherein the carbon atom concentration of said trench insulating film is more than 1×1015 cm−3, and the carbon atom concentration of said bottom insulating film is less than 1×1015 cm−3.
6. The silicon carbide semiconductor device according to claim 1, wherein said bottom insulating film has a thickness of more than 100 nm.
7. The silicon carbide semiconductor device according to claim 1, wherein said trench insulating film is a thermal oxidation film of silicon carbide.
8. The silicon carbide semiconductor device according to claim 1, wherein said bottom insulating film is formed of at least any one of silicon oxide, silicon nitride, and phosphorus silicate glass.
9. The silicon carbide semiconductor device according to claim 1, wherein said bottom insulating film is a thermal oxidation film of a film containing silicon and containing no carbon.
US13/958,073 2012-09-12 2013-08-02 Silicon carbide semiconductor device Abandoned US20140070233A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US13/958,073 US20140070233A1 (en) 2012-09-12 2013-08-02 Silicon carbide semiconductor device
US14/957,267 US9679986B2 (en) 2012-09-12 2015-12-02 Silicon carbide semiconductor device

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201261700084P 2012-09-12 2012-09-12
JP2012200179A JP2014056913A (en) 2012-09-12 2012-09-12 Silicon carbide semiconductor device
JP2012-200179 2012-09-12
US13/958,073 US20140070233A1 (en) 2012-09-12 2013-08-02 Silicon carbide semiconductor device

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US14/957,267 Continuation US9679986B2 (en) 2012-09-12 2015-12-02 Silicon carbide semiconductor device

Publications (1)

Publication Number Publication Date
US20140070233A1 true US20140070233A1 (en) 2014-03-13

Family

ID=50232343

Family Applications (2)

Application Number Title Priority Date Filing Date
US13/958,073 Abandoned US20140070233A1 (en) 2012-09-12 2013-08-02 Silicon carbide semiconductor device
US14/957,267 Active US9679986B2 (en) 2012-09-12 2015-12-02 Silicon carbide semiconductor device

Family Applications After (1)

Application Number Title Priority Date Filing Date
US14/957,267 Active US9679986B2 (en) 2012-09-12 2015-12-02 Silicon carbide semiconductor device

Country Status (5)

Country Link
US (2) US20140070233A1 (en)
EP (1) EP2897175A4 (en)
JP (1) JP2014056913A (en)
CN (1) CN104541376A (en)
WO (1) WO2014041879A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107658340B (en) * 2017-09-02 2019-05-21 西安交通大学 The silicon carbide MOSFET device and preparation method of a kind of low on-resistance of double grooves, small grid charge
JP7230477B2 (en) * 2018-12-12 2023-03-01 株式会社デンソー Manufacturing method of trench gate type switching element

Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010052617A1 (en) * 2000-03-01 2001-12-20 Shindengen Electric Manufacturing Co., Ltd Transistor and method of manufacturing the same
US20040089910A1 (en) * 2002-03-19 2004-05-13 Infineon Technologies Ag Power transistor
US20050167742A1 (en) * 2001-01-30 2005-08-04 Fairchild Semiconductor Corp. Power semiconductor devices and methods of manufacture
US20070037327A1 (en) * 2005-08-09 2007-02-15 Robert Herrick Structure and method for forming inter-poly dielectric in a shielded gate field effect transistor
US20070138546A1 (en) * 2005-12-15 2007-06-21 Kabushiki Kaisha Toshiba Semiconductor device
US20070190712A1 (en) * 2006-02-10 2007-08-16 Nanya Technology Corporation Semiconductor device having a trench gate and method of fabricating the same
US20090078995A1 (en) * 2007-09-20 2009-03-26 Rohm Co., Ltd. Semiconductor device and method of manufacturing semiconductor device
US20090111231A1 (en) * 2005-06-29 2009-04-30 Grebs Thomas E Method for Forming Shielded Gate Field Effect Transistor Using Spacers
US20090315083A1 (en) * 2008-06-20 2009-12-24 James Pan Structure and Method for Forming a Thick Bottom Dielectric (TBD) for Trench-Gate Devices
US20100006928A1 (en) * 2008-07-09 2010-01-14 James Pan Structure and Method for Forming a Shielded Gate Trench FET with an Inter-electrode Dielectric Having a Low-k Dielectric Therein
US20100065904A1 (en) * 2008-09-16 2010-03-18 James Pan High density trench field effect transistor
US20100193799A1 (en) * 2008-12-25 2010-08-05 Rohm Co., Ltd. Semiconductor device and method of manufacturing semiconductor device
US20110303975A1 (en) * 2005-06-10 2011-12-15 Hamza Yilmaz Field effect transistor with self-aligned source and heavy body regions
US20120184095A1 (en) * 2011-01-13 2012-07-19 Infineon Technologies Austria Ag Method for Manufacturing a Semiconductor Device
US20120217577A1 (en) * 2011-02-25 2012-08-30 Renesas Electronics Corporation Semiconductor device
US20120235229A1 (en) * 2011-03-16 2012-09-20 Probst Dean E Inter-poly dielectric in a shielded gate mosfet device

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07122749A (en) 1993-09-01 1995-05-12 Toshiba Corp Semiconductor device and its manufacture
DE69534888T2 (en) 1994-04-06 2006-11-02 Denso Corp., Kariya Manufacturing method for semiconductor device with trench
JP3471473B2 (en) 1994-04-06 2003-12-02 株式会社デンソー Semiconductor device and manufacturing method thereof
FR2738394B1 (en) 1995-09-06 1998-06-26 Nippon Denso Co SILICON CARBIDE SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD THEREOF
US5637898A (en) 1995-12-22 1997-06-10 North Carolina State University Vertical field effect transistors having improved breakdown voltage capability and low on-state resistance
JP3471509B2 (en) 1996-01-23 2003-12-02 株式会社デンソー Silicon carbide semiconductor device
US5998833A (en) 1998-10-26 1999-12-07 North Carolina State University Power semiconductor devices having improved high frequency switching and breakdown characteristics
US6291298B1 (en) 1999-05-25 2001-09-18 Advanced Analogic Technologies, Inc. Process of manufacturing Trench gate semiconductor device having gate oxide layer with multiple thicknesses
JP3664158B2 (en) * 2002-02-19 2005-06-22 日産自動車株式会社 Silicon carbide semiconductor device and manufacturing method thereof
TWI248136B (en) 2002-03-19 2006-01-21 Infineon Technologies Ag Method for fabricating a transistor arrangement having trench transistor cells having a field electrode
US6861701B2 (en) 2003-03-05 2005-03-01 Advanced Analogic Technologies, Inc. Trench power MOSFET with planarized gate bus
US6809005B2 (en) 2003-03-12 2004-10-26 Infineon Technologies Ag Method to fill deep trench structures with void-free polysilicon or silicon
JP4867171B2 (en) 2005-01-21 2012-02-01 富士電機株式会社 Manufacturing method of semiconductor device
US7648877B2 (en) 2005-06-24 2010-01-19 Fairchild Semiconductor Corporation Structure and method for forming laterally extending dielectric layer in a trench-gate FET
JP5017865B2 (en) 2006-01-17 2012-09-05 富士電機株式会社 Semiconductor device
CN101542739B (en) 2006-11-21 2011-03-23 住友电气工业株式会社 Silicon carbide semiconductor device and process for producing the same
KR100824205B1 (en) 2006-12-26 2008-04-21 매그나칩 반도체 유한회사 Dmos transistor and manufacturing method thereof
US8017404B2 (en) 2007-09-12 2011-09-13 Kao Corporation Steroid hormone assay method
JP2009088440A (en) * 2007-10-03 2009-04-23 Oki Semiconductor Co Ltd Semiconductor device and its manufacturing method
JP5452876B2 (en) * 2008-03-13 2014-03-26 ローム株式会社 Semiconductor device and manufacturing method thereof
KR101535222B1 (en) 2008-04-17 2015-07-08 삼성전자주식회사 Semiconductor device and method of fabricating the same
EP3614441B1 (en) 2008-05-20 2023-04-19 Rohm Co., Ltd. Semiconductor device
US7872305B2 (en) 2008-06-26 2011-01-18 Fairchild Semiconductor Corporation Shielded gate trench FET with an inter-electrode dielectric having a nitride layer therein
JP2010098141A (en) * 2008-10-16 2010-04-30 Sumitomo Electric Device Innovations Inc Method of manufacturing semiconductor device
JP2010129820A (en) * 2008-11-28 2010-06-10 Toyota Motor Corp Semiconductor apparatus
US8735906B2 (en) 2009-04-13 2014-05-27 Rohm Co., Ltd. Semiconductor device and method of manufacturing semiconductor device
JP2010263104A (en) 2009-05-08 2010-11-18 Elpida Memory Inc Semiconductor device and method of manufacturing the same
US8247296B2 (en) 2009-12-09 2012-08-21 Semiconductor Components Industries, Llc Method of forming an insulated gate field effect transistor device having a shield electrode structure
US8021947B2 (en) 2009-12-09 2011-09-20 Semiconductor Components Industries, Llc Method of forming an insulated gate field effect transistor device having a shield electrode structure
JP5680326B2 (en) * 2010-04-01 2015-03-04 トヨタ自動車株式会社 Manufacturing method of semiconductor device
US8487370B2 (en) 2010-07-30 2013-07-16 Infineon Technologies Austria Ag Trench semiconductor device and method of manufacturing
JP5707770B2 (en) 2010-08-03 2015-04-30 住友電気工業株式会社 Semiconductor device and manufacturing method thereof
JP2012038771A (en) * 2010-08-03 2012-02-23 Sumitomo Electric Ind Ltd Semiconductor device and manufacturing method thereof
WO2012098861A1 (en) * 2011-01-17 2012-07-26 パナソニック株式会社 Semiconductor device and method for manufacturing same
WO2012105170A1 (en) * 2011-02-02 2012-08-09 パナソニック株式会社 Semiconductor device and manufacturing method thereof

Patent Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010052617A1 (en) * 2000-03-01 2001-12-20 Shindengen Electric Manufacturing Co., Ltd Transistor and method of manufacturing the same
US20050167742A1 (en) * 2001-01-30 2005-08-04 Fairchild Semiconductor Corp. Power semiconductor devices and methods of manufacture
US20040089910A1 (en) * 2002-03-19 2004-05-13 Infineon Technologies Ag Power transistor
US20110303975A1 (en) * 2005-06-10 2011-12-15 Hamza Yilmaz Field effect transistor with self-aligned source and heavy body regions
US20090111231A1 (en) * 2005-06-29 2009-04-30 Grebs Thomas E Method for Forming Shielded Gate Field Effect Transistor Using Spacers
US20070037327A1 (en) * 2005-08-09 2007-02-15 Robert Herrick Structure and method for forming inter-poly dielectric in a shielded gate field effect transistor
US20070138546A1 (en) * 2005-12-15 2007-06-21 Kabushiki Kaisha Toshiba Semiconductor device
US20070190712A1 (en) * 2006-02-10 2007-08-16 Nanya Technology Corporation Semiconductor device having a trench gate and method of fabricating the same
US20090078995A1 (en) * 2007-09-20 2009-03-26 Rohm Co., Ltd. Semiconductor device and method of manufacturing semiconductor device
US20090315083A1 (en) * 2008-06-20 2009-12-24 James Pan Structure and Method for Forming a Thick Bottom Dielectric (TBD) for Trench-Gate Devices
US20100006928A1 (en) * 2008-07-09 2010-01-14 James Pan Structure and Method for Forming a Shielded Gate Trench FET with an Inter-electrode Dielectric Having a Low-k Dielectric Therein
US20100065904A1 (en) * 2008-09-16 2010-03-18 James Pan High density trench field effect transistor
US20100193799A1 (en) * 2008-12-25 2010-08-05 Rohm Co., Ltd. Semiconductor device and method of manufacturing semiconductor device
US20120184095A1 (en) * 2011-01-13 2012-07-19 Infineon Technologies Austria Ag Method for Manufacturing a Semiconductor Device
US20120217577A1 (en) * 2011-02-25 2012-08-30 Renesas Electronics Corporation Semiconductor device
US20120235229A1 (en) * 2011-03-16 2012-09-20 Probst Dean E Inter-poly dielectric in a shielded gate mosfet device

Non-Patent Citations (8)

* Cited by examiner, † Cited by third party
Title
Akashi et al. SIMS study of SiC single crystal oxidized in atmosphere containing isotopic water vapor, Journal of the Ceramic Society of Japan, Vol. 116, No. 1357, (2008) pp. 960-964. *
Chang et al. High-carbon concentrations at the silicon dioxide-silicon carbide interface identified by electron energy loss spectroscopy, Appl. Phys. Lett. 77, 2000, pp. 2186-2188. *
Chang et al. Nanoscale Characterization of the Silicon Dioxide-Silicon Carbide Interface Using Elemental Mapping by Energy-Filtered Transmission Electron Microscopy, Journal Electronic Materials, Vol. 32, No. 5, 2003, pp. 464-469. *
Chaudhry et al. A study of native oxides of beta-SiC using Auger electron spectroscopy, J. Mater. Res., Vol. 4, No. 2, Mar/Apr 1989, pp. 404-407. *
Hijikata et al. Composition analysis of SiO2/SiC interfaces by electron spectroscopic measurements using slope-shaped oxide films, Applied Surface Science, Vol. 184, 2001, pp. 161-166. *
Lu et al. Thermal Oxidation of Sputtered Silicon Carbide Thin Films, J. Electrochem. Soc. 1984 volume 131, issue 8, pp. 1907-1914. *
Poggi et al. Characterization of a thermal oxidation process on SiC preamorphized by Ar ion implantation, Materials Science Forum Vols 457-460 (2004) pp 1357-1360. *
Vathulya et al. "On the correlation between the carbon content and the electrical quality of thermally grown oxides on p-type 6H-silicon carbide." Appl. Phys. Lett., vol. 73, pp. 2161-2163, (1988). *

Also Published As

Publication number Publication date
EP2897175A4 (en) 2016-06-01
CN104541376A (en) 2015-04-22
US9679986B2 (en) 2017-06-13
WO2014041879A1 (en) 2014-03-20
US20160087065A1 (en) 2016-03-24
EP2897175A1 (en) 2015-07-22
JP2014056913A (en) 2014-03-27

Similar Documents

Publication Publication Date Title
US9276106B2 (en) Silicon carbide semiconductor device and method for manufacturing same
US8952393B2 (en) Silicon carbide semiconductor device
US9000447B2 (en) Silicon carbide semiconductor device
US9627487B2 (en) Method for manufacturing silicon carbide semiconductor device and silicon carbide semiconductor device
US20160126347A1 (en) Silicon carbide semiconductor device
US10192967B2 (en) Silicon carbide semiconductor with trench gate
US20170207311A1 (en) Silicon carbide semiconductor device and method for manufacturing same
US9543412B2 (en) Method for manufacturing silicon carbide semiconductor device
JP6443531B2 (en) Silicon carbide semiconductor device
US8927368B2 (en) Method for manufacturing silicon carbide semiconductor device
US9299790B2 (en) Silicon carbide semiconductor device
US9679986B2 (en) Silicon carbide semiconductor device
US8878192B2 (en) Silicon carbide semiconductor device
US20140042460A1 (en) Silicon carbide semiconductor device
US9793365B2 (en) Method for manufacturing silicon carbide semiconductor device having trench
US20130341648A1 (en) Method for manufacturing silicon carbide semiconductor device and silicon carbide semiconductor device
US20130306987A1 (en) Silicon carbide semiconductor device and method for manufacturing same

Legal Events

Date Code Title Description
AS Assignment

Owner name: SUMITOMO ELECTRIC INDUSTRIES, LTD., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MASUDA, TAKEYOSHI;SAITOH, YU;HAYASHI, HIDEKI;AND OTHERS;SIGNING DATES FROM 20130624 TO 20130626;REEL/FRAME:030934/0094

STCB Information on status: application discontinuation

Free format text: ABANDONED -- AFTER EXAMINER'S ANSWER OR BOARD OF APPEALS DECISION