US20130307122A1 - Bipolar transistor with embedded epitaxial external base region and method of forming the same - Google Patents

Bipolar transistor with embedded epitaxial external base region and method of forming the same Download PDF

Info

Publication number
US20130307122A1
US20130307122A1 US13/625,211 US201213625211A US2013307122A1 US 20130307122 A1 US20130307122 A1 US 20130307122A1 US 201213625211 A US201213625211 A US 201213625211A US 2013307122 A1 US2013307122 A1 US 2013307122A1
Authority
US
United States
Prior art keywords
base region
forming
layer
external base
bipolar transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US13/625,211
Inventor
Yu-dong Wang
Jun Fu
Jie Cui
Yue Zhao
Zhi-hong Liu
Wei Zhang
Gao-qing Li
Zheng-li Wu
Ping Xu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tsinghua University
Original Assignee
Tsinghua University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to CN201210153148.X priority Critical
Priority to CN 201210153410 priority patent/CN102651384B/en
Priority to CN201210153063.1 priority
Priority to CN201210153410.0 priority
Priority to CN 201210153063 priority patent/CN102664190B/en
Priority to CN201210153148.XA priority patent/CN102651390B/en
Application filed by Tsinghua University filed Critical Tsinghua University
Assigned to TSINGHUA UNIVERSITY reassignment TSINGHUA UNIVERSITY ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CUI, JIE, FU, JUN, LI, Gao-qing, LIU, Zhi-hong, WANG, Yu-dong, WU, Zheng-li, XU, PING, ZHANG, WEI, ZHAO, YUE
Publication of US20130307122A1 publication Critical patent/US20130307122A1/en
Application status is Abandoned legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234Bipolar junction transistors [BJT]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004Base region of bipolar transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234Bipolar junction transistors [BJT]
    • H01L29/66242Heterojunction transistors [HBT]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73Bipolar junction transistors
    • H01L29/737Hetero-junction transistors
    • H01L29/7371Vertical transistors
    • H01L29/7378Vertical transistors comprising lattice mismatched active layers, e.g. SiGe strained layer transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0804Emitter regions of bipolar transistors
    • H01L29/0817Emitter regions of bipolar transistors of heterojunction bipolar transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/207Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds further characterised by the doping material

Abstract

The present invention discloses a bipolar transistor with an embedded epitaxial external base region, which is designed to solve the problem of the TED effect with the prior art structures. The bipolar transistor with an embedded epitaxial external base region of the present invention comprises at least a collector region, a base region and an external base region on the collector region, an emitter on the base region, and sidewalls at both sides of the emitter. The external base region is grown through an in-situ doping selective epitaxy process and is embedded in the collector region. A portion of the external base region is located beneath the sidewalls. The present invention discloses a method of forming a bipolar transistor with an embedded epitaxial external base region. The bipolar transistor with an embedded epitaxial external base region of the present invention avoids the TED effect and reduces the resistance of the external base region of the device so that the performance of the device is improved. The method of forming a bipolar transistor with an embedded epitaxial external base region of the present invention achieves the aforesaid bipolar transistor with an embedded epitaxial external base region, and features concise steps, a low cost and simple operations, and the structure obtained has good performance.

Description

    BACKGROUND OF THE INVENTION
  • 1. Technical Field
  • The present invention relates to a bipolar transistor with an embedded epitaxial external base region and a method of forming the same.
  • 2. Description of Related Art
  • Millimeter wave and terahertz (THZ) applications will become the future development trend of wireless technologies, examples of which are millimeter wave communication, THZ communication, THZ imaging and the like. Currently, implementation of these applications mainly relies on Group III-V compound devices, and this has shortcomings such as a low integration level and a high cost. With the continuous development of the technologies, SiGe devices and technologies will become a competitor of the Group III-V compound devices. Currently, the SiGe technologies are widely used in such fields as communication, radar and high-speed circuits. The cut-off frequency Ft of the commercial SiGe process of the IBM has reached 350 GHz, and the maximum oscillation frequency Fmax of the SiGe devices developed by the European IHP has reached 500 GHz at the normal temperature. For the future millimeter wave and THZ applications, the SiGe devices still need to be continuously improved in performance, and this requires a novel structure for the SiGe devices.
  • External base regions of conventional bipolar transistors are usually processed through ion implantation and the performance of the resulting structures has shortcomings such as transient enhanced diffusion (TED) effect which will degrade the microwave performance of the devices. Some novel SiGe Heterojunction bipolar devices are formed by raised extrinsic base regions, but the external base regions beneath sidewalls in the resulting structures have a relatively large resistance, which reduces the microwave performance of the devices.
  • BRIEF SUMMARY OF THE INVENTION
  • To overcome the aforesaid shortcomings, the present invention provides a bipolar transistor with an embedded epitaxial external base region which can avoid the TED effect.
  • To achieve the aforesaid objective, in an aspect, the present invention provides a bipolar transistor with an embedded epitaxial external base region, which comprises at least a collector region, a base region and an external base region on the collector region, an emitter on the base region, and sidewalls at both sides of the emitter. The external base region is grown through an in-situ doping selective epitaxy process and is embedded in the collector region.
  • Particularly, a portion of the external base region is located beneath the sidewalls.
  • In another aspect, the present invention provides a method of forming a bipolar transistor with an embedded epitaxial external base region, which comprises at least the following steps:
  • 3.1 forming a collector region of a first doping type;
  • 3.2 forming a base region of a second doping type on the resulting structure of the step 3.1;
  • 3.3 depositing a first dielectric layer on the base region;
  • 3.4 opening a window in the first dielectric layer;
  • 3.5 forming a polycrystalline layer of the first doping type and a second dielectric layer in sequence on the resulting structure of the step 3.4;
  • 3.6 etching the second dielectric layer and the polycrystalline layer through photolithography to form an emitter, and removing exposed portions of the first dielectric layer;
  • 3.7 depositing a third dielectric layer and forming a sidewall structure on a side surface of the resulting emitter structure through an anisotropic etching process;
  • 3.8 etching portions of the base region that are not covered in the resulting structure of the step 3.7 by using the emitter and the sidewall structure as a mask, with an etching thickness being greater than a thickness of the base region;
  • 3.9 forming an external base region of the second doping type on the resulting structure of the step 3.8 through an in-situ doping selective epitaxy process;
  • 3.10 forming a layer of metal silicide structure on a surface of the external base region; and
  • 3.11 forming a contact hole on the resulting structure of the step 3.10 to lead out an electrode of the emitter and an electrode of the base region.
  • Particularly, the polycrystalline layer of the step 3.5 is a polysilicon layer or a poly-SiGe layer, and the dielectric layers are formed of silicon oxide or silicon nitride.
  • Particularly, the etching thickness of the step 3.8 ranges between 10 nm and 2000 nm, and the sidewall is undercut during the etching of the base region.
  • In a further aspect, the present invention provides a method of forming a bipolar transistor with an embedded epitaxial external base region, which comprises at least the following steps:
  • 6.1 forming a collector region of a first doping type;
  • 6.2 forming a base region of a second doping type on the resulting structure of the step 6.1;
  • 6.3 forming a first dielectric layer on the base region;
  • 6.4 removing exposed portions of the first dielectric layer through photolithography to form a sacrifice emitter;
  • 6.5 etching portions of the base region that are not covered by the sacrifice emitter, with an etching thickness being greater than a thickness of the base region;
  • 6.6 forming an external base region of the second doping type on the resulting structure of the step 6.5;
  • 6.7 depositing a second dielectric layer to form a planarized surface that exposes a top surface of the sacrifice emitter;
  • 6.8 removing portions of a surface layer of the sacrifice emitter to obtain a window, and forming an inner sidewall structure on an inner sidewall of the window;
  • 6.9 removing portions of the sacrifice emitter which are not covered by the inner sidewall;
  • 6.10 depositing a polycrystalline layer;
  • 6.11 removing edge portions of the polycrystalline layer of the step 6.10 and the second dielectric layer of the step 6.7 to form an emitter;
  • 6.12 depositing a metal material on surfaces of the external base region and the emitter to form a metal silicide; and 6.13 forming a contact hole on the resulting structure of the step 6.12 to lead out an electrode of the emitter and an electrode of the base region.
  • Particularly, the base region is formed of silicon (Si), SiGe or carbon-doped SiGe.
  • Particularly, the first dielectric layer is a composite dielectric layer, which comprises a silicon oxide layer deposited on a surface of the base region and a silicon nitride layer deposited on a surface of the silicon oxide layer.
  • In yet another aspect, the present invention provides a method of forming a bipolar transistor with an embedded epitaxial external base region, which comprises at least the following steps:
  • 9.1 forming a collector region of a first doping type;
  • 9.2 forming a base region of a second doping type on the resulting structure of the step 9.1;
  • 9.3 depositing a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer in sequence on the resulting structure of the step 9.2;
  • 9.4 opening a window in the second silicon oxide layer and the silicon nitride layer;
  • 9.5 removing portions of the first silicon oxide layer that are within the window to expose the base region and to form an emitter window;
  • 9.6 depositing a polycrystalline layer on the resulting structure of the step 9.5;
  • 9.7 planarizing the resulting structure of the step 9.6 to expose the second silicon oxide layer;
  • 9.8 removing the second silicon oxide layer and portions of the silicon nitride layer that are not covered by the polycrystalline layer;
  • 9.9 forming a first sidewall on a side surface of the polycrystalline layer, and removing portions of the first silicon oxide layer that are not covered by the first sidewall;
  • 9.10 etching portions of the base region that are not covered, with an etching thickness being greater than a thickness of the base region;
  • 9.11 forming an external base region of the second doping type on the resulting structure of the step 9.10;
  • 9.12 depositing a dielectric layer to form a second sidewall outside the first sidewall;
  • 9.13 depositing a metal layer on the resulting structure of the step 9.12, forming a metal silicide on the external base region and forming a metal silicide on the polycrystalline layer; and
  • 9.14 forming a contact hole on the resulting structure of the step 9.13 to lead out an electrode of the emitter and an electrode of the base region.
  • Particularly, the base region is made of Si or SiGe.
  • Particularly, the sidewall is undercut during the etching of the base region.
  • Particularly, the metal deposited is one of Ti, Co or Ni.
  • Particularly, the external base region is formed through an epitaxy growth process, the external base region is formed of Si, SiGe or carbon-doped SiGe, and the impurity is doped at a concentration of 1E19 to 1E21 cm−3.
  • The bipolar transistor with an embedded epitaxial external base region of the present invention is provided with an embedded epitaxial base region, and can avoid the TED effect and also reduce the resistance of the external base region of the device so that the performance of the device is improved.
  • The method of forming a bipolar transistor with an embedded epitaxial external base region of the present invention achieves the aforesaid bipolar transistor with an embedded epitaxial external base region. The second and the third methods achieve the aforesaid bipolar transistor with an embedded epitaxial external base region through self alignment, and feature concise steps, a low cost and simple operations, and the structures obtained have good performance.
  • BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
  • FIG. 1 to FIG. 7 are schematic flowchart diagrams of a first preferred embodiment of the present invention;
  • FIG. 8 to FIG. 17 are schematic flowchart diagrams of a second preferred embodiment of the present invention; and
  • FIG. 18 to FIG. 28 are schematic flowchart diagrams of a third preferred embodiment of the present invention.
  • DETAILED DESCRIPTION OF THE INVENTION
  • Hereinbelow, the present invention will be described in detail with reference to the attached drawings and preferred embodiments thereof.
  • A bipolar transistor with an embedded epitaxial external base region of the present invention comprises at least a collector region, a base region and an external base region on the collector region, an emitter on the base region, and sidewalls at both sides of the emitter. The external base region is grown through an in-situ doping selective epitaxy process and is embedded in the collector region.
  • Preferably, a portion of the external base region is located beneath the sidewalls. That is, when the structure is formed, a certain degree of undercutting is performed so that the performance of the bipolar transistor with an embedded epitaxial external base region of the present invention is improved.
  • The structure of the present invention is not limited to the Si bipolar transistor, and may also be made of other materials such as SiGe or Group III-V compounds.
  • The bipolar transistor with an embedded epitaxial external base region of the present invention is provided with the embedded epitaxial base region, and can avoid the TED effect and also reduce the resistance of the external base region of the device so that the performance of the device is improved.
  • The bipolar transistor with an embedded epitaxial external base region of the present invention at least comprises three kinds of basic structures. To achieve the three kinds of structures, the present invention provides three forming methods correspondingly.
  • Structure I: as shown in FIG. 1, a collector region 101 of a first doping type is formed. A layer of doped base region 102 of a second doping type is formed on the collector region 101 through an epitaxy growth process. The base region 102 may be formed of Si, SiGe or carbon-doped SiGe. A first dielectric layer is deposited on the base region 102. The first dielectric layer is preferably a composite dielectric layer, which comprises a silicon oxide layer 104 and a silicon nitride layer 106 in sequence from bottom to top. The silicon oxide layer is an etch stop layer.
  • As shown in FIG. 2, the silicon nitride layer 106 is etched through photolithography to form an emitter window, and then the silicon oxide layer 104 is selectively etched to expose monocrystals of the base region 102. The selective etching may be achieved through dry etching or wet etching
  • As shown in FIG. 3, a polycrystalline layer 108 and a second dielectric layer 110 are deposited. The polycrystalline layer 108 may be a polysilicon layer or a poly-SiGe layer. The polycrystalline layer 108 needs to be doped and may be doped through ion implantation or in-situ doping, and the impurity is of the first doping type. The dielectric layer 110 may be a silicon oxide layer or a silicon nitride layer.
  • As shown in FIG. 4, the second dielectric layer 110 and the polycrystalline layer 108 are etched through photolithography to form an emitter, and exposed portions of the silicon oxide layer 104 and the silicon nitride layer 106 are removed to expose the monocrystals of the base region 102.
  • As shown in FIG. 5, a third dielectric layer is deposited, and a sidewall structure 113 is formed on a side surface of the resulting emitter structure through an anisotropic etching process.
  • As shown in FIG. 6, by using the emitter structure as a mask, the epitaxial base region 102 is etched to the collector region 101 to obtain an etched region 115. The main purpose of this step is to reduce the TED effect. To reduce the resistance of the external base region, an etching thickness shall be greater than a thickness of the epitaxial base region 102. The preferred etching thickness ranges between 10 nm and 2000 nm. It is best to perform a certain degree of undercutting, which can further reduce the resistance of the external base region.
  • As shown in FIG. 7, a layer of external base region 120 is formed on the etched structure through an in-situ doping selective epitaxy process. The epitaxial layer may be formed of Si, SiGe or carbon-doped SiGe. The impurity is of the second doping type. In order to reduce the resistance of the external base region 120, the doping concentration shall be as high as possible and is generally from 1E19 to 1E21 cm−3. For an NPN device, the impurity is generally boron.
  • A layer of metal silicide structure is formed on a surface of the external base region. Then, a contact hole is formed on the resulting structure to lead out an electrode of the emitter and an electrode of the base region. The method of forming a bipolar transistor with an embedded epitaxial external base region of the present invention achieves the aforesaid bipolar transistor with an embedded epitaxial external base region, and features concise steps, a low cost and simple operations, and the structure obtained has good performance.
  • Preferred embodiment I: as shown in FIG. 1 to FIG. 7, a collector region 101 of a first doping type is formed, and a layer of doped base region 102 is formed on the collector region 101 through an epitaxy growth process, with the base region being carbon-doped SiGe of a second doping type. A silicon oxide layer 104 and a silicon nitride layer 106 are deposited on the base region 102 in sequence.
  • The silicon nitride layer 106 is etched through photolithography to form an emitter window, and then the silicon oxide layer 104 is dry etched to expose monocrystals of the base region 102. A polysilicon layer 108 and a silicon oxide layer 110 are deposited. The polysilicon layer 108 of the first doping type is obtained through in-situ doping. The second dielectric layer 110 and the polycrystalline layer 108 are etched through photolithography to form an emitter. Exposed portions of the silicon oxide layer 104 and the silicon nitride layer 106 are removed to expose the monocrystals of the base region 102.
  • A third dielectric layer is deposited, and a sidewall structure 113 is formed on a side surface of the resulting emitter structure through an anisotropic etching process. By using the emitter structure as a mask, the epitaxial base region 102 is etched to the collector region 101 to obtain an etched region 115, with the etching thickness being 1000 nm and undercutting being performed concomitantly.
  • A layer of Si external base region 120 is formed on the etched structure through an in-situ doping selective epitaxy process, with the impurity being boron and the doping concentration being 1E20 cm−3. A layer of metal silicide structure is formed on a surface of the external base region. Then, a contact hole is formed on the resulting structure to lead out an electrode of the emitter and an electrode of the base region. Thus, the device is finished.
  • Structure II: as shown in FIG. 8, a collector region 201 of a first doping type is formed. A layer of doped base region 202 of a second doping type is formed on the collector region 201 through an epitaxy growth process. The base region 202 may be formed of Si or SiGe. A dielectric layer is deposited on the base region 202. The dielectric layer is preferably a composite dielectric layer, which comprises a silicon oxide layer 204 and a silicon nitride layer 206 in sequence from bottom to top. The silicon oxide layer is an etch stop layer.
  • As shown in FIG. 9, the silicon nitride layer 206 and the silicon oxide layer 204 are etched through photolithography to form a sacrifice emitter.
  • As shown in FIG. 10, the epitaxial base region 202 is etched to the collector region 201 to form an etched structure 210. The main purpose of this step is to reduce the TED effect. To reduce the resistance of the external base region, an etching thickness shall be greater than a thickness of the epitaxial base region 202. It is best to perform a certain degree of undercutting, which can further reduce the resistance of the external base region.
  • As shown in FIG. 11, a layer of external base region 220 is formed through an in-situ doping selective epitaxy process. The epitaxial layer may be formed of Si or SiGe. In order to reduce the resistance of the external base region, the doping concentration shall be as high as possible and is generally from 1E19 to 1E21 cm−3.
  • As shown in FIG. 12, a silicon oxide layer 212 is deposited and then planarized through a chemical mechanical planarization (CMP) process or an etch-back process to expose the silicon nitride layer 206 of the sacrifice emitter.
  • As shown in FIG. 13, the silicon nitride layer 206 of the sacrifice emitter is removed through wet etching, and then a layer of silicon nitride is deposited and formed into an inner sidewall 214 through an anisotropic etching process.
  • As shown in FIG. 14, portions of the silicon oxide layer 204 in an emitter window which are not covered by the inner sidewall 214 are removed through a selective dry etching process or a selective wet etching process.
  • As shown in FIG. 15, a polycrystalline layer 224 is deposited on the resulting structure.
  • As shown in FIG. 16, the polycrystalline layer 224 and the silicon oxide layer 212 are etched through photolithography in sequence to form an emitter.
  • As shown in FIG. 17, a metal material is deposited on surfaces of the external base region 220 and the emitter and then annealed to form a metal silicide structure 228. The metal deposited may be one of Ti, Co or Ni, but is not limited thereto.
  • A contact hole is formed on the resulting structure to lead out an electrode of the emitter and an electrode of the base region.
  • Preferred embodiment II: as shown in FIG. 8 to FIG. 17, a collector region 201 of a first doping type is formed. A layer of SiGe-doped base region 202 of a second doping type is formed on the collector region 201 through an epitaxy growth process. A silicon oxide layer 204 and a silicon nitride layer 206 are deposited in sequence on the base region 202.
  • The silicon nitride layer 206 and the silicon oxide layer 204 are etched through photolithography to form a sacrifice emitter. The epitaxial base region 202 is etched to the collector region 201 to form an etched structure 210. An etching thickness is greater than a thickness of the epitaxial base region 202, and a certain degree of undercutting is performed. A layer of SiGe external base region 220 is formed through an in-situ doping selective epitaxy process, with the doping concentration being 1E20 cm−3.
  • A silicon oxide layer 212 is deposited and then planarized through an etch-back process to expose the silicon nitride layer 206 of the sacrifice emitter. The silicon nitride layer 206 of the sacrifice emitter is removed through wet etching, and then a layer of silicon nitride is deposited and formed into an inner sidewall 214 through an anisotropic etching process. Portions of the silicon oxide layer 204 in an emitter window which are not covered by the inner sidewall 214 are removed through a selective dry etching process.
  • A polycrystalline layer 224 is deposited on the resulting structure, and the polycrystalline layer 224 and the silicon oxide layer 212 are etched through photolithography in sequence to form an emitter. Ti is deposited on surfaces of the external base region 220 and the emitter and then annealed to form a metal silicide structure 228. A contact hole is formed on the resulting structure to lead out an electrode of the emitter and an electrode of the base region.
  • Structure III: as shown in FIG. 18, a collector region 301 of a first doping type is formed. A layer of doped base region 302 of a second doping type is formed on the collector region 301 through an epitaxy growth process. The base region 302 may be formed of Si or SiGe. On the base region 302 is deposited a dielectric layer, which comprises a first silicon oxide layer 304, a silicon nitride layer 306 and a second silicon oxide layer 308 in sequence from bottom to top. The second silicon oxide layer 308 is an etch stop layer for protecting the epitaxial base region 302 from being damaged in such processes as the etching process.
  • As shown in FIG. 19, the second silicon oxide layer 308 and the silicon nitride layer 306 are etched through photolithography to form a window.
  • As shown in FIG. 20, a window is opened in the first silicon oxide layer 304 through a selective dry etching process or a selective wet etching process to form an emitter window.
  • As shown in FIG. 21, a first polycrystalline layer 310 is deposited on the resulting structure, with the first polycrystalline layer 310 being filled in the emitter window and also covering a surface of the resulting structure.
  • As shown in FIG. 22, a surface layer of the first polycrystalline layer 310 is removed, and the first polycrystalline layer 310 is planarized to the second silicon oxide layer 308. Then, peripheral portions of the dielectric layer are removed through a CMP process or an etch-back process.
  • As shown in FIG. 23, the second silicon oxide layer 308 and portions of the silicon nitride layer 306 that are not covered by the first polycrystalline layer 310 are removed through a selective etching process.
  • As shown in FIG. 24, a silicon nitride dielectric layer is deposited on the resulting structure and then etched into a first sidewall 312 structure; and then, portions of the first silicon oxide layer 304 that are not covered by the first sidewall 312 are etched off.
  • As shown in FIG. 25, the external base region 302 is etched to the collector region 301 to form an etched structure 314. The main purpose of this step is to reduce the TED effect. To reduce the resistance of the external base region, an etching thickness shall be greater than a thickness of the epitaxial base region 302. It is best to perform a certain degree of undercutting, which can further reduce the resistance of the external base region. In the etching process, a portion of a surface of the first polycrystalline layer on the emitter is also etched off.
  • As shown in FIG. 26, a layer of external base region 320 is formed through an in-situ doping selective epitaxy process. The epitaxial layer may be formed of Si or SiGe. In order to reduce the resistance of the external base region 320, the doping concentration shall be as high as possible and is generally from 1E19 to 1E21 cm−3. A second polycrystalline layer 318 is also deposited on the emitter.
  • As shown in FIG. 27, a dielectric layer (e.g., a silicon nitride dielectric layer) is deposited and then etched into a second sidewall 313 at the position of the first sidewall 312.
  • As shown in FIG. 28, a metal layer is deposited on the resulting structure, a metal silicide 324 is formed on the external base region 320 and a metal silicide 324 is formed on the second polycrystalline layer 318.
  • A contact hole is formed on the resulting structure to lead out an electrode of the emitter and an electrode of the base region.
  • Preferred embodiment III: as shown in FIG. 18 to FIG. 28, a collector region 301 of a first doping type is formed. A layer of Si-doped base region 302 of a second doping type is formed on the collector region 301 through an epitaxy growth process. On the base region 302 is deposited a dielectric layer, which comprises a first silicon oxide layer 304, a silicon nitride layer 306 and a second silicon oxide layer 308 in sequence from bottom to top. The second silicon oxide layer 308 and the silicon nitride layer 306 are etched through photolithography to form a window.
  • A window is opened in the first silicon oxide layer 304 through a selective dry etching process to form an emitter window. A first polycrystalline layer 310 is deposited on the resulting structure, with the first polycrystalline layer 310 being filled in the emitter window and also covering a surface of the resulting structure. A surface layer of the first polycrystalline layer 310 is removed, and the first polycrystalline layer 310 is planarized to the second silicon oxide layer 308. Then, peripheral portions of the dielectric layer are removed through a CMP process.
  • The second silicon oxide layer 308 and portions of the silicon nitride layer 306 that are not covered by the first polycrystalline layer 310 are removed through a selective etching process. A silicon nitride dielectric layer is deposited on the resulting structure and then etched into a first sidewall 312 structure; and then, portions of the first silicon oxide layer 304 that are not covered by the first sidewall 312 are etched off.
  • The external base region 302 is etched to the collector region 301 to form an etched structure 314, with an etching thickness being greater than a thickness of the epitaxial base region 302 and a certain degree of undercutting being performed concomitantly. In the etching process, a portion of a surface of the first polycrystalline layer on the emitter is also etched off.
  • A layer of Si external base region 320 is formed through an in-situ doping selective epitaxy process, with the doping concentration being 1E20 cm−3. A second polycrystalline layer 318 is also deposited on the emitter. A silicon nitride dielectric layer is deposited and then etched into a second sidewall 313 at the position of the first sidewall 312. A metal layer is deposited on the resulting structure, a metal silicide 324 is formed on the external base region 320 and a metal silicide 324 is formed on the second polycrystalline layer 318. A contact hole is formed on the resulting structure to lead out an electrode of the emitter and an electrode of the base region.
  • What described above are only preferred embodiments of the present invention but are not intended to limit the scope of the present invention. Accordingly, any modifications or substitutions that can be readily devised by those skilled in the art within the technical scope of the present invention shall also fall within the scope of the present invention. Therefore, the protective scope of the present invention shall be governed by the claims.

Claims (19)

1. A bipolar transistor with an embedded epitaxial external base region, comprising at least a collector region, a base region and an external base region on the collector region, an emitter on the base region, and sidewalls at both sides of the emitter, wherein the external base region is grown through an in-situ doping selective epitaxy process and is embedded in the collector region.
2. The bipolar transistor with an embedded epitaxial external base region of claim 1, wherein a portion of the external base region is located beneath the sidewalls.
3. A method of forming a bipolar transistor with an embedded epitaxial external base region, comprising at least the following steps:
3.1 forming a collector region of a first doping type;
3.2 forming a base region of a second doping type on the resulting structure of the step 3.1;
3.3 depositing a first dielectric layer on the base region;
3.4 opening a window in the first dielectric layer;
3.5 forming a polycrystalline layer of the first doping type and a second dielectric layer in sequence on the resulting structure of the step 3.4;
3.6 etching the second dielectric layer and the polycrystalline layer through photolithography to form an emitter, and removing exposed portions of the first dielectric layer;
3.7 depositing a third dielectric layer and forming a sidewall structure on a side surface of the resulting emitter structure through an anisotropic etching process;
3.8 etching portions of the base region that are not covered in the resulting structure of the step 3.7 by using the emitter and the sidewall structure as a mask, with an etching thickness being greater than a thickness of the base region;
3.9 forming an external base region of the second doping type on the resulting structure of the step 3.8 through an in-situ doping selective epitaxy process;
3.10 forming a layer of metal silicide structure on a surface of the external base region; and
3.11 forming a contact hole on the resulting structure of the step 3.10 to lead out an electrode of the emitter and an electrode of the base region.
4. The method of forming a bipolar transistor with an embedded epitaxial external base region of claim 3, wherein the polycrystalline layer of the step 3.5 is a polysilicon layer or a poly-SiGe layer, and the dielectric layers are formed of silicon oxide or silicon nitride.
5. The method of forming a bipolar transistor with an embedded epitaxial external base region of claim 3, wherein the etching thickness of the step 3.8 ranges between 10 nm and 2000 nm, and the sidewall is undercut during the etching of the base region.
6. A method of forming a bipolar transistor with an embedded epitaxial external base region, comprising at least the following steps:
6.1 forming a collector region of a first doping type;
6.2 forming a base region of a second doping type on the resulting structure of the step 6.1;
6.3 forming a first dielectric layer on the base region;
6.4 removing exposed portions of the first dielectric layer through photolithography to form a sacrifice emitter;
6.5 etching portions of the base region that are not covered by the sacrifice emitter, with an etching thickness being greater than a thickness of the base region;
6.6 forming an external base region of the second doping type on the resulting structure of the step 6.5;
6.7 depositing a second dielectric layer to form a planarized surface that exposes a top surface of the sacrifice emitter;
6.8 removing portions of a surface layer of the sacrifice emitter to obtain a window, and forming an inner sidewall structure on an inner sidewall of the window;
6.9 removing portions of the sacrifice emitter which are not covered by the inner sidewall;
6.10 depositing a polycrystalline layer;
6.11 removing edge portions of the polycrystalline layer of the step 6.10 and the second dielectric layer of the step 6.7 to form an emitter;
6.12 depositing a metal material on surfaces of the external base region and the emitter to form a metal silicide; and
6.13 forming a contact hole on the resulting structure of the step 6.12 to lead out an electrode of the emitter and an electrode of the base region.
7. The method of forming a bipolar transistor with an embedded epitaxial external base region of claim 6, wherein the base region is formed of silicon (Si), SiGe or carbon-doped SiGe.
8. The method of forming a bipolar transistor with an embedded epitaxial external base region of claim 6, wherein the first dielectric layer is a composite dielectric layer, which comprises a silicon oxide layer deposited on a surface of the base region and a silicon nitride layer deposited on a surface of the silicon oxide layer.
9. A method of forming a bipolar transistor with an embedded epitaxial external base region, comprising at least the following steps:
9.1 forming a collector region of a first doping type;
9.2 forming a base region of a second doping type on the resulting structure of the step 9.1;
9.3 depositing a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer in sequence on the resulting structure of the step 9.2;
9.4 opening a window in the second silicon oxide layer and the silicon nitride layer;
9.5 removing portions of the first silicon oxide layer that are within the window to expose the base region and to form an emitter window;
9.6 depositing a polycrystalline layer on the resulting structure of the step 9.5;
9.7 planarizing the resulting structure of the step 9.6 to expose the second silicon oxide layer;
9.8 removing the second silicon oxide layer and portions of the silicon nitride layer that are not covered by the polycrystalline layer;
9.9 forming a first sidewall on a side surface of the polycrystalline layer, and removing portions of the first silicon oxide layer that are not covered by the first sidewall;
9.10 etching portions of the base region that are not covered, with an etching thickness being greater than a thickness of the base region;
9.11 forming an external base region of the second doping type on the resulting structure of the step 9.10;
9.12 depositing a dielectric layer to form a second sidewall outside the first sidewall;
9.13 depositing a metal layer on the resulting structure of the step 9.12, forming a metal silicide on the external base region and forming a metal silicide on the polycrystalline layer; and
9.14 forming a contact hole on the resulting structure of the step 9.13 to lead out an electrode of the emitter and an electrode of the base region.
10. The method of forming a bipolar transistor with an embedded epitaxial external base region of claim 9, wherein the base region is made of Si or SiGe.
11. The method of forming a bipolar transistor with an embedded epitaxial external base region of claim 9, wherein the sidewall is undercut during the etching of the base region.
12. The method of forming a bipolar transistor with an embedded epitaxial external base region of claim 9, wherein the metal deposited is one of Ti, Co or Ni.
13. The method of forming a bipolar transistor with an embedded epitaxial external base region of claim 9, wherein the external base region is formed through an epitaxy growth process, the external base region is formed of Si, SiGe or carbon-doped SiGe, and the impurity is doped at a concentration of 1E19 to 1E21 cm−3.
14. The method of forming a bipolar transistor with an embedded epitaxial external base region of claim 3, wherein the base region is formed of silicon (Si), SiGe or carbon-doped SiGe.
15. The method of forming a bipolar transistor with an embedded epitaxial external base region of claim 3, wherein the first dielectric layer is a composite dielectric layer, which comprises a silicon oxide layer deposited on a surface of the base region and a silicon nitride layer deposited on a surface of the silicon oxide layer.
16. The method of forming a bipolar transistor with an embedded epitaxial external base region of claim 6, wherein the sidewall is undercut during the etching of the base region.
17. The method of forming a bipolar transistor with an embedded epitaxial external base region of claim 6, wherein the metal deposited is one of Ti, Co or Ni.
18. The method of forming a bipolar transistor with an embedded epitaxial external base region of claim 3, wherein the external base region is formed through an epitaxy growth process, the external base region is formed of Si, SiGe or carbon-doped SiGe, and the impurity is doped at a concentration of 1E19 to 1E21 cm−3.
19. The method of forming a bipolar transistor with an embedded epitaxial external base region of claim 6, wherein the external base region is formed through an epitaxy growth process, the external base region is formed of Si, SiGe or carbon-doped SiGe, and the impurity is doped at a concentration of 1E19 to 1E21 cm−3.
US13/625,211 2012-05-16 2012-09-24 Bipolar transistor with embedded epitaxial external base region and method of forming the same Abandoned US20130307122A1 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
CN 201210153410 CN102651384B (en) 2012-05-16 2012-05-16 Bipolar transistor with embedded epitaxial outer base region and fabrication method of bipolar transistor
CN201210153063.1 2012-05-16
CN201210153410.0 2012-05-16
CN 201210153063 CN102664190B (en) 2012-05-16 2012-05-16 Embedded epitaxial external base region bipolar transistor and manufacturing method thereof
CN201210153148.XA CN102651390B (en) 2012-05-16 2012-05-16 Bipolar transistor and method for preparing an epitaxial base region embedded outer
CN201210153148.X 2012-05-16

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14/335,468 US9012291B2 (en) 2012-05-16 2014-07-18 Bipolar transistor with embedded epitaxial external base region and method of forming the same

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US14/335,468 Division US9012291B2 (en) 2012-05-16 2014-07-18 Bipolar transistor with embedded epitaxial external base region and method of forming the same

Publications (1)

Publication Number Publication Date
US20130307122A1 true US20130307122A1 (en) 2013-11-21

Family

ID=49580663

Family Applications (2)

Application Number Title Priority Date Filing Date
US13/625,211 Abandoned US20130307122A1 (en) 2012-05-16 2012-09-24 Bipolar transistor with embedded epitaxial external base region and method of forming the same
US14/335,468 Expired - Fee Related US9012291B2 (en) 2012-05-16 2014-07-18 Bipolar transistor with embedded epitaxial external base region and method of forming the same

Family Applications After (1)

Application Number Title Priority Date Filing Date
US14/335,468 Expired - Fee Related US9012291B2 (en) 2012-05-16 2014-07-18 Bipolar transistor with embedded epitaxial external base region and method of forming the same

Country Status (1)

Country Link
US (2) US20130307122A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160126573A (en) 2015-04-24 2016-11-02 삼성전자주식회사 Semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130009280A1 (en) * 2011-07-06 2013-01-10 International Business Machines Corporation Bipolar junction transistors with a link region connecting the intrinsic and extrinsic bases

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4897703A (en) * 1988-01-29 1990-01-30 Texas Instruments Incorporated Recessed contact bipolar transistor and method
US5985708A (en) * 1996-03-13 1999-11-16 Kabushiki Kaisha Toshiba Method of manufacturing vertical power device
US20020084494A1 (en) * 2000-12-31 2002-07-04 Kamel Benaissa Method for making high gain bipolar transistors in CMOS process
US7074623B2 (en) * 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
JP3507830B1 (en) * 2002-10-04 2004-03-15 松下電器産業株式会社 Semiconductor device
US7005359B2 (en) * 2003-11-17 2006-02-28 Intel Corporation Bipolar junction transistor with improved extrinsic base region and method of fabrication
JP4775688B2 (en) * 2004-07-16 2011-09-21 オンセミコンダクター・トレーディング・リミテッド Semiconductor device
JP2006128628A (en) * 2004-09-29 2006-05-18 Sanyo Electric Co Ltd Semiconductor device
US20060170074A1 (en) * 2004-12-28 2006-08-03 Yoshikazu Ibara Semiconductor device
JP2006294990A (en) * 2005-04-13 2006-10-26 Rohm Co Ltd Semiconductor device
US7446009B2 (en) * 2005-11-11 2008-11-04 Sanyo Electric Co., Ltd. Manufacturing method for semiconductor device
US20080217742A1 (en) * 2007-03-09 2008-09-11 International Business Machines Corporation Tailored bipolar transistor doping profile for improved reliability
CN102104062B (en) * 2009-12-21 2012-08-01 上海华虹Nec电子有限公司 Bipolar transistor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130009280A1 (en) * 2011-07-06 2013-01-10 International Business Machines Corporation Bipolar junction transistors with a link region connecting the intrinsic and extrinsic bases

Also Published As

Publication number Publication date
US20140329368A1 (en) 2014-11-06
US9012291B2 (en) 2015-04-21

Similar Documents

Publication Publication Date Title
US6531369B1 (en) Heterojunction bipolar transistor (HBT) fabrication using a selectively deposited silicon germanium (SiGe)
US8735993B2 (en) FinFET body contact and method of making same
US6417059B2 (en) Process for forming a silicon-germanium base of a heterojunction bipolar transistor
JP4652764B2 (en) Bipolar transistor having a self-aligned silicide and a self-aligned emitter contact boundary
US8415250B2 (en) Method of forming silicide contacts of different shapes selectively on regions of a semiconductor device
US9490348B2 (en) Method of forming a FinFET having an oxide region in the source/drain region
US5915183A (en) Raised source/drain using recess etch of polysilicon
US6864560B2 (en) Bipolar transistor structure with a shallow isolation extension region providing reduced parasitic capacitance
US8785285B2 (en) Semiconductor devices and methods of manufacture thereof
US7943995B2 (en) NMOS device, PMOS device, and SiGe HBT device formed on SOI substrate and method of fabricating the same
CN1288745C (en) Bipolar transistor with raised extrinsic base and method for forming same
US7022578B2 (en) Heterojunction bipolar transistor using reverse emitter window
US6940149B1 (en) Structure and method of forming a bipolar transistor having a void between emitter and extrinsic base
US7119416B1 (en) Bipolar transistor structure with self-aligned raised extrinsic base and methods
US8937299B2 (en) III-V finFETs on silicon substrate
EP0558100A2 (en) Bipolar transistor
JP4448462B2 (en) Method of fabricating a bipolar transistor
KR100486304B1 (en) Method for manufacturing self-aligned BiCMOS
US9324846B1 (en) Field plate in heterojunction bipolar transistor with improved break-down voltage
JPH0677245A (en) Bipolar transistor and manufacture thereof
CN101410959B (en) Bipolar transistor with dual shallow trench isolation and low base resistance
US7462547B2 (en) Method of fabricating a bipolar transistor having reduced collector-base capacitance
JP3552989B2 (en) Bipolar device and manufacturing method thereof
US7005359B2 (en) Bipolar junction transistor with improved extrinsic base region and method of fabrication
US6809024B1 (en) Method to fabricate high-performance NPN transistors in a BiCMOS process

Legal Events

Date Code Title Description
AS Assignment

Owner name: TSINGHUA UNIVERSITY, CHINA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WANG, YU-DONG;FU, JUN;CUI, JIE;AND OTHERS;REEL/FRAME:029684/0512

Effective date: 20121123

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION