US20130188963A1

US20130188963A1 - Applying controlled impedance to improve optical transceiver bandwidth

Info

Publication number: US20130188963A1
Application number: US13/730,452
Authority: US
Inventors: Gil Afriat; Lior Horwitz; Dror Lazar; Assaf Issachar; Alexander Pogrebinsky; Adee O. Ran; Ehud Shoor; Roi Bar; Rushdy A. SABA
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2012-01-23
Filing date: 2012-12-28
Publication date: 2013-07-25
Also published as: US20130189856A1; TW201349770A; US8989588B2; TWI489799B; WO2013112489A1; US20130188965A1; TW201334439A; TWI508472B; US9800350B2

Abstract

An optical transceiver includes an optical receiver IC coupled to a processor IC. The processor IC includes an integrated optical receiver front end circuit, and includes an integrated inductor to control the LC frequency response of a signal from the optical receiver IC to the output of the front end circuit. The inductor is coupled in series between interface components of the processor IC and an input of the front end circuit. The inductor is configured to adjust an effective input reactance of the front end circuit, which operates to control the LC frequency response of a signal from the optical receiver IC to an output of the front end circuit.

Description

RELATED APPLICATIONS

This patent application is a non-provisional utility application based on, and claims the benefit of priority of, U.S. Provisional Application No. 61/589,717, filed Jan. 23, 2012, and U.S. Provisional Application No. 61/590,172, filed Jan. 24, 2012.

FIELD

Embodiments of the invention are generally related to optical interconnections, and more particularly to applying equalization to optical transceiver systems.

COPYRIGHT NOTICE/PERMISSION

Portions of the disclosure of this patent document may contain material that is subject to copyright protection. The copyright owner has no objection to the reproduction by anyone of the patent document or the patent disclosure as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever. The copyright notice applies to all data as described below, and in the accompanying drawings hereto, as well as to any software described below: Copyright © 2012, Intel Corporation, All Rights Reserved.

BACKGROUND

The rising demand for computing and multimedia devices has increased demand for interconnecting devices. The interconnection of computing devices to each other, and peripherals to computing devices continues to raise the demand for faster (e.g., higher bandwidth) data communication links. The currently desired bandwidths cannot be delivered reliably by electrical interconnections over the distances required for modern electronic equipment.
Optical channel solutions have the potential to provide longer range and higher speed capabilities. However, optical channel solutions for removable interconnections with modern electronics have practical considerations that are different from previous uses of optical communications solutions. Optical devices that provide the bandwidths desired (currently on the order of 25 Gb/s per channel) are typically of a physical size that introduces challenges for automatic alignment.
Specifically referring to the receiver side, higher speed, small photodetectors are small enough that the active area to focus on requires a level of precision that is difficult to achieve with traditional manufacturing equipment. Additionally, the size of the devices has decreased to the point where the bandwidth of the devices becomes affected by the parasitic reactive effects (inductance and capacitance) of traces, pads, and pins/bumps used to interconnect separate integrated circuits. Theoretical designs may not be amenable to high volume manufacturing (HVM).

BRIEF DESCRIPTION OF THE DRAWINGS

The following description includes discussion of figures having illustrations given by way of example of implementations of embodiments of the invention. The drawings should be understood by way of example, and not by way of limitation. As used herein, references to one or more “embodiments” are to be understood as describing a particular feature, structure, or characteristic included in at least one implementation of the invention. Thus, phrases such as “in one embodiment” or “in an alternate embodiment” appearing herein describe various embodiments and implementations of the invention, and do not necessarily all refer to the same embodiment. However, they are also not necessarily mutually exclusive.

FIG. 1 is a block diagram of an embodiment of an optical transceiver with a front end circuit integrated onto a processor IC.

FIG. 2A is a block diagram of an embodiment of a transmitter of an optical transceiver.

FIG. 2B is a block diagram of an embodiment of a receiver of an optical transceiver.

FIG. 3 is a block diagram of an embodiment of an optical transceiver with an inductor coupled to an integrated front end circuit.

FIG. 4 is a schematic diagram of an embodiment of an input to an integrated front end circuit.

FIGS. 5A-5B illustrate graphical representations of frequency response curves for an optical transceiver with a front end circuit integrated on a processor IC.

FIG. 6 is a flow diagram of an embodiment of receiving a signal with an optical transceiver that includes an inductor to control an input response of an integrated front end circuit.

FIGS. 7A-7B represent an optical transceiver system in accordance with any embodiment described herein.

FIG. 8 is a block diagram of an embodiment of a computing system in which an optical transceiver can be used.

FIG. 9 is a block diagram of an embodiment of a mobile device in which an optical transceiver can be used.

Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein. An overview of embodiments of the invention is provided below, followed by a more detailed description with reference to the drawings.

DETAILED DESCRIPTION

As described herein, an optical transceiver includes an optical receiver IC coupled to a processor IC. The processor IC includes an integrated optical receiver front end circuit, and includes an integrated inductor to control the LC frequency response of a signal from the optical receiver IC to the output of the front end circuit. The inductor is coupled in series between interface components of the processor IC and an input of the front end circuit. The inductor is configured to adjust an effective input reactance of the front end circuit, which operates to control the LC frequency response of a signal from the optical receiver IC to an output of the front end circuit.
Integrating the front end circuit (e.g., including a transimpedance amplifier) provides noise advantages, but introduces bandwidth constraints, as described in more detail below. By adding a series inductor to control the frequency response of the front end circuit, parasitic properties and bandwidth constraints can actually be used to an advantage. As described herein, an inductor controls a peaking response to amplify high frequency signal components. In conjunction with a bandwidth-limiting front end circuit, the overall circuit can achieve a desired behavior. The bandwidth limitation can effectively operate as a low pass filter, while peaking control can effectively operate as high frequency preemphasis. The end result is a desired overall frequency response with noise suppression.
FIG. 1 is a block diagram of an embodiment of an optical transceiver with a front end circuit integrated onto a processor IC. Transceiver 100 represents elements of an optical transceiver. More particularly, transceiver 100 includes processor IC (integrated circuit) 110 coupled to optical IC 140. Optical IC 140 represents an integrated circuit device on which one or more optical components (e.g., lasers such as VCSELs (vertical cavity surface emitting lasers), photodiodes) are disposed. A component can be considered disposed on an integrated circuit when it is integrated into the substrate such as by lithographic processing. A component can be considered disposed on a substrate when it is built into a substrate and/or manufactured onto the substrate such as by soldering, wirebonding, adhering, using flip-chip connection, or other forms of mounting or manufacturing. Both optical IC 140 and processor IC 110 are disposed on a substrate of transceiver 100, and interconnected on the substrate. For example, both ICs can be mounted on the same PCB (printed circuit board).
Processor IC 110 includes process logic 120, which can include, for example, transmit and/or receive processing logic and/or other signal processing logic. Process logic 120 can be implemented as a configured logic array, a processor circuit, controller unit, or other processing element. Process logic 120 processes electrical signals to perform transmit and/or receive functions (TX/RX). Traditionally, processor IC 110 only includes processor logic 120. In one embodiment, processor IC 110 includes front end device 130 integrated on processor IC 110.
Front end device 130 interfaces between optical IC 140 and process logic 120. Thus, front end device 130 can provide an optical to electrical (e.g., digital) conversion, or generate a digital representation of a received optical signal as received by an optical receiver of optical IC 140. In one embodiment, front end device 130 includes a transimpedance amplifier (TIA) that converts a current signal from a photodetector into a digital (e.g., binary stream) representation. In one embodiment, both processor logic 120 and front end 130 are manufactured using CMOS (complementary metal-oxide-semiconductor) technology.
Traditionally, front end device 130 (including a TIA) resides in a discrete O/E (optical to electrical) interface IC. In the traditional approach, front end device 130 can be designed with bond pads that allow an interface with very low electrical parasitics to optical IC 140. For example, an O/E interface IC can be disposed physically close to optical IC 140 and have relatively short bond wires. In one embodiment, front end 130 can be bonded using flip chip technology. However, integrating the optical receive front end 130 makes the interface to optical IC 140 more difficult than when it resides in a discrete IC. The integrated front end 130 has a physical interface that can include one or more traces (e.g., on a PCB or other substrate), and/or longer bond wires (e.g., from optical IC 140 to the substrate).
Thus, integration of front end 130 into or onto processor IC 110 introduces higher electrical parasitics. In particular, parasitic capacitance increases due to the presence of traces and pads, and parasitic inductance increases due to longer bond wire. Collectively the capacitance and inductance can be referred to as reactance, where the parasitic reactive effects (or simply “parasitics”) introduce peaking in the receiver transfer function. The peaking is caused because the reactive elements cause resonance at higher frequency. The peaking in turn introduces higher jitter due to inter symbol interference (ISI) effects.
As described herein, the resonance and therefore the peaking can be controlled by the addition of an inductor component at the input of front end device 130 (the input with respect to received signals from a photodetector (PD) of optical IC 140). The inductor is configured to control the frequency response of the signal input of front end 130.
FIG. 2A is a block diagram of an embodiment of a transmitter of an optical transceiver. Transmitter 202 can represent one example embodiment of a transmitter portion of transceiver 100. Thus, processor 212 can represent components of processor IC 110. Processor 212 includes data source 222, which can generate data responsive to external components or users (not shown). In one embodiment, data source 222 generates N bits of parallel data, which are serialized by serializer 232. Clock 224 generates clock signal(s) to control the operation of data source 222 and serializer 232. It will be understood that serializer 232 can use a modified or different clock signal from data source 222. VCSEL driver 234 represents a driver stage that drives the operation of laser 242. Laser 242 is located on an optical IC separate from processor 212. Laser 242 optically transmits the signal generated by data source 222.
FIG. 2B is a block diagram of an embodiment of a receiver of an optical transceiver. Receiver 204 can represent one example embodiment of a receiver portion of transceiver 100. Thus, processor 214 can represent components of processor IC 110. In one embodiment, processor 214 is part of the same processor IC as processor 212 of FIG. 2A.
PD 244 receives an optical signal, and passes it to processor 214. In one embodiment, the processor IC includes a front end circuit, including TIA 250. In one embodiment, TIA 250 includes an inductor element (not specifically shown) configured to control the input reactance of TIA 250. It will be understood that TIA 250 has parasitic inductance; however, the inductor referred to is a designed integrated component that is not simply the parasitic inductance of the input. The inductor is configured with a value to control the LC frequency response to a desired performance.
TIA 250 can be connected to amplifier 260 to provide further amplification of the signal. In one embodiment, amplifier 260 is a limited post amplifier. In one embodiment, the output of amplifier 260 is sampled by data slicers 272 and 274. In one embodiment, the data slicers operate at a half rate clock. The clock (including a half rate clock signal if used) can be generated by CDR (clock and data recovery) circuit 276. The sampled data can then be fed back to CDR 276 to synchronize the clock signal, as well as being fed to deserializer 282 to generate an N-bit parallel digital signal. Process logic 284 receives the parallel signal and processes it.
FIG. 3 is a block diagram of an embodiment of an optical transceiver with an inductor coupled to an integrated front end circuit. Transceiver system 300 is one example of elements of a transceiver system in accordance with any embodiment described herein. The primary focus of discussion with respect to transceiver 300 is the receiver portion of the transceiver.
Transceiver 300 includes optical IC 310, which includes photodetector 314. Optical IC 310 includes physical interface 312, which can include pins or bumps or pads on the IC itself that connect to corresponding interface hardware on a substrate on which the IC is disposed. Trace 320 represents the physical interconnection hardware of the substrate, which can include pads, bond wires, traces, or other features. Trace 320 allows physical interface 312 of optical IC 310 to connect to physical interface 332 of processor IC 330. As mentioned above, small features of the packaging or the module/system, such as the physical interface hardware (e.g., pads, traces), become significant to the signal integrity. Pads and traces become resonant, which reduces the bandwidth of the transceiver. Modifying the bond wires can adjust the frequency response of the transceiver, but there are significant practical limitations to how long a bond wire can before introducing other issues. Also, a wirebond connection is not a good connection solution for processor IC 330, which is better connected by using flip-chip mounting.
In one embodiment, processor IC 330 is flip-chip connected to a substrate of transceiver 300 (thus, physical interface 332 includes bumps for the flip-chip connection), onto traces that can then be connected via wirebond to optical IC 310. In addition to such controls, in one embodiment, processor IC 330 includes inductor 334 integrated between physical interface 332 and TIA 336. Thus, an inductor is placed between the optical IC interconnection and the front end circuit. In one embodiment, inductor 334 is considered to be part of TIA 336, but can still be understood as providing an inductor or reactive component at the input of the TIA.
In one embodiment, inductor 334 is configured to tune the parasitics of transceiver 300. Thus, instead of having an inductive value that dominates the inductance of the input, inductor 334 can be of a value comparable with the inductance of the parasitic inputs. Thus, inductor 334 can simply add enough reactance to tune the parasitic properties of the circuit to a desired behavior. Inductor 334 controls the interface parasitics by using the parasitics in combination with the inductor. Another way to think of inductor 334 is that the transfer function of TIA 336 is designed to have an overall desired characteristic, and inductor 334 can be made of a value that provides the desired function when placed in series with the interface components that provide the parasitics.
With the tuning of inductor 334, TIA 336 can operate to provide a desired bandwidth while suppressing noise. The filtered signal is provided to process logic 338 as a digital signal for processing by the process components.
FIG. 4 is a schematic diagram of an embodiment of an input to an integrated front end circuit. Schematic 400 illustrates a circuit equivalent diagram of the receiver portion shown in transceiver 300. PD 410 receives the optical signal, and corresponds to PD 314 of transceiver 300. In one embodiment, processor IC 330 of transceiver 300 can be implemented as a router ASIC (application specific integrated circuit). Integrating the optical receiver front end (including TIA) into the full router ASIC introduces electrical parasitics into the transceiver.
In schematic 400, all circuit elements except for Ls (inductor 450) are parasitic elements. Cpd+Cb (capacitor 420) represents capacitance of PD 410 (Cpd) and wirebond (Cb) capacitance. Lb (inductor 430) represents wirebond inductance. Ctb (capacitor 440) represents PCB trace capacitance (Ctrace) and flip-chip bump capacitance (Cbump). Cin_TIA (capacitor 460) represents parasitic capacitance inside the router IC (e.g., processor IC 330) at the input of the TIA (e.g., TIA 336). Rin (resistor 470) represents input resistance seen at the TIA input.
It will be understood that there are degrees of freedom in changing the parasitic elements. For example, Lb can be bounded below by the shortest length required for the bond wire, but can be increased somewhat. Additionally, the processor IC (e.g., an ASIC) can be designed to match the module structure of the transceiver and the transfer function of PD 410 to create a desired flat transfer function. More discussion of the transfer functions follows below with respect to FIGS. 5A and 5B.
Additionally, as described herein, Ls is added in series between the physical interface of PD 410 and the input of the front end circuit. It will be understood that in one embodiment Ls is not a discrete inductor disposed on the substrate between the optical IC and the processor IC. Rather, Ls is integrated onto the processor IC. Ls is designed into the system and provided with a specific value. Ls can be considered to have a discrete value, in that it is designed into the system, even though it is not a discrete component in the sense that it is integrated onto the IC. The optical IC and processor IC are coupled via the substrate. Ls is configured with a value that controls the effective input reactance as seen from PD 410. Looking from PD 410, all the parasitics affect the input reactance. Inductor 450 is added to control the input reactance to control the LC (inductor-capacitor) frequency response of the input signals.
As mentioned above, at the frequencies of interest (the frequencies at which PD 410 is operated), the reactive components resonate. Inductor 450 can tune the resonance to be an advantage to the overall transfer function of the receiver portion. While a single PD 410 is illustrated, it will be understood that PD 410 can be part of a photodetector or photodiode array. There can be a corresponding input path similar to schematic 400 for each PD in the array. While specific values of the components are not shown, because they are dependent on frequencies of interest, processes used, transceiver design, and other factors, those skilled in the art will understand how to configure Ls to tune the input response. In one embodiment, the value of Ls is comparable to the value of Lb.
It will be understood that the complete receiver front end transfer function is composed of two transfer functions. The first is the transfer function of the PD to the input of the integrated circuit (e.g., integrated TIA). This transfer function includes the transfer function of the PD itself, and includes the physical connections between the PD and the input of the TIA. The second transfer function is the transfer function of the TIA itself, from the input current to the output voltage. The combination of these transfer functions provides the overall transfer function for the receiver from the PD to the output of the digital signal for the process unit.
FIGS. 5A-5B illustrate graphical representations of frequency response curves for an optical transceiver with a front end circuit integrated on a processor IC. Graph 510 illustrates curve 512, which represents the transfer function of the receiver front end circuit without the addition of a series inductor. It will be observed that the peaking of curve 512 occurs above 10 GHz, where the desired curve would peak closer to 10 GHz. Curve 512 can be affected to a certain extent with a change to wirebonds, as discussed above. Such changes can reduce the peaking frequency, but the inventors found that the changes also increase the peaking height, which is not a desired result.
Curve 514 illustrates an embodiment of a transfer function of the receiver front end circuit with the series inductor. The peaking of the curve has been shifted back to around 10 GHz, as desired, without increasing the height of the peaking. Additionally, the height of the peaking has been slightly decreased, and the bandwidth of the peak widened. That characteristic of the curve provides a beneficial effect, as shown in graph 520.
In graph 520, curve 514 is again displayed. Curve 522 represents a transfer function for the TIA front end circuit. The bandwidth of the TIA is only about 6.5 GHz, and acts as a low pass filter. Curve 526 represents the overall receiver front end transfer function, and is the product of the transfer functions represented by curves 514 and 522. Curve 526 exhibits a bandwidth of approximately 12 GHz without any peaking.
Thus, it will be understood that the input hardware including the integrated inductor act to amplify the high frequency signal (as shown in curve 512), which is then attenuated by the operation of the TIA itself (as shown by curve 522). Thus, the overall input provides a desired bandwidth with good frequency response (e.g., no peaking), while also operating to filter noise, or provide low noise at the output of the front end circuit. The peaking seen in curve 514 compensates for the lower bandwidth of the TIA as seen in curve 522. In one embodiment, the value of the series inductor can be selected based on the desired transfer function 514 needed to generate transfer function 526. The value of the inductor can be selected to configure the circuit to compensate for the lower bandwidth of the TIA, and control the peak value of the LC frequency response.
FIG. 6 is a flow diagram of an embodiment of receiving a signal with an optical transceiver that includes an inductor to control an input response of an integrated front end circuit. In one embodiment, a transceiver module receives an optical input signal at a photodetector or photodiode of an optical IC mounted on a substrate of the module or system, 602. The photodetector converts the optical signal into an electrical signal, 604. As is understood, the signal from the photodetector is a current-based signal in response to the light received. The electrical current signal is passed from the photodetector through interface components and the substrate to a processor IC mounted on the substrate, 606.
The electrical current signal is routed to an input of a front end conversion circuit (e.g., a TIA) via a series input inductor, 608. The series inductor is configured to control the LC frequency response of the input signal, 610. The inductor can operate to control the peaking of the input frequency response to control an overall input response. The conversion circuit converts the electrical signal into a digital signal, 612, and the front end circuit passes the digital signal to a process component for signal processing, 614.
FIGS. 7A-7B represent an optical transceiver system in accordance with any embodiment described herein. Referring to FIG. 7A, module 700 is part of an optical transceiver. Module 700 includes a substrate or PCB on which a processor IC and optical IC are mounted as seen in portion 702 (see FIG. 7B). Portion 702 can be a metal ground top layer of PCB or substrate 704 of module 700. In one embodiment a plastic cover, or cover of other material optically transparent at the communication frequency of interest, is included in transceiver module 700. The cover can provide transmitter and receiver lens systems, and couple into an OM1 (62.5/125 um) multimode TX/RX fiber pair (fibers 740) via a simple connector.
The pads at the top of PCB 704 were used for contacts inside a socket. The lens systems can include 90 degree bending mirrors enabling a side connection of the fiber to the module and bringing the full solution (transceiver module and fiber connector) to a height of merely 1.85 mm, which allows for implementation in laptops and handheld devices.
In accordance with one specific configuration tested, module 700 provided a low cost and small form factor solution while exhibiting full duplex error free performance at 25 Gb/s, and consuming low power. In one embodiment, transceiver module 700 can be designed to support four channels, which each support 25 Gb/s communication, each channel using a pair of VCSELs and photodiodes, and all four channels being processed with all necessary TX/RX logic in a processor IC (e.g., processor IC 710 of portion 702).
Referring to FIG. 7B, the ICs (e.g., processor IC and optical IC 720) are connected via traces 730, which can include PCB traces, pads and bondwires (as shown). Optical IC 720 includes one or more PDs, and processor IC 710 processes signals received via the PD. Processor IC 710 includes an integrated inductor (not seen) that controls the input response of signals received from the PD. As shown, the photodiode is wire bonded onto pads on a 12 mm×12 mm standard FR-4 PCB, and the photodiode connects via the board traces to a CMOS transceiver IC, which is flip-chip soldered onto the PCB.
The PD used in testing was specified for a 12.5 Gb/s data rate (with typical −3 dB bandwidth of 15.8 GHz, 32 um aperture, capacitance of 135 fF, and 0.5 A/W responsivity at 850 nm), but was used at 25 Gb/s. The processor IC (710) was fabricated with a standard 28 nm CMOS process and integrates all required TX/RX circuits.
In one embodiment, the circuit is usable in an optical small form factor pluggable (SFP) transceiver. The PCB includes pads to connect to a peripheral port, and includes the optical IC and the processor IC with integrated inductor as described herein. The transceiver can be enclosed in an appropriate housing to interface with a corresponding port. In one embodiment, the same transceiver can be integrated onto a PCB of a computing device and used as a peripheral port.
FIG. 8 is a block diagram of an embodiment of a computing system in which an optical transceiver can be used. System 800 represents a computing device in accordance with any embodiment described herein, and can be a laptop computer, a desktop computer, a server, a gaming or entertainment control system, a scanner, copier, printer, or other electronic device. System 800 includes processor 820, which provides processing, operation management, and execution of instructions for system 800. Processor 820 can include any type of microprocessor, central processing unit (CPU), processing core, or other processing hardware to provide processing for system 800. Processor 820 controls the overall operation of system 800, and can be include, one or more programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application specific integrated circuits (ASICs), programmable logic devices (PLDs), or the like, or a combination of such devices.
Memory 830 represents the main memory of system 800, and provides temporary storage for code to be executed by processor 820, or data values to be used in executing a routine. Memory 830 can include one or more memory devices such as read-only memory (ROM), flash memory, one or more varieties of random access memory (RAM), or other memory devices, or a combination of such devices. Memory 830 stores and hosts, among other things, operating system (OS) 832 to provide a software platform for execution of instructions in system 800. Additionally, other instructions 834 are stored and executed from memory 830 to provide the logic and the processing of system 800. OS 832 and instructions 834 are executed by processor 820.
Processor 820 and memory 830 are coupled to bus/bus system 810. Bus 810 is an abstraction that represents any one or more separate physical buses, communication lines/interfaces, and/or point-to-point connections, connected by appropriate bridges, adapters, and/or controllers. Therefore, bus 810 can include, for example, one or more of a system bus, a Peripheral Component Interconnect (PCI) bus, a HyperTransport or industry standard architecture (ISA) bus, a small computer system interface (SCSI) bus, a universal serial bus (USB), or an Institute of Electrical and Electronics Engineers (IEEE) standard 1394 bus (commonly referred to as “Firewire”). The buses of bus 810 can also correspond to interfaces in network interface 850.
System 800 also includes one or more input/output (I/O) interface(s) 840, network interface 850, one or more internal mass storage device(s) 860, and peripheral interface 870 coupled to bus 810. I/O interface 840 can include one or more interface components through which a user interacts with system 800 (e.g., video, audio, and/or alphanumeric interfacing). Network interface 850 provides system 800 the ability to communicate with remote devices (e.g., servers, other computing devices) over one or more networks. Network interface 850 can include an Ethernet adapter, wireless interconnection components, USB (universal serial bus), or other wired or wireless standards-based or proprietary interfaces.
Storage 860 can be or include any conventional medium for storing large amounts of data in a nonvolatile manner, such as one or more magnetic, solid state, or optical based disks, or a combination. Storage 860 hold code or instructions and data 862 in a persistent state (i.e., the value is retained despite interruption of power to system 800). Storage 860 can be generically considered to be a “memory,” although memory 830 is the executing or operating memory to provide instructions to processor 820. Whereas storage 860 is nonvolatile, memory 830 can include volatile memory (i.e., the value or state of the data is indeterminate if power is interrupted to system 800).
Peripheral interface 870 can include any hardware interface not specifically mentioned above. Peripherals refer generally to devices that connect dependently to system 800. A dependent connection is one where system 800 provides the software and/or hardware platform on which an operation executes, and with which a user interacts.
In one embodiment, system 800 can include one or more receptacles 882 with housing 884 to receive plug 892 or mate with plug 892 to connect to external device 890. Receptacle 882 includes housing 884, which provides the mechanical connection mechanisms. As used herein, mating one connector with another refers to providing a mechanical connection. The mating of one connector with another typically also provides a communication connection. Receptacle 882 can connect directly to one or more buses of bus system 810, or receptacle 882 can be associated directly with one or more devices, such as network interface 850, I/O interface 840, storage 860, peripheral interface 870, or processor 820.
Plug 892 is a connector plug that allows external device 890 (which can be any of the same types of devices discussed above) to interconnect with device 800. Plug 892 can be directly built into external device 890 (with or without a cord or cable 894), or can be interconnected to external device 890 via a standalone cable 894. In one embodiment, plug 892 supports communication via an optical interface or both an optical interface and an electrical interface. The interconnection of receptacle 882 to bus 810 can similarly include an optical path or both an optical and electrical signal path. Receptacle 882 can also include an optical communication connection that is converted to an electrical signal prior to being placed on bus 810.
In one embodiment, one or more components of system 800 include an optical interface. The optical components can interface with one or more other components internally to system 800, and/or with one or more external devices 890 via receptacle(s) 882. Receptacle 882 provides the hardware port through which external optical signals can be exchanged, for example, with peripheral devices. The optical interface can be performed with an optical transceiver in accordance with any embodiment described herein. The optical transceiver includes a receiver portion that has an integrated input inductor to control an LC frequency response of the receiver input.
FIG. 9 is a block diagram of an embodiment of a mobile device in which an optical transceiver can be used. Device 900 represents a mobile computing device, such as a computing tablet, a mobile phone or smartphone, a wireless-enabled e-reader, or other mobile device. It will be understood that certain of the components are shown generally, and not all components of such a device are shown in device 900.
Device 900 includes processor 910, which performs the primary processing operations of device 900. Processor 910 can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor 910 include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting device 900 to another device. The processing operations can also include operations related to audio I/O and/or display I/O.
In one embodiment, device 900 includes audio subsystem 920, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into device 900, or connected to device 900. In one embodiment, a user interacts with device 900 by providing audio commands that are received and processed by processor 910.
Display subsystem 930 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device. Display subsystem 930 includes display interface 932, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface 932 includes logic separate from processor 912 to perform at least some processing related to the display. In one embodiment, display subsystem 930 includes a touchscreen device that provides both output and input to a user.
I/O controller 940 represents hardware devices and software components related to interaction with a user. I/O controller 940 can operate to manage hardware that is part of audio subsystem 920 and/or display subsystem 930. Additionally, I/O controller 940 illustrates a connection point for additional devices that connect to device 900 through which a user might interact with the system. For example, devices that can be attached to device 900 might include microphone devices, speaker or stereo systems, video systems or other display device, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.
As mentioned above, I/O controller 940 can interact with audio subsystem 920 and/or display subsystem 930. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of device 900. Additionally, audio output can be provided instead of or in addition to display output. In another example, if display subsystem includes a touchscreen, the display device also acts as an input device, which can be at least partially managed by I/O controller 940. There can also be additional buttons or switches on device 900 to provide I/O functions managed by I/O controller 940.
In one embodiment, I/O controller 940 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, gyroscopes, global positioning system (GPS), or other hardware that can be included in device 900. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).
In one embodiment, device 900 includes power management 950 that manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem 960 includes memory device(s) 962 for storing information in device 900. Memory subsystem 960 can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem 960 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of system 900.
Connectivity 970 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable device 900 to communicate with external devices. The device could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.
Connectivity 970 can include multiple different types of connectivity. To generalize, device 900 is illustrated with cellular connectivity 972 and wireless connectivity 974. Cellular connectivity 972 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, LTE (long term evolution—also referred to as “4G”), or other cellular service standards. Wireless connectivity 974 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth), local area networks (such as WiFi), and/or wide area networks (such as WiMax), or other wireless communication. Wireless communication refers to transfer of data through the use of modulated electromagnetic radiation through a non-solid medium. Wired communication (including optical communication) occurs through a solid communication medium.
Peripheral connections 980 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that device 900 could both be a peripheral device (“to” 982) to other computing devices, as well as have peripheral devices (“from” 984) connected to it. Device 900 commonly has a “docking” connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on device 900. Additionally, a docking connector can allow device 900 to connect to certain peripherals that allow device 900 to control content output, for example, to audiovisual or other systems.
In addition to a proprietary docking connector or other proprietary connection hardware, device 900 can make peripheral connections 980 via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other type.
In one embodiment, any one or more of the interconnections or I/O can be performed optically. Thus, I/O controller 940, display subsystem 930, memory 960, connectivity 970, and/or peripheral connections 980 can have an optical connection with processor 910 or with an external component. In the case of an optical connection, an optical transceiver in accordance with any embodiment described herein can be used. The optical transceiver includes a receiver portion that has an integrated input inductor to control an LC frequency response of the receiver input.
In one aspect, an apparatus includes an optical receiver integrated circuit (IC) disposed on a substrate; and a processor IC including signal processing logic and an optical receiver front end circuit and interface components to connect to the optical IC via the substrate, the processor IC disposed on the substrate, and including an integrated inductor coupled in series between the interface components and an input of the front end circuit, the inductor configured to adjust an effective input reactance of the front end circuit, the effective input reactance to control an LC frequency response of a signal from the optical receiver IC to an output of the front end circuit.
In one embodiment, the optical receiver IC includes a photodiode array. In one embodiment, the substrate comprises a printed circuit board. In one embodiment, the front end circuit includes a transimpedance amplifier (TIA). In one embodiment, the interface components include processor IC package bumps or pins. In one embodiment, the inductor is configured to value comparable in size to parasitic inductance of a bond wire to connect the processor IC with the processor IC package. In one embodiment, the inductor is configured to value to adjust peaking of an LC frequency response of the input of the front end circuit to compensate for limited bandwidth of the front end circuit. In one embodiment, the inductor is configured to adjust a shape of the LC frequency response of the input of the front end circuit without increasing a peak value of the LC frequency response.
In one aspect, an optical small form factor pluggable (SFP) transceiver includes a printed circuit board (PCB) including pads to electrically connect to a peripheral port; an optical receiver integrated circuit (IC) disposed on the PCB; and a processor IC including signal processing logic and an optical receiver front end circuit and interface components to connect to the optical IC via the PCB, the processor IC disposed on the PCB, and including an integrated inductor coupled in series between the interface components and an input of the front end circuit, the inductor configured to adjust an effective input reactance of the front end circuit, the effective input reactance to control an LC frequency response of a signal from the optical receiver IC to an output of the front end circuit; and a connector housing to at least partially enclose the printed circuit board.
In one embodiment, the optical receiver IC includes a photodiode array. In one embodiment, the front end circuit includes a transimpedance amplifier (TIA). In one embodiment, the interface components include processor IC package bumps or pins. In one embodiment, the inductor is configured to value comparable in size to parasitic inductance of a bond wire to connect the processor IC with the processor IC package. In one embodiment, the inductor is configured to value to adjust peaking of an LC frequency response of the input of the front end circuit to compensate for limited bandwidth of the front end circuit. In one embodiment, the inductor is configured to adjust a shape of the LC frequency response of the input of the front end circuit without increasing a peak value of the LC frequency response.
In one aspect, a method includes converting a received optical signal into an electrical signal via a photodetector of an optical receiver integrated circuit (IC); passing the electrical signal from the optical receiver IC to interface components of a processor IC via traces of a substrate on which the optical receiver IC and processor IC are disposed; routing the electrical signal to a front end circuit via the interface components and via an integrated series inductor coupled between the interface components and the front end circuit, wherein the inductor is configured to adjust an effective input reactance of the front end circuit, the effective input reactance to control an LC frequency response of a signal from the optical receiver IC to an output of the front end circuit; converting the electrical signal into a digital signal via the front end circuit; and processing the digital signal with processing logic of the processor IC.
In one embodiment, the front end circuit includes a transimpedance amplifier (TIA). In one embodiment, the inductor is configured to value comparable in size to parasitic inductance of a bond wire to connect the processor IC with a processor IC package in which the processor IC is disposed. In one embodiment, the inductor is configured to value to adjust peaking of an LC frequency response of the input of the front end circuit to compensate for limited bandwidth of the front end circuit. In one embodiment, the inductor is configured to adjust a shape of the LC frequency response of the input of the front end circuit without increasing a peak value of the LC frequency response.
Flow diagrams as illustrated herein provide examples of sequences of various process actions. Although shown in a particular sequence or order, unless otherwise specified, the order of the actions can be modified. Thus, the illustrated embodiments should be understood only as an example, and the process can be performed in a different order, and some actions can be performed in parallel. Additionally, one or more actions can be omitted in various embodiments; thus, not all actions are required in every embodiment. Other process flows are possible.
To the extent various operations or functions are described herein, they can be described or defined as software code, instructions, configuration, and/or data. The content can be directly executable (“object” or “executable” form), source code, or difference code (“delta” or “patch” code). The software content of the embodiments described herein can be provided via an article of manufacture with the content stored thereon, or via a method of operating a communication interface to send data via the communication interface. A machine readable storage medium can cause a machine to perform the functions or operations described, and includes any mechanism that stores information in a form accessible by a machine (e.g., computing device, electronic system, etc.), such as recordable/non-recordable media (e.g., read only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.). A communication interface includes any mechanism that interfaces to any of a hardwired, wireless, optical, etc., medium to communicate to another device, such as a memory bus interface, a processor bus interface, an Internet connection, a disk controller, etc. The communication interface can be configured by providing configuration parameters and/or sending signals to prepare the communication interface to provide a data signal describing the software content. The communication interface can be accessed via one or more commands or signals sent to the communication interface.
Various components described herein can be a means for performing the operations or functions described. Each component described herein includes software, hardware, or a combination of these. The components can be implemented as software modules, hardware modules, special-purpose hardware (e.g., application specific hardware, application specific integrated circuits (ASICs), digital signal processors (DSPs), etc.), embedded controllers, hardwired circuitry, etc.
Besides what is described herein, various modifications can be made to the disclosed embodiments and implementations of the invention without departing from their scope. Therefore, the illustrations and examples herein should be construed in an illustrative, and not a restrictive sense. The scope of the invention should be measured solely by reference to the claims that follow.

Claims

What is claimed is:

1. An apparatus comprising:

an optical receiver integrated circuit (IC) disposed on a substrate; and

a processor IC including signal processing logic and an optical receiver front end circuit and interface components to connect to the optical IC via the substrate, the processor IC disposed on the substrate, and including an integrated inductor coupled in series between the interface components and an input of the front end circuit, the inductor configured to adjust an effective input reactance of the front end circuit, the effective input reactance to control an LC frequency response of a signal from the optical receiver IC to an output of the front end circuit.

2. The apparatus of claim 1, wherein the optical receiver IC includes a photodiode array.

3. The apparatus of claim 1, wherein the substrate comprises a printed circuit board.

4. The apparatus of claim 1, wherein the front end circuit includes a transimpedance amplifier (TIA).

5. The apparatus of claim 1, wherein the interface components include processor IC package bumps or pins.

6. The apparatus of claim 5, wherein the inductor is configured to value comparable in size to parasitic inductance of a bond wire to connect the processor IC with the processor IC package.

7. The apparatus of claim 1, wherein the inductor is configured to value to adjust peaking of an LC frequency response of the input of the front end circuit to compensate for limited bandwidth of the front end circuit.

8. The apparatus of claim 7, wherein the inductor is configured to adjust a shape of the LC frequency response of the input of the front end circuit without increasing a peak value of the LC frequency response.

9. An optical small form factor pluggable (SFP) transceiver comprising:

a printed circuit board (PCB) including

pads to electrically connect to a peripheral port;

an optical receiver integrated circuit (IC) disposed on the PCB; and

a processor IC including signal processing logic and an optical receiver front end circuit and interface components to connect to the optical IC via the PCB, the processor IC disposed on the PCB, and including an integrated inductor coupled in series between the interface components and an input of the front end circuit, the inductor configured to adjust an effective input reactance of the front end circuit, the effective input reactance to control an LC frequency response of a signal from the optical receiver IC to an output of the front end circuit; and

a connector housing to at least partially enclose the printed circuit board.

10. The SFP transceiver of claim 9, wherein the optical receiver IC includes a photodiode array.

11. The SFP transceiver of claim 9, wherein the front end circuit includes a transimpedance amplifier (TIA).

12. The SFP transceiver of claim 9, wherein the interface components include processor IC package bumps or pins.

13. The SFP transceiver of claim 12, wherein the inductor is configured to value comparable in size to parasitic inductance of a bond wire to connect the processor IC with the processor IC package.

14. The SFP transceiver of claim 9, wherein the inductor is configured to value to adjust peaking of an LC frequency response of the input of the front end circuit to compensate for limited bandwidth of the front end circuit.

15. The SFP transceiver of claim 14, wherein the inductor is configured to adjust a shape of the LC frequency response of the input of the front end circuit without increasing a peak value of the LC frequency response.

16. A method comprising:

converting a received optical signal into an electrical signal via a photodetector of an optical receiver integrated circuit (IC);

passing the electrical signal from the optical receiver IC to interface components of a processor IC via traces of a substrate on which the optical receiver IC and processor IC are disposed;

routing the electrical signal to a front end circuit via the interface components and via an integrated series inductor coupled between the interface components and the front end circuit,

wherein the inductor is configured to adjust an effective input reactance of the front end circuit, the effective input reactance to control an LC frequency response of a signal from the optical receiver IC to an output of the front end circuit;

converting the electrical signal into a digital signal via the front end circuit; and

processing the digital signal with processing logic of the processor IC.

17. The method of claim 16, wherein the front end circuit includes a transimpedance amplifier (TIA).

18. The method of claim 16, wherein the inductor is configured to value comparable in size to parasitic inductance of a bond wire to connect the processor IC with a processor IC package in which the processor IC is disposed.

19. The method of claim 16, wherein the inductor is configured to value to adjust peaking of an LC frequency response of the input of the front end circuit to compensate for limited bandwidth of the front end circuit.

20. The method of claim 19, wherein the inductor is configured to adjust a shape of the LC frequency response of the input of the front end circuit without increasing a peak value of the LC frequency response.