US20130137273A1 - Semiconductor Processing System - Google Patents

Semiconductor Processing System Download PDF

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Publication number
US20130137273A1
US20130137273A1 US13305161 US201113305161A US20130137273A1 US 20130137273 A1 US20130137273 A1 US 20130137273A1 US 13305161 US13305161 US 13305161 US 201113305161 A US201113305161 A US 201113305161A US 20130137273 A1 US20130137273 A1 US 20130137273A1
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semiconductor processing
semiconductor
semiconductor substrate
reactor chamber
processing system
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US13305161
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Manfred Engelhardt
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Infineon Technologies AG
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Infineon Technologies AG
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68785Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by the mechanical construction of the susceptor, stage or support
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34Sputtering
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/4401Means for minimising impurities, e.g. dust, moisture or residual gas, in the reaction chamber
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/458Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
    • C23C16/4582Rigid and flat substrates, e.g. plates or discs
    • C23C16/4583Rigid and flat substrates, e.g. plates or discs the substrate being supported substantially horizontally
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/50Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/50Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
    • C23C16/505Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges
    • C23C16/509Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges using internal electrodes
    • C23C16/5096Flat-bed apparatus
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67017Apparatus for fluid treatment
    • H01L21/67063Apparatus for fluid treatment for etching
    • H01L21/67069Apparatus for fluid treatment for etching for drying etching
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6838Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping with gripping and holding devices using a vacuum; Bernoulli devices

Abstract

The semiconductor processing system includes a reactor chamber that has an upper wall and a lower wall. A hold member is disposed in the reactor chamber to hold a semiconductor substrate in such a way that it faces the lower wall of the reactor chamber.

Description

    TECHNICAL FIELD
  • The present invention relates to a semiconductor processing system, a semiconductor processing apparatus, and a method for processing a semiconductor substrate.
  • BACKGROUND
  • In semiconductor processing technology very often films or layers are deposited onto a semiconductor substrate surface and later on selectively removed by known methods. The removal of films may result in particles, defects, flakes, etc., on the wafer, in particular in lift-off processes. It is important to reduce or even eliminate such a deposition of particles, defects, flakes, etc., as they are a potential source of defects and malfunctions of an electronic device or circuit fabricated on the semiconductor wafer.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The accompanying drawings are included to provide a further understanding of embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and together with the description serve to explain principles of embodiments. Other embodiments and many of the intended advantages of embodiments will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.
  • FIG. 1 shows a schematic cross-sectional side view representation of a semiconductor processing system according to an embodiment;
  • FIG. 2 shows a schematic cross-sectional side view representation of a semiconductor processing system according to an embodiment;
  • FIG. 3 shows a schematic cross-sectional side view representation of a semiconductor processing system according to an embodiment;
  • FIG. 4 shows a schematic cross-sectional side view representation of a semiconductor processing system according to an embodiment;
  • FIG. 5 shows a schematic cross-sectional side view representation of a semiconductor processing system according to an embodiment;
  • FIG. 6 shows a flow diagram for illustrating a method for processing a semiconductor substrate according to an embodiment; and
  • FIGS. 7 a and 7 b show schematic cross-sectional side view representations for illustrating an embodiment of the removal of material by upside down wafer processing.
  • DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
  • The aspects and embodiments are now described with reference to the drawings, wherein like reference numerals are generally utilized to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more aspects of the embodiments. It may be evident, however, to one skilled in the art that one or more aspects of the embodiments may be practiced with a lesser degree of the specific details. In other instances, known structures and elements are shown in schematic form in order to facilitate describing one or more aspects of the embodiments. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. It should be noted further that the drawings are not to scale or not necessarily to scale.
  • In addition, while a particular feature or aspect of an embodiment may be disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms “include”, “have”, “with” or other variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term “comprise”. The terms “coupled” and “connected”, along with derivatives may be used. It should be understood that these terms may be used to indicate that two elements co-operate or interact with each other regardless of whether they are in direct physical or electrical contact, or they are not in direct contact with each other. Also, the term “exemplary” is merely meant as an example, rather than the best or optimal. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
  • Embodiments as described herein comprise processing apparatuses and process reactors. It is to be understood that these processing apparatuses and process reactors virtually enclose all sorts of equipment and devices which are known in the art for conducting any sorts of processes with semiconductor substrates, semiconductor wafers, semiconductor chips and semiconductor dies. In particular, such apparatuses should be mentioned herein in which semiconductor substrates of all kinds can be oxidized, etched, coated with any sort of layer materials or treated with heat, pressure and moisture or annealed with temperature processes. More specifically, those apparatuses are particularly significant in which semiconductor substrates are coated with layers of all kinds by chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), sputtering and any one of these deposition methods with the assistance of radio frequency excitation.
  • Referring to FIG. 1, there is shown a schematic cross-sectional side view representation of a semiconductor processing system according to a first aspect. The semiconductor processing system 10 comprises a reactor chamber 1 comprising an upper wall 1A and a lower wall 1B, and a hold member 2 disposed in the reactor chamber 1 to hold a semiconductor substrate 3 in such a way that it faces the lower wall 1B of the reactor chamber 1.
  • The way of processing the semiconductor substrate may be described with the term “upside down wafer processing”. This upside down wafer processing will reduce or even eliminate deposition of particles, defects, flakes, etc., on the semiconductor substrate. Due to simple gravitational forces the particles, defects and flakes will not tend to remain on the semiconductor substrate surface but will fall down so that they can be taken along by any sort of flowing process gas or plasma in the direction of an outlet opening of the reactor chamber. Several further embodiments may assist the process of removing particles, defects and flakes as will be shown later.
  • According to an embodiment of the semiconductor processing system 10, the semiconductor processing system 10 is configured such that in an upright standing position of the reactor chamber 1 for its intended use the semiconductor substrate faces the lower wall of the reactor chamber, in particular the exposed surface of the semiconductor substrate is directed downwards to the lower wall of the reactor chamber. According to an embodiment thereof, the hold member is disposed in an upper half of the reactor chamber.
  • According to an embodiment of the semiconductor processing system 10, the upper wall 1A comprises an inlet opening and the lower wall 1B comprises an outlet opening. The inlet opening may be connected to a process gas reservoir whereas the outlet opening may be connected to an exhaust pump.
  • According to an embodiment of the semiconductor processing system 10, a plasma generation unit (not shown) is coupled to the reactor chamber. More specifically, the plasma generation unit is coupled to an inlet opening formed in the upper wall 1A of the reactor chamber 1.
  • According to an embodiment of the semiconductor processing system 10, the hold member 2 is comprised of a wafer chuck. The wafer chuck can be constructed as known in the art, in particular by comprising a plurality of through-conduits leading to openings at a surface of the wafer chuck so that a semiconductor wafer can be sucked onto the surface of the wafer chuck by applying a vacuum to the through-conduits.
  • According to an embodiment of the semiconductor processing system 10, a radio frequency unit is connected to the hold member. More specifically, it can be connected in such a way to the hold member that an electrical conduction line between the radio frequency unit and the hold member is fed through an opening in the upper wall 1A of the reactor chamber 1. Moreover, the hold member 2 may comprise a first main surface to hold the semiconductor substrate 3 thereupon and a second main surface opposite to the first main surface, wherein the radio frequency generator unit is connected to the second main surface of the hold member.
  • According to an embodiment of the semiconductor processing system 10, the system further comprises a magnet to distract material fragments or particles released from the semiconductor substrate 3. The magnet can be disposed outside the reactor chamber. Moreover, the magnet can be disposed such that one of the poles (N or S) of the magnet is facing the exposed surface of the semiconductor substrate 3.
  • A second aspect is related to a semiconductor processing apparatus, comprising a process chamber, a hold member disposed in the process chamber to hold a semiconductor substrate so that an exposed surface of the semiconductor substrate can be processed, wherein the processing apparatus is configured so that in an upright standing position of the processing apparatus the exposed surface of the semiconductor substrate is directed downwards.
  • Embodiments of the second aspect can be formed in connection with any feature or embodiment as described above in connection with the first aspect.
  • In the following further embodiments of a semiconductor processing system will be described. The description of those features described above in connection with FIG. 1 and carrying the same reference numerals will not be repeated.
  • Referring to FIG. 2, there is shown a schematic cross-sectional side view representation of a semiconductor processing system according to an embodiment. The semiconductor processing system 20 comprises in the upper wall 1A of the reactor chamber 1 an inlet opening 1A.1 connected with a process gas reservoir (not shown) and in the lower wall 1B an outlet opening 1B.1 connected with an exhaust pump (not shown). In addition there is provided a radio frequency unit 4 for generating a radio frequency signal and feeding the radio frequency signal via an electrical connection line 4.1 to the hold member 2. The hold member 2 is preferably comprised of a wafer chuck. The electrical connection line 4.1 is fed through an opening 1A.2 of the upper wall 1A of the reactor chamber 1. The silicon wafer 3 is shown to have structures 3.1 to be removed, e.g. by etching. A specific example will be shown later.
  • Referring to FIG. 3, there is shown a schematic cross-sectional side view representation of a semiconductor processing system according to an embodiment. The semiconductor processing system 30 comprises in addition to that one shown in FIG. 2 a plasma generation unit 5 coupled to the reactor chamber 1. In the plasma generation unit 5 a plasma is generated either by microwave excitation or by transformer (i.e., inductively) coupled plasma generation and fed into the reactor chamber 1 through a further inlet opening 1A.3 in the upper wall 1A of the reactor chamber 1.
  • Referring to FIG. 4, there is shown a schematic cross-sectional side view representation of a semiconductor processing system according to an embodiment. The semiconductor processing system 40 of FIG. 4 differs from that one shown in FIG. 3 only in that the radio frequency unit 4 is omitted. Instead the hold member 2 is directly mechanically fixed at the upper wall 1A.
  • Referring to FIG. 5, there is shown a schematic cross-sectional side view representation of a semiconductor processing system according to an embodiment. The semiconductor processing system 50 of FIG. 5 differs from that one shown in FIG. 4 only in that a magnet 6 is disposed below the reactor chamber 1. The magnet 6 can be either a permanent magnet or an electro magnet. The purpose of the magnet 6 is to distract particles from the semiconductor wafer 3 so that they can easily be pumped out of the reactor chamber 1. In the embodiment of FIG. 5 the north pole of the magnet 6 faces the semiconductor substrate 3.
  • Referring to FIG. 6, there is shown a flow diagram for illustrating a method for processing a semiconductor substrate according to an embodiment. The method 60 comprises providing a reactor chamber comprising an upper wall and a lower wall and a hold member to hold a semiconductor substrate to be processed (61), and placing the semiconductor substrate onto a hold member in such a way that it faces the lower wall of the reactor chamber (62).
  • According to an embodiment of the method 60, the method 60 further comprises feeding a process gas into the reactor chamber.
  • According to an embodiment of the method 60, the method 60 further comprises feeding a radio frequency signal into the reactor chamber, in particular to the hold member.
  • According to an embodiment of the method 60, the method 60 further comprises feeding a plasma gas into the reactor chamber.
  • According to an embodiment of the method 60, the method 60 further comprises removing structures from an exposed surface of the semiconductor substrate, in particular by isotropic etching or ashing.
  • According to an embodiment of the method 60, the method 60 further comprises pumping out materials or media through an outlet opening of the reactor chamber.
  • According to an embodiment of the method 60, the reactor chamber is provided such that the hold member is disposed in an upper half of the reactor chamber.
  • FIGS. 7 a and 7 b show schematic cross-sectional side view representations to illustrate an example for a structure or material to be removed by upside down wafer processing. FIG. 7 a shows a silicon wafer 3 carrying a film 3.1 that is to be patterned. For that purpose an organic film 3.2 is deposited onto the film 3.1 and structured thereafter in order to form a mask pattern. Thereafter a hard mask film 3.3 is deposited onto the organic film 3.2 and the film 3.1 as indicated by the arrows resulting in the intermediate product shown in FIG. 7 a. Thereafter the overhang structures have to be removed which is at best performed by upside down wafer processing as described in the aspects of this application. The removal can be performed by isotropic etching or ashing. FIG. 7 b shows the result in the form of a structured hard mask 3.3 (e.g., Ni) so that in a further step the film 3.1 can be patterned.
  • While the invention has been illustrated and described with respect to one or more implementations, alterations and/or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular regard to the various functions performed by the above described components or structures (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component or structure which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the invention.

Claims (25)

    What is claimed is:
  1. 1. A semiconductor processing system, comprising:
    a reactor chamber comprising an upper wall and a lower wall;
    a hold member disposed in the reactor chamber to hold a semiconductor substrate in such a way that the semiconductor substrate faces the lower wall of the reactor chamber.
  2. 2. The semiconductor processing system according to claim 1, wherein the upper wall comprises an inlet opening and the lower wall comprises an outlet opening.
  3. 3. The semiconductor processing system according to claim 2, wherein the inlet opening is connected to a process gas reservoir.
  4. 4. The semiconductor processing system according to claim 2, wherein the outlet opening is connected to an exhaust pump.
  5. 5. The semiconductor processing system according to claim 1, further comprising a plasma generation unit coupled to the reactor chamber.
  6. 6. The semiconductor processing system according to claim 5, wherein the plasma generation unit is coupled to an inlet opening formed in the upper wall of the reactor chamber.
  7. 7. The semiconductor processing system according to claim 1, wherein the hold member comprises a wafer chuck.
  8. 8. The semiconductor processing system according to claim 1, further comprising a radio frequency unit connected to the hold member.
  9. 9. The semiconductor processing system according to claim 8, further comprising an electrical connection line between the radio frequency unit and the hold member, the electrical connection line fed through an opening in the upper wall of the reactor chamber.
  10. 10. The semiconductor processing system according to claim 1, further comprising a magnet to distract material fragments or particles released from the semiconductor substrate.
  11. 11. The semiconductor processing system according to claim 10, wherein the magnet is disposed outside the reactor chamber.
  12. 12. A semiconductor processing apparatus, comprising:
    a process chamber; and
    a hold member disposed in the process chamber to hold a semiconductor substrate so that an exposed surface of the semiconductor substrate can be processed;
    wherein the semiconductor processing apparatus is configured so that in an upright standing position of the semiconductor processing apparatus the exposed surface of the semiconductor substrate is directed downwards.
  13. 13. The semiconductor processing apparatus according to claim 12, wherein the hold member comprises a wafer chuck.
  14. 14. The semiconductor processing apparatus according to claim 12, further comprising a radio frequency generation unit connected to the hold member.
  15. 15. The semiconductor processing apparatus according to claim 14, wherein
    the hold member comprises a first main surface to hold the semiconductor substrate thereupon and a second main surface opposite to the first main surface, and
    the radio frequency generator unit is connected to the second main surface of the hold member.
  16. 16. The semiconductor processing apparatus according to claim 12, wherein
    the process chamber comprises an upper wall and an opposite lower wall, and
    an inlet opening is formed in the upper wall and an outlet opening is formed in the lower wall.
  17. 17. The semiconductor processing apparatus according to claim 16, wherein the inlet opening is connected to a process gas reservoir.
  18. 18. The semiconductor processing apparatus according to claim 16, wherein the outlet opening is connected to an exhaust pump.
  19. 19. The semiconductor processing apparatus according to claim 12, further comprising a plasma generation unit coupled to the process chamber.
  20. 20. The semiconductor processing apparatus according to claim 12, further comprising a magnet disposed in such a way so as to distract material fragments or particles released from the exposed surface of the semiconductor substrate.
  21. 21. The semiconductor processing apparatus according to claim 20, wherein one of the poles of the magnet faces the semiconductor substrate.
  22. 22. A method for processing a semiconductor substrate, the method comprising:
    providing a reactor chamber comprising an upper wall and a lower wall and a hold member to hold a semiconductor substrate to be processed;
    placing the semiconductor substrate onto the hold member in such a way that it faces the lower wall of the reactor chamber; and
    processing the semiconductor substrate while the semiconductor substrate faces the lower wall of the reactor chamber.
  23. 23. The method according to claim 22, wherein processing the semiconductor substrate comprises feeding a process gas into the reactor chamber.
  24. 24. The method according to claim 22, wherein processing the semiconductor substrate comprises feeding a radio frequency signal into the reactor chamber.
  25. 25. The method according to claim 22, wherein processing the semiconductor substrate comprises feeding a plasma gas into the reactor chamber.
US13305161 2011-11-28 2011-11-28 Semiconductor Processing System Abandoned US20130137273A1 (en)

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US5731130A (en) * 1996-11-12 1998-03-24 Vanguard International Semiconductor Corporation Method for fabricating stacked capacitors on dynamic random access memory cells
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US20030180495A1 (en) * 1999-02-09 2003-09-25 Kazunori Ito Optical device substrate film-formation apparatus, optical disk substrate film-formation method, substrate holder manufacture method, substrate holder, optical disk and a phase-change recording type of optical disk
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