US20130121084A1 - Method and apparatus to provide data including hard bit data and soft bit data to a rank modulation decoder - Google Patents

Method and apparatus to provide data including hard bit data and soft bit data to a rank modulation decoder Download PDF

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US20130121084A1
US20130121084A1 US13293988 US201113293988A US20130121084A1 US 20130121084 A1 US20130121084 A1 US 20130121084A1 US 13293988 US13293988 US 13293988 US 201113293988 A US201113293988 A US 201113293988A US 20130121084 A1 US20130121084 A1 US 20130121084A1
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voltage
bit
threshold
soft
hard
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US13293988
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US8456919B1 (en )
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Seungjune Jeon
Sergey Anatolievich Gorobets
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SanDisk Technologies LLC
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SanDisk Technologies LLC
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642Sensing or reading circuits; Data output circuits
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1072Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in multilevel memories

Abstract

A method includes providing data including hard bit data and soft bit data to a rank modulation decoder.

Description

    FIELD OF THE DISCLOSURE
  • [0001]
    The present disclosure is generally related to decoding data at a rank modulation decoder.
  • BACKGROUND
  • [0002]
    Non-volatile memory devices, such as universal serial bus (USB) flash memory devices or removable storage cards, have allowed for increased portability of data and software applications. Flash memory devices can enhance data storage density by storing multiple bits in each flash memory cell. For example, Multi-Level Cell (MLC) flash memory devices provide increased storage density by storing 3 bits per cell, 4 bits per cell, or more.
  • [0003]
    Storing multiple bits of information in a single flash memory cell typically includes mapping sequences of bits to states of the flash memory cell. For example, a first sequence of bits “110” may correspond to a first state of a flash memory cell and a second sequence of bits “010” may correspond to a second state of the flash memory cell. After determining that a sequence of bits is to be stored into a particular flash memory cell, the flash memory cell may be programmed to a state that corresponds to the sequence of bits.
  • [0004]
    Alternatively, multiple bits of information in a single flash memory cell may be stored as relative voltage levels of multiple cells of the memory rather than as absolute voltage levels in each cell. For example, each storage element of the memory may have a threshold voltage corresponding to a state of the storage element. A group of storage elements may store data based on relative threshold voltages of the storage elements in the group. Data may be read from the group of storage elements by ranking the storage elements according to threshold voltages and mapping the ranking to a corresponding data value at a rank modulation decoder.
  • [0005]
    Once the memory cells in the memory device have been programmed, data may be read from the memory cells by sensing the programming states of the memory cells. However, sensed programming states can sometimes vary from the written programming states due to one or more factors. Error correction decoding can be used to correct data errors resulting from sensed programming states that do not match written programming states.
  • SUMMARY
  • [0006]
    Improved error correction capability of a rank modulation decoder may be achieved by decoding data using soft bits and hard bits. To illustrate, soft bits and hard bits may be used as an input to a rank modulation decoder to enhance error correction capability in a multi-level-cell (MLC) memory system, as compared to a decoding scheme that is based on using hard bits only as an input to the rank modulation decoder.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0007]
    FIG. 1 is a block diagram of a first illustrative embodiment of a system that provides data including hard bit data and soft bit data to a rank modulation decoder;
  • [0008]
    FIG. 2 is a diagram illustrating use of soft bits and hard bits in rank modulation decoding;
  • [0009]
    FIG. 3 is a general diagram illustrating a particular embodiment of a sensing scheme and includes a graphical depiction of cell state distributions and threshold read voltages for hard bits and additional sensed (soft) bits provided to a rank modulation decoder;
  • [0010]
    FIG. 4 is a general diagram graphically illustrating states of a three-cell rank modulation group;
  • [0011]
    FIG. 5 is a general diagram illustrating an example of hard bit thresholds in a three-cell group using rank modulation decoding;
  • [0012]
    FIG. 6 is a general diagram illustrating an example of soft bit thresholds in a three-cell group using rank modulation decoding;
  • [0013]
    FIG. 7 is a general diagram illustrating an example of soft bit thresholds in a four cell group using rank modulation decoding;
  • [0014]
    FIG. 8 is a general diagram illustrating an example of one soft bit threshold per hard bit region in a two cell group using rank modulation decoding; and
  • [0015]
    FIG. 9 is a flow diagram illustrating a particular embodiment of a method of providing data including hard bit data and soft bit data to a rank modulation decoder.
  • DETAILED DESCRIPTION
  • [0016]
    Decoding techniques may provide improved error correction as data storage device dimensions decrease and storage density increases. Using soft bits and hard bits as an input to a rank modulation decoder in multi-level-cell (MLC) memory systems can enhance error correction capability.
  • [0017]
    Systems and methods of providing data including hard bit data and soft bit data to a rank modulation decoder include a capability to provide data including hard bit data and soft bit data read from a memory of a data storage device to the rank modulation decoder.
  • [0018]
    Referring to FIG. 1, a particular illustrative embodiment of a system of providing data including hard bit data and soft bit data to a rank modulation decoder is depicted and generally designated 100. The system 100 includes a data storage device 102 coupled to a host device 130. The data storage device 102 includes a memory 104 coupled to a controller 106 via a bus 150.
  • [0019]
    The data storage device 102 may be a memory card, such as a Secure Digital SD® card, a microSD® card, a miniSD™ card (trademarks of SD-3C LLC, Wilmington, Del.), a MultiMediaCard™ (MMC™) card (trademark of JEDEC Solid State Technology Association, Arlington, Va.), or a CompactFlash® (CF) card (trademark of SanDisk Corporation, Milpitas, Calif.). As another example, the data storage device 102 may be embedded memory in the host device 130, such as eMMC® (trademark of JEDEC Solid State Technology Association, Arlington, Va.) memory and eSD memory, as illustrative examples.
  • [0020]
    The memory 104 may be a non-volatile memory of a flash device, such as a NAND flash device, a NOR flash device, or any other type of flash device. The memory 104 includes a memory portion 110 and read thresholds 120. The memory portion 110 includes a plurality of storage elements, such as memory cells of a multi-level cell (MLC) memory. A group of storage elements 112 may include multiple MLC storage elements, such as representative storage elements 113, 115, 117 of a word line 119 of a flash memory device. Each storage element 113-117 may have a threshold voltage corresponding to a state of the storage element (e.g., a predefined state corresponding to a particular range of threshold voltage values). The group of storage elements 112 may store data based on relative threshold voltages (or states) of the storage elements 113-117. The states of the storage elements 113-117 may be read by comparing the threshold voltages to one or more of the read thresholds 120.
  • [0021]
    The read thresholds 120 include a hard bits threshold 122 and a soft bits threshold 124. As described in further detail with respect to FIG. 3, the hard bits threshold 122 may include threshold read voltages for hard bits (e.g., voltages AR, BR, . . . GR in FIG. 3) and the soft bits threshold 124 may include threshold read voltages for additional sensed bits or soft bits (e.g., voltages AR-V1, AR+V2, AR-V3, AR+V4, in FIG. 3). To illustrate, the storage elements 113-117 may each be programmed to one of multiple predefined states. Each of the predefined states may be mapped to a particular bit value (e.g. a single bit value (“0” or “1”) or a multi-bit value, such as “101”). The bit value that corresponds to the determined MLC state is referred to as “hard bit(s)”. Additional information that can be used to indicate a reliability of the reading of the storage element is referred to as a “soft bit”. A soft bit can be used by an error correction coding (ECC) engine 108 within a rank modulation decoder 116 in conjunction with one or more hard bits to enhance a reading operation by indicating a relative reliability of the hard bits read from the memory 104.
  • [0022]
    The controller 106 includes the ECC engine 108 and the rank modulation decoder 116. The ECC engine 108 may be configured to detect errors in the read data corresponding to the storage elements 112. An output of the rank modulation decoder 116 may be provided to the host device 130 while the data storage device 102 is operatively coupled to the host device 130.
  • [0023]
    To write data to the memory 104, the controller 106 may provide a rank modulation codeword 140 to the memory 104 via the bus 150. For example, the bus 150 may be a Secure Digital (SD) bus. The memory 104 is configured to store the representation of the rank modulation codeword 140 in the memory portion 110. The rank modulation codeword 140 may be based on a non-binary symbol, such as symbol indicating a ranking of cells in one or more groups of cells according to relative threshold voltages of the cells. A number of cells in each group may equal the size of the non-binary symbol. A ranking of cells in each group (i.e., a relative threshold voltage each cell is programmed to) indicates a value of the non-binary symbol. For example, a three-cell group may have six possible rankings and each possible ranking may correspond to a value of a non-binary symbol. For a group including cell 1, cell 2, and cell 3, having threshold voltages V1, V2, and V3, respectively, values of the non-binary symbol can correspond to rankings of the cells according to: V1>V2>V3=000, V1>V3>V2=001, V2>V1>V3=010, V2>V3>V1=011, V3>V1>V2=100, and V3>V2>V1=101, as an illustrative, non-limiting example.
  • [0024]
    The controller 106 may be configured to receive memory access requests from the host device 130 and to process data read from the memory 104. The controller 106 may be configured to receive hard bit values 152 and soft bit values 154 from the memory 104. For example, the hard bit values 152 and the soft bit values 154 may correspond to a representation of a rank modulation codeword read from the memory 104 and may include information about the representation of the rank modulation codeword 140 stored in the memory portion 110. To illustrate, each of the storage elements 113-117 may be programmed to a particular state to have relative values of the threshold voltages of the storage elements 113-117 set to a particular ranking order. For example, a threshold voltage within a defined range of values may indicate a particular state that is represented by a bit pattern. The hard bit values and the soft bit values of the bit patterns of each storage element of the group of storage elements 112 may correspond to the representation of the rank modulation codeword read from the MLC memory.
  • [0025]
    The host device 130 may be configured to provide data to be stored at the memory 104 or to request data to be read from the memory 104. For example, the host device 130 may include a mobile telephone, a music or video player, a gaming console, an electronic book reader, a personal digital assistant (PDA), a computer, such as a laptop computer, a notebook computer, or a tablet, any other electronic device, or any combination thereof.
  • [0026]
    During operation, the host device 130 may instruct the controller 106 to retrieve data corresponding to the group of storage elements 112, such as the storage elements 113-117, from the memory 104. The memory 104 may be configured to read the representation of the rank modulation codeword 140 from the group of storage elements 112 by comparing cell threshold voltages in the memory portion 110 to the hard bit thresholds 122 to generate the hard bit values 152 and to the soft bit thresholds 124 to generate the soft bit values 154. For example, each storage element 113-117 may have a threshold voltage corresponding to a state of the storage element. The state of each storage element 113-117 (i.e., a range of threshold voltage values) may be read by comparing the threshold voltage of each of the storage elements 113-117 to the hard bit thresholds 122 to generate the hard bit values 152 and a sub-range of threshold voltage values may be read by comparing the threshold voltage of each of the storage elements 113-117 to the soft bit thresholds 124 to generate the soft bit values 154. The controller 106 may provide the hard bit values 152 and the soft bit values 154 as an input to the rank modulation decoder 116.
  • [0027]
    The rank modulation decoder 116 may be configured to map the hard bit values 152 to an ECC codeword that is decodable by the ECC engine 108. For example, the ECC engine may be a Reed Solomon ECC engine, a Bose-Chaudhuri-Hocquenghem (BCH) ECC engine, a low-density parity-check ECC engine, one or more other ECC engines, or any combination thereof. The rank modulation decoder 116 may convert the hard bit values 152 to an ECC codeword that is input to the ECC engine 108.
  • [0028]
    The soft bit values 154 may provide reliability information about the states read from the storage elements 113-117 in the memory portion 110. The reliability information may include, for each storage element 113-117 that is read, a value that indicates a likelihood that the hard bit values for that storage element are correct. For example, the soft bit values 154 may be used by the rank modulation decoder 116 to obtain a reliability indicator for each bit of the ECC codeword provided to the ECC engine 108, such as a log-likelihood ratio (LLR). The rank modulation decoder 116 may be configured to use the reliability information to guide error correction processing at the ECC engine 108 to generate decoded data bits based on the received hard bit values 152 and the soft bit values 154. For example, the ECC engine 108 may perform probabilistic decoding by iteratively updating bit estimates and LLRs of the bit estimates based on bit estimates and LLRs of the bit estimates of a prior iteration of a decoding process to converge to a most probable ECC codeword. The soft bit values 154 enable the rank modulation decoder 116 to establish initial reliability values (e.g., LLRs) that are more accurate than default LLRs that may be used by conventional decoders that use hard bits only. Using more accurate initial reliability values (e.g. LLRs based on the soft bit values 154) enables the rank modulation decoder 116 to converge more quickly and/or more accurately. As a result, decoding of a representation of an ECC codeword may be performed with reduced latency, with improved error correction capability, or a combination thereof.
  • [0029]
    Rank modulation is a technique in which information may be stored as relative voltage levels of multiple cells of the memory rather than as absolute voltage levels in each cell. For example, in a single level cell (SLC) memory having four cells, four bits may be stored as absolute voltage levels in each cell of the cells. In a two-bits-per-cell (2-BPC) memory having four cells, 8 bits (e.g., 2×4) may be stored.
  • [0030]
    In contrast to storing data as absolute voltage levels, rank modulation using four cells to represent information may be described by denoting the four cells as 1, 2, 3, and 4, respectively. Each of the four cells 1-4 may have a corresponding threshold voltage denoted by V1, V2, V3, and V4, respectively. The four cells 1-4 may be ranked or represented in descending order of their respective voltage levels. For example, a 3-4-1-2 ranking of voltage levels may represent that V3>V4>V1>V2.
  • [0031]
    Accordingly, there are 4! (i.e., 4 factorial)=24 combinations (i.e., rankings of voltage levels) for the four cells. By using four memory cells in a rank modulation scheme, log2 24=4.585 bits may be represented. This number is slightly higher than that of a conventional SLC memory using four cells but lower than a conventional 2-BPC memory having four cells.
  • [0032]
    Table 1 illustrates a number of bits that can be stored in an M-cell unit.
  • [0000]
    TABLE 1
    Rank
    Modulation 1-BPC 2-BPC 3-BPC
    M cells log2 (M!) M 2M 3M
    2 cells 1 2 4 6
    3 cells 2.585 3 6 9
    4 cells 4.585 4 8 12
  • [0033]
    If four cells are used together for rank modulation, when writing information to a memory, user data may be mapped to one of the twenty four combinations by some predefined mapping, such as a Gray mapping, and the voltage cell may be programmed according to the predefined voltage rank among the four cells. For example, if the chosen rank combination is 3-4-1-2, the voltage may be programmed such that V3>V4>V1>V2. When the user data is read back, the relative voltages of the four cells may be sensed and a ranking may be determined. For example, if U1, U2, U3, and U4 denote the sensed voltages of the cells 1, 2, 3, and 4, respectively, and if it is determined that U3>U4>U1>U2, then it may be determined that the 3-4-1-2 combination is correctly read among the twenty four possible combinations. If other ranks, such as 4-3-1-2 or 3-1-4-2 were read, a read error may be detected and handled using error correction coding. Either binary or non-binary error correction codes may be used.
  • [0034]
    An illustrative example of using rank modulation in a two cell unit is shown in FIG. 2. FIG. 2 depicts a general diagram 200 illustrating a use of soft bits and hard bits in rank modulation decoding. The diagram 200 includes the memory 104 coupled to the controller 106 via the bus 150.
  • [0035]
    The memory 104 (shown with dashed lines) includes a table 210, the first representative storage element 113, and the second representative storage element 115. The table 210 may include hard bit data and soft bit data, such as hard bits 260 and soft bits 262, respectively, stored in latches or registers of the memory 104. The hard bit data and the soft bit data indicates a threshold voltage range for each storage element, enabling determination of a relative voltage level (i.e., a ranking) of the storage elements that indicates stored information at the first storage element 113 and at the second storage element 115.
  • [0036]
    To illustrate, each of the storage elements 113, 115 may have a corresponding threshold voltage. For example, the first storage element 113 may have a first threshold voltage V1 230 in a first voltage range VT1 250 and the second storage element 115 may have a second threshold voltage V2 232 in a second voltage range VT2 252. For example, the first voltage range VT1 250 may be from zero volts to two volts and the second voltage range VT2 252 may also be from zero volts to two volts.
  • [0037]
    The hard bits 260 may indicate results of comparing the threshold voltage of each particular cell (e.g., the first threshold voltage V1 230 and the second threshold voltage V2 232) to one or more hard bit thresholds. For example, data may be read from the first storage element 113 and from the second storage element 115 by comparing a threshold voltage of each storage elements to a first hard bit threshold or read voltage VR1 242 and to a second hard bit threshold or read voltage VR2 246. As illustrated, the first hard bit read voltage VR1 242 is less than the second hard bit read voltage VR2 246.
  • [0038]
    The hard bits 260 (i.e., HB1, HB2) having a value of “11” may correspond to a threshold voltage value greater than the second hard bit read voltage VR2 246. The hard bits 260 having a value of “10” may correspond to a threshold voltage value between the first hard bit read voltage VR1 242 and the second hard bit read voltage VR2 246. The hard bits 260 having a value of “00” may correspond to a threshold voltage value less than the first hard bit read voltage VR1 242.
  • [0039]
    As illustrated, the first threshold voltage V1 230 is greater than the first hard bit read voltage VR1 242 and less than the second hard bit read voltage VR2
  • [0040]
    246. The second threshold voltage V2 232 is less than the first hard bit read voltage VR1 242 and less than the second hard bit read voltage VR2 246. Accordingly, the hard bits 260 having a value of “10” (i.e., illustrated as HB1=1 and HB2=0 in the table 210) indicates that the first threshold voltage V1 230 is greater than the first hard bit read voltage VR1 242 and less than the second hard bit read voltage VR2 246. Similarly, the hard bits 260 having a value of “00” (i.e., illustrated as HB1=0 and HB2=0 in the table 210) indicates that the second threshold voltage V2 232 is less than the first hard bit read voltage VR1 242 and less than the second hard bit read voltage VR2 246.
  • [0041]
    The soft bits 262 may indicate results of comparing the threshold voltage of each particular cell (e.g., the first threshold voltage V1 230 and the second threshold voltage V2 232) to one or more soft bit thresholds. For example, the threshold voltage of the first storage element 113 and of the second storage element 115 may be compared to a first soft bit threshold or read voltage S1 240, a second soft bit threshold or read voltage S2 244, and a third soft bit threshold or read voltage S3 248. As illustrated, the first soft bit read voltage S1 240 may be less than the second soft bit read voltage S2 244, and the second soft bit read voltage S2 244 may be less than the third soft bit read voltage S3 248. In addition, the first hard bit read voltage VR1 242 may be less than the second soft bit read voltage S2 244 and greater than the first soft bit read voltage S1 240, and the second hard bit read voltage VR2 246 may be greater than the second soft bit read voltage S2 244 and less than the third soft bit read voltage S3 248. A first difference between the first soft bit read voltage S1 240 and the first hard bit read voltage VR1 242 may be substantially equal to a second difference between the first hard bit read voltage VR1 242 and the second soft bit read voltage S2 244.
  • [0042]
    The soft bits 262 (i.e., SB1, SB2) having a value of “11” may correspond to a threshold voltage value greater than the third soft bit read voltage S3 248. The soft bits 262 having a value of “10” may correspond to a threshold voltage value between the third soft bit read voltage S3 248 and the second soft bit read voltage S2 244. The soft bits 262 having a value of “01” may correspond to a threshold voltage value between the second soft bit read voltage S2 244 and the first soft bit read voltage S1 240. The soft bits 262 having a value of “00” may correspond to a threshold voltage value less than the first soft bit read voltage S1 240. Accordingly, the soft bits 262 for storage element 113 having a value of “10” indicates that the first threshold voltage V1 230 has a value between the third soft bit read voltage S3 248 and the second soft bit read voltage S2 244. Similarly, the soft bits 262 for storage element 115 having a value of “01” indicates that the second threshold voltage V2 232 has a value between the second soft bit read voltage S2 244 and the first soft bit read voltage S1 240.
  • [0043]
    The controller 106 (shown with dashed lines) includes the rank modulation decoder 116 that includes a mapper 220, a reliability indicator 222, and the error correction engine 108. The controller 106 may be configured to provide data read from the memory 104 to the rank modulation decoder 116. The data may include hard bit data, such as the hard bits 260, and soft bit data, such as the soft bits 262. For example, the controller 106 may receive data from the table 210 and provide the HB1, HB2, SB1, and SB2 values for each cell to the rank modulation decoder 116.
  • [0044]
    The mapper 220 may be configured to logically partition the data into groups of bits. Each group of bits may correspond to a group of cells in the memory 104. For example, the first storage element 113 and the second storage element 115 may correspond to one group of bits. The mapper 220 may be further configured to rank cells of each particular group of cells according to cell threshold voltages. For example, the mapper 220 may compare the first threshold voltage V1 230 and the second threshold voltage V2 232 and generate a ranking based on the comparison. For example, if the first threshold voltage V1 230 is greater than the second threshold voltage V2 232, a ranking of “1-2” may be generated by the mapper 220. Similarly, if the second threshold voltage V2 232 is greater than the first threshold voltage V1 230, a ranking of “2-1” may be generated by the mapper 220.
  • [0045]
    The mapper 220 may be further configured to map each group of bits to a data value according to the cell ranking of the group of cells corresponding to the group of bits. For example, the mapper 220 may generate a single bit symbol or data value (e.g., a “1” or a “0”) based on a comparison of the first threshold voltage V1 230 and the second threshold voltage V2 232. If the first threshold voltage V1 230 is greater than the second threshold voltage V2 232, a data value of “1” may be generated by the mapper 220. If the second threshold voltage V2 232 is greater than the first threshold voltage V1 230, a value of “0” may be generated by the mapper 220. As another example, more than two storage elements can correspond to the group of bits. For example and as explained above, four cells or storage elements may be used to represent the data. In that case, the mapper 220 may generate a multi-bit symbol or data value (e.g., a 5-bit data value of “11001”, “01100, etc.) based on a comparison of the threshold voltages of each cell. The mapper 220 may send the data values based on cell ranking to the ECC engine 108 as an ECC codeword 270.
  • [0046]
    The reliability indicator 222 may be configured to indicate a relative reliability of bit values in the ECC codeword 270 generated by the mapper 220 and may send relative reliability values to the ECC engine 108 as ECC soft bits 272. The relative reliability may be based at least in part on a difference between the threshold voltages of the cells of each particular group as determined based on the soft bit thresholds S1-S3. For example, the relative reliability may increase as a difference between cell threshold voltages increases. To illustrate, if the difference between the first threshold voltage V1 230 and the second threshold voltage V2 232 is large, the relative reliability of the data value generated by the mapper 220 may be higher than if the difference between the first threshold voltage V1 230 and the second threshold voltage V2 232 is small. For example, a reliability indicator of “1” may indicate that the difference between the first threshold voltage V1 230 and the second threshold voltage V2 232 is large, and a reliability indicator of “0” may indicate that the difference between the first threshold voltage V1 230 and the second threshold voltage V2 232 is small.
  • [0047]
    The reliability indicator 222 may be configured to determine whether the first threshold voltage V1 230 and the second threshold voltage V2 232 are in adjacent sub-regions. For example, the first hard bit read voltage VR1 242 and the second hard bit read voltage VR2 246 may divide the first voltage range VT1 250 into three regions. The first soft bit read voltage S1 240, the second soft bit read voltage S2 244, and the third soft bit read voltage S3 248 may divide each region into two sub-regions. Based on the hard bits 260 and the soft bits 262, the reliability indicator 222 can determine which of the six sub-regions the first threshold voltage V1 230 is in and which of the six sub-regions the second threshold voltage V2 232 is in. When the first threshold voltage V1 230 and the second threshold voltage V2 232 are in adjacent sub-regions, a “0” may be output by the reliability indicator 222. When the first threshold voltage V1 230 and the second threshold voltage V2 232 are not in adjacent sub-regions, a “1” (or a larger number) may be output by the reliability indicator 222.
  • [0048]
    The controller 106 may be configured to initiate an ECC procedure on the ECC codeword 270 by providing the ECC codeword 270 and the ECC soft bits 272 to the ECC engine 108. For example, the ECC engine 108 may employ an ECC decoding scheme, such as a Reed Solomon ECC decoding scheme, a Bose-Chaudhuri-Hocquenghem (BCH) ECC decoding scheme, a low-density parity-check ECC decoding scheme, one or more other ECC decoding schemes, or any combination thereof. The ECC engine 108 may provide output data indicating that the ECC codeword 270 was correctly decoded.
  • [0049]
    During operation, the controller 106 may be instructed by the host device (not shown) to retrieve data corresponding to the storage elements 113, 115 from the memory 104. The controller 106 may provide data including hard bit data, such as hard bits 260 (i.e., HB1, HB2), and soft bit data, such as soft bits 262 (i.e., SB1, SB2), to the rank modulation decoder 116. The rank modulation decoder 116 may be configured to logically partition the data into groups of bits, where each group of bits may correspond to a group of cells in the memory 104. For example, the mapper 220 may compare the first threshold voltage V1 230 and the second threshold voltage V2 232 and generate a ranking based on the comparison. The rank modulation decoder 116 may be further configured to map each group of bits to a data value according to the cell ranking of the group of cells corresponding to the group of bits. For example, the mapper 220 may generate a data value based on a comparison of the first threshold voltage V1 230 and the second threshold voltage V2 232 and may send the data value based on cell ranking to the ECC engine 108 as the ECC codeword 270. A relative reliability of bit values in the ECC codeword 270 generated by the mapper 220 may be determined by the reliability indicator 222 and relative reliability values may be sent to the ECC engine 108 as the ECC soft bits 272. For example, if the difference between the first threshold voltage V1 230 and the second threshold voltage V2 232 is large, the relative reliability of the data value generated by the mapper 220 may be higher than if the difference between the first threshold voltage V1 230 and the second threshold voltage V2 232 is small. The controller 106 may be configured to initiate an ECC procedure on the ECC codeword 270 by providing the ECC codeword 270 and the ECC soft bits 272 to the ECC engine 108. The ECC engine 108 may provide output data indicating that the ECC codeword 270 was correctly decoded.
  • [0050]
    As illustrated by being shown with dashed lines, one or more components of FIG. 2 may be moved from a location as shown to a different location. For example, the mapper 220, the reliability indicator 222, or both, may be within the memory 104.
  • [0051]
    FIG. 3 shows an embodiment 300 of a sensing scheme and includes a graphical depiction 302 of cell distributions for voltage regions (i.e. states) (Er, A, . . . G) of a storage element of a memory, such as a representative memory cell 310, and threshold read voltages for hard bits (e.g., voltages AR, BR, . . . GR) and for additional sensed soft bits (e.g., voltages AR-V1, AR+V2, AR-V3, AR+V4, . . . ). A table 304 illustrates a mapping of each voltage interval between adjacent threshold read voltages to a set of six bits including three hard bits (HB1, HB2, HB3) and three soft bits (SB1, SB2, SB3). A pattern of hard bits and soft bits at the memory cell 310 may have a threshold voltage 312 corresponding to a state of the memory cell 310. A pattern of hard bits and soft bits at the memory cell 310 may be generated by comparing the threshold voltage 312 to the threshold read voltages for hard bits (e.g., voltages AR, BR, . . . GR) to generate hard bits 314 and to the threshold read voltages for soft bits (e.g., voltages AR-V1, AR+V2, AR-V3, AR+V4, . . . ) to generate soft bits 316.
  • [0052]
    The hard bits 314 indicate which state (Er-G) the threshold voltage 312 is in, and the soft bits 316 indicate whether the threshold voltage 312 is within a center of the state's voltage range or near an edge of the state's voltage range (e.g., indicates a proximity to voltage CR). As an example, a first voltage difference (V1) between a first soft bit threshold (e.g., CR-V1) and a particular hard bit threshold (e.g., CR) is substantially equal to a second voltage difference (V2) between the particular hard bit threshold (e.g., CR) and a second soft bit threshold (e.g., CR+V2). Further, as illustrated in FIG. 3, a third voltage difference (V3) between a third soft bit threshold and the particular hard bit threshold (CR) is substantially equal to a fourth voltage difference (V4) between the particular hard bit threshold (CR) and a fourth soft bit threshold. As illustrated, the first voltage difference (V1) is different than the third voltage difference (V3). As illustrated, the threshold voltage 312 is between BR and CR, indicating that the cell 310 is in state “B”, corresponding to hard bits “100”. The threshold voltage 312 is also in a sub-region between CR-V1 and CR, corresponding to a soft bit value of “001”.
  • [0053]
    The controller 106 may provide the hard bits 314 and the soft bits 316 to an input of a rank modulation decoder 320 to obtain decoded data. The soft bits 316 may include reliability information about the hard bits read from the memory cell 310. The rank modulation decoder 320 may be configured to use the soft bits 316 indicating a sub-region of the cell's state (i.e., the sub-region of the state “B” closest to the voltage CR) to guide error correction processing based on the received soft bits, such as by generating ECC soft bits to be input to an ECC decoder, such as the ECC soft bits 272 of FIG. 2.
  • [0054]
    Referring to FIG. 4, a general diagram graphically illustrating states of a three-cell rank modulation group is depicted and generally designated 400. The diagram 400 illustrates three axes labeled as U1, U2, and U3 that define a space (U1, U2, U3). Planes U1=U2, U2=U3, and U3=U1 are illustrated that partition the space (U1, U2, U3) into 3!=6 regions. Four of the six regions (i.e., regions C, D, E, and F) are shown and two of the six regions (i.e., regions A and B) are hidden by the planes. For example, the states of the three-cell rank modulation group may correspond to states of a three-cell group including cell 1, cell 2, and cell 3 (e.g. the storage elements 113, 115, and 117 of FIG. 1, respectively) where U1 is a threshold voltage of cell 1 (e.g. the storage element 113), U2 is a threshold voltage of cell 2 (e.g. the storage element 115), and U3 is a threshold voltage of cell 3 (e.g. the storage element 117). Each region A-F corresponds to a different data value stored in the three-cell rank modulation group. To illustrate, region E corresponds to the state U1>U3>U2.
  • [0055]
    Referring to FIG. 5, a general diagram 500 illustrates an example of hard bit thresholds of the three-cell rank modulation group of FIG. 4. The diagram 500 illustrates intersections between the line U3 of FIG. 4 and each of two surfaces: U3=U1 at U1=u1 and U3=U2 at U2=u2, where u1 and u2 correspond to voltage measurements of one of the three cells (i.e., cell 1) and another one of the three cells (i.e., cell 2), respectively. An upper portion or top line 510 corresponds to a region where u1<u2, and a lower portion or bottom line 520 corresponds to a region where u1>u2. The voltage measurements u1 and u2 may correspond to voltage thresholds that may be used to determine hard bit values.
  • [0056]
    For example, a threshold voltage (u1) of cell 1 and a threshold voltage (u2) of cell 2 may be measured (or otherwise determined). The threshold voltages u1 and u2 may be used as hard bit thresholds to compare to a threshold voltage (u3) of cell 3. If u1<u2 and the threshold voltage of cell 3 is less than u1, then a hard bit may indicate that a measure point (e.g., a threshold voltage of cell 3) is within region A. If u1<u2 and the threshold voltage of cell 3 is between u1 and u2, then a hard bit may indicate that the measure point is within region B. If u1>u2 and the threshold voltage of cell 3 is greater than u2, then a hard bit may indicate that the measure point is within region C. Similarly, If u2<u1 and the threshold voltage of cell 3 is less than u2, then a hard bit may indicate that the measure point is within region D. If u2<u1 and the threshold voltage of cell 3 is between u1 and u2, then a hard bit may indicate that the measure point is within region E. If u2<u1 and the threshold voltage of cell 3 is greater than u1, then a hard bit may indicate that the measure point is within region F. As illustrated, a hard bit that corresponds to a hard bit threshold may only provide information as to which particular region among the six regions the measure point belongs to.
  • [0057]
    Referring to FIG. 6, a general diagram illustrating an example of soft bit thresholds in a three-cell group in rank modulation decoding is depicted and generally designated 600. The diagram 600 illustrates dividing each hard bit region of FIG. 5 (i.e., hard bit regions A, B, C, D, E, and F) into smaller sub-regions (i.e., sub-regions A1, A2, B1, B2, C1, C2, D1, D2, E1, E2, F1, F2). For example, soft bit thresholds (denoted by T1, T2, . . . T6) may be added between the values of u1 and u2 to divide each hard bit region into smaller regions. As illustrated in FIG. 5, six regions or possible results from voltage sensing may be achieved using only hard bits, and three bits may be used to represent this result. If soft bits and hard bits are used as shown in FIG. 6, twelve possible results from voltage sensing may be achieved, and four bits may be used to represent this result.
  • [0058]
    Referring to FIG. 7, a general diagram illustrating an example of soft bit thresholds in a four cell group in rank modulation decoding is depicted and generally designated 700. A top line 710 illustrates using hard bits only, a middle line 720 illustrates the addition of one soft bit threshold per hard bit region, and a bottom line 730 illustrates the addition of two soft bit thresholds per hard bit region. The variables w1, w2, w3, and w4 may correspond to voltage measurements u1, u2, u3, and u4 in ascending order of voltage. Accordingly, there are 3!=6 possible combinations (i.e., for w1, w2, and w3) for comparison to w4. As illustrated, there are four regions shown in the top line 710 (i.e., using hard bits only), where each of the four regions has six possible combinations, for a total of twenty four possible combinations. Accordingly, five bits may be used to represent the twenty four combinations. There are eight regions shown in the middle line 720 (i.e., adding one soft bit threshold per hard bit region of line 710), where each of the eight regions has six possible combinations, for a total of forty eight possible combinations. Accordingly, six bits may be used to represent the forty eight combinations. There are twelve regions shown in the bottom line 730 (i.e., adding two soft bit thresholds per hard bit region of line 710), where each of the twelve regions has six possible combinations, for a total of seventy two possible combinations. Accordingly, seven bits may be used to represent the seventy two combinations. Similarly, another number of soft bit thresholds per hard bit region, such as three soft bit thresholds or more, may also be added per hard bit region. Alternatively, the number of soft bit thresholds per hard bit region may not be uniform. For example, the number of soft bit thresholds may differ between a hard bit region defined by w1 and w2 and a hard bit region defined by w2 and w3.
  • [0059]
    Each line shown in FIG. 5 (i.e., line 510, line 520), FIG. 6 (i.e., line 610, line 620), and FIG. 7 (i.e., line 710, line 720, line 730) may be referred to as a projection line. For M-cell rank modulation, if L soft bit thresholds are added per projection line, a number of bits that can represent a voltage sensing result may be represented as log2(M-1)!(M+L) (rounded up to a nearest integer value), where (M-1)! is the number of cases (projection lines). For example, for M=3 as illustrated in FIG. 6, the number of projection lines is (3-1)!=2 (i.e. a line for the case U1>U2 and a line for the case U1<U2), and for M=4 as illustrated in FIG. 7, the number of cases is (4−1)!=6 (i.e. a line for each of the cases W1>W2>W3, W1>W3>W2, W2>W1>W3, W2>W3>W1, W3>W1>W1, and W3>W2>W1). (M+L) is the number of regions per projection line.
  • [0060]
    For example, when writing data to a memory when M=2, a first cell (cell 1) may be programmed at a voltage V1 and a second cell (cell 2) may be programmed at a voltage V2 to store a hard bit X such that V1>V2 if X=0, and V1<V2 if X=1. When reading the data, a voltage U1 may be sensed in cell 1 and a voltage U2 may be sensed in cell 2. A hard bit Y (an estimate of X) may be read such that Y=0 if U1>U2, and Y=1 if U1<U2.
  • [0061]
    An uncertainty due to physical effects may be modeled such that U1=V1+N1, and U2=V2+N2, where N1 and N2 are random variables that describe the uncertainty. Any arbitrary random variables may be used, including zero-mean Gaussian random variables.
  • [0062]
    For example, a transition probability matrix can be illustrated for a hard bit only case as follows:
  • [0000]
    Q hard = ( P ( U 1 > U 2 | V 1 > V 2 ) P ( U 1 > U 2 | V 1 < V 2 ) P ( U 1 < U 2 | V 1 > V 2 ) P ( U 1 < U 2 | V 1 < V 2 ) ) .
  • [0000]
    where P(A|B) indicates the probability of A given B. For example, P(U1>U21V1>V2) indicates the probability that cell 1 is read as having a greater threshold voltage than cell 2 given that cell 1 is programmed to have a greater threshold than cell 2. If programming occurs such that |V1-V2|=d, then the transition probability matrix in terms of the uncertainty or noise variables and the voltage spacing d may be illustrated as
  • [0000]
    Q hard = ( P ( N 1 - N 2 > - d | X = 0 ) P ( N 1 - N 2 > - d | X = 1 ) P ( N 1 - N 2 < - d | X = 0 ) P ( N 1 - N 2 < - d | X = 1 ) ) .
  • [0063]
    N may be defined as N=N1−N2 to simplify the notation
  • [0000]
    Q hard = ( P ( N > - d | X = 0 ) P ( N > d | X = 1 ) P ( N < - d | X = 0 ) P ( N < d | X = 1 ) ) .
  • [0064]
    Note that an expectation of N(E(N))=E(N1)−E(N2) and a variance of N(Var(N))=Var(N1)+Var(N2).
  • [0065]
    If the M cells have identical noise variances, the overall noise variance is M times each cell's noise variance. That is, the M-cell noise sigma (i.e., standard deviation) will be √{square root over (M)} times the noise sigma of one cell. The transition probability matrix for hard bits may be used to compare a cell information capacity using hard bits only to rank modulation cell information capacity using hard bits and soft bits, as explained with respect to FIG. 8.
  • [0066]
    Referring to FIG. 8, a general diagram illustrating an example of one soft bit threshold per hard bit region in a two cell (i.e., M=2) group is depicted and generally designated 800. A first soft bit threshold T1 and a second soft bit threshold T2 are illustrated defining sub-regions R1, R2, R3, and R4.
  • [0067]
    Using FIG. 8, a transition probability matrix may be determined
  • [0000]
    Q soft 1 = ( P ( R 1 | V 1 > V 2 ) P ( R 1 | V 1 < V 2 ) P ( R 2 | V 1 > V 2 ) P ( R 2 | V 1 < V 2 ) P ( R 3 | V 1 > V 2 ) P ( R 3 | V 1 < V 2 ) P ( R 4 | V 1 > V 2 ) P ( R 4 | V 1 < V 2 ) )
  • [0068]
    If h1 and h2 are defined such that U1−T1=h1 and T2−U1=h2, then
  • [0000]
    Q soft 1 = ( P ( U 2 < U 1 - h 1 | V 1 > V 2 ) P ( U 2 < U 1 - h 1 | V 1 < V 2 ) P ( U 1 - h 1 < U 2 < U 1 | V 1 > V 2 ) P ( U 1 - h 1 < U 2 < U 1 | V 1 < V 2 ) P ( U 1 < U 2 < U 1 + h 2 | V 1 > V 2 ) P ( U 1 < U 2 < U 1 + h 2 | V 1 < V 2 ) P ( U 1 + h 2 < U 2 | V 1 > V 2 ) P ( U 1 + h 2 < U 2 | V 1 < V 2 ) )
  • [0069]
    In terms of noise variables:
  • [0000]
    Q soft 1 = ( P ( N > - d + h 1 | X = 0 ) P ( N > d + h 1 | X = 1 ) P ( - d + h 1 > N > - d | X = 0 ) P ( d + h 1 > N > d | X = 1 ) P ( - d > N > - d - h 2 | X = 0 ) P ( d > N > d - h 2 | X = 1 ) P ( N < - d - h 2 | X = 0 ) P ( N < d - h 2 | X = 1 ) )
  • [0070]
    Each memory cell, such as the memory cell 310 of FIG. 3, has a theoretical storage capacity to store an amount of information, referred to as an information capacity (C). The information capacity (C) is a function of probabilities that particular data values are stored to a cell and probabilities of errors occurring to the stored data values due to noise or other effects in the cell. A theoretical lower bound of a cell's information capacity occurs when all data values are equally probable to be stored in the cell (known as “information capacity with scrambler assumption”—data is assumed to be scrambled prior to storage and therefore all data values are equally probable). An information capacity (C) in bits/cell and a lower bound information capacity with scrambler assumption (Cscramble) may be calculated as follows:
  • [0000]
    C = max p ( X ) X , R p ( R | X ) p ( X ) log 2 p ( R | X ) X p ( R | X ) p ( X ) , C scramble = 1 X X , Y p ( R | X ) log 2 p ( R | X ) X X p ( R | X ) ,
  • [0000]
    where X is the original hard bits that were written in a writing operation, R is a voltage region that is sensed during a read operation, and |X| is the number of possible hard bits.
  • [0071]
    For example, in 3-cell rank modulation with hard bits only, X may be one of the 3!=6 combinations (|X|=6) and R may be one of the 6 voltage regions. A conditional probability mass function (PMF) p(R|X) may be given as the transition probability matrix Qsoft1 as illustrated above.
  • [0072]
    Table 2 (below) illustrates, for several values of cell error rate (CER) and voltage spacing (d) between program states of cells in a rank modulation scheme, examples of soft bit threshold shift (h) values, cell information capacity values, and cell lifetime capacity values. Table 2 provides examples for cells that can be programmed to a threshold voltage in a 2 volt (V) range from −1V to 1V and having a 0.002% CER, a 0.2% CER, and a 1% CER in a conventional SLC scheme not using rank modulation (the CER corresponding to a noise standard deviation (sigma) of 0.2435, 0.3474, and 0.4299, respectively). For M=2, it may be assumed that the noise component in each cell is independent and identically distributed zero-mean Gaussian random variables with variance σ2. Accordingly, E(N)=0 and Var(N)=2σ2. A symmetric scheme h1=h2 may be used.
  • [0073]
    For each CER, examples are given for d=2V (i.e. the cells are programmed to −1V or to 1V), d=1V (i.e. the cells are programmed to −1V, 0V, or 1V), d=⅔V (i.e. the cells are programmed to −1V, −⅓V, ⅓V, or 1V), and d=0.5V (i.e. the cells are programmed to −1V, —⅓V, 0V, ½V, or 1V). For each value of d, an “optimal” soft-bit threshold shift (e.g. h1=h2) is provided as a value calculated to provide a theoretical maximum information capacity per cell. Information capacity is provided for the cells using hard bits only and using one soft bit for comparison purposes.
  • [0074]
    In addition, Table 2 provides examples of a lifetime information capacity of cells as the information capacity multiplied by (2/d), where 2/d indicates a number of data values that may be sequentially written to a group of cells without erasing the cells. For example, when d=2, each cell is programmed to −1V or to 1V, and a group of cells is erased each time a new data value is written to the group (i.e. changing a ranking from “1-2” to “2-1” or from “2-1” to “1-2”). In contrast, when d=½, the group of cells may be written four times without erasing. To illustrate:
  • [0075]
    Write #1: Program cell 1 to −1V, cell 2 to −½V; rank =“0-1”; data=0
  • [0076]
    Write #2: Program cell 1 to 0V, cell 2 to −½V; rank=“1-0”; data=1
  • [0077]
    Write #3: Program cell 1 to 0V, cell 2 to ½V; rank=“0-1”; data=0
  • [0078]
    Write #4: Program cell 1 to 1V, cell 2 to ½V; rank=“1-0”; data=1
  • [0079]
    Because using d=½ may result in four times fewer cell erasures than using d=2, a cell lifetime that may otherwise be limited by a number of erase cycles may be extended by a factor of four by using d=½ as compared to d=2.
  • [0000]
    TABLE 2
    optimal Lifetime capacity:
    CER (%) w/o Noise voltage soft-bit capacity capacity * (2/d)
    Rank Mod, sigma for spacing: d = threshold Hard bit Hard bit
    SLC +/− 1 V single cell |V1 − V2| shift: h only 1 Soft bit only 1 Soft bit
    0.002% 0.2435 2 0.2856 0.9997 0.9999 0.9997 0.9999
    0.002% 0.2435 1 0.3622 0.8586 0.9099 1.7171 1.8198
    0.002% 0.2435 0.3928 0.5788 0.6709 1.7365 2.0127
    0.002% 0.2435   0.5 0.4234 0.3846 0.4723 1.5383 1.8893
     0.2% 0.3474 2 0.4541 0.9792 0.9897 0.9792 0.9897
     0.2% 0.3474 1 0.5459 0.6155 0.7055 1.2309 1.4110
     0.2% 0.3474 0.6072 0.3453 0.4291 1.0360 1.2874
     0.2% 0.3474   0.5 0.6378 0.2118 0.2741 0.8474 1.0965
       1% 0.4299 2 0.6072 0.9192 0.9527 0.9192 0.9527
       1% 0.4299 1 0.7144 0.4638 0.5564 0.9277 1.1128
       1% 0.4299 0.7603 0.2416 0.3098 0.7248 0.9293
       1% 0.4299   0.5 0.7909 0.1440 0.1903 0.5759 0.7612
  • [0080]
    As illustrated in Table 2, information capacity is improved using one soft bit as compared to using hard bits only. In addition, although cell information capacity is reduced as d is increased, cell lifetime information capacity may instead increase as d is increased. A similar analysis for rank modulation of M>2 cells may also be performed.
  • [0081]
    FIG. 9 depicts a flowchart that illustrates an embodiment of a method of providing data including hard bit data and soft bit data to a rank modulation decoder. The method 900 may be performed in a data storage device having a flash multi-level cell (MLC) memory. For example, the method 900 may be performed in the data storage device 102 of FIG. 1.
  • [0082]
    Hard bit data and soft bit data may be read from a flash memory, at 902. For example, the memory 104 may be configured to read the representation of the rank modulation codeword 140 from the group of storage elements 112 by comparing cell threshold voltages in the memory portion 110 to the hard bit thresholds 122 to generate the hard bit values 152 and to the soft bit thresholds 124 to generate the soft bit values 154.
  • [0083]
    Data, including hard bit data (e.g. the hard bit values 152 of FIG. 1) and soft bit data (e.g. the soft bit values 154 of FIG. 1), may be provided to a rank modulation decoder, at 904. For example, the memory 104 may include read circuitry configured to compare cell threshold voltages to one or more hard bit thresholds to generate the hard bit values 152 and to one or more soft bit thresholds to generate the soft bit values 154, latches configured to latch results of the comparisons, and a bus interface configured to provide the the hard bit values 152 and the soft bit values 154 to the rank modulation decoder 116.
  • [0084]
    To illustrate, the data may be read from multiple cells of a memory, such as the storage elements 113-117 of the memory 104, where each particular cell of the multiple cells has a threshold voltage, and where the hard bit data includes hard bits that indicate results of comparing the threshold voltage of each particular cell to one or more hard bit thresholds and where the soft bit data includes soft bits that indicate results of comparing the threshold voltage of each particular cell to one or more soft bit thresholds.
  • [0085]
    For example, the first storage element 113 may have the first threshold voltage V1 230 in the first voltage range VT1 250 and the second storage element 115 may have the second threshold voltage V2 232 in the second voltage range VT2 252. Data may be read from the first storage element 113 and from the second storage element 115 based on comparisons of threshold voltages of the first storage element 113 and the second storage element 115 to the first hard bit threshold VR1 242 and to the second hard bit threshold VR2 246 to generate the hard bits 260. The hard bits 260 may indicate results of the comparisons of the threshold voltage of each particular cell (e.g., the first threshold voltage V1 230 and the second threshold voltage V2 232) and may indicate whether the first threshold voltage V1 230 is greater than or less than the second threshold voltage V2 232. For example, the hard bits 260 (i.e., HB1, HB2) having a value of “11” may correspond to a threshold voltage value greater than the second hard bit read voltage VR2 246. The hard bits 260 having a value of “10” may correspond to a threshold voltage value between the first hard bit read voltage VR1 242 and the second hard bit read voltage VR2 246. The hard bits 260 having a value of “00” may correspond to a threshold voltage value less than the first hard bit read voltage VR1 242.
  • [0086]
    The soft bits may indicate results of comparing the threshold voltage of each particular cell (e.g., the first threshold voltage V1 230 and the second threshold voltage V2 232) to one or more soft bit thresholds (also referred to as soft bit read voltages) and may indicate whether the first threshold voltage V1 230 is greater than or less than the first soft bit read voltage (e.g., threshold S1 240). For example, the threshold voltage of the first storage element 113 and of the second storage element 115 may be compared to the first soft bit read voltage or threshold S1 240, to the second soft bit read voltage or threshold S2 244, and to the third soft bit read voltage or threshold S3 248. In addition, the soft bits may indicate whether the first threshold voltage V1 230 is greater than or less than the second soft bit read voltage S2 244, where the first soft bit read voltage S1 240 is less than the second threshold voltage V2 232, and where the second soft bit read voltage S2 244 is greater than the second threshold voltage V2 232.
  • [0087]
    The method 900 may be performed on a multi-cell rank modulation group, such as a three-cell rank modulation group. For example, the flash memory 104 may include a third cell (i.e., the storage element 117) having a third threshold voltage. The hard bit data may further indicate whether the third threshold voltage is in a first range of voltages that are less than the first threshold voltage V1 230 and the second threshold voltage V2 232, in a second range of voltages that are between the first threshold voltage V1 230 and the second threshold voltage V2 232, or in a third range of voltages that are greater than the first threshold voltage V1 230 and the second threshold voltage V2 232. The soft bit data may indicate whether the third threshold voltage is in one or more sub-ranges of the first range of voltages, the second range of voltages, or the third range of voltages.
  • [0088]
    The controller 106 may be configured to provide data read from the memory 104 to the rank modulation decoder 116. For example, the controller 106 may receive the data via a bus interface and may provide the received data to an input of the rank modulation decoder 116. The data may include the hard bits 260 and the soft bits 262. The rank modulation decoder 116 may be configured to logically partition the data into groups of bits, where each group of bits corresponds to a group of cells in the memory 104, and may rank cells of each particular group of cells according to cell threshold voltages to produce a cell ranking of the particular group of cells. For example, the mapper 220 may compare the first threshold voltage V1 230 and the second threshold voltage V2 232 and generate a ranking based on the comparison. The rank modulation decoder 116 may be configured to map each group of bits to a data value according to the cell ranking of the group of cells corresponding to the group of bits. For example, the mapper 220 may generate a data value based on a comparison of the first threshold voltage V1 230 and the second threshold voltage V2 232 and may send the data value based on cell ranking to the ECC engine 108 as the ECC codeword 270.
  • [0089]
    By providing data including hard bit data and soft bit data to a rank modulation decoder, error correction at the rank modulation decoder may be performed more quickly and/or accurately as compared to rank modulation decoding using hard bits only. As explained with reference to Table 2, cell information capacity may be increased by using rank modulation decoding using hard bits and soft bits as compared to rank modulation decoding using hard bits only.
  • [0090]
    Although various components depicted herein are illustrated as block components and described in general terms, such components may include one or more microprocessors, state machines, or other circuits configured to enable a data storage device, such as the data storage device 102 of FIG. 1, to perform the particular functions attributed to such components, or any combination thereof. For example, the rank modulation decoder 116 of FIG. 1 and FIG. 2 may represent physical components, such as controllers, processors, state machines, logic circuits, or other structures to logically partition the data into groups of bits, where each group of bits corresponds to a group of cells in a flash memory, to rank cells of each particular group of cells, and to map each group of bits to a data value according to the cell ranking of the group of cells corresponding to the group of bits.
  • [0091]
    The rank modulation decoder 116 may be implemented using a microprocessor or microcontroller programmed to generate data from rank modulated data using soft bits. In a particular embodiment, the controller 106 includes a processor executing instructions that are stored at the memory 104. Alternatively, or in addition, executable instructions that are executed by the processor may be stored at a separate memory location that is not part of the memory 104, such as at a read-only memory (ROM) (not shown).
  • [0092]
    In a particular embodiment, the data storage device 102 may be a portable device configured to be selectively coupled to one or more external devices. For example, the data storage device 102 may be a removable device such as a Universal Serial Bus (USB) flash drive or a removable memory card, as illustrative examples. However, in other embodiments, the data storage device 102 may be attached or embedded within one or more host devices, such as within a housing of a portable communication device. For example, the data storage device 102 may be within a packaged apparatus, such as a wireless telephone, a personal digital assistant (PDA), a gaming device or console, a portable navigation device, a computer, or other device that uses internal non-volatile memory. In a particular embodiment, the data storage device 102 includes a non-volatile memory, such as a Flash memory (e.g., NAND, NOR, Multi-Level Cell (MLC), Divided bit-line NOR (DINOR), AND, high capacitive coupling ratio (HiCR), asymmetrical contactless transistor (ACT), or other Flash memories), an erasable programmable read-only memory (EPROM), an electrically-erasable programmable read-only memory (EEPROM), a read-only memory (ROM), a one-time programmable memory (OTP), or any other type of memory.
  • [0093]
    The illustrations of the embodiments described herein are intended to provide a general understanding of the various embodiments. Other embodiments may be utilized and derived from the disclosure, such that structural and logical substitutions and changes may be made without departing from the scope of the disclosure. This disclosure is intended to cover any and all subsequent adaptations or variations of various embodiments.
  • [0094]
    The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the scope of the present disclosure. Thus, to the maximum extent allowed by law, the scope of the present invention is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.

Claims (20)

  1. 1. A method comprising:
    providing data including hard bit data and soft bit data to a rank modulation decoder,
    wherein the rank modulation decoder is configured to:
    logically partition the data into groups of bits, wherein each group of bits corresponds to a group of cells in a flash memory;
    rank cells of each particular group of cells according to cell threshold voltages to produce a cell ranking of the particular group of cells; and
    map each group of bits to a data value according to the cell ranking of the group of cells corresponding to the group of bits.
  2. 2. The method of claim 1, wherein the data is read from multiple cells of a the flash memory, wherein each particular cell of the multiple cells has a threshold voltage, and wherein the hard bit data includes hard bits that indicate results of comparing the threshold voltage of each particular cell of the multiple cells to one or more hard bit read voltages.
  3. 3. The method of claim 2, wherein the soft bit data includes soft bits that indicate results of comparing the threshold voltage of each particular cell of the multiple cells to one or more soft bit read voltages.
  4. 4. (canceled)
  5. 5. The method of claim 1, further comprising reading the hard bit data and the soft bit data from a the flash memory.
  6. 6. The method of claim 5, wherein the flash memory includes a first cell having a first threshold voltage and a second cell having a second threshold voltage, and wherein the hard bit data indicates whether the first threshold voltage is greater than or less than the second threshold voltage.
  7. 7. The method of claim 6, wherein the soft bit data indicates whether the first threshold voltage is greater than or less than a first soft bit read voltage.
  8. 8. The method of claim 7, wherein the soft bit data further indicates whether the first threshold voltage is greater than or less than a second soft bit read voltage, wherein the first soft bit read voltage is less than the second threshold voltage, and wherein the second soft bit read voltage is greater than the second threshold voltage.
  9. 9. The method of claim 8, wherein a first difference between the first soft bit read voltage and the second threshold voltage is substantially equal to a second difference between the second threshold voltage and the second soft bit read voltage.
  10. 10. The method of claim 6, wherein the flash memory includes a third cell having a third threshold voltage, and wherein the hard bit data further indicates whether the third threshold voltage is in a first range of voltages that are less than the first threshold voltage and the second threshold voltage, in a second range of voltages that are between the first threshold voltage and the second threshold voltage, or in a third range of voltages that are greater than the first threshold voltage and the second threshold voltage, and wherein the soft bit data indicates whether the third threshold voltage is in one or more sub-ranges of the first range of voltages, the second range of voltages, or the third range of voltages.
  11. 11. A data storage device comprising:
    a memory;
    a rank modulation decoder; and
    a controller configured to provide data read from the memory to the rank modulation decoder, wherein the data includes hard bit data and soft bit data, wherein the memory is a flash memory and wherein the rank modulation decoder is configured to:
    logically partition the data into groups of bits, wherein each group of bits corresponds to a group of cells in the flash memory;
    rank storage elements of each particular group of storage elements according to storage element threshold voltages to produce a storage element ranking of the particular group of storage elements; and
    map each group of bits to a data value.
  12. 12. The data storage device of claim 11, wherein the data is read from multiple storage elements of the flash memory, wherein each particular storage element of the multiple storage elements has a threshold voltage, and wherein the hard bit data includes hard bits that indicate results of comparing the threshold voltage of each particular storage element to one or more hard bit read voltages.
  13. 13. The data storage device of claim 12, wherein the soft bit data includes soft bits that indicate results of comparing the threshold voltage of each particular storage element to one or more soft bit read voltages.
  14. 14-15. (canceled)
  15. 16. The data storage device of claim 12, wherein the multiple storage elements include a first storage element having a first threshold voltage and a second storage element having a second threshold voltage, and wherein the hard bit data indicates whether the first threshold voltage is greater than or less than the second threshold voltage.
  16. 17. The data storage device of claim 16, wherein the soft bit data indicates whether the first threshold voltage is greater than or less than a first soft bit read voltage.
  17. 18. The data storage device of claim 17, wherein the soft bit data further indicates whether the first threshold voltage is greater than or less than a second soft bit read voltage, wherein the first soft bit read voltage is less than the second threshold voltage, and wherein the second soft bit read voltage is greater than the second threshold voltage.
  18. 19. The data storage device of claim 18, wherein a first difference between the first soft bit read voltage and the second threshold voltage is substantially equal to a second difference between the second threshold voltage and the second soft bit read voltage.
  19. 20. The data storage device of claim 16, wherein the multiple storage elements include a third storage element having a third threshold voltage, and wherein the hard bit data further indicates whether the third threshold voltage is in a first range of voltages that are less than the first threshold voltage and the second threshold voltage, in a second range of voltages that are between the first threshold voltage and the second threshold voltage, or in a third range of voltages that are greater than the first threshold voltage and the second threshold voltage, and wherein the soft bit data indicates whether the third threshold voltage is in one or more sub-ranges of the first range of voltages, the second range of voltages, or the third range of voltages.
  20. 21. A method comprising:
    providing data including hard bit data and soft bit data to a rank modulation decoder; and
    reading the hard bit data and the soft bit data from a flash memory;
    wherein the flash memory includes a first cell having a first threshold voltage and a second cell having a second threshold voltage, and wherein the hard bit data indicates whether the first threshold voltage is greater than or less than the second threshold voltage.
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Cited By (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130268723A1 (en) * 2012-03-08 2013-10-10 Texas A&M University System Flash memories using minimum push up, multi-cell and multi-permutation schemes for data storage
US20130275829A1 (en) * 2012-04-12 2013-10-17 Seagate Technology Llc Using a soft decoder with hard data
US9058289B2 (en) 2011-11-07 2015-06-16 Sandisk Enterprise Ip Llc Soft information generation for memory systems
US9092350B1 (en) 2013-03-15 2015-07-28 Sandisk Enterprise Ip Llc Detection and handling of unbalanced errors in interleaved codewords
US9129665B2 (en) 2013-12-17 2015-09-08 Sandisk Enterprise Ip Llc Dynamic brownout adjustment in a storage device
US9136877B1 (en) 2013-03-15 2015-09-15 Sandisk Enterprise Ip Llc Syndrome layered decoding for LDPC codes
US9152556B2 (en) 2007-12-27 2015-10-06 Sandisk Enterprise Ip Llc Metadata rebuild in a flash memory controller following a loss of power
US9159437B2 (en) 2013-06-11 2015-10-13 Sandisk Enterprise IP LLC. Device and method for resolving an LM flag issue
US20150304125A1 (en) * 2012-04-16 2015-10-22 Entropic Communications, Llc Progressive modulation for downstream access
US9236886B1 (en) 2013-03-15 2016-01-12 Sandisk Enterprise Ip Llc Universal and reconfigurable QC-LDPC encoder
US9235509B1 (en) 2013-08-26 2016-01-12 Sandisk Enterprise Ip Llc Write amplification reduction by delaying read access to data written during garbage collection
US9235245B2 (en) 2013-12-04 2016-01-12 Sandisk Enterprise Ip Llc Startup performance and power isolation
US9239751B1 (en) 2012-12-27 2016-01-19 Sandisk Enterprise Ip Llc Compressing data from multiple reads for error control management in memory systems
US9244763B1 (en) 2013-03-15 2016-01-26 Sandisk Enterprise Ip Llc System and method for updating a reading threshold voltage based on symbol transition information
US9244785B2 (en) 2013-11-13 2016-01-26 Sandisk Enterprise Ip Llc Simulated power failure and data hardening
US9263156B2 (en) 2013-11-07 2016-02-16 Sandisk Enterprise Ip Llc System and method for adjusting trip points within a storage device
US9298608B2 (en) 2013-10-18 2016-03-29 Sandisk Enterprise Ip Llc Biasing for wear leveling in storage systems
US9367246B2 (en) 2013-03-15 2016-06-14 Sandisk Technologies Inc. Performance optimization of data transfer for soft information generation
WO2016094741A1 (en) * 2014-12-10 2016-06-16 California Institute Of Technology Improving nand flash reliability with rank modulation
US9384126B1 (en) 2013-07-25 2016-07-05 Sandisk Technologies Inc. Methods and systems to avoid false negative results in bloom filters implemented in non-volatile data storage systems
US9390814B2 (en) 2014-03-19 2016-07-12 Sandisk Technologies Llc Fault detection and prediction for data storage elements
US9390021B2 (en) 2014-03-31 2016-07-12 Sandisk Technologies Llc Efficient cache utilization in a tiered data structure
US9436831B2 (en) 2013-10-30 2016-09-06 Sandisk Technologies Llc Secure erase in a memory device
US9442662B2 (en) 2013-10-18 2016-09-13 Sandisk Technologies Llc Device and method for managing die groups
US9443601B2 (en) 2014-09-08 2016-09-13 Sandisk Technologies Llc Holdup capacitor energy harvesting
US9448876B2 (en) 2014-03-19 2016-09-20 Sandisk Technologies Llc Fault detection and prediction in storage devices
US9454420B1 (en) 2012-12-31 2016-09-27 Sandisk Technologies Llc Method and system of reading threshold voltage equalization
US9454448B2 (en) 2014-03-19 2016-09-27 Sandisk Technologies Llc Fault testing in storage devices
US9501398B2 (en) 2012-12-26 2016-11-22 Sandisk Technologies Llc Persistent storage device with NVRAM for staging writes
US9520162B2 (en) 2013-11-27 2016-12-13 Sandisk Technologies Llc DIMM device controller supervisor
US9520197B2 (en) 2013-11-22 2016-12-13 Sandisk Technologies Llc Adaptive erase of a storage device
US9524235B1 (en) 2013-07-25 2016-12-20 Sandisk Technologies Llc Local hash value generation in non-volatile data storage systems
US9582058B2 (en) 2013-11-29 2017-02-28 Sandisk Technologies Llc Power inrush management of storage devices
US9612948B2 (en) 2012-12-27 2017-04-04 Sandisk Technologies Llc Reads and writes between a contiguous data block and noncontiguous sets of logical address blocks in a persistent storage device
US9626400B2 (en) 2014-03-31 2017-04-18 Sandisk Technologies Llc Compaction of information in tiered data structure
US9626399B2 (en) 2014-03-31 2017-04-18 Sandisk Technologies Llc Conditional updates for reducing frequency of data modification operations
US9639463B1 (en) 2013-08-26 2017-05-02 Sandisk Technologies Llc Heuristic aware garbage collection scheme in storage systems
US9652381B2 (en) 2014-06-19 2017-05-16 Sandisk Technologies Llc Sub-block garbage collection
US9699263B1 (en) 2012-08-17 2017-07-04 Sandisk Technologies Llc. Automatic read and write acceleration of data accessed by virtual machines
US9697267B2 (en) 2014-04-03 2017-07-04 Sandisk Technologies Llc Methods and systems for performing efficient snapshots in tiered data structures
US9703636B2 (en) 2014-03-01 2017-07-11 Sandisk Technologies Llc Firmware reversion trigger and control
US9703816B2 (en) 2013-11-19 2017-07-11 Sandisk Technologies Llc Method and system for forward reference logging in a persistent datastore
US9703491B2 (en) 2014-05-30 2017-07-11 Sandisk Technologies Llc Using history of unaligned writes to cache data and avoid read-modify-writes in a non-volatile storage device
US9772935B2 (en) 2014-09-16 2017-09-26 Empire Technology Development Llc Data storage based on rank modulation in single-level flash memory
US9870830B1 (en) * 2013-03-14 2018-01-16 Sandisk Technologies Llc Optimal multilevel sensing for reading data from a storage medium
US9916197B2 (en) 2012-03-08 2018-03-13 California Institute Of Technology Rank-modulation rewriting codes for flash memories

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8644067B2 (en) * 2011-11-30 2014-02-04 Sandisk Technologies Inc. Systems and methods of decoding data using soft bits at a non-binary decoder that uses probabilistic decoding
JP2014157650A (en) * 2013-02-18 2014-08-28 Toshiba Corp Semiconductor memory device
US20160317712A1 (en) 2013-12-19 2016-11-03 Juvora Limited Dental implant incorporating an apatite
US9553608B2 (en) 2013-12-20 2017-01-24 Sandisk Technologies Llc Data storage device decoder and method of operation
US9306600B2 (en) 2014-01-06 2016-04-05 Micron Technology, Inc. Read threshold calibration for LDPC
US9589654B2 (en) 2014-04-15 2017-03-07 Empire Technology Development Llc Rank determination of circuits with distinct current carrying capabilities
US9202558B1 (en) * 2014-08-12 2015-12-01 Empire Technology Development Llc Programming memory cells according to a rank modulation scheme
KR20160073834A (en) * 2014-12-17 2016-06-27 에스케이하이닉스 주식회사 Semiconductor memory device and operating method thereof

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7656706B2 (en) * 2007-01-05 2010-02-02 The Texas A&M University System Storing information in a memory
US7844879B2 (en) * 2006-01-20 2010-11-30 Marvell World Trade Ltd. Method and system for error correction in flash memory
US7904783B2 (en) * 2006-09-28 2011-03-08 Sandisk Corporation Soft-input soft-output decoder for nonvolatile memory
US20110296274A1 (en) * 2010-05-31 2011-12-01 International Business Machines Corporation Data encoding in solid-state storage devices
US8209588B2 (en) * 2007-12-12 2012-06-26 Anobit Technologies Ltd. Efficient interference cancellation in analog memory cell arrays
US8208304B2 (en) * 2008-11-16 2012-06-26 Anobit Technologies Ltd. Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N
US8225180B2 (en) * 2007-11-20 2012-07-17 California Institute Of Technology Error correcting codes for rank modulation
US8228701B2 (en) * 2009-03-01 2012-07-24 Apple Inc. Selective activation of programming schemes in analog memory cell arrays
US8245094B2 (en) * 2007-11-20 2012-08-14 California Institute of Technology Texas A & M Rank modulation for flash memories

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2823620B1 (en) 2001-04-12 2003-08-15 France Telecom encoding / decoding method of a stream of digital data coded with bit interleaving in multiple transmission and reception in the presence of intersymbol interference and corresponding system
US7366202B2 (en) 2003-12-08 2008-04-29 Colubris Networks, Inc. System and method for interference mitigation for wireless communication
US7814401B2 (en) 2006-12-21 2010-10-12 Ramot At Tel Aviv University Ltd. Soft decoding of hard and soft bits read from a flash memory

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7844879B2 (en) * 2006-01-20 2010-11-30 Marvell World Trade Ltd. Method and system for error correction in flash memory
US7904783B2 (en) * 2006-09-28 2011-03-08 Sandisk Corporation Soft-input soft-output decoder for nonvolatile memory
US7656706B2 (en) * 2007-01-05 2010-02-02 The Texas A&M University System Storing information in a memory
US8225180B2 (en) * 2007-11-20 2012-07-17 California Institute Of Technology Error correcting codes for rank modulation
US8245094B2 (en) * 2007-11-20 2012-08-14 California Institute of Technology Texas A & M Rank modulation for flash memories
US8209588B2 (en) * 2007-12-12 2012-06-26 Anobit Technologies Ltd. Efficient interference cancellation in analog memory cell arrays
US8208304B2 (en) * 2008-11-16 2012-06-26 Anobit Technologies Ltd. Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N
US8228701B2 (en) * 2009-03-01 2012-07-24 Apple Inc. Selective activation of programming schemes in analog memory cell arrays
US20110296274A1 (en) * 2010-05-31 2011-12-01 International Business Machines Corporation Data encoding in solid-state storage devices

Cited By (57)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9152556B2 (en) 2007-12-27 2015-10-06 Sandisk Enterprise Ip Llc Metadata rebuild in a flash memory controller following a loss of power
US9483210B2 (en) 2007-12-27 2016-11-01 Sandisk Technologies Llc Flash storage controller execute loop
US9239783B2 (en) 2007-12-27 2016-01-19 Sandisk Enterprise Ip Llc Multiprocessor storage controller
US9158677B2 (en) 2007-12-27 2015-10-13 Sandisk Enterprise Ip Llc Flash storage controller execute loop
US9448743B2 (en) 2007-12-27 2016-09-20 Sandisk Technologies Llc Mass storage controller volatile memory containing metadata related to flash memory storage
US9058289B2 (en) 2011-11-07 2015-06-16 Sandisk Enterprise Ip Llc Soft information generation for memory systems
US9230652B2 (en) * 2012-03-08 2016-01-05 California Institute Of Technology Flash memories using minimum push up, multi-cell and multi-permutation schemes for data storage
US20130268723A1 (en) * 2012-03-08 2013-10-10 Texas A&M University System Flash memories using minimum push up, multi-cell and multi-permutation schemes for data storage
US20160170684A1 (en) * 2012-03-08 2016-06-16 California Institute Of Technology Flash memories using minimum push up, multi-cell and multi-permutation schemes for data storage
US9666280B2 (en) * 2012-03-08 2017-05-30 California Institute Of Technology Flash memories using minimum push up, multi-cell and multi-permutation schemes for data storage
US9916197B2 (en) 2012-03-08 2018-03-13 California Institute Of Technology Rank-modulation rewriting codes for flash memories
US20130275829A1 (en) * 2012-04-12 2013-10-17 Seagate Technology Llc Using a soft decoder with hard data
US8943384B2 (en) * 2012-04-12 2015-01-27 Seagate Technology Llc Using a soft decoder with hard data
US20150304125A1 (en) * 2012-04-16 2015-10-22 Entropic Communications, Llc Progressive modulation for downstream access
US9780962B2 (en) * 2012-04-16 2017-10-03 Entropic Communications, Llc Progressive modulation for downstream access
US9699263B1 (en) 2012-08-17 2017-07-04 Sandisk Technologies Llc. Automatic read and write acceleration of data accessed by virtual machines
US9501398B2 (en) 2012-12-26 2016-11-22 Sandisk Technologies Llc Persistent storage device with NVRAM for staging writes
US9239751B1 (en) 2012-12-27 2016-01-19 Sandisk Enterprise Ip Llc Compressing data from multiple reads for error control management in memory systems
US9612948B2 (en) 2012-12-27 2017-04-04 Sandisk Technologies Llc Reads and writes between a contiguous data block and noncontiguous sets of logical address blocks in a persistent storage device
US9454420B1 (en) 2012-12-31 2016-09-27 Sandisk Technologies Llc Method and system of reading threshold voltage equalization
US9870830B1 (en) * 2013-03-14 2018-01-16 Sandisk Technologies Llc Optimal multilevel sensing for reading data from a storage medium
US9367246B2 (en) 2013-03-15 2016-06-14 Sandisk Technologies Inc. Performance optimization of data transfer for soft information generation
US9236886B1 (en) 2013-03-15 2016-01-12 Sandisk Enterprise Ip Llc Universal and reconfigurable QC-LDPC encoder
US9092350B1 (en) 2013-03-15 2015-07-28 Sandisk Enterprise Ip Llc Detection and handling of unbalanced errors in interleaved codewords
US9136877B1 (en) 2013-03-15 2015-09-15 Sandisk Enterprise Ip Llc Syndrome layered decoding for LDPC codes
US9244763B1 (en) 2013-03-15 2016-01-26 Sandisk Enterprise Ip Llc System and method for updating a reading threshold voltage based on symbol transition information
US9159437B2 (en) 2013-06-11 2015-10-13 Sandisk Enterprise IP LLC. Device and method for resolving an LM flag issue
US9384126B1 (en) 2013-07-25 2016-07-05 Sandisk Technologies Inc. Methods and systems to avoid false negative results in bloom filters implemented in non-volatile data storage systems
US9524235B1 (en) 2013-07-25 2016-12-20 Sandisk Technologies Llc Local hash value generation in non-volatile data storage systems
US9235509B1 (en) 2013-08-26 2016-01-12 Sandisk Enterprise Ip Llc Write amplification reduction by delaying read access to data written during garbage collection
US9639463B1 (en) 2013-08-26 2017-05-02 Sandisk Technologies Llc Heuristic aware garbage collection scheme in storage systems
US9361221B1 (en) 2013-08-26 2016-06-07 Sandisk Technologies Inc. Write amplification reduction through reliable writes during garbage collection
US9298608B2 (en) 2013-10-18 2016-03-29 Sandisk Enterprise Ip Llc Biasing for wear leveling in storage systems
US9442662B2 (en) 2013-10-18 2016-09-13 Sandisk Technologies Llc Device and method for managing die groups
US9436831B2 (en) 2013-10-30 2016-09-06 Sandisk Technologies Llc Secure erase in a memory device
US9263156B2 (en) 2013-11-07 2016-02-16 Sandisk Enterprise Ip Llc System and method for adjusting trip points within a storage device
US9244785B2 (en) 2013-11-13 2016-01-26 Sandisk Enterprise Ip Llc Simulated power failure and data hardening
US9703816B2 (en) 2013-11-19 2017-07-11 Sandisk Technologies Llc Method and system for forward reference logging in a persistent datastore
US9520197B2 (en) 2013-11-22 2016-12-13 Sandisk Technologies Llc Adaptive erase of a storage device
US9520162B2 (en) 2013-11-27 2016-12-13 Sandisk Technologies Llc DIMM device controller supervisor
US9582058B2 (en) 2013-11-29 2017-02-28 Sandisk Technologies Llc Power inrush management of storage devices
US9235245B2 (en) 2013-12-04 2016-01-12 Sandisk Enterprise Ip Llc Startup performance and power isolation
US9129665B2 (en) 2013-12-17 2015-09-08 Sandisk Enterprise Ip Llc Dynamic brownout adjustment in a storage device
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US9697267B2 (en) 2014-04-03 2017-07-04 Sandisk Technologies Llc Methods and systems for performing efficient snapshots in tiered data structures
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US9772935B2 (en) 2014-09-16 2017-09-26 Empire Technology Development Llc Data storage based on rank modulation in single-level flash memory
US9983991B2 (en) 2014-09-16 2018-05-29 Empire Technology Development Llc Data storage based on rank modulation in single-level flash memory
WO2016094741A1 (en) * 2014-12-10 2016-06-16 California Institute Of Technology Improving nand flash reliability with rank modulation

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