US20120241834A1 - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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Publication number
US20120241834A1
US20120241834A1 US13/234,052 US201113234052A US2012241834A1 US 20120241834 A1 US20120241834 A1 US 20120241834A1 US 201113234052 A US201113234052 A US 201113234052A US 2012241834 A1 US2012241834 A1 US 2012241834A1
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Prior art keywords
sidewall
dimension
formed
semiconductor device
pattern
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Abandoned
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US13/234,052
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English (en)
Inventor
Fumiharu Nakajima
Toshiya Kotani
Hiromitsu Mashita
Takafumi Taguchi
Ryota Aburada
Chikaaki Kodama
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Toshiba Corp
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Toshiba Corp
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Publication date
Priority to JP2011066181A priority Critical patent/JP5395837B2/ja
Priority to JP2011-066181 priority
Application filed by Toshiba Corp filed Critical Toshiba Corp
Assigned to KABUSHIKI KAISHA TOSHIBA reassignment KABUSHIKI KAISHA TOSHIBA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ABURADA, RYOTA, KOTANI, TOSHIYA, TAGUCHI, TAKAFUMI, KODAMA, CHIKAAKI, MASHITA, HIROMITSU, NAKAJIMA, FUMIHARU
Publication of US20120241834A1 publication Critical patent/US20120241834A1/en
Application status is Abandoned legal-status Critical

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226Via connections in a multilevel interconnection structure
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338Process specially adapted to improve the resolution of the mask
    • HELECTRICITY
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31144Etching the insulating layers by chemical or physical means using masks
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816Aspects relating to the layout of the pattern or to the size of vias or trenches
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    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688Integrated circuits having a three-dimensional layout
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    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • H01L27/11517Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate
    • H01L27/11521Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region
    • H01L27/11524Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
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    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • H01L27/11517Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate
    • H01L27/11551Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels
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    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • H01L27/11563Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM
    • H01L27/11568Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region
    • H01L27/1157Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
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    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • H01L27/11563Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM
    • H01L27/11578Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels
US13/234,052 2011-03-24 2011-09-15 Semiconductor device and method of manufacturing the same Abandoned US20120241834A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2011066181A JP5395837B2 (ja) 2011-03-24 2011-03-24 半導体装置の製造方法
JP2011-066181 2011-03-24

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/025,372 US9177854B2 (en) 2011-03-24 2013-09-12 Method of manufacturing semiconductor device using sidewall films for pitch multiplication in forming interconnects
US14/858,726 US20160013097A1 (en) 2011-03-24 2015-09-18 Semiconductor device and method of manufacturing the same
US15/226,852 US9917049B2 (en) 2011-03-24 2016-08-02 Semiconductor device having contacts in drawing area and the contacts connected to word lines extending from element formation area

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US14/025,372 Active US9177854B2 (en) 2011-03-24 2013-09-12 Method of manufacturing semiconductor device using sidewall films for pitch multiplication in forming interconnects
US14/858,726 Abandoned US20160013097A1 (en) 2011-03-24 2015-09-18 Semiconductor device and method of manufacturing the same
US15/226,852 Active US9917049B2 (en) 2011-03-24 2016-08-02 Semiconductor device having contacts in drawing area and the contacts connected to word lines extending from element formation area

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US14/025,372 Active US9177854B2 (en) 2011-03-24 2013-09-12 Method of manufacturing semiconductor device using sidewall films for pitch multiplication in forming interconnects
US14/858,726 Abandoned US20160013097A1 (en) 2011-03-24 2015-09-18 Semiconductor device and method of manufacturing the same
US15/226,852 Active US9917049B2 (en) 2011-03-24 2016-08-02 Semiconductor device having contacts in drawing area and the contacts connected to word lines extending from element formation area

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Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120020158A1 (en) * 2010-07-21 2012-01-26 Kabushiki Kaisha Toshiba Semiconductor memory device and manufacturing method thereof
US20130237051A1 (en) * 2011-12-27 2013-09-12 Keisuke Kikutani Method of manufacturing semiconductor device
US8785327B2 (en) * 2012-01-06 2014-07-22 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
US20140248765A1 (en) * 2011-10-24 2014-09-04 SK Hynix Inc. Semiconductor memory device having dummy conductive patterns on interconnection and fabrication method thereof
US20140293694A1 (en) * 2006-06-27 2014-10-02 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory having a word line bent towards a select gate line side
JP2015060873A (ja) * 2013-09-17 2015-03-30 株式会社東芝 半導体装置およびその製造方法
US20150108619A1 (en) * 2013-10-21 2015-04-23 Applied Materials, Inc. Method for patterning a semiconductor substrate
US20150179563A1 (en) * 2013-07-22 2015-06-25 Kabushiki Kaisha Toshiba Semiconductor device
US20150263032A1 (en) * 2014-03-11 2015-09-17 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and method for manufacturing same
US20160035396A1 (en) * 2014-08-04 2016-02-04 Kabushiki Kaisha Toshiba Semiconductor device
US9257367B2 (en) 2013-03-07 2016-02-09 Kabushiki Kaisha Toshiba Integrated circuit device, method for producing mask layout, and program for producing mask layout
US20160141297A1 (en) * 2014-11-13 2016-05-19 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US20160300791A1 (en) * 2015-04-09 2016-10-13 Jong-Min Lee Semiconductor devices
US20170133267A1 (en) * 2014-09-09 2017-05-11 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the semiconductor device
US9741582B2 (en) * 2014-07-31 2017-08-22 Micron Technology, Inc. Method of forming a semiconductor device including a pitch multiplication
US9858995B1 (en) * 2016-12-22 2018-01-02 Macronix International Co., Ltd. Method for operating a memory device
US10497566B1 (en) * 2018-06-19 2019-12-03 Macronix International Co., Ltd. Layout design for fanout patterns in self-aligned double patterning process
US10529579B2 (en) 2014-07-31 2020-01-07 Micron Technology, Inc. Method of forming a semiconductor device including a pitch multiplication

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014229694A (ja) * 2013-05-21 2014-12-08 株式会社東芝 半導体装置およびその製造方法
US9911693B2 (en) * 2015-08-28 2018-03-06 Micron Technology, Inc. Semiconductor devices including conductive lines and methods of forming the semiconductor devices
KR20170120895A (ko) 2016-04-22 2017-11-01 삼성전자주식회사 집적회로 소자 및 그 제조 방법

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070158688A1 (en) * 2005-09-30 2007-07-12 Dirk Caspary Memory device and a method of forming a memory device
US20090154240A1 (en) * 2007-12-17 2009-06-18 Samsung Electronics Co., Ltd. Nand flash memory devices having wiring with integrally-formed contact pads and dummy lines and methods of manufacturing the same
US20090263749A1 (en) * 2008-04-17 2009-10-22 Samsung Electronics Co., Ltd. Method of forming fine patterns of semiconductor device
US20100038795A1 (en) * 2008-08-18 2010-02-18 Ryota Aburada Method of fabricating semiconductor device and semiconductor device
US20100155959A1 (en) * 2008-12-24 2010-06-24 Samsung Electronics Co., Ltd. Semiconductor Devices Having Narrow Conductive Line Patterns and Related Methods of Forming Such Semiconductor Devices
US20110237081A1 (en) * 2009-07-02 2011-09-29 Micron Technology, Inc. Methods of Forming Memory; and Methods of Forming Vertical Structures
US20110256723A1 (en) * 2010-04-15 2011-10-20 Hynix Semiconductor Inc. Method for forming semiconductor device

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6888755B2 (en) 2002-10-28 2005-05-03 Sandisk Corporation Flash memory cell arrays having dual control gates per memory cell charge storage element
US7151040B2 (en) 2004-08-31 2006-12-19 Micron Technology, Inc. Methods for increasing photo alignment margins
JP4498088B2 (ja) * 2004-10-07 2010-07-07 株式会社東芝 半導体記憶装置およびその製造方法
US7655536B2 (en) * 2005-12-21 2010-02-02 Sandisk Corporation Methods of forming flash devices with shared word lines
JP4909735B2 (ja) * 2006-06-27 2012-04-04 株式会社東芝 不揮発性半導体メモリ
JP5132098B2 (ja) 2006-07-18 2013-01-30 株式会社東芝 半導体装置
US7807575B2 (en) * 2006-11-29 2010-10-05 Micron Technology, Inc. Methods to reduce the critical dimension of semiconductor devices
US7795080B2 (en) * 2007-01-15 2010-09-14 Sandisk Corporation Methods of forming integrated circuit devices using composite spacer structures
US7592225B2 (en) 2007-01-15 2009-09-22 Sandisk Corporation Methods of forming spacer patterns using assist layer for high density semiconductor devices
JP2009016444A (ja) * 2007-07-02 2009-01-22 Toshiba Corp 半導体メモリ
JP2010087301A (ja) 2008-09-30 2010-04-15 Toshiba Corp 半導体装置の製造方法
KR101565798B1 (ko) 2009-03-31 2015-11-05 삼성전자주식회사 콘택 패드와 도전 라인과의 일체형 구조를 가지는 반도체 소자
JP2011061003A (ja) 2009-09-10 2011-03-24 Elpida Memory Inc 配線パターン形成方法および半導体装置の製造方法、半導体装置、データ処理システム
KR101736983B1 (ko) * 2010-06-28 2017-05-18 삼성전자 주식회사 반도체 소자 및 반도체 소자의 패턴 형성 방법
KR101756226B1 (ko) * 2010-09-01 2017-07-11 삼성전자 주식회사 반도체 소자 및 그 반도체 소자의 패턴 형성방법
US8922020B2 (en) * 2010-12-29 2014-12-30 Macronix International Co., Ltd. Integrated circuit pattern and method

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070158688A1 (en) * 2005-09-30 2007-07-12 Dirk Caspary Memory device and a method of forming a memory device
US20090154240A1 (en) * 2007-12-17 2009-06-18 Samsung Electronics Co., Ltd. Nand flash memory devices having wiring with integrally-formed contact pads and dummy lines and methods of manufacturing the same
US20090263749A1 (en) * 2008-04-17 2009-10-22 Samsung Electronics Co., Ltd. Method of forming fine patterns of semiconductor device
US20100038795A1 (en) * 2008-08-18 2010-02-18 Ryota Aburada Method of fabricating semiconductor device and semiconductor device
US20100155959A1 (en) * 2008-12-24 2010-06-24 Samsung Electronics Co., Ltd. Semiconductor Devices Having Narrow Conductive Line Patterns and Related Methods of Forming Such Semiconductor Devices
US20110237081A1 (en) * 2009-07-02 2011-09-29 Micron Technology, Inc. Methods of Forming Memory; and Methods of Forming Vertical Structures
US20110256723A1 (en) * 2010-04-15 2011-10-20 Hynix Semiconductor Inc. Method for forming semiconductor device

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Bencher, C., "An assessment of patternng options for 15 nm hafl-pitch," 25-27 April 2011, IEEE, VLSI Technology, Systems and Applications (VLSI-TSA), 2011 International Symposium on, pages 1 -2. *
Bencher. C. et al. "Gridded design rule scaling; taking the CPU toward the 16 nm node," 2009, Optical Microlithography XXII, Proc. of SPIE Vol. 7274, pp. 72740G-1 to 72740G-10. *

Cited By (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8994180B2 (en) * 2006-06-27 2015-03-31 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory having a word line bent towards a select gate line side
US9202816B2 (en) 2006-06-27 2015-12-01 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory having a word line bent towards a select gate line side
US20140293694A1 (en) * 2006-06-27 2014-10-02 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory having a word line bent towards a select gate line side
US20120020158A1 (en) * 2010-07-21 2012-01-26 Kabushiki Kaisha Toshiba Semiconductor memory device and manufacturing method thereof
US20140248765A1 (en) * 2011-10-24 2014-09-04 SK Hynix Inc. Semiconductor memory device having dummy conductive patterns on interconnection and fabrication method thereof
US9087986B2 (en) * 2011-10-24 2015-07-21 SK Hynix Inc. Semiconductor memory device having dummy conductive patterns on interconnection and fabrication method thereof
US8975178B2 (en) * 2011-12-27 2015-03-10 Kabushiki Kaisha Toshiba Method of manufacturing a memory device using fine patterning techniques
US20130237051A1 (en) * 2011-12-27 2013-09-12 Keisuke Kikutani Method of manufacturing semiconductor device
US8785327B2 (en) * 2012-01-06 2014-07-22 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
US9257367B2 (en) 2013-03-07 2016-02-09 Kabushiki Kaisha Toshiba Integrated circuit device, method for producing mask layout, and program for producing mask layout
US20150179563A1 (en) * 2013-07-22 2015-06-25 Kabushiki Kaisha Toshiba Semiconductor device
JP2015060873A (ja) * 2013-09-17 2015-03-30 株式会社東芝 半導体装置およびその製造方法
US20150108619A1 (en) * 2013-10-21 2015-04-23 Applied Materials, Inc. Method for patterning a semiconductor substrate
US9698015B2 (en) * 2013-10-21 2017-07-04 Applied Materials, Inc. Method for patterning a semiconductor substrate
US20150263032A1 (en) * 2014-03-11 2015-09-17 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and method for manufacturing same
US10438809B2 (en) 2014-07-31 2019-10-08 Micron Technology, Inc. Method of forming a semiconductor device including a pitch multiplication
US10529579B2 (en) 2014-07-31 2020-01-07 Micron Technology, Inc. Method of forming a semiconductor device including a pitch multiplication
US9741582B2 (en) * 2014-07-31 2017-08-22 Micron Technology, Inc. Method of forming a semiconductor device including a pitch multiplication
US9666239B2 (en) * 2014-08-04 2017-05-30 Kabushiki Kaisha Toshiba Semiconductor device
US20160035396A1 (en) * 2014-08-04 2016-02-04 Kabushiki Kaisha Toshiba Semiconductor device
US20170133267A1 (en) * 2014-09-09 2017-05-11 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the semiconductor device
US9786556B2 (en) * 2014-09-09 2017-10-10 Toshiba Memory Corporation Semiconductor device and method of manufacturing the semiconductor device
US10304845B2 (en) * 2014-11-13 2019-05-28 Toshiba Memory Corporation Semiconductor device and method of manufacturing the same
US20160141297A1 (en) * 2014-11-13 2016-05-19 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US9865613B2 (en) * 2015-04-09 2018-01-09 Samsung Electronics Co., Ltd. Semiconductor devices
US20160300791A1 (en) * 2015-04-09 2016-10-13 Jong-Min Lee Semiconductor devices
US9858995B1 (en) * 2016-12-22 2018-01-02 Macronix International Co., Ltd. Method for operating a memory device
US10497566B1 (en) * 2018-06-19 2019-12-03 Macronix International Co., Ltd. Layout design for fanout patterns in self-aligned double patterning process

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