US20120126896A1 - Offset cancellation for continuous-time circuits - Google Patents
Offset cancellation for continuous-time circuits Download PDFInfo
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- US20120126896A1 US20120126896A1 US12/954,090 US95409010A US2012126896A1 US 20120126896 A1 US20120126896 A1 US 20120126896A1 US 95409010 A US95409010 A US 95409010A US 2012126896 A1 US2012126896 A1 US 2012126896A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
- H03F3/45197—Pl types
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
- H03F3/45928—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit
- H03F3/45968—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit by offset reduction
- H03F3/45973—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit by offset reduction by using a feedback circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/375—Circuitry to compensate the offset being present in an amplifier
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/405—Indexing scheme relating to amplifiers the output amplifying stage of an amplifier comprising more than three power stages
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45354—Indexing scheme relating to differential amplifiers the AAC comprising offset means
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45374—Indexing scheme relating to differential amplifiers the AAC comprising one or more discrete resistors
Definitions
- the present invention relates generally to electrical circuits. More particularly, the present invention relates to offset cancellation for continuous-time circuits.
- a high speed serial interface may be used to communicate between devices in a system.
- HSSI high speed serial interface
- the transmitter in such a system it is the intention for the transmitter in such a system to transmit a digital (binary) signal having two distinctive levels, and well-defined (i.e., very steep) transitions from either of these levels to the other level.
- Such steep transitions are essential to transmitting data at high speed.
- the medium that conveys the signal from the transmitter to the receiver usually imposes losses on the signal being transmitted. These losses generally include diminished signal amplitude and reduced transition steepness.
- Equalization circuitry is typically among the first circuitry that the incoming signal sees when it reaches the receiver. Equalization circuitry may be designed to amplify higher frequencies so as to respond strongly and rapidly to transitions detected in the received signal. This strong and rapid response is intended to restore the original steepness to these transitions, thereby making it possible for further circuitry of the receiver to correctly interpret the signal, even at the very high data rate of that signal.
- the continuous-time circuit includes a multi-stage amplifier chain, including a first amplifier stage and a last amplifier stage, and an offset cancellation loop.
- the offset cancellation loop is configured to receive an output of the last amplifier stage and to provide an offset correction voltage signal to the first amplifier stage.
- the first amplifier stage may include an input transistor and an offset compensation transistor.
- the source of the offset compensation transistor may be electrically connected to the drain of the input transistor, and a voltage on the gate of the offset compensation transistor may be determined by the offset correction voltage signal.
- the offset correction voltage signal may be generated using a single transconductance amplifier.
- the offset compensation loop may create one dominant pole and a single consequential parasitic pole so as to have greater stability and may advantageously achieve a second-order roll-off in response magnitude at higher frequencies.
- the multi-stage amplifier chain may comprise a multi-stage equalizer chain.
- Another embodiment relates to a method of offset cancellation for a continuous-time circuit.
- a continuous-time input signal is received and amplified by a series of amplifier stages so as to generate a continuous-time output signal.
- the continuous-time output signal is input into an offset cancellation loop, and the offset cancellation loop generates an offset correction voltage signal.
- the offset correction voltage signal is applied to a gate of an offset compensation transistor in an amplifier stage.
- Another embodiment relates to an integrated circuit that includes a cascaded circuit having multiple equalizer stages, including a first equalizer stage and a last equalizer stage, and an offset cancellation loop.
- the first equalizer stage is configured to receive a differential input signal
- the last equalizer stage is configured to output a differential output signal.
- the offset cancellation loop is configured to receive the differential output signal and to generate a differential offset correction voltage signal which is applied within the first equalizer stage.
- the first equalizer stage includes at least a pair of input transistors, a pair of offset compensation transistors, and a pair of resistors. The gates of the input transistors are configured to receive the differential input signal.
- each offset compensation transistor is electrically connected to a drain of a corresponding input transistor, and voltages applied to the gates of the offset compensation transistors are determined by the differential offset correction voltage signal.
- Each said resistor is configured in parallel with a channel of a corresponding offset compensation transistor.
- FIG. 1 shows a conventional circuit for offset cancellation of a continuous-time circuit.
- FIG. 2 is a circuit diagram depicting the conventional technique for applying of an offset cancellation loop signal to a first equalizer stage.
- FIG. 3 shows a circuit for offset cancellation of a continuous-time circuit in accordance with an embodiment of the invention.
- FIG. 4 is a circuit diagram depicting the application of an offset cancellation loop signal to a first equalizer/amplifier stage in accordance with an embodiment of the invention.
- FIG. 5 is a Bode plot providing a comparison between the conventional offset cancellation loop of FIG. 1 and the offset cancellation loop of
- FIG. 3 in accordance with an embodiment of the invention.
- FIG. 6 shows the transient response of the offset compensation loop in accordance with an embodiment of the invention.
- FIG. 7 compares the forward gain of the conventional offset cancellation loop and the offset cancellation loop in accordance with an embodiment of the invention.
- FIG. 8 shows a circuit for offset cancellation of a continuous-time circuit comprising a chain of amplifiers in accordance with an embodiment of the invention.
- FIG. 9 is a simplified partial block diagram of a field programmable gate array (FPGA) that may be configured to implement an embodiment of the present invention.
- FPGA field programmable gate array
- FIG. 10 shows a block diagram of an exemplary digital system that may be configured to utilize an embodiment of the present invention.
- the first equalizer stage (Eq 1 ) has an input load (R L ) and receives an input current which is equal to an offset input current (I 0FF — IN ) minus a correction current (I CORR ).
- Eq 1 may be configured to amplify higher frequencies so as to increase the steepness of transitions in the input current.
- Eq 1 The output of Eq 1 is connected to the input of the second equalizer stage (Eq 2 ).
- the output of Eq 2 is connected to the input of the third equalizer stage (Eq 3 ).
- the output of Eq 3 is connected to the input of the fourth equalizer stage (Eq 4 ).
- Each of these further stages (Eq 2 , Eq 3 , and Eq 4 ) may be configured to further increase steepness to the detected transition or otherwise shape the signal.
- a first transconductance amplifier (gm 1 ) drives a feedback load, represented by capacitor C F and resistor R F , which realizes the dominant pole (Dominant pole) of this feedback loop.
- Other components in the loop contribute parasitic poles which affect the phase margin of this entire loop.
- a first parasitic pole is due to the low-pass filter, represented by resistor R IN and capacitor C IN , at the input of gm 1 (i.e. at the input of the offset compensation loop).
- a second parasitic pole is due to a second transconductance amplifier (gm 2 ) which has an input signal (V CORR ) driven by gm 1 and which provides the correction current (I CORR ) as its output.
- the third parasitic pole (Parasitic pole 3 ) is due to the effective current summation ( ⁇ ) which occurs as the offset cancellation loop signal (I CORR ) is applied to the input of the first equalizer stage (Eq 1 ).
- the first equalizer stage may include a pair of differential transistors (M 1 and M 2 ), impedances (Z 1 and Z 2 ), with a virtual ground in between the impedances), and tail current sources (I 1 and I 2 ).
- the differential output (OUTP and OUTN) of this first stage is provided as the differential input of the next stage (Eq 2 ).
- the conventional technique for offset cancellation in continuous-time circuits injects current into the compensated stage using a feedback filtered voltage.
- stabilization of the conventional circuit can be problematic, especially for high gain loops.
- the instability of the conventional circuit is due, at least in part, to the presence of the multiple parasitic poles.
- the offset cancellation circuit 300 provides the following benefits and advantages.
- the offset cancellation signal may be kept in the voltage domain throughout, rather than needing to change it to the current domain.
- the second transconductance amplifier (gm 2 ) may be advantageously eliminated.
- the number of non-trivial parasitic poles in the feedback path is reduced from three to two, and the reduced number of poles increases the stability of the circuit.
- a smaller overall loop gain may be used to compensate a same amount of offset. In other words, the range of offset may be larger than in the conventional approach. This is because the compensating switch resistance is varied, not the current in the tail current source.
- the offset current is not wasted, as in the case of a pseudo differential stage.
- FIG. 3 shows a circuit 300 for offset cancellation of a continuous-time circuit in accordance with an embodiment of the invention.
- four equalizer stages (Eq 1 , Eq 2 , Eq 3 , and Eq 4 ) are cascaded in a serial chain.
- Other embodiments may have a different number of stages and/or may have cascaded amplifier (rather than equalizer) stages.
- the first equalizer stage (Eq 1 ) receives an input current which is equal to an offset input current (I OFF — IN ).
- I OFF — IN offset input current
- V CORR correction voltage
- the correction voltage (V CORR ) output by gm 1 in combination with the feedback load represented by C F and R F ) is sent directly to the first stage (without the need for gm 2 ).
- the first parasitic pole (Parasitic pole 1 ) is due to the low-pass filter, represented by resistor R IN and capacitor C IN , at the input of gm 1 .
- the second parasitic pole (Parasitic pole A) is due to the first equalizer stage (Eq 1 ) and, as discussed below, may be neglected for phase margin analysis.
- Eq 1 the first equalizer stage
- FIG. 4 depicts a circuit implementation of a first equalizer stage (Eq 1 in FIG. 3 ) showing the application of the offset cancellation loop voltage in accordance with an embodiment of the invention. As described below, this control voltage may be used to cancel the offset of the cascaded equalizer chain.
- the first equalizer stage may include a pair of differential transistors (M 1 and M 2 ), a pair of offset input transistors (Mlsp and Mlsn), a pair of offset compensation transistors (Mofcp and Mofcn).
- the stage also includes impedances (Z 1 and Z 2 ), with a virtual ground therebetween), resistors (Rfxp and Rfxn), and current sources (I 1 ,I 2 , Isp and Isn).
- M 1 and M 2 may be NMOS transistors with gate width/length of Win/Lin
- Mlsp and Mlsn may be PMOS transistors with gate width/length W 1 /L 1
- Mofcp and Mofcn may be NMOS transistors with gate width/length W 2 /L 2
- the first equalizer stage also includes
- the differential offset voltage inputs (VOFP and VOFN) are buffered by source follower circuits (comprising current source Isp and transistor Mlsp, and current source Isn and transistor Mlsn, respectively).
- the buffered differential voltage inputs (vsfp and vsfn) are applied to the gates of the offset compensation transistors (Mofcp and Mofcn, respectively) which are operating in the “linear” region.
- a differential voltage is developed by the feedback loop as VOFP rises and VOFN falls (and vice-versa) in response to a DC (direct current) offset in the chain.
- the bleed resistors (Rfxp and Rfxn) allow some of the current to bypass Mofcp and Mofcn.
- the amplitude of the correctable offset voltage is determined, in part, by the ratio of resistance between Rfxp and Mofcp (and between Rfxn and Mofcn).
- the amplitude of the correctable offset voltage increases if more of the current is modulated by Mofcp and Mofcn.
- Mofcp and Mofcn also act as additional source degeneration resistors that degrade the effective gain of the input pair (M 1 and M 2 ) and so reduces the bandwidth and gain of the stage, i.e. decreases the AC (alternating current) performance of the stage.
- Rfxp and Rfxn are removed (i.e. set to infinity or open circuit), then all the current flows through, and is modulated by, Mofcp and Mofcn. In that case, the maximum achievable correctable offset voltage is reached, but the AC performance of the equalization stage is at a minimum.
- the maximum achievable correctable offset voltage is determined, at least in part, by the product of the tail current (i.e. I 1 and I 2 ) and the range of the variable channel resistance of offset compensation transistor (i.e. the channel resistance of Mofcp and Mofcn).
- Rfxp and Rfxn are set to zero (i.e.
- the differential offset voltages VOFP and VOFN effectively modulate the offset compensation voltages vocn and vocp, where vocn is the voltage at the drain of M 1 , and vocp is the voltage at the drain of M 2 .
- These offset compensation voltages vocn and vocp cause corresponding voltage changes in the differential voltage outputs (OUTP and OUTN), and these differential voltage outputs are provided as the differential voltage inputs of the next stage (Eq 2 ).
- Non-dominant pole A is created by the source follower circuits. (This is the same Non-dominant pole A as in FIG. 3 .)
- Non-dominant pole A is at a frequency of approximately 5 to 6 GHz with minimal power consumption (about 100 microamperes).
- the frequency of Non-dominant pole A is substantially higher (by orders of magnitude) than the frequencies of the parasitic poles shown in FIG. 1 . As such, Non-dominant pole A may be neglected for phase margin analysis.
- the NMOS transistors Mofcp and Mofcn may be maintained in the linear region by sizing them appropriately and by using the PMOS level shifters (Mlsp and Mlsn configured as source followers).
- the source follower circuits also serve as fail safes.
- the source follower circuits may be configured to ensure that, if the threshold voltages of Mlsp and Mlsn are high, the gate voltages (vsfp and vsfn) applied to Mofcp and Mofcn will still be sufficient to keep them in the linear region.
- the offset compensation loop has one secondary pole (at the input of the offset compensation loop) of consequence and one dominant pole.
- the overall loop gain of the circuit 300 in FIG. 3 may be about 10 dB less than the overall loop gain of the circuit 100 in FIG. 1
- the circuit 300 of FIG. 3 has greater offset cancellation ability since it uses the whole tail current, which can be large.
- the reduced loop gain of the circuit 300 in FIG. 3 makes it easier to stabilize the loop.
- variations in process, voltage and temperature (PVT) have less detrimental effects on stability.
- FIG. 5 is a Bode plot providing a comparison between the conventional offset cancellation loop 100 of FIG. 1 and the offset cancellation loop 300 of FIG. 3 in accordance with an embodiment of the invention.
- the Bode plot shows magnitude (in dB) and phase (in degrees) versus frequency (in Hz) for the conventional and new loops.
- the offset cancellation loop 300 of FIG. 3 was implemented with a similar loop filter size as the conventional offset cancellation loop 100 of FIG. 1 .
- a first Bode magnitude plot 502 shows the loop gain for the conventional offset cancellation loop 100 of FIG. 1
- a second Bode magnitude plot 504 shows the loop gain for the offset cancellation loop 300 of FIG. 3
- a first Bode phase plot 506 shows the frequency-response phase shift of the conventional offset cancellation loop 100 of FIG. 1
- a second Bode phase plot 508 shows the frequency-response phase shift of the conventional offset cancellation loop 300 of FIG. 1 .
- the 0 dB frequency is higher for the conventional offset cancellation loop 100 than for the offset cancellation loop 300 of FIG. 3 .
- the conventional offset cancellation loop 100 of FIG. 1 has a 4 th -order roll-off beyond 100 MHz, while the offset cancellation loop 300 of FIG. 3 has a less-steep 2 nd -order roll-off beyond 300 MHz.
- the phase shift plot begins to bend at much lower frequencies for the conventional offset cancellation loop 100 of FIG. 1 (which begins to bend at around 5 MHz) than for the offset cancellation loop 300 of FIG. 3 (which begins to bend at around 20 MHz).
- the phase margin improvement is about 27 degrees (the difference between the phase margin of about 60 degrees for the loop of FIG. 1 and the phase margin of about 87 degrees for the loop of FIG. 3 ).
- the offset cancellation loop 300 of FIG. 3 is substantially more stable than the conventional offset cancellation loop 100 of FIG. 1 .
- the offset cancellation loop 300 of FIG. 3 can tolerate a substantially greater open loop phase shift (or time delay) before becoming unstable.
- the parasitic poles in the loop 100 of FIG. 1 may make that loop unstable.
- the fewer poles in the loop 300 FIG. 3 also makes loop stability easier to manage for a given filter size.
- the Bode plot of FIG. 5 shows that a phase margin of greater than 80 degrees is achievable with a similar area for the loop filter of FIG. 3 (as compared with the area for the loop filter of FIG. 1 ). However, if a lower phase margin may be tolerated (for example, 60 degrees), then the area for the loop filter of FIG. 3 may be reduced (as compared with the area for the loop filter of FIG. 1 ) while maintaining the same stability.
- FIG. 6 shows the transient response of the offset compensation loop 300 in accordance with an embodiment of the invention.
- the bottom graph shows the output signal 604 which is responsive to the DC offset voltages of the input signal 602 .
- the input signal 602 corresponds to the voltage of input signal I OFF — IN
- the output signal 604 corresponds to the voltage signal V OFF — OUT .
- FIG. 7 shows the forward gain 702 of the conventional offset cancellation loop 100 of FIG. 1 and the forward gain 704 of the offset cancellation loop 300 of FIG. 3 in accordance with an embodiment of the invention.
- the forward gain curve is lower overall for the offset cancellation loop 300 of FIG. 3 .
- a slight degradation in effective gm also causes a lowering in peaking frequency and overall bandwidth.
- the DC gain may need to be increased.
- FIG. 8 shows a circuit 800 for offset cancellation of a continuous-time circuit comprising a circuit of cascaded amplifiers in accordance with an embodiment of the invention.
- This circuit 800 is similar to the circuit 300 in FIG. 3 . The difference is that the chain of equalizer stages (Eq 1 , Eq 2 , Eq 3 , and Eq 4 ) is replaced by a more general chain of amplifier stages (Amp 1 , Amp 2 , Amp 3 , and Amp 4 ).
- the first amplifier stage (Amp 1 ) may be implemented as shown in FIG. 4 .
- FIG. 9 is a simplified partial block diagram of a field programmable gate array (FPGA) 900 that can include aspects of the present invention. It should be understood that embodiments of the present invention can be used in numerous types of integrated circuits such as field programmable gate arrays (FPGAs), programmable logic devices (PLDs), complex programmable logic devices (CPLDs), programmable logic arrays (PLAs), digital signal processors (DSPs) and application specific integrated circuits (ASICs).
- FPGAs field programmable gate arrays
- PLDs programmable logic devices
- CPLDs complex programmable logic devices
- PLAs programmable logic arrays
- DSPs digital signal processors
- ASICs application specific integrated circuits
- FPGA 900 includes within its “core” a two-dimensional array of programmable logic array blocks (or LABs) 902 that are interconnected by a network of column and row interconnect conductors of varying length and speed.
- LABs 902 include multiple (e.g., 10) logic elements (or LEs).
- An LE is a programmable logic block that provides for efficient implementation of user defined logic functions.
- An FPGA has numerous logic elements that can be configured to implement various combinatorial and sequential functions.
- the logic elements have access to a programmable interconnect structure.
- the programmable interconnect structure can be programmed to interconnect the logic elements in almost any desired configuration.
- FPGA 900 may also include a distributed memory structure including random access memory (RAM) blocks of varying sizes provided throughout the array.
- RAM random access memory
- the RAM blocks include, for example, blocks 904 , blocks 906 , and block 908 .
- These memory blocks can also include shift registers and FIFO buffers.
- FPGA 900 may further include digital signal processing (DSP) blocks 910 that can implement, for example, multipliers with add or subtract features.
- DSP digital signal processing
- IOEs Input/output elements
- Each IOE 912 is coupled to an external terminal (i.e., a pin) of FPGA 900 .
- a transceiver (TX/RX) channel array may be arranged as shown, for example, with each TX/RX channel circuit 920 being coupled to several LABs.
- a TX/RX channel circuit 920 may include, among other circuitry, the offset cancellation circuitry described herein.
- FPGA 900 is described herein for illustrative purposes only and that the present invention can be implemented in many different types of PLDs, FPGAs, and ASICs.
- FIG. 10 shows a block diagram of an exemplary digital system 1000 that can embody techniques of the present invention.
- System 1000 may be a programmed digital computer system, digital signal processing system, specialized digital switching network, or other processing system. Moreover, such systems can be designed for a wide variety of applications such as telecommunications systems, automotive systems, control systems, consumer electronics, personal computers, Internet communications and networking, and others. Further, system 1000 may be provided on a single board, on multiple boards, or within multiple enclosures.
- System 1000 includes a processing unit 1002 , a memory unit 1004 , and an input/output (I/O) unit 1006 interconnected together by one or more buses.
- FPGA 1008 is embedded in processing unit 1002 .
- FPGA 1008 can serve many different purposes within the system 1000 .
- FPGA 1008 can, for example, be a logical building block of processing unit 1002 , supporting its internal and external operations.
- FPGA 1008 is programmed to implement the logical functions necessary to carry on its particular role in system operation.
- FPGA 1008 can be specially coupled to memory 1004 through connection 1010 and to I/O unit 1006 through connection 1012 .
- Processing unit 1002 may direct data to an appropriate system component for processing or storage, execute a program stored in memory 1004 , receive and transmit data via I/O unit 1006 , or other similar function.
- Processing unit 1002 may be a central processing unit (CPU), microprocessor, floating point coprocessor, graphics coprocessor, hardware controller, microcontroller, field programmable gate array programmed for use as a controller, network controller, or any type of processor or controller. Furthermore, in many embodiments, there is often no need for a CPU.
- one or more FPGAs 1008 may control the logical operations of the system.
- one or more FPGAs 1008 may control the logical operations of the system.
- FPGA 1008 acts as a reconfigurable processor that may be reprogrammed as needed to handle a particular computing task. Alternately, FPGA 1008 may itself include an embedded microprocessor.
- Memory unit 1004 may be a random access memory (RAM), read only memory (ROM), fixed or flexible disk media, flash memory, tape, or any other storage means, or any combination of these storage means.
Abstract
Description
- 1. Technical Field
- The present invention relates generally to electrical circuits. More particularly, the present invention relates to offset cancellation for continuous-time circuits.
- 2. Description of the Background Art
- A high speed serial interface (“HSSI”) may be used to communicate between devices in a system. Typically, it is the intention for the transmitter in such a system to transmit a digital (binary) signal having two distinctive levels, and well-defined (i.e., very steep) transitions from either of these levels to the other level. Such steep transitions are essential to transmitting data at high speed. The medium that conveys the signal from the transmitter to the receiver usually imposes losses on the signal being transmitted. These losses generally include diminished signal amplitude and reduced transition steepness.
- To maintain accurate, high-speed data transmission, it is necessary for the circuitry to compensate for these losses. One compensation technique is to use what is called equalization at the receiver. Equalization circuitry is typically among the first circuitry that the incoming signal sees when it reaches the receiver. Equalization circuitry may be designed to amplify higher frequencies so as to respond strongly and rapidly to transitions detected in the received signal. This strong and rapid response is intended to restore the original steepness to these transitions, thereby making it possible for further circuitry of the receiver to correctly interpret the signal, even at the very high data rate of that signal.
- It is highly desirable to improve equalizers and other continuous-time circuits for high-speed serial interfaces and other applications.
- One embodiment relates to a continuous-time circuit configured with an offset cancellation loop. The continuous-time circuit includes a multi-stage amplifier chain, including a first amplifier stage and a last amplifier stage, and an offset cancellation loop. The offset cancellation loop is configured to receive an output of the last amplifier stage and to provide an offset correction voltage signal to the first amplifier stage.
- The first amplifier stage may include an input transistor and an offset compensation transistor. The source of the offset compensation transistor may be electrically connected to the drain of the input transistor, and a voltage on the gate of the offset compensation transistor may be determined by the offset correction voltage signal. The offset correction voltage signal may be generated using a single transconductance amplifier. The offset compensation loop may create one dominant pole and a single consequential parasitic pole so as to have greater stability and may advantageously achieve a second-order roll-off in response magnitude at higher frequencies. The multi-stage amplifier chain may comprise a multi-stage equalizer chain.
- Another embodiment relates to a method of offset cancellation for a continuous-time circuit. A continuous-time input signal is received and amplified by a series of amplifier stages so as to generate a continuous-time output signal. The continuous-time output signal is input into an offset cancellation loop, and the offset cancellation loop generates an offset correction voltage signal. The offset correction voltage signal is applied to a gate of an offset compensation transistor in an amplifier stage.
- Another embodiment relates to an integrated circuit that includes a cascaded circuit having multiple equalizer stages, including a first equalizer stage and a last equalizer stage, and an offset cancellation loop. The first equalizer stage is configured to receive a differential input signal, and the last equalizer stage is configured to output a differential output signal. The offset cancellation loop is configured to receive the differential output signal and to generate a differential offset correction voltage signal which is applied within the first equalizer stage. The first equalizer stage includes at least a pair of input transistors, a pair of offset compensation transistors, and a pair of resistors. The gates of the input transistors are configured to receive the differential input signal. The source of each offset compensation transistor is electrically connected to a drain of a corresponding input transistor, and voltages applied to the gates of the offset compensation transistors are determined by the differential offset correction voltage signal. Each said resistor is configured in parallel with a channel of a corresponding offset compensation transistor.
- Other embodiments, aspects and features are also disclosed.
-
FIG. 1 shows a conventional circuit for offset cancellation of a continuous-time circuit. -
FIG. 2 is a circuit diagram depicting the conventional technique for applying of an offset cancellation loop signal to a first equalizer stage. -
FIG. 3 shows a circuit for offset cancellation of a continuous-time circuit in accordance with an embodiment of the invention. -
FIG. 4 is a circuit diagram depicting the application of an offset cancellation loop signal to a first equalizer/amplifier stage in accordance with an embodiment of the invention. -
FIG. 5 is a Bode plot providing a comparison between the conventional offset cancellation loop ofFIG. 1 and the offset cancellation loop of -
FIG. 3 in accordance with an embodiment of the invention. -
FIG. 6 shows the transient response of the offset compensation loop in accordance with an embodiment of the invention. -
FIG. 7 compares the forward gain of the conventional offset cancellation loop and the offset cancellation loop in accordance with an embodiment of the invention. -
FIG. 8 shows a circuit for offset cancellation of a continuous-time circuit comprising a chain of amplifiers in accordance with an embodiment of the invention. -
FIG. 9 is a simplified partial block diagram of a field programmable gate array (FPGA) that may be configured to implement an embodiment of the present invention. -
FIG. 10 shows a block diagram of an exemplary digital system that may be configured to utilize an embodiment of the present invention. - For the purposes of discussion and not limitation, it is generally assumed that the cascaded circuits described below receive (and output) data signals that are differential signals. However, it should be appreciated that principles of the presently-disclosed invention may also apply to single-ended signals.
- Conventional continuous-time cascaded circuits typically employ a feedback loop that filters an output offset voltage, pass it though a high-gain amplifier, and apply a feedback current to the first stage of the circuit to reduce the offset in a continuous time manner. Such a conventional continuous-time cascaded circuit with a feedback loop is shown in
FIG. 1 . Note that continuous-time circuits operate on continuous-time signals, as opposed to sampled discrete-time signals. - In the
example circuit 100 shown inFIG. 1 , four equalizer stages (Eq1, Eq2, Eq3, and Eq4) are cascaded in a serial chain. The first equalizer stage (Eq1) has an input load (RL) and receives an input current which is equal to an offset input current (I0FF— IN) minus a correction current (ICORR). Eq1 may be configured to amplify higher frequencies so as to increase the steepness of transitions in the input current. - The output of Eq1 is connected to the input of the second equalizer stage (Eq2). The output of Eq2 is connected to the input of the third equalizer stage (Eq3). Finally, the output of Eq3 is connected to the input of the fourth equalizer stage (Eq4). Each of these further stages (Eq2, Eq3, and Eq4) may be configured to further increase steepness to the detected transition or otherwise shape the signal.
- As further seen in
FIG. 1 , a first transconductance amplifier (gm1) drives a feedback load, represented by capacitor CF and resistor RF, which realizes the dominant pole (Dominant pole) of this feedback loop. Other components in the loop contribute parasitic poles which affect the phase margin of this entire loop. - In the feedback loop of
FIG. 1 , there is one dominant pole (Dominant pole) and three non-trivial parasitic poles. A first parasitic pole (Parasitic pole 1) is due to the low-pass filter, represented by resistor RIN and capacitor CIN, at the input of gm1 (i.e. at the input of the offset compensation loop). A second parasitic pole (Parasitic pole 2) is due to a second transconductance amplifier (gm2) which has an input signal (VCORR) driven by gm1 and which provides the correction current (ICORR) as its output. The third parasitic pole (Parasitic pole 3) is due to the effective current summation (Σ) which occurs as the offset cancellation loop signal (ICORR) is applied to the input of the first equalizer stage (Eq1). - A conventional circuit implementation of a first equalizer stage showing the application of the offset cancellation loop signal is shown in
FIG. 2 . As shown, the first equalizer stage may include a pair of differential transistors (M1 and M2), impedances (Z1 and Z2), with a virtual ground in between the impedances), and tail current sources (I1 and I2). In this conventional circuit, the offset cancellation loop signal (ICORR) is applied by the differential current output of gm2 (shown as the variable current sources Iofn and Iofp, where ICORR=Iofp-Iofn) being fed in parallel to the tail current sources (I1 and I2, respectively). The differential output (OUTP and OUTN) of this first stage is provided as the differential input of the next stage (Eq2). - As discussed above, the conventional technique for offset cancellation in continuous-time circuits injects current into the compensated stage using a feedback filtered voltage. Applicants have determined, however, that stabilization of the conventional circuit can be problematic, especially for high gain loops. Applicants believe that the instability of the conventional circuit is due, at least in part, to the presence of the multiple parasitic poles.
- In comparison with the conventional offset
cancellation circuit 100 described above, the offsetcancellation circuit 300 disclosed herein provides the following benefits and advantages. First, the offset cancellation signal may be kept in the voltage domain throughout, rather than needing to change it to the current domain. Second, the second transconductance amplifier (gm2) may be advantageously eliminated. Third, the number of non-trivial parasitic poles in the feedback path is reduced from three to two, and the reduced number of poles increases the stability of the circuit. Fourth, by controlling the switch resistance directly, a smaller overall loop gain may be used to compensate a same amount of offset. In other words, the range of offset may be larger than in the conventional approach. This is because the compensating switch resistance is varied, not the current in the tail current source. Finally, the offset current is not wasted, as in the case of a pseudo differential stage. -
FIG. 3 shows acircuit 300 for offset cancellation of a continuous-time circuit in accordance with an embodiment of the invention. In the particular embodiment depicted inFIG. 3 , four equalizer stages (Eq1, Eq2, Eq3, and Eq4) are cascaded in a serial chain. Other embodiments may have a different number of stages and/or may have cascaded amplifier (rather than equalizer) stages. - The first equalizer stage (Eq1) receives an input current which is equal to an offset input current (IOFF
— IN). In contrast to the conventional circuit inFIG. 1 , there is no effective current summation (Σ) with a correction current (ICORR) generated by gm2. Instead, the correction voltage (VCORR) output by gm1 (in combination with the feedback load represented by CF and RF) is sent directly to the first stage (without the need for gm2). - In the feedback loop of
FIG. 3 , there is one dominant pole (Dominant pole) and only two non-trivial parasitic poles. The first parasitic pole (Parasitic pole 1) is due to the low-pass filter, represented by resistor RIN and capacitor CIN, at the input of gm1. The second parasitic pole (Parasitic pole A) is due to the first equalizer stage (Eq1) and, as discussed below, may be neglected for phase margin analysis. Hence, in comparison toFIG. 1 , two detrimental parasitic poles have been eliminated in the feedback path ofFIG. 3 . -
FIG. 4 depicts a circuit implementation of a first equalizer stage (Eq1 inFIG. 3 ) showing the application of the offset cancellation loop voltage in accordance with an embodiment of the invention. As described below, this control voltage may be used to cancel the offset of the cascaded equalizer chain. - As shown, the first equalizer stage may include a pair of differential transistors (M1 and M2), a pair of offset input transistors (Mlsp and Mlsn), a pair of offset compensation transistors (Mofcp and Mofcn). The stage also includes impedances (Z1 and Z2), with a virtual ground therebetween), resistors (Rfxp and Rfxn), and current sources (I1,I2, Isp and Isn). In this particular implementation, M1 and M2 may be NMOS transistors with gate width/length of Win/Lin , Mlsp and Mlsn may be PMOS transistors with gate width/length W1/L1, and Mofcp and Mofcn may be NMOS transistors with gate width/length W2/L2. In addition, the first equalizer stage also includes
- In this circuit, the voltage output (VCORR) of the transconductance amplifier/low pass filter combination in
FIG. 3 is input to the first stage directly as differential offset voltage inputs VOFP and VOFN, where VCORR=VOFP−VOFN. As seen inFIG. 4 , the differential offset voltage inputs (VOFP and VOFN) are buffered by source follower circuits (comprising current source Isp and transistor Mlsp, and current source Isn and transistor Mlsn, respectively). The buffered differential voltage inputs (vsfp and vsfn) are applied to the gates of the offset compensation transistors (Mofcp and Mofcn, respectively) which are operating in the “linear” region. Note that, as the gate voltage on an NMOS transistor (such as, Mofcp or Mofcn) in the linear region increases, its channel resistance drops. On the other hand, as the gate voltage on an NMOS transistor in the linear region decreases, its channel resistance increases. - During offset compensation, a differential voltage is developed by the feedback loop as VOFP rises and VOFN falls (and vice-versa) in response to a DC (direct current) offset in the chain. The bleed resistors (Rfxp and Rfxn) allow some of the current to bypass Mofcp and Mofcn.
- In this circuit, the amplitude of the correctable offset voltage is determined, in part, by the ratio of resistance between Rfxp and Mofcp (and between Rfxn and Mofcn). The amplitude of the correctable offset voltage increases if more of the current is modulated by Mofcp and Mofcn. However, Mofcp and Mofcn also act as additional source degeneration resistors that degrade the effective gain of the input pair (M1 and M2) and so reduces the bandwidth and gain of the stage, i.e. decreases the AC (alternating current) performance of the stage. By selecting an appropriate resistance ratio, a practical compromise between offset cancellation and the performance of the equalization stage may be achieved.
- On one extreme, if Rfxp and Rfxn are removed (i.e. set to infinity or open circuit), then all the current flows through, and is modulated by, Mofcp and Mofcn. In that case, the maximum achievable correctable offset voltage is reached, but the AC performance of the equalization stage is at a minimum. The maximum achievable correctable offset voltage is determined, at least in part, by the product of the tail current (i.e. I1 and I2) and the range of the variable channel resistance of offset compensation transistor (i.e. the channel resistance of Mofcp and Mofcn). On the other extreme, if Rfxp and Rfxn are set to zero (i.e. short circuits), then none of the current flows through, and none of the current is modulated by, Mofcp and Mofcn. In that case, the amplitude of the correctable offset voltage is zero, while the AC performance of the equalization stage is at a maximum.
- Hence, given the above discussion and finite fixed Rfxp and Rfxn, it is apparent that the differential offset voltages VOFP and VOFN effectively modulate the offset compensation voltages vocn and vocp, where vocn is the voltage at the drain of M1, and vocp is the voltage at the drain of M2. These offset compensation voltages vocn and vocp cause corresponding voltage changes in the differential voltage outputs (OUTP and OUTN), and these differential voltage outputs are provided as the differential voltage inputs of the next stage (Eq2).
- As further shown in
FIG. 4 , a non-dominant pole (Non-dominant pole A) is created by the source follower circuits. (This is the same Non-dominant pole A as inFIG. 3 .) In one implementation of the circuit, Non-dominant pole A is at a frequency of approximately 5 to 6 GHz with minimal power consumption (about 100 microamperes). The frequency of Non-dominant pole A is substantially higher (by orders of magnitude) than the frequencies of the parasitic poles shown inFIG. 1 . As such, Non-dominant pole A may be neglected for phase margin analysis. - Note that, in the embodiment of
FIG. 4 , the NMOS transistors Mofcp and Mofcn may be maintained in the linear region by sizing them appropriately and by using the PMOS level shifters (Mlsp and Mlsn configured as source followers). The source follower circuits also serve as fail safes. In particular, the source follower circuits may be configured to ensure that, if the threshold voltages of Mlsp and Mlsn are high, the gate voltages (vsfp and vsfn) applied to Mofcp and Mofcn will still be sufficient to keep them in the linear region. - In accordance with an embodiment of the invention, the offset compensation loop has one secondary pole (at the input of the offset compensation loop) of consequence and one dominant pole. In one embodiment, while the overall loop gain of the
circuit 300 inFIG. 3 may be about 10 dB less than the overall loop gain of thecircuit 100 inFIG. 1 , thecircuit 300 ofFIG. 3 has greater offset cancellation ability since it uses the whole tail current, which can be large. In addition, the reduced loop gain of thecircuit 300 inFIG. 3 makes it easier to stabilize the loop. Furthermore, without multiple parasitic poles, variations in process, voltage and temperature (PVT) have less detrimental effects on stability. -
FIG. 5 is a Bode plot providing a comparison between the conventional offsetcancellation loop 100 ofFIG. 1 and the offsetcancellation loop 300 ofFIG. 3 in accordance with an embodiment of the invention. The Bode plot shows magnitude (in dB) and phase (in degrees) versus frequency (in Hz) for the conventional and new loops. In generating the Bode plot, the offsetcancellation loop 300 ofFIG. 3 was implemented with a similar loop filter size as the conventional offsetcancellation loop 100 ofFIG. 1 . - A first
Bode magnitude plot 502 shows the loop gain for the conventional offsetcancellation loop 100 ofFIG. 1 , and a secondBode magnitude plot 504 shows the loop gain for the offsetcancellation loop 300 ofFIG. 3 . A firstBode phase plot 506 shows the frequency-response phase shift of the conventional offsetcancellation loop 100 ofFIG. 1 , and a secondBode phase plot 508 shows the frequency-response phase shift of the conventional offsetcancellation loop 300 ofFIG. 1 . - As seen in the magnitude plots, the 0 dB frequency is higher for the conventional offset
cancellation loop 100 than for the offsetcancellation loop 300 ofFIG. 3 . However, as seen in the phase plots, the conventional offsetcancellation loop 100 ofFIG. 1 has a 4th-order roll-off beyond 100 MHz, while the offsetcancellation loop 300 ofFIG. 3 has a less-steep 2nd-order roll-off beyond 300 MHz. As such, the phase shift plot begins to bend at much lower frequencies for the conventional offsetcancellation loop 100 ofFIG. 1 (which begins to bend at around 5 MHz) than for the offsetcancellation loop 300 ofFIG. 3 (which begins to bend at around 20 MHz). - It turns out that, for this particular simulation corner, the phase margin improvement is about 27 degrees (the difference between the phase margin of about 60 degrees for the loop of
FIG. 1 and the phase margin of about 87 degrees for the loop ofFIG. 3 ). This indicates that the offsetcancellation loop 300 ofFIG. 3 is substantially more stable than the conventional offsetcancellation loop 100 ofFIG. 1 . In other words, the offsetcancellation loop 300 ofFIG. 3 can tolerate a substantially greater open loop phase shift (or time delay) before becoming unstable. In other simulation corners, the parasitic poles in theloop 100 ofFIG. 1 may make that loop unstable. The fewer poles in theloop 300FIG. 3 also makes loop stability easier to manage for a given filter size. - The Bode plot of
FIG. 5 shows that a phase margin of greater than 80 degrees is achievable with a similar area for the loop filter ofFIG. 3 (as compared with the area for the loop filter ofFIG. 1 ). However, if a lower phase margin may be tolerated (for example, 60 degrees), then the area for the loop filter ofFIG. 3 may be reduced (as compared with the area for the loop filter ofFIG. 1 ) while maintaining the same stability. -
FIG. 6 shows the transient response of the offsetcompensation loop 300 in accordance with an embodiment of the invention. The top graph shows aninput signal 602 that starts at 0 volts at time t=0, steps down to negative 60 millivolts near time t=20 ns, then steps up to positive 60 millivolts near time t=150 ns. The bottom graph shows theoutput signal 604 which is responsive to the DC offset voltages of theinput signal 602. In particular, referring toFIG. 3 , theinput signal 602 corresponds to the voltage of input signal IOFF— IN, and theoutput signal 604 corresponds to the voltage signal VOFF— OUT. As seen, it takes approximately 50 nanoseconds for theloop 300 to compensate for each voltage step in the input signal. As further seen inFIG. 6 , there is a residual offset of about +1 mV for the −60 mV input step and a residual offset of about −1 mV for the +60 mV input step. -
FIG. 7 shows theforward gain 702 of the conventional offsetcancellation loop 100 ofFIG. 1 and theforward gain 704 of the offsetcancellation loop 300 ofFIG. 3 in accordance with an embodiment of the invention. As seen, the forward gain curve is lower overall for the offsetcancellation loop 300 ofFIG. 3 . Applicants believe that this is because adding the transistors Mofcp and Mofcn decreases the effective gain of the first stage. A slight degradation in effective gm also causes a lowering in peaking frequency and overall bandwidth. Hence, in order to compensate for this degradation in the gain of the stage that would otherwise occur, the DC gain may need to be increased. -
FIG. 8 shows acircuit 800 for offset cancellation of a continuous-time circuit comprising a circuit of cascaded amplifiers in accordance with an embodiment of the invention. Thiscircuit 800 is similar to thecircuit 300 inFIG. 3 . The difference is that the chain of equalizer stages (Eq1, Eq2, Eq3, and Eq4) is replaced by a more general chain of amplifier stages (Amp1, Amp2, Amp3, and Amp4). In accordance with an embodiment of the invention, the first amplifier stage (Amp1) may be implemented as shown inFIG. 4 . -
FIG. 9 is a simplified partial block diagram of a field programmable gate array (FPGA) 900 that can include aspects of the present invention. It should be understood that embodiments of the present invention can be used in numerous types of integrated circuits such as field programmable gate arrays (FPGAs), programmable logic devices (PLDs), complex programmable logic devices (CPLDs), programmable logic arrays (PLAs), digital signal processors (DSPs) and application specific integrated circuits (ASICs). -
FPGA 900 includes within its “core” a two-dimensional array of programmable logic array blocks (or LABs) 902 that are interconnected by a network of column and row interconnect conductors of varying length and speed.LABs 902 include multiple (e.g., 10) logic elements (or LEs). - An LE is a programmable logic block that provides for efficient implementation of user defined logic functions. An FPGA has numerous logic elements that can be configured to implement various combinatorial and sequential functions. The logic elements have access to a programmable interconnect structure. The programmable interconnect structure can be programmed to interconnect the logic elements in almost any desired configuration.
-
FPGA 900 may also include a distributed memory structure including random access memory (RAM) blocks of varying sizes provided throughout the array. The RAM blocks include, for example, blocks 904, blocks 906, and block 908. These memory blocks can also include shift registers and FIFO buffers. -
FPGA 900 may further include digital signal processing (DSP) blocks 910 that can implement, for example, multipliers with add or subtract features. Input/output elements (IOEs) 912 located, in this example, around the periphery of the chip support numerous single-ended and differential input/output standards. EachIOE 912 is coupled to an external terminal (i.e., a pin) ofFPGA 900. A transceiver (TX/RX) channel array may be arranged as shown, for example, with each TX/RX channel circuit 920 being coupled to several LABs. A TX/RX channel circuit 920 may include, among other circuitry, the offset cancellation circuitry described herein. - It is to be understood that
FPGA 900 is described herein for illustrative purposes only and that the present invention can be implemented in many different types of PLDs, FPGAs, and ASICs. - The present invention can also be implemented in a system that has a FPGA as one of several components.
FIG. 10 shows a block diagram of an exemplarydigital system 1000 that can embody techniques of the present invention.System 1000 may be a programmed digital computer system, digital signal processing system, specialized digital switching network, or other processing system. Moreover, such systems can be designed for a wide variety of applications such as telecommunications systems, automotive systems, control systems, consumer electronics, personal computers, Internet communications and networking, and others. Further,system 1000 may be provided on a single board, on multiple boards, or within multiple enclosures. -
System 1000 includes aprocessing unit 1002, amemory unit 1004, and an input/output (I/O)unit 1006 interconnected together by one or more buses. According to this exemplary embodiment,FPGA 1008 is embedded inprocessing unit 1002.FPGA 1008 can serve many different purposes within thesystem 1000.FPGA 1008 can, for example, be a logical building block ofprocessing unit 1002, supporting its internal and external operations.FPGA 1008 is programmed to implement the logical functions necessary to carry on its particular role in system operation.FPGA 1008 can be specially coupled tomemory 1004 throughconnection 1010 and to I/O unit 1006 throughconnection 1012. -
Processing unit 1002 may direct data to an appropriate system component for processing or storage, execute a program stored inmemory 1004, receive and transmit data via I/O unit 1006, or other similar function.Processing unit 1002 may be a central processing unit (CPU), microprocessor, floating point coprocessor, graphics coprocessor, hardware controller, microcontroller, field programmable gate array programmed for use as a controller, network controller, or any type of processor or controller. Furthermore, in many embodiments, there is often no need for a CPU. - For example, instead of a CPU, one or
more FPGAs 1008 may control the logical operations of the system. As another example, -
FPGA 1008 acts as a reconfigurable processor that may be reprogrammed as needed to handle a particular computing task. Alternately,FPGA 1008 may itself include an embedded microprocessor.Memory unit 1004 may be a random access memory (RAM), read only memory (ROM), fixed or flexible disk media, flash memory, tape, or any other storage means, or any combination of these storage means. - In the above description, numerous specific details are given to provide a thorough understanding of embodiments of the invention. However, the above description of illustrated embodiments of the invention is not intended to be exhaustive or to limit the invention to the precise forms disclosed. One skilled in the relevant art will recognize that the invention can be practiced without one or more of the specific details, or with other methods, components, etc.
- In other instances, well-known structures or operations are not shown or described in detail to avoid obscuring aspects of the invention. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. These modifications may be made to the invention in light of the above detailed description.
Claims (22)
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US12/954,090 US8183921B1 (en) | 2010-11-24 | 2010-11-24 | Offset cancellation for continuous-time circuits |
JP2011255026A JP6106358B2 (en) | 2010-11-24 | 2011-11-22 | Offset cancellation for continuous-time circuits |
EP11190439.7A EP2458731B1 (en) | 2010-11-24 | 2011-11-24 | Offset cancellation for continuous-time circuits |
CN201110400674.7A CN102480271B (en) | 2010-11-24 | 2011-11-24 | Be configured with offset cancellation loop continuous time circuit and skew eliminate method |
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US12/954,090 US8183921B1 (en) | 2010-11-24 | 2010-11-24 | Offset cancellation for continuous-time circuits |
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US8456215B2 (en) * | 2011-09-25 | 2013-06-04 | Realtek Semiconductor Corp. | Limiting amplifier and method thereof |
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EP2779438B1 (en) | 2013-03-15 | 2016-10-26 | Dialog Semiconductor B.V. | DC blocker for a high gain amplifier circuit |
US9917707B2 (en) | 2014-09-11 | 2018-03-13 | The Hong Kong University Of Science And Technology | Adaptive cascaded equalization circuits with configurable roll-up frequency response for spectrum compensation |
US11444580B2 (en) | 2020-04-01 | 2022-09-13 | Stmicroelectronics International N.V. | Devices and methods for offset cancellation |
JP2022049988A (en) | 2020-09-17 | 2022-03-30 | キオクシア株式会社 | Semiconductor integrated circuit, receiver, and dc offset cancellation method |
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Publication number | Publication date |
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EP2458731B1 (en) | 2018-08-15 |
JP2012114914A (en) | 2012-06-14 |
CN102480271A (en) | 2012-05-30 |
EP2458731A3 (en) | 2017-04-19 |
US8183921B1 (en) | 2012-05-22 |
EP2458731A2 (en) | 2012-05-30 |
JP6106358B2 (en) | 2017-03-29 |
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