US20120119180A1 - Non-volatile memory device and method of fabricating the same - Google Patents

Non-volatile memory device and method of fabricating the same Download PDF

Info

Publication number
US20120119180A1
US20120119180A1 US13/355,878 US201213355878A US2012119180A1 US 20120119180 A1 US20120119180 A1 US 20120119180A1 US 201213355878 A US201213355878 A US 201213355878A US 2012119180 A1 US2012119180 A1 US 2012119180A1
Authority
US
United States
Prior art keywords
electrode
electrodes
non
volatile memory
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US13/355,878
Inventor
June-mo Koo
Suk-pil Kim
Tae-eung Yoon
Original Assignee
Koo June-Mo
Kim Suk-Pil
Yoon Tae-Eung
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to KR1020080061110A priority Critical patent/KR20100001260A/en
Priority to KR10-2008-0061110 priority
Priority to US12/366,151 priority patent/US8124968B2/en
Application filed by Koo June-Mo, Kim Suk-Pil, Yoon Tae-Eung filed Critical Koo June-Mo
Priority to US13/355,878 priority patent/US20120119180A1/en
Publication of US20120119180A1 publication Critical patent/US20120119180A1/en
Application status is Abandoned legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/102Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
    • H01L27/1021Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components including diodes only
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/101Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/24Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying or switching without a potential-jump barrier or surface barrier, e.g. resistance switching non-volatile memory structures
    • H01L27/2409Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying or switching without a potential-jump barrier or surface barrier, e.g. resistance switching non-volatile memory structures comprising two-terminal selection components, e.g. diodes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/24Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying or switching without a potential-jump barrier or surface barrier, e.g. resistance switching non-volatile memory structures
    • H01L27/2463Arrangements comprising multiple bistable or multistable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays, details of the horizontal layout
    • H01L27/2481Arrangements comprising multiple bistable or multistable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays, details of the horizontal layout arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays, details of the vertical layout
    • H01L27/249Arrangements comprising multiple bistable or multistable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays, details of the horizontal layout arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays, details of the vertical layout the switching components being connected to a common vertical conductor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/06Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/12Details
    • H01L45/122Device geometry
    • H01L45/1226Device geometry adapted for essentially horizontal current flow, e.g. bridge type devices
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/14Selection of switching materials
    • H01L45/141Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H01L45/144Tellurides, e.g. GeSbTe
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/14Selection of switching materials
    • H01L45/145Oxides or nitrides
    • H01L45/146Binary metal oxides, e.g. TaOx

Abstract

Provided are a non-volatile memory device which can be extended in a stack structure and thus can be highly integrated, and a method of manufacturing the non-volatile memory device. The non-volatile memory device includes: at least one first electrode, at least one second electrode crossing the at least one first electrode, at least one data storing layer interposed between the at least one first electrode and the second electrode, at a region in which the at least one first electrode crosses the at least one second electrode and at least one metal silicide layer interposed between the at least one first electrode and the at least one second electrode, at the region in which the at least one first electrode crosses the at least one second electrode.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is a divisional application of co-pending U.S. application Ser. No. 12/366,151 filed Feb. 5, 2009, which claims the benefit of Korean Patent Application No. 10-2008-0061110, filed on Jun. 26, 2008, the disclosures of which are each hereby incorporated by reference herein in their entireties.
  • BACKGROUND
  • 1. Technical Field
  • The present invention relates to a semiconductor device, and more particularly, to a non-volatile memory device which can be extended in a multi-layer structure, and to a method of manufacturing the non-volatile memory device.
  • 2. Description of the Related Art
  • Semiconductor devices may be required to be small in size and also to process large amounts of data. Thus, as a result, the operational speed and integration degree of non-volatile memory devices may need to be increased. In this respect, a multi-layered non-volatile memory device may be more beneficial for high integration than a conventional single-layered non-volatile memory device.
  • When using a multi-layered non-volatile memory device, memory cells can be stacked vertically on the same footprint as that of a single-layered non-volatile memory device. However, it may be difficult to connect and select memory cells of each layer in a multi-layered non-volatile memory device. Also, a multi-layered non-volatile memory device may require more manufacturing processes as the stacking number of the layers is increased, thereby possibly also increasing the manufacturing costs associated therewith.
  • SUMMARY OF THE INVENTION
  • In accordance with an example embodiment, a non-volatile memory device is provided. The non-volatile memory device includes at least one first electrode, at least one second electrode crossing the at least one first electrode, at least one data storing layer interposed between the at least one first electrode and the at least one second electrode, at a region in which the at least one first electrode crosses the at least one second electrode and at least one metal silicide layer interposed between the at least one first electrode and the at least one second electrode, at a region in which the at least one first electrode crosses the at least one second electrode.
  • The at least one metal silicide layer may be interposed between the at least one first electrode and the at least one data storing layer, and the at least one first electrode may comprise a first semiconductor, and the first semiconductor may contact the at least one metal silicide layer so as to form a schottky diode.
  • The non-volatile memory device may further comprise at least one junction layer interposed between the at least one first electrode and the at least one metal silicide layer, and the at least one first electrode may comprise a first semiconductor having a first conductivity, and the at least one junction layer may comprise a second semiconductor having a second conductivity which is opposite to the first conductivity. The at least one junction layer may be recessed in a sidewall of the at least one first electrode. The at least one metal silicide layer may be interposed between the at least one junction layer and the at least one second electrode. The at least one data storing layer may be interposed between the at least one junction layer and the at least one metal silicide layer. The at least one data storing layer may be interposed between the at least one first electrode and the at least one junction layer.
  • The at least one first electrode may comprise a plurality of first electrodes, and the at least one second electrode may comprise a plurality of second electrodes arranged between the plurality of the first electrodes. The plurality of the first electrodes may be stacked as a plurality of stacked layers, and the at least one metal silicide layer may comprise a plurality of metal silicide layers interposed between the plurality of the first electrodes and the plurality of the second electrodes.
  • In accordance with an example embodiment, a non-volatile memory is provided. The non-volatile memory includes at least one first electrode, at least one second electrode crossing the at least one first electrode and at least one data storing layer disposed at a cross point of the at least one first electrode and the at least one second electrode. The at least one first electrode comprises a first semiconductor having a first conductivity, and the at least one second electrode comprises a third semiconductor having a second conductivity, which is opposite to the first conductivity, and a buried layer buried in the third semiconductor, wherein the buried layer comprises a metal or metal silicide.
  • In accordance with an example embodiment of the present invention, a method of manufacturing a non-volatile memory device is provided. The method includes forming at least one first electrode, forming at least one metal silicide layer on a sidewall of the at least one first electrode, forming at least one data storing layer on a sidewall of the at least one first electrode and forming at least one second electrode crossing the at least one first electrode, by interposing the at least one metal silicide layer and the at least one data storing layer between the at least one first electrode and the second electrode, at a region in which the at least one first electrode crosses the at least one second electrode.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • Example embodiments of the present invention can be understood in more detail from the following description, taken in conjunction with the accompanying drawings of which:
  • FIG. 1 is a perspective view illustrating a non-volatile memory device according to an example embodiment;
  • FIG. 2 is a perspective view illustrating a non-volatile memory device according to an example embodiment;
  • FIG. 3 is a perspective view illustrating a non-volatile memory device according to an example embodiment;
  • FIG. 4 is a perspective view illustrating a non-volatile memory device according to an example embodiment;
  • FIG. 5 is a perspective view illustrating a non-volatile memory device according to an example embodiment;
  • FIG. 6 is a cross-sectional view of the non-volatile memory device of FIG. 5 cut along a line VI-VP, according to an example embodiment;
  • FIG. 7 is a perspective view illustrating a non-volatile memory device according to an example embodiment;
  • FIG. 8 is a cross-sectional view of the non-volatile memory device of FIG. 7 cut along a line VII-VIP, according to an example embodiment;
  • FIG. 9 is a perspective view illustrating a non-volatile memory device according to an example embodiment;
  • FIG. 10 is a cross-sectional view of the non-volatile memory device of FIG. 9 cut along a line X-X′, according to an example embodiment;
  • FIG. 11 is a perspective view illustrating a non-volatile memory device according to an example embodiment;
  • FIG. 12 is a cross-sectional view of the non-volatile memory device of FIG. 11 cut along a line XII-XII′according to an example embodiment;
  • FIGS. 13 through 18 are cross-sectional views illustrating a method of manufacturing a non-volatile memory device, according to an example embodiment;
  • FIGS. 19 through 21 are cross-sectional views illustrating a method of manufacturing a non-volatile memory device, according to an example embodiment;
  • FIG. 22 is a cross-sectional view for explaining a method of manufacturing a non-volatile memory device, according to an example embodiment; and
  • FIGS. 23 and 24 are cross-sectional views illustrating a method of manufacturing a non-volatile memory device, according to an example embodiment.
  • DETAILED DESCRIPTION OF THE EXAMPLE EMBODIMENTS OF THE INVENTION
  • The inventive concept will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. The invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. In the drawings, the thicknesses of layers and regions are exaggerated for clarity.
  • FIG. 1 is a perspective view illustrating a non-volatile memory device according to an example embodiment.
  • Referring to FIG. 1, at least one first electrode 110 and at least one second electrode 160 may be arranged to cross each other. For example, one second electrode 160 may be arranged to cross between a pair of first electrodes 110 at right angles. However, this embodiment is not limited thereto, and for example, the first electrodes 110 and the second electrode 160 may be arranged to cross one another at a predetermined angle.
  • At least one data storing layer 150 may be interposed between the first electrodes 110 and the second electrode 160. For example, data storing layers 150 may be interposed at cross points of the first electrodes 110 and the second electrode 160. However, this embodiment is not limited thereto. In another example, the data storing layers 150 may be connected to each other to form a broad layer between the first electrodes 110 and the second electrodes 160.
  • The data storing layers 150 may locally store resistance variation, and control the flow of current between the first electrodes 110 and the second electrode 160. For example, the data storing layers 150 may have high resistance, low resistance, or insulating properties, according to an applied voltage. The variable resistance characteristics of the data storing layers 150 may be used in data storage of the non-volatile memory device.
  • For example, the data storing layers 150 may function as a phase change resistor, and in this case, the non-volatile memory device may operate as a phase-change random access memory (PRAM). For example, a phase change resistor may include a calcogenide compound such as GST (GeSbxTey). The phase change resistor may be in a high resistance state or a low resistance state according to the crystallization states thereof.
  • Alternatively, the data storing layers 150 may function as, for example, a variable resistor, and in this case, the non-volatile memory device may operate as a resistance random access memory (RRAM). A variable resistor is different from a phase change resistor in that resistance can be varied without a change of the crystalline state of the variable resistor. However, variable resistors may be understood in the context of a broad concept including phase change resistors. Examples of materials functioning as a variable resistor may include but are not limited to nickel oxide (NiO), niobium pentoxide (Nb2O5), and zinc oxide (ZnO).
  • Alternatively, the data storing layers 150 may function, for example, as an insulation destroying material. For example, the data storing layers 150 may include an insulating material such as an oxide whose insulation can be destroyed according to an applied voltage. The non-volatile memory device as described above may be used as a one-time program (OTP) memory. An OTP memory may be used in products requiring very large memory capacity despite only being programmed once.
  • As the insulation destroying material may not recover its insulation characteristics, it may be referred to as a fuse. On the other hand, the above-described phase change resistor and/or variable resistor may be referred to as anti-fuses because of the change of their conductivity.
  • At least one junction layer 140 and at least one metal silicide layer 145 may be further interposed between the first electrodes 110 and the second electrode 160 at a region in which the first electrodes 110 cross the second electrode 160. For example, junction layers 140 may be arranged to contact the first electrodes 110 and the data storing layers 150 may be arranged to contact sidewalls of the second electrode 160, and the metal silicide layers 145 may be interposed between the data storing layers 150 and the junction layers 140.
  • The first electrodes 110 may include a first semiconductor having a first conductivity, and the junction layers 140 may include a second semiconductor having a second conductivity, which is opposite to the first conductivity. For example, the first semiconductor may be doped with first conductive impurities, and the second semiconductor may be doped with second conductive impurities. For example, the first conductivity may be N type, and the second conductivity may be P type. Alternatively, the first conductivity may be P type, and the second conductivity may be N type.
  • Accordingly, as the first electrodes 110 and the junction layers 140 contact each other, they may form a diode junction or a PN junction. Such diode junction may rectify current flow between the first electrodes 110 and the second electrode 160. That is, the current flow between the first electrodes 110 and the second electrode 160 may have directivity according to the polarity of the diode junction or PN junction.
  • The junction layers 140 may be locally provided to be recessed from sidewalls of the first electrodes 110. Accordingly, there may be no need to allocate space for forming the junction layers 140, and thus the non-volatile memory device can be readily highly integrated. In addition, by recessing the junction layers 140 in local portions of the first electrodes 110, the diode junction or PN junction can be reduced, thereby reducing line resistance of the first electrodes 110.
  • The metal silicide layers 145 may function as, for example, diffusion barriers. Accordingly, diffusion of impurities in the junction layers 140 may be blocked by the metal silicide layers 145. Also, the metal silicide layers 145 may help reduce contact resistance between the metal silicide layers 145 and the junction layers 140. For example, the metal silicide layers 145 may include one of titanium silicide, cobalt silicide, nickel silicide, tungsten silicide, zirconium silicide, molybdenum silicide, halfnium silicide, and platinum silicide, or a stacking structure formed of at least two of these.
  • The second electrode 160 may include a conductor and/or semiconductor. For example, the second electrode 160 may include one of polysilicon, metal, and metal silicide, or a stacking structure formed of at least two of these.
  • The non-volatile memory device according to the current example embodiment may constitute memory cells. For example, each of the first electrodes 110 may be a bit line, and the second electrode 160 may be a word line, or vice versa.
  • FIG. 2 is a perspective view illustrating a non-volatile memory device according to another example embodiment. The non-volatile memory device of FIG. 2 may correspond to that of FIG. 1 with some modified or omitted components. Accordingly, common description in these two embodiments will not be repeated.
  • Referring to FIG. 2, the junction layers 140 of FIG. 1 are omitted, and the metal silicide layers 145 a may be interposed between the data storing layers 150 and the first electrodes 110. The first electrodes 110 may be semiconductors. The metal silicide layers 145 a contact the first electrodes 110 to form a schottky diode or a schottky barrier. Accordingly, in the current example embodiment, a schottky diode may rectify electric current instead of the PN junction diode of FIG. 1.
  • A schottky diode may refer to a junction barrier between metal and a semiconductor. However, a metal silicide-semiconductor junction is also known to form a schottky diode, while forming a stable interface compared to a metal-semiconductor junction.
  • Accordingly, the non-volatile memory device according to the current embodiment can be simplified by using a schottky diode instead of a PN junction diode. Thus, the non-volatile memory device can be readily highly integrated.
  • FIG. 3 is a perspective view illustrating a non-volatile memory device according to another example embodiment. The non-volatile memory device of FIG. 3 may correspond to that of FIG. 1 with some modified or omitted components. Accordingly, common description in these two embodiments will not be repeated.
  • Referring to FIG. 3, the data storing layers 150 may be interposed between the junction layers 140 and the first electrodes 110. The metal silicide layers 145 may be interposed between the junction layers 140 and the second electrode 160.
  • In the current example embodiment, the first electrodes 110 and the junction layers 140 do not directly form a PN junction. However, as the data storing layers 150 are changed into a low resistance state during the operation of the non-volatile memory device, the first electrodes 110 and the junction layers 140 may faun a PN junction. Accordingly, the non-volatile memory device according to the current example embodiment may operate in the same manner as the non-volatile memory device of FIG. 1.
  • FIG. 4 is a perspective view illustrating a non-volatile memory device according to another example embodiment. The non-volatile memory device of FIG. 4 may correspond to that of FIG. 1 with some modified or omitted components. Accordingly, common description in these two embodiments will not be repeated.
  • Referring to FIG. 4, the data storing layers 150 may be directly interposed at cross points of the first electrodes 110 and the second electrodes 160 a without interposing the junction layers 140 and the metal silicide layers 145 illustrated FIG. 1. For example, the first electrodes 110 may include a first semiconductor having a first conductivity, and a second electrode 160 a may include a third semiconductor 162 having a second conductivity and a buried layer 165. The buried layer 165 may be buried inside the third semiconductor 162.
  • When the data storing layers 150 are changed into a low resistance state, the first electrodes 110 and the second electrode 160 a form a PN junction and can function as a diode. The buried layer 165 may be formed of a conductor having a lower resistance than the third semiconductor 162, such as, for example, metal or metal silicide, to reduce resistance of the second electrode 160 a.
  • FIG. 5 is a perspective view illustrating a non-volatile memory device according to another example embodiment, and FIG. 6 is a cross-sectional view of the non-volatile memory device of FIG. 5 cut along a line VI-VI′. The non-volatile memory device of FIG. 5 is based on that of FIG. 1, and thus common description of the two example embodiments may not be repeated.
  • Referring to FIGS. 5 and 6, a plurality of first electrodes 110 may be arranged two-dimensionally and stacked three-dimensionally. A plurality of second electrodes 160 may extend across the stacked first electrodes 110. The second electrodes 160 may be arranged between the first electrodes 110, and spaced apart from each other in the extension direction of the first electrodes 110. For example, the first electrodes 110 and the second electrodes 160 may be arranged to cross each other at right angles.
  • The junction layers 140 and the metal silicide layers 145 may be disposed at cross points of the first electrodes 110 and the second electrodes 160, and interposed between the first electrodes 110 and the data storing layers 150. The data storing layers 150 may be interposed between the first electrodes 110 and the second electrodes 160. For example, the data storing layers 150 may be cylindrically-shaped and surrounding a group of second electrodes 160 interposed between one pair of the first electrodes 110. However, the form of the data storing layers 150 is not limited thereto. For example, as illustrated in FIG. 1, the data storing layers 150 may be limited to regions in which the first electrodes 110 cross the second electrodes 160.
  • In such a three-dimensional structure, the second electrodes 160 between the first electrodes 110 may be shared by memory cells on both sides of the second electrodes 160. Meanwhile, the first electrodes 110 in each layer may be accessed for operation by being divided into two groups, odd-numbered and even-numbered groups. That is, the first electrodes 110 in each layer may be accessed for operation by one pair of bit lines.
  • In the non-volatile memory device according to the current example embodiment, the plurality of memory cells may be arranged three-dimensionally. The number of the memory cells may be readily adjusted by, for example, adjusting the number and length of the first electrodes 110 and the second electrodes 160.
  • Accordingly, the non-volatile memory device can be readily highly integrated, and thus may be used in high capacity products.
  • FIG. 7 is a perspective view illustrating a non-volatile memory device according to another example embodiment, and FIG. 8 is a cross-sectional view of the non-volatile memory device of FIG. 7 cut along a line VII-VII′. The non-volatile memory device of FIG. 7 is based on that of FIG. 2, and thus common description in the two example embodiments may not be repeated.
  • Referring to FIGS. 7 and 8, a plurality of the first electrodes 110 may be arranged two-dimensionally and stacked three-dimensionally. A plurality of second electrodes 160 may extend across the stacked first electrodes 110. The second electrodes 160 may be arranged between the first electrodes 110, and spacer apart from each other in the extension direction of the first electrodes 110. For example, the first electrodes 110 and the second electrodes 160 may be arranged to cross each other at right angles.
  • The metal silicide layers 145 a may be interposed between the first electrodes 110 and the second electrodes 160, in a region in which the first electrodes 110 cross the second electrode 160, and interposed between the data storing layers 150 and the first electrodes 110. For example, the data storing layers 150 may be cylindrically-shaped as described with reference to FIGS. 5 and 6, but the form of the data storing layers 150 is not limited thereto.
  • In this three-dimensional structure, the second electrodes 160 between the first electrodes 110 may be shared by memory cells on both sides of the second electrodes 160. Meanwhile, the first electrodes 110 in each layer may be accessed for operation in two, odd-numbered and even-numbered groups. For example, the first electrodes 110 in each layer may be accessed for operation by one pair of bit lines.
  • FIG. 9 is a perspective view illustrating a non-volatile memory device according to another example embodiment, and FIG. 10 is a cross-sectional view of the non-volatile memory device of FIG. 9 cut along a line X-X′. The non-volatile memory device of FIG. 9 is based on that of FIG. 3, and thus common description in the two example embodiments may not be repeated.
  • Referring to FIGS. 9 and 10, a plurality of first electrodes 110 may be arranged two-dimensionally and stacked three-dimensionally. A plurality of second electrodes 160 may extend across the stacked first electrodes 110. The second electrodes 160 may be arranged between the first electrodes 110, and spaced apart from each other in the extension direction of the first electrodes 110. For example, the first electrodes 110 and the second electrodes 160 may be arranged to cross each other at right angles.
  • The junction layers 140 and the metal silicide layers 145 may be interposed between the first electrodes 110 and the second electrodes 160, at a region in which the first electrodes 110 cross the second electrodes 160. The data storing layers 150 may be interposed between the first electrodes 110 and the junction layers 140.
  • In this three-dimensional structure, the second electrodes 160 between the first electrodes 110 may be shared by memory cells on both sides of the second electrodes 160. Meanwhile, the first electrodes 110 in each layer may be accessed for operation in two, odd-numbered and even-numbered groups. For example, the first electrodes 110 in each layer may be accessed for operation by one pair of bit lines.
  • FIG. 11 is a perspective view illustrating a non-volatile memory device according to another example embodiment, and FIG. 12 is a cross-sectional view of the non-volatile memory device of FIG. 11 cut along a line XII-XII′. The non-volatile memory device of FIG. 11 is based on that of FIG. 4, and thus common description in the two example embodiments may not be repeated.
  • Referring to FIGS. 11 and 12, a plurality of first electrodes 110 may be arranged two-dimensionally and stacked three-dimensionally. A plurality of second electrodes 160 a may extend across the stacked first electrodes 110. The second electrodes 160 a may be arranged between the first electrodes 110, and spaced apart from each other in the extension direction of the first electrodes 110. For example, the first electrodes 110 and the second electrodes 160 a may be arranged to cross each other at right angles. For example, the data storing layers 150 may be cylindrically-shaped between the first electrodes 110 and the second electrodes 160 a, as described with reference to FIGS. 5 and 6.
  • In this three-dimensional structure, the second electrodes 160 a between the first electrodes 110 may be shared by memory cells on both sides of the second electrodes 160 a. Meanwhile, the first electrodes 110 in each layer may be accessed for operation in two, odd-numbered and even-numbered groups. For example, the first electrodes 110 in each layer may be accessed for operation by one pair of bit lines.
  • FIGS. 13 through 18 are cross-sectional views illustrating a method of manufacturing a non-volatile memory device, according to an example embodiment.
  • Referring to FIG. 13, a stack structure of first electrodes 110 may be formed. The first electrodes 110 may be arranged to be separated from one another by insulating layers 120. Each insulating layers 120 may include a complex layer formed of one material or various insulating materials.
  • For example, the insulating layers 120 and the first electrodes 110 may be stacked alternately, and trenches 125 may be formed between the stack structures of the first electrodes 110. During the formation process, for example, the first electrodes 110 may be doped with first conductive impurities using an in-situ doping method while being formed or using an ion implantation method after the trenches 125 are formed. The trenches 125 may be formed by, for example, photolithography and etching. The number of the first electrodes 110 and the trenches 125 may be selected according to the capacity of the non-volatile memory device, and does not limit the scope of the present example embodiment.
  • Referring to FIG. 14, the sidewalls of the first electrodes 110 are recessed to form grooves 130. The grooves 130 may extend the portion of the trenches 125 between the first electrodes 110. For example, the grooves 130 may be formed by etching the first electrodes 110 to a predetermined depth using an isotropic etching method such as a wet etching method or a chemical dry etching method. An etching chemical may enter sidewalls of the first electrodes 110 through the trenches 125.
  • Referring to FIG. 15, junction layers 140 may be formed on the sidewalls of the first electrodes 110. For example, the junction layers 140 may be doped with second conductive impurities using an in-situ doping method while the junction layers 140 are formed, or using an ion implantation method after the junction layers 140 are formed. An example of the ion implantation method includes but is not limited to a high angle ion implantation method.
  • For example, the junction layers 140 may be formed by depositing a semiconductor material in the trenches 125 to fill the grooves 130 using a chemical vapor deposition (CVD) method, and then anisotropically etching the semiconductor material to remain in the grooves 130. The anisotropic etching may be, for example, plasma dry etching.
  • Alternatively, the junction layers 140 may be formed using, for example, a selective epitaxial growth method. According to the selective epitaxial growth method, the junction layers 140 may not be grown on the insulating layers 120 but only on the sidewalls of the first electrodes 140, selectively.
  • Referring to FIG. 16, metal silicide layers 145 may be formed on the junction layers 140 in the trenches 125. The metal silicide layers 145 may be formed not on the insulating layers 120 but selectively only on the junction layers 140. When using a self-aligned silicidation method, the metal silicide layers 145 may be selectively formed only on the junction layers 140.
  • For example, a metal layer may be formed on an inner surface of the trenches 125 and a first heat treatment process may be performed. Accordingly, as the metal layer and the junction layers 140 react with each other, a first metal silicide may be formed. In this case, as the insulating layers 120 and the metal layer do not react with each other, a first metal silicide is not formed on the insulating layers 120. Next, the remaining metal layer may be selectively removed using, for example, a wet etching method while leaving the first metal silicide. Next, selectively, the first metal silicide may be converted into a second metal silicide using, for example, a second heat treatment process. Accordingly, the metal silicide layers 145 may be formed of the first metal silicide and/or the second metal silicide.
  • Referring to FIG. 17, data storing layers 150 may be formed on the metal silicide layers 145 and the insulating layers 120 in the trenches 125. For example, the data storing layers 150 may be formed using a chemical vapor deposition (CVD) method, by which the sidewalls of the trenches 125 can be sufficiently coated.
  • Referring to FIG. 18, second electrodes 160 may be formed on the data storing layers 150 inside the trenches 125. For example, the second electrodes 160 may be formed by forming conductive layers to fill the trenches 125 and then planarizing the conductive layers.
  • According to the above-described method of manufacturing a non-volatile memory device, memory cells having a stack structure can be formed economically in a single process.
  • FIGS. 19 through 21 are cross-sectional views illustrating a method of manufacturing a non-volatile memory device, according to another example embodiment. The method illustrated in FIGS. 19 through 21 is a modified version of the method illustrated in FIGS. 13 through 18 and described above, and thus common description of the two example embodiments will not be repeated. For example, the operation illustrated in FIG. 19 may be performed after the operation illustrated in FIG. 14.
  • Referring to FIG. 19, data storing layers 150 may be formed on sidewalls of the first electrodes 110 in the grooves 130. For example, the data storing layers 150 may be formed by forming material layers and then anisotropically etching the material layers in the form of spacers. However, in another example embodiment, the data storing layers 150 may be extended along the surfaces of the first electrodes 110 and the insulating layers 120 inside the trenches 125 and the grooves 130, unlike FIG. 19.
  • Referring to FIG. 20, junction layers 140 may be formed on the data storing layers 150 inside the grooves 130.
  • Referring to FIG. 21, the metal silicide layers 145 may be formed on the junction layers 140, and the second electrodes 160 may be formed inside the trenches 125.
  • FIG. 22 is a cross-sectional view for explaining a method of manufacturing a non-volatile memory device, according to another example embodiment. The method explained with reference to FIG. 22 is a modified version of the method illustrated in FIGS. 13 through 18 and described above, and thus common description of the two example embodiments will not be repeated. For example, the operation illustrated in FIG. 22 may be performed after the operation illustrated in FIG. 13.
  • Referring to FIG. 22, metal silicide layers 145 a may be formed on sidewalls of the first electrodes 110 exposed by the trenches 125. The metal silicide layers 145 a may be formed using a method similar to the method of forming the metal silicide layers 145 described with reference to FIG. 16. However, the metal silicide layers 145 a are different from the metal silicide layers 145 of FIG. 16 in that they are formed by reaction of the semiconductor material of the first electrodes 110 with a metal.
  • Next, the data storing layers 150 may be formed on the metal silicide layers 145 a inside the trenches 125.
  • Next, as described with reference to FIG. 18, second electrodes 160 may be formed on the data storing layers 150 so as to fill the trenches 125 as illustrated in FIG. 8.
  • FIGS. 23 and 24 are cross-sectional views illustrating a method of manufacturing a non-volatile memory device, according to another example embodiment. The method illustrated in FIGS. 23 and 24 is a modified version of the method illustrated in FIGS. 13 through 18 and described above, and thus common description of the two example embodiments will not be repeated. For example, the operation of FIG. 23 may be performed after the operation of FIG. 13.
  • Referring to FIG. 23, the data storing layers 150 may be formed on a sidewall surface of the first electrodes 110 and the insulating layers 120 inside the trenches 125 of FIG. 13. Next, a third semiconductor 162 may be formed on the data storing layers 150 inside the trenches 125. For example, the third semiconductor 162 may be formed by depositing a semiconductor material so as not to fill the trenches 125 and then anisotropically etching the semiconductor material in the form of spacers. Holes 164 may be defined inside the third semiconductor 162.
  • Next, buried layers 165 may be formed inside the holes 164. The buried layers 165 may be formed of, for example, metal or metal silicide. For example, the metal may be applied using a physical vapor deposition (PVD) method, and the metal silicide may be applied using a self-alignment formation method or a CVD method. The third semiconductor 162 and the buried layers 165 may together constitute second electrodes 160 a.
  • Having described the exemplary embodiments of the present invention, it is further noted that it is readily apparent to those of reasonable skill in the art that various modifications may be made without departing from the spirit and scope of the invention which is defined by the metes and bounds of the appended claims.

Claims (14)

1. A non-volatile memory comprising:
at least one first electrode;
at least one second electrode crossing the at least one first electrode; and
at least one data storing layer disposed at a cross point of the at least one first electrode and the at least one second electrode,
wherein the at least one first electrode comprises a first semiconductor having a first conductivity, and the at least one second electrode comprises a third semiconductor having a second conductivity, which is opposite to the first conductivity, and a buried layer buried in the third semiconductor, wherein the buried layer comprises one of a metal or metal silicide.
2. The non-volatile memory device of claim 1, wherein at least one metal silicide layer is interposed between the at least one first electrode and the at least one data storing layer.
3. The non-volatile memory device of claim 2, wherein the first semiconductor contacts the at least one metal silicide layer so as to form a schottky diode.
4. The non-volatile memory device of claim 2, further comprising at least one junction layer interposed between the at least one first electrode and the at least one metal silicide layer, and the at least one junction layer comprises a second semiconductor having a second conductivity which is opposite to the first conductivity.
5. The non-volatile memory device of claim 4, wherein the at least one junction layer is recessed in a sidewall of the at least one first electrode.
6. The non-volatile memory device of claim 4, wherein the at least one metal silicide layer is interposed between the at least one junction layer and the at least one second electrode.
7. The non-volatile memory device of claim 6, wherein the at least one data storing layer is interposed between the at least one junction layer and the at least one metal silicide layer.
8. The non-volatile memory device of claim 6, wherein the at least one data storing layer is interposed between the at least one first electrode and the at least one junction layer.
9. The non-volatile memory device of claim 1, wherein the at least one second electrode comprises a metal.
10. The non-volatile memory device of claim 1, wherein the at least one first electrode and the at least one second electrode are arranged to cross each other at a right angle.
11. The non-volatile memory device of claim 1, wherein the data storing layer comprises a variable resistor.
12. The non-volatile memory device of claim 1, wherein the at least one first electrode comprises a plurality of first electrodes, and the at least one second electrode comprises a plurality of second electrodes disposed between the plurality of the first electrodes.
13. The non-volatile memory device of claim 12, wherein the plurality of the first electrodes are stacked as a plurality of stacked layers, and the at least one metal silicide layer comprises a plurality of metal silicide layers interposed between the plurality of the first electrodes and the plurality of the second electrodes.
14. The non-volatile memory device of claim 13, wherein the at least one data storing layer extending across the plurality of the first electrodes constituting a plurality of stacked layers.
US13/355,878 2008-06-26 2012-01-23 Non-volatile memory device and method of fabricating the same Abandoned US20120119180A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020080061110A KR20100001260A (en) 2008-06-26 2008-06-26 Non-volatile memory device and method of fabricating the same
KR10-2008-0061110 2008-06-26
US12/366,151 US8124968B2 (en) 2008-06-26 2009-02-05 Non-volatile memory device
US13/355,878 US20120119180A1 (en) 2008-06-26 2012-01-23 Non-volatile memory device and method of fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/355,878 US20120119180A1 (en) 2008-06-26 2012-01-23 Non-volatile memory device and method of fabricating the same

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US12/366,151 Division US8124968B2 (en) 2008-06-26 2009-02-05 Non-volatile memory device

Publications (1)

Publication Number Publication Date
US20120119180A1 true US20120119180A1 (en) 2012-05-17

Family

ID=41446368

Family Applications (2)

Application Number Title Priority Date Filing Date
US12/366,151 Active 2029-11-28 US8124968B2 (en) 2008-06-26 2009-02-05 Non-volatile memory device
US13/355,878 Abandoned US20120119180A1 (en) 2008-06-26 2012-01-23 Non-volatile memory device and method of fabricating the same

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US12/366,151 Active 2029-11-28 US8124968B2 (en) 2008-06-26 2009-02-05 Non-volatile memory device

Country Status (4)

Country Link
US (2) US8124968B2 (en)
JP (1) JP2010010688A (en)
KR (1) KR20100001260A (en)
CN (1) CN101615656A (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8710484B2 (en) 2010-02-23 2014-04-29 Panasonic Corporation Method for manufacturing non-volatile memory device, non-volatile memory element, and non-volatile memory device
US8976566B2 (en) 2010-09-29 2015-03-10 Micron Technology, Inc. Electronic devices, memory devices and memory arrays
US9034710B2 (en) 2010-12-27 2015-05-19 Micron Technology, Inc. Methods of forming a nonvolatile memory cell and methods of forming an array of nonvolatile memory cells
US9111788B2 (en) 2008-06-18 2015-08-18 Micron Technology, Inc. Memory device constructions, memory cell forming methods, and semiconductor construction forming methods
US9184385B2 (en) 2011-04-15 2015-11-10 Micron Technology, Inc. Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells
US9257648B2 (en) 2011-02-24 2016-02-09 Micron Technology, Inc. Memory cells, methods of forming memory cells, and methods of programming memory cells
US9343665B2 (en) 2008-07-02 2016-05-17 Micron Technology, Inc. Methods of forming a non-volatile resistive oxide memory cell and methods of forming a non-volatile resistive oxide memory array
US9343145B2 (en) 2008-01-15 2016-05-17 Micron Technology, Inc. Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices
US9406878B2 (en) 2010-11-01 2016-08-02 Micron Technology, Inc. Resistive memory cells with two discrete layers of programmable material, methods of programming memory cells, and methods of forming memory cells
US9412421B2 (en) 2010-06-07 2016-08-09 Micron Technology, Inc. Memory arrays
US9454997B2 (en) 2010-12-02 2016-09-27 Micron Technology, Inc. Array of nonvolatile memory cells having at least five memory cells per unit cell, having a plurality of the unit cells which individually comprise three elevational regions of programmable material, and/or having a continuous volume having a combination of a plurality of vertically oriented memory cells and a plurality of horizontally oriented memory cells; array of vertically stacked tiers of nonvolatile memory cells
US20160365384A1 (en) * 2015-06-10 2016-12-15 SK Hynix Inc. Electronic device

Families Citing this family (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20090109804A (en) * 2008-04-16 2009-10-21 삼성전자주식회사 Non-volatile memory device and method of fabricating the same
KR20090115288A (en) * 2008-05-01 2009-11-05 삼성전자주식회사 Non-volatile memory device and method of fabricating the same
US8211743B2 (en) 2008-05-02 2012-07-03 Micron Technology, Inc. Methods of forming non-volatile memory cells having multi-resistive state material between conductive electrodes
JP5230274B2 (en) * 2008-06-02 2013-07-10 株式会社東芝 Nonvolatile semiconductor memory device
KR20100001260A (en) * 2008-06-26 2010-01-06 삼성전자주식회사 Non-volatile memory device and method of fabricating the same
JP5356005B2 (en) * 2008-12-10 2013-12-04 株式会社東芝 Nonvolatile semiconductor memory device and manufacturing method thereof
JP4956598B2 (en) * 2009-02-27 2012-06-20 シャープ株式会社 Nonvolatile semiconductor memory device and manufacturing method thereof
JP5558090B2 (en) * 2009-12-16 2014-07-23 株式会社東芝 Variable resistance memory cell array
KR20110093309A (en) * 2010-02-12 2011-08-18 주식회사 하이닉스반도체 3d non-volatile memory device and method for manufacturing the same
KR101652873B1 (en) * 2010-02-18 2016-08-31 삼성전자주식회사 Three Dimensional Semiconductor Memory Device And Method Of Operating The Same
JP5450165B2 (en) 2010-02-26 2014-03-26 株式会社東芝 Method of manufacturing a nonvolatile semiconductor memory device, and a nonvolatile semiconductor memory device
US20110241077A1 (en) * 2010-04-06 2011-10-06 Macronix International Co., Ltd. Integrated circuit 3d memory array and manufacturing method
US8427859B2 (en) 2010-04-22 2013-04-23 Micron Technology, Inc. Arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells
US8624217B2 (en) 2010-06-25 2014-01-07 International Business Machines Corporation Planar phase-change memory cell with parallel electrical paths
US8803214B2 (en) 2010-06-28 2014-08-12 Micron Technology, Inc. Three dimensional memory and methods of forming the same
CN102473707A (en) * 2010-07-01 2012-05-23 松下电器产业株式会社 Nonvolatile memory cell, nonvolatile memory cell array, and method for manufacturing the nonvolatile memory cell array
US8575008B2 (en) 2010-08-31 2013-11-05 International Business Machines Corporation Post-fabrication self-aligned initialization of integrated devices
US8187932B2 (en) 2010-10-15 2012-05-29 Sandisk 3D Llc Three dimensional horizontal diode non-volatile memory array and method of making thereof
US8759809B2 (en) 2010-10-21 2014-06-24 Micron Technology, Inc. Integrated circuitry comprising nonvolatile memory cells having platelike electrode and ion conductive material layer
US8796661B2 (en) 2010-11-01 2014-08-05 Micron Technology, Inc. Nonvolatile memory cells and methods of forming nonvolatile memory cell
KR101811308B1 (en) * 2010-11-10 2017-12-27 삼성전자주식회사 Non-volatile memory device having resistance changeable element and method of forming the same
KR101147481B1 (en) * 2010-12-06 2012-05-21 서울대학교산학협력단 One-time programmable nonvolatile memory array having vertically stacked structure and method for operating and fabricating the same
US8791447B2 (en) 2011-01-20 2014-07-29 Micron Technology, Inc. Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells
US10333064B2 (en) * 2011-04-13 2019-06-25 Micron Technology, Inc. Vertical memory cell for high-density memory
JP5674548B2 (en) 2011-04-28 2015-02-25 株式会社日立製作所 A semiconductor memory device
US9343672B2 (en) * 2011-06-07 2016-05-17 Samsung Electronics Co., Ltd. Nonvolatile memory devices, nonvolatile memory cells and methods of manufacturing nonvolatile memory devices
KR20130004784A (en) 2011-07-04 2013-01-14 삼성전자주식회사 Non-volatile memory device having resistance changeable element and method of forming the same
US8937292B2 (en) * 2011-08-15 2015-01-20 Unity Semiconductor Corporation Vertical cross point arrays for ultra high density memory applications
JP2013197396A (en) * 2012-03-21 2013-09-30 Toshiba Corp Semiconductor memory device and method of manufacturing the same
CN103474570B (en) * 2012-06-06 2016-03-30 复旦大学 Resistive memory integrated in the rear end of the structure and preparation method of an integrated circuit
US9018613B2 (en) 2012-08-14 2015-04-28 Kabushiki Kaisha Toshiba Semiconductor memory device with a memory cell block including a block film
US8841649B2 (en) 2012-08-31 2014-09-23 Micron Technology, Inc. Three dimensional memory array architecture
US8729523B2 (en) 2012-08-31 2014-05-20 Micron Technology, Inc. Three dimensional memory array architecture
TWI473262B (en) * 2012-10-03 2015-02-11 Powerchip Technology Corp Resistive random access memory and fabrication method thereof
KR20140046809A (en) * 2012-10-11 2014-04-21 에스케이하이닉스 주식회사 Resistance variable memory device and method for fabricating the same
JP6009971B2 (en) * 2012-11-16 2016-10-19 株式会社東芝 The semiconductor memory device and manufacturing method thereof
JP6251688B2 (en) 2012-12-26 2017-12-20 ソニーセミコンダクタソリューションズ株式会社 Memory device and the manufacturing method thereof
US20140217349A1 (en) * 2013-02-05 2014-08-07 Micron Technology, Inc. Methods of Forming Memory and Methods of Forming Vertically-Stacked Structures
US8971092B2 (en) 2013-02-28 2015-03-03 Kabushiki Kaisha Toshiba Semiconductor memory device
US9214351B2 (en) 2013-03-12 2015-12-15 Macronix International Co., Ltd. Memory architecture of thin film 3D array
KR20140113024A (en) * 2013-03-15 2014-09-24 에스케이하이닉스 주식회사 Resistance variable Memory Device And Method of Driving The Same
US9728584B2 (en) 2013-06-11 2017-08-08 Micron Technology, Inc. Three dimensional memory array with select device
US9231029B2 (en) 2013-12-18 2016-01-05 Kabushiki Kaisha Toshiba Semiconductor memory device and method for manufacturing same
JP6169023B2 (en) * 2014-03-13 2017-07-26 株式会社東芝 Non-volatile memory
US9397146B2 (en) 2014-05-15 2016-07-19 Globalfoundries Singapore Pte. Ltd. Vertical random access memory with selectors
US9502642B2 (en) 2015-04-10 2016-11-22 Micron Technology, Inc. Magnetic tunnel junctions, methods used while forming magnetic tunnel junctions, and methods of forming magnetic tunnel junctions
US9530959B2 (en) 2015-04-15 2016-12-27 Micron Technology, Inc. Magnetic tunnel junctions
US9520553B2 (en) 2015-04-15 2016-12-13 Micron Technology, Inc. Methods of forming a magnetic electrode of a magnetic tunnel junction and methods of forming a magnetic tunnel junction
US9257136B1 (en) 2015-05-05 2016-02-09 Micron Technology, Inc. Magnetic tunnel junctions
US9960346B2 (en) 2015-05-07 2018-05-01 Micron Technology, Inc. Magnetic tunnel junctions
US9595669B2 (en) * 2015-06-30 2017-03-14 Western Digital Technologies, Inc. Electroplated phase change switch
US9812507B2 (en) 2016-03-11 2017-11-07 Toshiba Memory Corporation Semiconductor memory device
US9947721B2 (en) * 2016-04-01 2018-04-17 Micron Technology, Inc. Thermal insulation for three-dimensional memory arrays
US9680089B1 (en) 2016-05-13 2017-06-13 Micron Technology, Inc. Magnetic tunnel junctions
US20180138292A1 (en) * 2016-11-11 2018-05-17 Sandisk Technologies Llc Methods and apparatus for three-dimensional nonvolatile memory

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6420215B1 (en) * 2000-04-28 2002-07-16 Matrix Semiconductor, Inc. Three-dimensional memory array and method of fabrication
US6642603B1 (en) * 2002-06-27 2003-11-04 Matrix Semiconductor, Inc. Same conductivity type highly-doped regions for antifuse memory cell
US20040002186A1 (en) * 2002-06-27 2004-01-01 Vyvoda Michael A. Electrically isolated pillars in active devices
US20060110877A1 (en) * 2004-11-10 2006-05-25 Park Yoon-Dong Memory device including resistance change layer as storage node and method(s) for making the same
US20060237756A1 (en) * 2005-04-20 2006-10-26 Jae-Hyun Park Phase change memory devices and their methods of fabrication
US20080265235A1 (en) * 2007-04-27 2008-10-30 Takeshi Kamigaichi Nonvolatile semiconductor memory device and manufacturing method thereof
US8124968B2 (en) * 2008-06-26 2012-02-28 Samsung Electronics Co., Ltd. Non-volatile memory device

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02203565A (en) * 1989-02-01 1990-08-13 Hitachi Ltd Semiconductor device and its manufacture
US5998244A (en) * 1996-08-22 1999-12-07 Micron Technology, Inc. Memory cell incorporating a chalcogenide element and method of making same
US6627530B2 (en) * 2000-12-22 2003-09-30 Matrix Semiconductor, Inc. Patterning three dimensional structures
US6579760B1 (en) * 2002-03-28 2003-06-17 Macronix International Co., Ltd. Self-aligned, programmable phase change memory
JP4403356B2 (en) * 2002-10-29 2010-01-27 ソニー株式会社 Semiconductor memory and manufacturing method thereof
US20050158950A1 (en) * 2002-12-19 2005-07-21 Matrix Semiconductor, Inc. Non-volatile memory cell comprising a dielectric layer and a phase change material in series
US7767499B2 (en) * 2002-12-19 2010-08-03 Sandisk 3D Llc Method to form upward pointing p-i-n diodes having large and uniform current
US7383476B2 (en) * 2003-02-11 2008-06-03 Sandisk 3D Llc System architecture and method for three-dimensional memory
CN1764982B (en) * 2003-03-18 2011-03-23 株式会社东芝 Phase-change memory device and its manufacture method
WO2004100267A1 (en) * 2003-04-03 2004-11-18 Hewlett-Packard Development Company, L.P. Cubic memory array
JP2004319587A (en) * 2003-04-11 2004-11-11 Sharp Corp Memory cell, memory, and method of manufacturing memory cell
CN101553925B (en) * 2006-11-15 2013-08-14 桑迪士克3D公司 P-I-N diode crystallized adjacent to silicide in series with a dielectric antifuse and methods of forming the same
KR100663358B1 (en) * 2005-02-24 2007-01-02 삼성전자주식회사 Phase change memory devices employing cell diodes and methods of fabricating the same
JP2008078404A (en) * 2006-09-21 2008-04-03 Toshiba Corp Semiconductor memory and manufacturing method thereof
JP2008085003A (en) * 2006-09-27 2008-04-10 Matsushita Electric Ind Co Ltd Variable resistance memory device
JP4577695B2 (en) * 2006-11-07 2010-11-10 エルピーダメモリ株式会社 The method of manufacturing a semiconductor memory device and a semiconductor memory device
KR101196392B1 (en) * 2006-11-28 2012-11-02 삼성전자주식회사 Non-volatile Memory Device and method of fabricating the same
JP5091491B2 (en) * 2007-01-23 2012-12-05 株式会社東芝 Nonvolatile semiconductor memory device
KR20090055874A (en) * 2007-11-29 2009-06-03 삼성전자주식회사 Non-volatile memory device and method of fabricating the same
KR101418434B1 (en) * 2008-03-13 2014-08-14 삼성전자주식회사 Non-volatile memory device, method of fabricating the same, and processing system comprising the same
KR20090109804A (en) * 2008-04-16 2009-10-21 삼성전자주식회사 Non-volatile memory device and method of fabricating the same

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6420215B1 (en) * 2000-04-28 2002-07-16 Matrix Semiconductor, Inc. Three-dimensional memory array and method of fabrication
US6642603B1 (en) * 2002-06-27 2003-11-04 Matrix Semiconductor, Inc. Same conductivity type highly-doped regions for antifuse memory cell
US20040002186A1 (en) * 2002-06-27 2004-01-01 Vyvoda Michael A. Electrically isolated pillars in active devices
US20060110877A1 (en) * 2004-11-10 2006-05-25 Park Yoon-Dong Memory device including resistance change layer as storage node and method(s) for making the same
US20060237756A1 (en) * 2005-04-20 2006-10-26 Jae-Hyun Park Phase change memory devices and their methods of fabrication
US20080265235A1 (en) * 2007-04-27 2008-10-30 Takeshi Kamigaichi Nonvolatile semiconductor memory device and manufacturing method thereof
US8124968B2 (en) * 2008-06-26 2012-02-28 Samsung Electronics Co., Ltd. Non-volatile memory device

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9343145B2 (en) 2008-01-15 2016-05-17 Micron Technology, Inc. Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices
US9805792B2 (en) 2008-01-15 2017-10-31 Micron Technology, Inc. Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices
US10262734B2 (en) 2008-01-15 2019-04-16 Micron Technology, Inc. Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices
US9111788B2 (en) 2008-06-18 2015-08-18 Micron Technology, Inc. Memory device constructions, memory cell forming methods, and semiconductor construction forming methods
US9559301B2 (en) 2008-06-18 2017-01-31 Micron Technology, Inc. Methods of forming memory device constructions, methods of forming memory cells, and methods of forming semiconductor constructions
US9257430B2 (en) 2008-06-18 2016-02-09 Micron Technology, Inc. Semiconductor construction forming methods
US9666801B2 (en) 2008-07-02 2017-05-30 Micron Technology, Inc. Methods of forming a non-volatile resistive oxide memory cell and methods of forming a non-volatile resistive oxide memory array
US9343665B2 (en) 2008-07-02 2016-05-17 Micron Technology, Inc. Methods of forming a non-volatile resistive oxide memory cell and methods of forming a non-volatile resistive oxide memory array
US8710484B2 (en) 2010-02-23 2014-04-29 Panasonic Corporation Method for manufacturing non-volatile memory device, non-volatile memory element, and non-volatile memory device
US9697873B2 (en) 2010-06-07 2017-07-04 Micron Technology, Inc. Memory arrays
US9412421B2 (en) 2010-06-07 2016-08-09 Micron Technology, Inc. Memory arrays
US10241185B2 (en) 2010-06-07 2019-03-26 Micron Technology, Inc. Memory arrays
US9989616B2 (en) 2010-06-07 2018-06-05 Micron Technology, Inc. Memory arrays
US9887239B2 (en) 2010-06-07 2018-02-06 Micron Technology, Inc. Memory arrays
US8976566B2 (en) 2010-09-29 2015-03-10 Micron Technology, Inc. Electronic devices, memory devices and memory arrays
US9406878B2 (en) 2010-11-01 2016-08-02 Micron Technology, Inc. Resistive memory cells with two discrete layers of programmable material, methods of programming memory cells, and methods of forming memory cells
US9454997B2 (en) 2010-12-02 2016-09-27 Micron Technology, Inc. Array of nonvolatile memory cells having at least five memory cells per unit cell, having a plurality of the unit cells which individually comprise three elevational regions of programmable material, and/or having a continuous volume having a combination of a plurality of vertically oriented memory cells and a plurality of horizontally oriented memory cells; array of vertically stacked tiers of nonvolatile memory cells
US9034710B2 (en) 2010-12-27 2015-05-19 Micron Technology, Inc. Methods of forming a nonvolatile memory cell and methods of forming an array of nonvolatile memory cells
US9257648B2 (en) 2011-02-24 2016-02-09 Micron Technology, Inc. Memory cells, methods of forming memory cells, and methods of programming memory cells
US9424920B2 (en) 2011-02-24 2016-08-23 Micron Technology, Inc. Memory cells, methods of forming memory cells, and methods of programming memory cells
US9184385B2 (en) 2011-04-15 2015-11-10 Micron Technology, Inc. Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells
US9741767B2 (en) * 2015-06-10 2017-08-22 SK Hynix Inc. Electronic device
US20160365384A1 (en) * 2015-06-10 2016-12-15 SK Hynix Inc. Electronic device

Also Published As

Publication number Publication date
US20090321878A1 (en) 2009-12-31
US8124968B2 (en) 2012-02-28
JP2010010688A (en) 2010-01-14
KR20100001260A (en) 2010-01-06
CN101615656A (en) 2009-12-30

Similar Documents

Publication Publication Date Title
CN101447502B (en) Non-volatile memory devices and methods of fabricating and using the same
EP2548238B1 (en) Method of forming bottom electrodes for use with metal oxide resistivity switching layers
US8120005B2 (en) Phase change memory devices and their methods of fabrication
US9034710B2 (en) Methods of forming a nonvolatile memory cell and methods of forming an array of nonvolatile memory cells
US8148193B2 (en) Semiconductor device and method of fabricating the same
KR101418434B1 (en) Non-volatile memory device, method of fabricating the same, and processing system comprising the same
US7838341B2 (en) Self-aligned memory cells and method for forming
US8445318B2 (en) Phase change memory devices including phase change layer formed by selective growth methods and methods of manufacturing the same
US8871559B2 (en) Methods for fabricating phase change memory devices
US20080272355A1 (en) Phase change memory device and method for forming the same
US7863173B2 (en) Variable resistance non-volatile memory cells and methods of fabricating same
US7824954B2 (en) Methods of forming phase change memory devices having bottom electrodes
KR100782496B1 (en) Methods fabricating of semiconductor devices having self-aligned cell diodes and methods fabricating of phase change memory devices using the same
CN102544049B (en) Three-dimensional semiconductor storage device and preparation method for three-dimensional semiconductor storage device
KR100827661B1 (en) Phase change memory devices having dual lower electrodes and methods fabricating the same
US20080247219A1 (en) Resistive Random Access Memory Devices Including Sidewall Resistive Layers and Related Methods
JP6059349B2 (en) Three-dimensional memory array architecture
KR100689831B1 (en) Phase change memory cells having a cell diode and a bottom electrode self-aligned with each other and methods of fabricating the same
JP4345676B2 (en) A semiconductor memory device
JP2011508979A (en) How memory cell and making the same using a bottom carbon nanotube reversible resistance-switching element has been selectively prepared formed on the conductive
US7612360B2 (en) Non-volatile memory devices having cell diodes
KR101535653B1 (en) Method of manufacturing a phase change memory element
EP3178113B1 (en) Fully isolated selector for memory device
CN102067315A (en) Non-volatile memory arrays comprising rail stacks with a shared diode component portion for diodes of electrically isolated pillars
KR20100031698A (en) Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION