US20120092048A1 - Compensation of phase lock loop (pll) phase distribution caused by power amplifier ramping - Google Patents
Compensation of phase lock loop (pll) phase distribution caused by power amplifier ramping Download PDFInfo
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- US20120092048A1 US20120092048A1 US13/280,610 US201113280610A US2012092048A1 US 20120092048 A1 US20120092048 A1 US 20120092048A1 US 201113280610 A US201113280610 A US 201113280610A US 2012092048 A1 US2012092048 A1 US 2012092048A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
- H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
- H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
- H03L2207/06—Phase locked loops with a controlled oscillator having at least two frequency control terminals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
- H03L2207/50—All digital phase-locked loop
Definitions
- DCOs Digitally controlled oscillators
- PLL phase-locked loop
- a DCO may be viewed as a circuit that seeks to transform an input control voltage signal to an output voltage signal having a desired frequency.
- the present application describes compensation of phase disturbances of a phase lock-loop during power ramp up or down of a power amplifier.
- the phase lock loops may be employed in wireless communication devices.
- Many specific details are set forth in the following description and in FIGS. 1-8 to provide a thorough understanding of various implementations.
- One skilled in the art will understand, however, that the subject matter described herein may have additional implementations, or that the concepts set forth may be practiced without several of the details described in the following description. More specifically, a system is described that is able to switch between type I and type II PLL modes depending on the power state of the power amplifier without introducing additional disturbances.
- second divider module 312 is configured to receive output signal S 2′ from DCO module 308 and reduce the frequency of output signal S 2′ by a divisor to produce a second divided signal S 7′ .
- the magnitude of the divisor is determined by the application desired.
- PA module 314 is configured to receive second divided signal S 7′ and amplify signal S 7′ and output this as amplified signal S 8′ .
- system 300 When differentiator module 320 is enabled, system 300 is in type I PLL mode and thus power ramp or down of PA module 314 may start. During power ramp or down of PA module 314 , tuning characteristics of DCO module 308 are modified, i.e. a frequency offset proportional to feedback signal S 9′ is added to control signal S 1′ . As a result of system 300 maintaining the frequency of output signal S 2′ , system 300 compensates for the added frequency offset of feedback signal S 9′ . Thus, signal S 1′ will be controlled such that the frequency of output signal S 2′ remains substantially constant and signal S 1′ will approximately follow the amplitude of feedback signal S 9′ proportionally. Moreover, due to the PLL digital phase error processing in Type I mode has a constant and finite gain for constant phase errors, the phase error will also be proportional to the amplitude of feedback signal S 9′ .
- a power state of PA module 314 is determined.
- the power state being either ramping up/down or constant.
- step 608 if the power of PA module 314 is ramping up/down, enable signal S 10′ is set to logical high that is input to differentiator module 316 . Thus, differentiator module 316 is enabled.
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- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Disclosed herein are techniques, systems, and methods relating to compensation of phase disturbances of a phase lock-loop during power ramp up or down of a power amplifier. More specifically, a phase lock-loop is described that is able to switch between type I and type II PLL modes depending on the power state of the power amplifier without introducing additional disturbances.
Description
- This Application is a Divisional Application of co-pending application Ser. No. 12/483,708, which was filed on Jun. 12, 2009. The entire contents of application Ser. No. 12/483,708 are hereby incorporated herein by reference.
- Digitally controlled oscillators (DCOs) are commonly employed in a variety of applications, including communication and timing circuitry. In particular, DCOs are commonly used in phase-locked loop (PLL) systems. Functionally, a DCO may be viewed as a circuit that seeks to transform an input control voltage signal to an output voltage signal having a desired frequency.
- In this case, the output signal of the PLL is normally compared against a reference signal, and a loop filter is used to tune the DCO in a manner dependent upon the comparison such that the output signal “matches” the reference signal. Such PLLs are usually used to synthesize signals at a desired frequency or, for example, to recover a clock signal from a data stream. PLLs can also be advantageously used in mobile radio for the purposes of signal modulation.
- The detailed description is described with reference to the accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The use of the same reference numbers in different figures indicates similar or identical items.
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FIG. 1 is a block diagram of a digital type II phase lock-loop. -
FIG. 2 is a block diagram of a digital type I phase lock-loop. -
FIG. 3 is a block diagram of a phase lock-loop comprising a differentiator module. -
FIG. 4 is a block diagram of the differentiator module ofFIG. 3 . -
FIG. 5 is a timing diagram of the phase lock-loop ofFIG. 3 . -
FIG. 6 is a flowchart employing the system ofFIG. 3 . -
FIG. 7 is a block diagram of a digital loop filter of the digital type I phase lock-loop ofFIG. 2 . -
FIG. 8 is a block diagram of a transceiver module of the phase lock-loop comprising a differentiator module ofFIG. 3 . - The present application describes compensation of phase disturbances of a phase lock-loop during power ramp up or down of a power amplifier. The phase lock loops may be employed in wireless communication devices. Many specific details are set forth in the following description and in
FIGS. 1-8 to provide a thorough understanding of various implementations. One skilled in the art will understand, however, that the subject matter described herein may have additional implementations, or that the concepts set forth may be practiced without several of the details described in the following description. More specifically, a system is described that is able to switch between type I and type II PLL modes depending on the power state of the power amplifier without introducing additional disturbances. -
FIG. 1 shows an overview of a digital type II phase lock loop (PLL) 100.PLL 100 comprises a time to digital converter (TDC)module 102, a digitalloop filter module 104, anintegrator module 106, a digital controlled oscillator (DCO)module 108, afirst divider module 110, asecond divider module 112, a power amplifier (PA)module 114, a sigma-delta module 116, and atarget frequency module 118.PLL 100 generates an output signal, viaDCO module 108, that is proportional to a reference signal or within a desired frequency band of a reference signal depending upon the application desired, described further below. -
DCO module 108 is configured to receive a control signal S1 fromintegrator module 106 and generate an output signal S2. Output signal S2 is controlled by, and has parameters dependent upon, control signal S1. More specifically, altering control signal S1 alters output signal S2. Thus, to obtain a desired output signal S2, control signal S1 is altered. -
First divider module 110 is configured to receive output signal S2 fromDCO module 108 and reduce the frequency of output signal S2 by a divisor to produce a divided signal S3. Thefirst divider module 110 is further configured to receive a signal Sdivisor that is output fromtarget frequency module 118 via sigma-delta module 116. Signal Sdivsor contains information regarding the divisor thatdivider module 110 employs to reduce the frequency of output signal S2. The magnitude of the divisor is determined by the application desired. -
TDC module 102 is configured to receive divided signal S3 fromdivider module 110 and further configured to receive a reference signal S4. Reference signal S4 may be any type of signal dependent upon the application desired.TDC module 102 determines a phase error between divided signal S3 and reference signal S4 (i.e. a relative phase difference between divided signal S3 and reference signal S4).TDC module 102 outputs this as comparison signal S5. - Digital
loop filter module 104 is configured to receive signal S5 fromTDC module 102. Digitalloop filter module 104 is a low pass filter and thus limits the bandwidth of signal S5 and outputs this as signal S6. Integrator module 106 is configured to receive signal S6 from digitalloop filter module 104.Integrator module 106 accumulates the phase error within signal S6 and outputs this as control signal S1. As mentioned above, altering of control signal S1 alters output signal S2. Output signal S2 is altered to have a frequency that is proportional to reference signal S4 as dependent upon the application desired. -
Second divider module 112 is configured to receive output signal S2 fromDCO module 108 and reduce the frequency of output signal S2 by a divisor to produce a second divided signal S7. The magnitude of the divisor is determined by the application desired.PA module 114 is configured to receive second divided signal S7 and amplify signal S7 and output this as amplified signal S8. - Type II PLL 100 offers many advantages as compared to other types of phase lock-loops, i.e., improved noise suppression of
DCO module 108. However,PA module 114 may generate an undesirable feedback signal S9 that is input to and picked up byDCO module 108 and that comprises a harmonic with the same frequency of output signal S2 that is output byDCO module 110. Signal S9 may introduce a phase transient withinPLL 100 when a power ofPA module 114 is ramping up or down, which is undesirable. To that end, a digital type I phase lock loop has characteristics that may be desirable during power ramp or down ofPA module 114, as described further below. -
FIG. 2 shows an overview of digital type IPLL 200. Portions ofPLL 200 are analogous to portions ofPLL 100 mentioned above with respect toFIG. 1 . More specifically, aTDC module 202, a digitalloop filter module 204, aDCO module 208, afirst divider module 210, asecond divider module 212, aPA module 214, a sigma-delta module 216, and atarget frequency module 218 are analogous toTDC module 102, digitalloop filter module 104,DCO module 108,first divider module 110,second divider module 112,PA module 114, sigma-delta module 116, andtarget frequency module 118, respectively, ofFIG. 1 . As such, any reference to any portion of the analogous portions ofPLL 100 may be applied analogous to the corresponding portion ofPLL 200. However, PLL 200 differs slightly fromPLL 100. More specifically,DCO module 208 is configured to receive signal S6 that is output from digitalloop filter module 204, i.e. signal S6 and signal S1 are substantially the same. - Type I PLL 200 offers some advantages as compared to other types of phase lock loops, i.e., improved linearity when employed as an inband phase modulator. Further,
PLL 200 permits static phase deviations ofDCO module 208. Since the phase error is not integrated inPLL 200, a constant phase error leads to a differing value of control signal S1. Further, as a result of feedback signal S9 fromPA module 214 modifying the tuning characteristics ofDCO module 208 by adding a frequency offset which is proportional to the power of feedback signal S9, the phase error is also proportional to the power of feedback signal S9. In contrast, the phase error is integrated in type IIPLL 100 and thus is controlled towards zero. However, in comparison withPLL 100, PLL 200 has drawbacks in noise suppression ofDCO module 208. Furthermore, PLL 200 may have phase drifts due to self-heating on the chip ofPLL 200, all of which is undesirable. - It may therefore be desirable to employ PLL 200 (type I PLL) during power ramp or down of
PA module 114 and employPLL 100 when power is substantially constant forPA module 114, i.e combining the phase transient behaviors of both type I PLL and type II PLL. Thus, during power ramp up or down ofPA module 114, the phase error will be approximately proportional to the power ofPA module 114 but will not change upon the power ofPA module 114 being substantially constant. Further, when the power has become substantially constant forPA module 114, the benefits of PLL 100 (type II PLL) are realized such as improved noise suppression ofDCO module 108. - Combining Phase Transient Behavior of Digital Type I Phase Lock Loops with Digital Type II Phase Lock Loops
-
FIG. 3 shows an overview of asystem 300 that employs the benefits of PLL 200 (type I PLL) during power ramp or down ofPA module 114 and employs the benefits of PLL 100 (type II PLL) when power has become substantially constant forPA module 114. Further,system 300 is able to switch between the type I PLL mode and the type II PLL mode without generating phase transients insystem 300 that may violate the phase error specification ofsystem 300. -
System 300 comprises a time to digital converter (TDC)module 302, a digitalloop filter module 304, anintegrator module 306, a digital controlled oscillator (DCO) 308, afirst divider module 310, asecond divider module 312, a power amplifier (PA) 314, a sigma-delta module 316, atarget frequency module 318, and adifferentiator module 320. - Switching to PLL type I
- Upon power ramp up or down of
PA module 114, it may be desired to switchsystem 300 to PLL type I mode. In PLL type I mode, feedback signal S9 is minimized, if not prevented, withinsystem 300. -
DCO module 308 is configured to receive a control signal S1′ fromintegrator module 306 and generate an output signal S2′. Output signal S2′ is controlled by, and parameters thereof dependent, on control signal S1′. More specifically, altering of control signal S1′ alters output signal S2′. Thus, to obtain a desired output signal S2′, control signal S1′ is altered. -
First divider module 310 is configured to receive output signal S2′ fromDOC module 308 and reduce the frequency of output signal S2′ by a divisor to produce a divided signal S3′.First divider module 110 is further configured to receive a signal Sdivisor′ that is output fromtarget frequency module 318 via sigma-delta module 316. Signal Sdivsor contains information regarding the divisor that dividermodule 310 employs to reduce the frequency of output signal S2′. The magnitude of the divisor is determined by the application desired. -
TDC module 302 is configured to receive divided signal S3′ fromdivider module 310 and further configured to receive a reference signal S4′. Reference signal S4′ may be any type of signal dependent upon the application desired.TDC module 302 determines a phase error between divided signal S3′ and reference signal S4′ (i.e. a relative phase difference between divided signal S3′ and reference signal S4′).TDC module 302 outputs this as comparison signal S5′. - Digital
loop filter module 304 is configured to receive signal S5′ fromTDC module 302. Digitalloop filter module 304 is a low pass filter and thus limits the bandwidth of signal S5′ and outputs this as signal S6′. Differentiator module 320 is enabled such that it is configured to receive signal S6′ from digitalloop filter module 304. -
FIG. 4 showsdifferentiator module 320 in further detail.Differentiator module 320 comprises a flip-flop 400 and an adder/subtractor 402. In a further implementation,differentiator module 320 comprises a plurality flip-flops depending upon the application desired. Flip-flop 400 is implemented as a D flip-flop, which is commonly known in the art, having a clock input 404, an output 406, and an enableinput 408. Enableinput 408 is configured to receive a signal S10′. To that end, when signal S10′ is set to logical high,differential module 320 is enabled. The data input D of flip-flop 400 is configured to receive signal S6′ and output a signal S11′. Adder/subtractor 402 is configured to receive signal S11′ from flip-flop 400 and further configured to receive signal S6′ fromdigital loop filter 304. Adder/subtractor 402 determines a difference of signal S11′ and S6′ and outputs this as signal S12′. Further, as a result of signal S6′ being constant in the locked state, output signal S12′ ofdifferentiator module 316 will remain at zero. -
Integrator module 306 is configured to receive signal S12′ fromdifferentiator module 320.Integrator module 306 accumulates the phase error within signal S12′ and outputs this as signal S1′. As mentioned above, altering of control signal S1′ alters output signal S2′. Output signal S2′ is altered to have a frequency that is proportional to reference signal S4′ depending on the application desired. Furthermore, as a result of signal S12′ output fromdifferentiator module 316 remaining at zero, signal S1′ does not change. To that end, as a result ofdifferentiator module 316 being enabled,integrator module 306 is not active from the point of view ofsystem 300. Thus,system 300 does not see/recognize any step during switching, as long as switching is done when the PLL phase error is settled. - Returning to
FIG. 3 ,second divider module 312 is configured to receive output signal S2′ fromDCO module 308 and reduce the frequency of output signal S2′ by a divisor to produce a second divided signal S7′. The magnitude of the divisor is determined by the application desired.PA module 314 is configured to receive second divided signal S7′ and amplify signal S7′ and output this as amplified signal S8′. - When
differentiator module 320 is enabled,system 300 is in type I PLL mode and thus power ramp or down ofPA module 314 may start. During power ramp or down ofPA module 314, tuning characteristics ofDCO module 308 are modified, i.e. a frequency offset proportional to feedback signal S9′ is added to control signal S1′. As a result ofsystem 300 maintaining the frequency of output signal S2′,system 300 compensates for the added frequency offset of feedback signal S9′. Thus, signal S1′ will be controlled such that the frequency of output signal S2′ remains substantially constant and signal S1′ will approximately follow the amplitude of feedback signal S9′ proportionally. Moreover, due to the PLL digital phase error processing in Type I mode has a constant and finite gain for constant phase errors, the phase error will also be proportional to the amplitude of feedback signal S9′. - Switching to PLL type II
- Upon the power of
PA module 314 becoming substantially constant, it may be desired to switchsystem 300 to PLL type II mode. To switchsystem 300 to PLL type II mode, flip-flop 400 ofdifferentiator module 320 is frozen. More specifically, enable signal S10′ input to enableinput 408 is set to zero. Thus, the value of flip-flop 400 withindifferentiator module 320 is set to hold anddifferentiator module 320 subtracts the last active value of signal S12′ from signal S6′. Thus,system 300 is in PLL type II mode asdifferentiator module 316 is no longer “cancelling”integrator module 308. Signal S6′ output fromdigital loop filter 304 stays at the actual level while signal S12′ input tointegrator module 308 is zero. Thus,differentiator module 316 has been “bypassed” without generating a phase transient withinsystem 300. - Transceiver Module Associated with
PA Module 314 - In a further implementation,
FIG. 8 showssystem 300 comprising a transceiver module 122, withPA module 114 being associated with transceiver module 122. Transceiver module 122 is configured to receive signal S7′. As a result,PLL 300 is switchable between type I mode and type II mode depending upon the power state of transceiver module 122 (i.e ramping or substantially constant), analogous to that above with respect toPA module 114. -
PLL 200 with Switchable Digital Loop Filter - Referring back to
FIG. 2 , in a further implementation, a transfer function of digitalloop filter module 204 may be switchable to enable changing of a behavior ofPLL 200, i.e. between type I mode and type II mode.FIG. 7 shows digitalloop filter module 204 in more detail. More specifically, a transfer function of digitalloop filter module 204 is switchable between a low pass filter with integrating behavior (pole at s=0) and a low pass filter without integrating behavior depending upon the power state of the power amplifier. When the power state ofPA module 214 becomes substantially constant, the integral loop factor of digitalloop filter module 204 is not zero and the transfer function of digitalloop filter module 204 is switched to a low pass filter with integrating behavior and thusPLL 200 is in type II mode. When the power state ofPA module 214 is ramping up or down, the integral loop factor of digitalloop filter module 204 is zero and the transfer function of digitalloop filter module 204 is switched to a low pass filter without integrating behavior and thusPLL 200 is in type I mode. As a result,PLL 200 is switchable between type I mode and type II mode depending upon the power state ofPA module 214. -
PLL 100 with Switchable Direct Connection - Referring back to
FIG. 1 , in a further implementation,integrator module 106 may be switchable such thatintegrator module 106 may be bypassed withinPLL 100 depending on the power state ofPA 114. More specifically, when the power state ofPA module 114 becomes substantially constant,integrator module 106 is not bypassed and is coupled toDCO module 108, as described above, and thusPLL 100 is in type II mode. When the power state ofPA module 114 is ramping up or down,integrator module 106 is bypassed such that digitalloop filter module 104 is coupled toDCO module 108, i.e.DCO module 108 is configured to receive signal S6 from digital loop filter module 104 (signal S6 and signal S1 are substantially the same), and thusPLL 100 is in type I mode. As a result,PLL 210 is switchable between type I mode and type II mode depending upon the power state ofPA module 114. -
FIG. 5 shows a timing diagram 500 of the switching ofsystem 300 between type I PLL mode and type II PLL mode. Timing diagram has 5differing time regions PA module 314. - During
time region 502, the power ofPA module 314 is substantially constant. Thussystem 300 is in PLL type II mode and enable signal S10′ is set to zero. - During
time region 504, the power ofPA module 314 is ramping up. Thussystem 300 is in PLL type I mode and enable signal S10′ is set to logical high. - During
time region 506, the power ofPA module 314 is substantially constant. Thussystem 300 is in PLL type II mode and enable signal S10′ is set to zero. - During
time region 508, the power ofPA module 314 is ramping down. Thussystem 300 is in PLL type I mode and enable signal S10′ is set to logical high. - During
time region 510, the power ofPA module 314 is substantially constant. Thussystem 300 is in PLL type II mode and enable signal S10′ is set to zero. - Further, timing diagram 500 shows output signal S2 of
PLL 100 and output signal S2′ ofsystem 300 versus the power state ofPA module 314. As is evident, a phase transient is introduced inPLL 100 after power ramp up or down whilesystem 300 operates without any disturbances. -
FIG. 6 shows amethod 600 of employingsystem 300. Theprocess 600 is illustrated as a collection of referenced acts arranged in a logical flow graph, which represent a sequence that can be implemented in hardware, software, or a combination thereof. The order in which the acts are described is not intended to be construed as a limitation, and any number of the described acts can be combined in other orders and/or in parallel to implement the process. - At
step 602, a power state ofPA module 314 is determined. The power state being either ramping up/down or constant. - At
step 604, if the power ofPA module 314 is constant, enable signal S10′ is set to zero that is input todifferentiator module 316. Thus,differentiator module 316 is not enabled. - At
step 606,system 300 is in type II PLL mode. - At
step 608, if the power ofPA module 314 is ramping up/down, enable signal S10′ is set to logical high that is input todifferentiator module 316. Thus,differentiator module 316 is enabled. - At
step 610,system 300 is in type I PLL mode. - Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as exemplary forms of implementing the claims.
Claims (15)
1. A method comprising:
determining a power state of a power amplifier to receive an output signal of a phase lock loop;
enabling the phase lock loop in first mode when the power state of the power amplifier is constant; and
enabling the phase lock loop in second mode when the power state of the power amplifier is ramping.
2. The method of claim 1 , wherein enabling the phase lock loop in the first mode includes setting an enable signal of a differentiator to a first state and enabling the phase lock loop in the second mode includes setting the enable signal of the differentiator to a second state.
3. The method of claim 2 , wherein enabling the phase lock loop in the first mode includes setting the enable signal of the differentiator module to zero such that a differentiator module is not enabled.
4. The method of claim 2 , wherein enabling the phase lock loop in the second mode includes setting the enable signal of the differentiator module to logical high such that a differentiator module is enabled.
5. The method of claim 2 , wherein setting the enable signal to the first state causes a flip-flop of the differentiator to set to a hold state.
6. The method of claim 2 , wherein setting the enable signal to the second state causes a flip-flop of the differentiator to provide an output signal.
7. The method as recited in claim 1 , further comprising compensating for a feedback signal comprising a harmonic with the same frequency of an output signal of the phase lock loop, the feedback signal generated by the power amplifier.
8. The method as recited in claim 1 , further comprising switching between the first mode and the second mode of the phase lock loop without generating additional disturbances within the phase lock loop.
9. A system comprising:
a transceiver module; and
a phase lock loop associated with the transceiver module, the phase lock loop to operate in a first mode when the transceiver module is in a first state and to operate in a second mode when the transceiver module is in a second state.
10. The system according to claim 9 , further comprising a power amplifier associated with the transceiver module, the power amplifier determining the first and second states.
11. The system according to claim 10 , wherein the first state is to occur when the power amplifier is in a substantially constant state and the second state is to occur when the power amplifier is ramping.
12. The system according to claim 9 , further comprising a differentiator to enable the phase lock loop to operate in the first and second modes.
13. The system according to claim 12 , wherein the differentiator is to receive an enable signal in a first state to enable the phase lock loop to operate in the first mode and the differentiator is to receive the enable signal in a second state to enable the phase lock loop to operate in the second mode.
14. The system according to claim 12 , wherein the differentiator includes a flip-flop, the flip-flop to receive an enable signal in a first state to enable the phase lock loop to operate in the first mode.
15. The system according to claim 14 , wherein the flip-flop is to receive the enable signal in a second state to enable the phase lock loop to operate in the second mode.
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US13/280,610 US20120092048A1 (en) | 2009-06-12 | 2011-10-25 | Compensation of phase lock loop (pll) phase distribution caused by power amplifier ramping |
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US12/483,708 US8058917B2 (en) | 2009-06-12 | 2009-06-12 | Compensation of phase lock loop (PLL) phase distribution caused by power amplifier ramping |
US13/280,610 US20120092048A1 (en) | 2009-06-12 | 2011-10-25 | Compensation of phase lock loop (pll) phase distribution caused by power amplifier ramping |
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US12/483,708 Division US8058917B2 (en) | 2009-06-12 | 2009-06-12 | Compensation of phase lock loop (PLL) phase distribution caused by power amplifier ramping |
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US13/280,610 Abandoned US20120092048A1 (en) | 2009-06-12 | 2011-10-25 | Compensation of phase lock loop (pll) phase distribution caused by power amplifier ramping |
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US12/483,708 Active 2029-07-19 US8058917B2 (en) | 2009-06-12 | 2009-06-12 | Compensation of phase lock loop (PLL) phase distribution caused by power amplifier ramping |
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US (2) | US8058917B2 (en) |
DE (1) | DE102010029977B4 (en) |
Cited By (1)
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US20120020390A1 (en) * | 2010-01-19 | 2012-01-26 | Panasonic Corporation | Angle modulator, transmission device, and wireless communication device |
Families Citing this family (8)
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TWI364169B (en) * | 2008-12-09 | 2012-05-11 | Sunplus Technology Co Ltd | All digital phase locked loop circuit |
US8248127B2 (en) * | 2010-08-05 | 2012-08-21 | Hong Kong Applied Science And Technology Research Institute Co., Ltd. | Digital phase lock system with dithering pulse-width-modulation controller |
KR101829404B1 (en) | 2011-02-04 | 2018-02-19 | 마벨 월드 트레이드 리미티드 | REFERENCE CLOCK COMPENSATION FOR FRACTIONAL-N PHASE LOCK LOOPS (PLLs) |
TWI520495B (en) * | 2013-06-06 | 2016-02-01 | 財團法人工業技術研究院 | Crystal-less clock generator and operation method thereof |
US9391624B1 (en) * | 2014-06-26 | 2016-07-12 | Marvell International Ltd. | Method and apparatus for avoiding dead zone effects in digital phase locked loops |
US9853807B2 (en) * | 2016-04-21 | 2017-12-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Automatic detection of change in PLL locking trend |
US10958278B2 (en) * | 2019-07-31 | 2021-03-23 | Intel Corporation | Techniques in phase-lock loop configuration in a computing device |
EP4064569A1 (en) * | 2021-03-23 | 2022-09-28 | Nxp B.V. | Type-i plls for phase-controlled applications |
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US6792282B1 (en) * | 2000-09-21 | 2004-09-14 | Skyworks Solutions, Inc. | Multiple step switched translation loop for power amplifier feedback control |
US20080116986A1 (en) * | 2006-11-17 | 2008-05-22 | Emmanouil Frantzeskakis | Method and System for Direct and Polar Modulation Using a Two Input PLL |
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FR2408243A1 (en) | 1977-11-04 | 1979-06-01 | Cit Alcatel | PHASE LOCKING LOOP |
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US7145399B2 (en) | 2002-06-19 | 2006-12-05 | Texas Instruments Incorporated | Type-II all-digital phase-locked loop (PLL) |
US7706495B2 (en) * | 2004-03-12 | 2010-04-27 | Panasonic Corporation | Two-point frequency modulation apparatus |
WO2006118056A1 (en) * | 2005-04-27 | 2006-11-09 | Matsushita Electric Industrial Co., Ltd. | Two-point modulation type phase modulating apparatus, polar modulation transmitting apparatus, radio transmitting apparatus, and wireless communication apparatus |
US7714669B2 (en) | 2008-06-16 | 2010-05-11 | Infineon Technologies Ag | Phase alignment circuit for a TDC in a DPLL |
-
2009
- 2009-06-12 US US12/483,708 patent/US8058917B2/en active Active
-
2010
- 2010-06-11 DE DE102010029977.4A patent/DE102010029977B4/en active Active
-
2011
- 2011-10-25 US US13/280,610 patent/US20120092048A1/en not_active Abandoned
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US6792282B1 (en) * | 2000-09-21 | 2004-09-14 | Skyworks Solutions, Inc. | Multiple step switched translation loop for power amplifier feedback control |
US20080116986A1 (en) * | 2006-11-17 | 2008-05-22 | Emmanouil Frantzeskakis | Method and System for Direct and Polar Modulation Using a Two Input PLL |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20120020390A1 (en) * | 2010-01-19 | 2012-01-26 | Panasonic Corporation | Angle modulator, transmission device, and wireless communication device |
US8576948B2 (en) * | 2010-01-19 | 2013-11-05 | Panasonic Corporation | Angle modulator, transmission device, and wireless communication device |
Also Published As
Publication number | Publication date |
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US8058917B2 (en) | 2011-11-15 |
DE102010029977A1 (en) | 2010-12-23 |
DE102010029977B4 (en) | 2019-05-09 |
US20100315140A1 (en) | 2010-12-16 |
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