US20120046929A1  Statistical Design with Importance Sampling Reuse  Google Patents
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 US20120046929A1 US20120046929A1 US12/859,871 US85987110A US2012046929A1 US 20120046929 A1 US20120046929 A1 US 20120046929A1 US 85987110 A US85987110 A US 85987110A US 2012046929 A1 US2012046929 A1 US 2012046929A1
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 G—PHYSICS
 G06—COMPUTING; CALCULATING OR COUNTING
 G06F—ELECTRIC DIGITAL DATA PROCESSING
 G06F11/00—Error detection; Error correction; Monitoring
 G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
 G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
 G06F11/0751—Error or fault detection not based on redundancy
 G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
 G06F11/076—Error or fault detection not based on redundancy by exceeding limits by exceeding a count or rate limit, e.g. word or bit count limit

 G—PHYSICS
 G06—COMPUTING; CALCULATING OR COUNTING
 G06F—ELECTRIC DIGITAL DATA PROCESSING
 G06F11/00—Error detection; Error correction; Monitoring
 G06F11/008—Reliability or availability analysis

 G—PHYSICS
 G06—COMPUTING; CALCULATING OR COUNTING
 G06F—ELECTRIC DIGITAL DATA PROCESSING
 G06F11/00—Error detection; Error correction; Monitoring
 G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
 G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
 G06F11/079—Root cause analysis, i.e. error or fault diagnosis

 G—PHYSICS
 G06—COMPUTING; CALCULATING OR COUNTING
 G06F—ELECTRIC DIGITAL DATA PROCESSING
 G06F30/00—Computeraided design [CAD]
 G06F30/30—Circuit design
 G06F30/32—Circuit design at the digital level
 G06F30/33—Design verification, e.g. functional simulation or model checking

 G—PHYSICS
 G06—COMPUTING; CALCULATING OR COUNTING
 G06F—ELECTRIC DIGITAL DATA PROCESSING
 G06F30/00—Computeraided design [CAD]
 G06F30/30—Circuit design
 G06F30/32—Circuit design at the digital level
 G06F30/33—Design verification, e.g. functional simulation or model checking
 G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation

 G—PHYSICS
 G06—COMPUTING; CALCULATING OR COUNTING
 G06F—ELECTRIC DIGITAL DATA PROCESSING
 G06F2111/00—Details relating to CAD techniques
 G06F2111/08—Probabilistic or stochastic CAD

 G—PHYSICS
 G06—COMPUTING; CALCULATING OR COUNTING
 G06F—ELECTRIC DIGITAL DATA PROCESSING
 G06F30/00—Computeraided design [CAD]
 G06F30/20—Design optimisation, verification or simulation
Definitions
 the present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for simulation based characterization of circuits using statistical design with importance sampling reuse.
 Sensitivity analysis is a wellknown technique in which the gradients of the various independent variables are used to determine the bounds of the nonfailure confidence region.
 accurate estimates of the failure rate are not typically produced by sensitivity analysis, as sensitivity analysis by its very nature cannot determine the exact overlapping impact of all independent variables on the cell failure rate at once.
 Another technique that can accurately estimate the failure rate is the grid analysis approach, in which the grid size can be made arbitrarily small.
 the number of simulations increases exponentially with the number of independent variables and typically a large amount of custom coded program control (scripting) must be employed to direct the analysis.
 a method, in a data processing system for determining failure rate of a device using importance sampling reuse.
 the method comprises performing, by the data processing system, a uniform sampling over a random sample space for a metric for the device with respect to an origin to form a set of samples.
 the set of samples comprises one or more failing samples.
 the method further comprises determining, by the data processing system, a center of gravity of the one or more failing samples with respect to the origin and determining, by the data processing system, importance samples based on the center of gravity of the one or more failing samples.
 the method further comprises selecting a new origin, recomputing, by the data processing system, new importance sampling weight ratios for the new origin, and determining, by the data processing system, a failure rate for the device based on the new importance sampling weight ratios for the new origin.
 a computer program product comprising a computer usable or readable medium having a computer readable program.
 the computer readable program when executed on a computing device, causes the computing device to perform various ones, and combinations of, the operations outlined above with regard to the method illustrative embodiment.
 a system/apparatus may comprise one or more processors and a memory coupled to the one or more processors.
 the memory may comprise instructions which, when executed by the one or more processors, cause the one or more processors to perform various ones, and combinations of, the operations outlined above with regard to the method illustrative embodiment.
 FIG. 1 is a schematic diagram of a memory cell within an array of memory cells that can be modeled in accordance with an illustrative embodiment
 FIGS. 2A2B and 3 A 3 B are graphs illustrating techniques employed in illustrative embodiments
 FIG. 4 is a flowchart illustrating operation of a centroidlocating technique in accordance with an illustrative embodiment
 FIG. 5 is a flowchart illustrating operation of a random direction vector technique in accordance with an illustrative embodiment
 FIG. 6 is a graph depicting global variability space in accordance with an illustrative embodiment
 FIGS. 7A and 7B are graphs illustrating global and local variation in two dimensions in accordance with an illustrative embodiment
 FIG. 8 illustrates how reusing the old set of samples for a new origin may underestimate fails in accordance with an illustrative embodiment
 FIGS. 9A and 9B illustrate alternative approaches to determining fails for a new origin in accordance with illustrative embodiments
 FIG. 10 illustrates an example application to importance sampling in accordance with an example embodiment
 FIG. 11 illustrates an example application for importance samples for multiple metrics in accordance with an example embodiment
 FIG. 12 is a graph illustrating importance sampling reuse for a set of process variations in accordance with an illustrative embodiment
 FIG. 13 illustrates an example application of importance sampling reuse for manufacturing variability in accordance with an example embodiment
 FIG. 14 is a graph illustrating the manufacturing variability space in accordance with an example embodiment
 FIG. 15 is a graph illustrating results for an example static random access memory in accordance with an illustrative embodiment
 FIG. 16 is a flowchart illustrating operation of a mechanism for statistical design with importance sampling reuse in accordance with an illustrative embodiment.
 FIG. 17 is a block diagram of an example data processing system in which aspects of the illustrative embodiments may be implemented.
 the illustrative embodiments provide a mechanism for reusing importance sampling for efficient cell failure rate estimation of process variations and other design considerations.
 the mechanism performs a search across circuit parameters to determine failures with respect to a set of performance variables.
 the initial search may be a uniform sampling of the parameter space.
 Mixture importance sampling (MIS) efficiently may estimate the single failure region.
 the mechanism finds a center of gravity for each metric/region and finds importance samples. Then, for each new origin corresponding to a process variation or other design consideration, the mechanism finds a suitable projection and recomputes new importance sampling (IS) ratios.
 IS new importance sampling
 Importance sampling is a general technique for estimating properties of a particular distribution, while only having samples generated from a different distribution rather than the distribution of interest.
 the term may refer to the process of sampling from this alternative distribution, the process of inference, or both.
 the idea behind importance sampling is that certain values of the input random variables in a simulation have more impact on the metric being estimated than others. If these “important” values are emphasized by sampling more frequently, then the estimator variance can be reduced.
 the basic methodology in importance sampling is to choose a distribution which encourages the important values. This use of biased distributions will result in a biased estimator if it is applied directly in the simulation. However, the simulation outputs are weighted to correct for the use of the biased distribution, and this ensures that the new importance sampling estimator is unbiased.
 the fundamental issue in implementing importance sampling simulation is the choice of the biased distribution which encourages the important regions of the input variables. Choosing or designing a good biased distribution is the art of importance sampling. The rewards for a good distribution can be huge runtime savings; the penalty for a bad distribution can be longer run times than for a general MonteCarlo simulation without importance sampling.
 the mechanism of the illustrative embodiments may first perform uniform sampling until a predetermined number of failing samples are encountered. Then, the mechanism may perform importance sampling simulation to determine a biased (distorted) distribution for performing a second sampling. The mechanism may then weight the results to determine failure rate or yield information. Finally, in accordance with an illustrative embodiment, the mechanism may reuse the samples from the biased distribution with respect to a new origin to determine the yield for the new origin. In an alternative embodiment, the mechanism may reuse the samples from the uniform sampling to determine a new biased distribution for the new origin and then weight the results to determine the yield for the new origin.
 the illustrative embodiments concern techniques for overcoming the limitations of traditional MonteCarlo analysis for circuits where the failure rate of the circuit being analyzed is very low. For instance, with respect to circuits having large arrays of identical cells, the cells are generally the determining factor in the failure rate, but only as a totality of the cells. Because millions of cells may be incorporated in a memory array, even very low failure rates contribute significantly to the failure rate of the individual memory devices or other devices that incorporate memory such arrays.
 the techniques used in the prior art either require exhaustive computation and storage, or do not perform well once there are more than a small number of variable design and process parameters, such as device areas or lengths and widths, doping densities, threshold voltages and other measures of design and process parameters.
 the illustrative embodiments provide a mechanism for using mixture importance sampling (MIS), which is a known technique, in a manner that effectively models memory cells.
 MIS mixture importance sampling
 MIS uses a mixture of two or more distributions for generating sample values, with at least one of the distributions biased to generate samples in a region of interest.
 the sample values are input vectors of design and processdependent electrical circuit parameters that determine the performance of the memory cell.
 the performance is measured in terms of operational performance values such as read and write delay time, writability (i.e., can the cell value be changed during a write) and read stability (i.e., will the cell hold its value during reads), as well as the margins associated with the read and write times, under the operational and circuit parametric conditions simulated.
 the illustrative embodiments provide a frontend mechanism to the MIS analysis that identifies and quantifies a particular region or regions of interest for further study via the MIS technique.
 the result is that the computational overhead and storage associated with the analysis is greatly reduced, while yielding the desired accuracy with respect to the failure mechanism(s) being studied.
 a priori information about the failure mechanisms to expect is useful. If it is known that a single dominant failure mode is present, such as in many static random access memory (SRAM) cell designs, then the identification of the region of interest is simplified. If it is known that multiple regions of interest having statistically significant impact will be present, then the analysis can proceed until all regions of interest are identified. If it is not known how many failure mechanisms will be of interest and/or significant within the probability space to be explored, then techniques must be employed that can handle either the singleregion or multiple region cases.
 SRAM static random access memory
 the MIS technique there are also two alternatives for applying the MIS technique. Either the regions of interest can be studied independently, or the sampling function for the MIS technique can include multiple sampling centers concentrated on the approximate centers of the multiple regions. The latter technique can be used to avoid error in failure rate prediction due to overlap of the regions of interest in one or more dimensions.
 Transistors P 10 , N 10 , P 11 , and N 11 form a crosscoupled static latch that provides the storage of a value in the cell.
 Transistors N 12 and N 13 provide for access to the value in response to a wordline select signal WL.
 Bitlines BLT (true bitline) and BLC (complement bitline) couple all cells in a column, so that when a row is selected by signal WL, only one row cell from each column is exposed to the memory logic.
 bitlines BLC and BLT are charged to voltages corresponding to the desired state of the memory cell and WL is activated (pulsed), setting the state of the latch formed by transistors P 10 , N 10 , P 11 and N 11 .
 the bitlines BLC and BLT are previously charged to opposite state predetermined voltages (generally V dd and ground), and to commence the read, WL is pulsed and a sense amplifier coupled to bitlines BLC and BLT determines the stored state by differential comparison of bitlines BLC and BLT.
 the cell will exhibit varying ability to perform to predetermined read/write cycle times and may be unstable in that the cell value does not remain constant after a write or when being read. As operating frequencies are increased and device sizes correspondingly decreased, the variations take on a statistically significantly greater range causing failure of an increasing number of devices in a lot.
 the illustrative embodiments are directed toward an efficient method for statistically analyzing the design of memory cells so that the yield of memory cells can be predicted accurately and further so that yields may be improved by selecting optimized nominal values for the device parameters and other environmental parameters such as operating voltages.
 While the illustrated cell is an example of a cell of order 4 that may be analyzed and improved by a method according to an embodiment of the invention, it should be understood that the techniques illustrated herein may be applied to memory cells of any order and design and to circuits other than memory circuits, as well.
 Order as used herein refers to the number of devices that implement the storage element of the cell exclusive of the bitline access transistors.
 a distribution 10 of operational performance values such as the abovementioned delay times and writability/read stability measures, generally following a Gaussian shape extends past 5 standard deviations (5 ⁇ ) on either side of a mean value.
 the input parameter values are generated by a similar Gaussian distribution of samples as generated around a nominal vector of cell parameter values by a MonteCarlo algorithm.
 Failure zone 12 A in the graph is located past the 5 ⁇ point and is shown as a shaded area.
 the yield of the cell modeled by distribution 10 can be predicted from the graph, and thus the yield of the overall device.
 the accuracy near failure zone 12 A is limited due to the relatively sparse distribution of samples in the tails of distribution 10 .
 the illustrative embodiments use MIS to concentrate sampling within one or more failure zones, so that more accurate estimates of yield are produced.
 a mixture 10 C of distributions 10 , 10 A, and 10 B is employed to improve the density of samples in zone 12 A, while ensuring that gaps are not left in the distribution that might otherwise miss other failures.
 the mixture sampling function distribution 10 C can be expressed by:
 ⁇ 1 and ⁇ 2 are coefficients used to control the mixture, which can be determined by the position of a new sampling function center ⁇ s 14 that is used to improve the concentration of samples around ⁇ s .
 ⁇ s is not the center of mixture sampling function distribution 10 C, but rather the center of gaussian distribution 10 A forming part of sampling function distribution 10 C.
 Uniform distribution U(x) 10 B is also included in the mixture, which helps in ensuring that some samples are present for all values within the interval over which uniform distribution 10 B extends.
 the choice of coefficients, in combination with the inclusion of the uniform distribution is made so that the number of samples in the region of interest is increased, but no “dead spots” are present in the analysis.
 the result of the mixture sampling function is to generate a relatively larger number of samples over zone 12 A (as compared to the distribution of FIG. 2A ), yielding a much more precise estimate of the impact of zone 12 A on.
 Results show a more than 10 ⁇ improvement (or greater, in proportion to the distance of zone 12 A from the nominal mean ⁇ ) in convergence time for estimates of the edges of failure zone 12 A, which results in a corresponding improvement in convergence of the calculation of overall device yield.
 FIG. 3A a first technique for locating sampling function center ⁇ s 14 , is depicted. Since memory cell operational performance variable failure regions generally will extend to the bounds of the analysis range (with respect to the parameter deviation) from the point at which the failures occur, failure regions can be ascribed to failure region boundaries beyond which the probability of failure only increases.
 the illustration is twodimensional but in actual practice, a larger number of dimensions are actually being evaluated simultaneously.
 a number of sample points are generated by uniformly sampling the variable memory cell parameter space, corresponding to the dots shown in the depicted example. Quasirandom sampling techniques can be used to improve the spread of the samples across the parameter space. In the depicted example, hollow dots depict nonfailing points and solid dots depict failing points.
 a threshold number of failures is accumulated, which may be qualified by observing their proximity in the parameter space if multiple failure regions might be present (in order to group the failures)
 a particular failure region of interest 20 B is identified and the vector centroid 14 of that region computed and used as new sampling function center ⁇ s 14 for subsequent MIS analysis.
 the vector centroid is computed from the vector distances of the points as the vector of average distance in each parameter space.
 the abovedescribed technique is especially applicable to the study of memory cell designs that have a single dominant failure region of interest. However, if it is not known in advance that there will be a single dominant region, the positions of the failure samples in parameter vector space can be observed and the samples grouped into one or more groups as mentioned above. If a group is much more distant from the nominal parameter vector, then that group may be discarded as being due to a relatively unimportant failure mechanism.
 the technique of the illustrative embodiments can be used to obtain better information about multiple failure mechanisms by the above grouping technique or discarding of groups.
 a threshold number of samples can then be collected for each group to be studied and either an independent set of MIS analyses can be conducted for each group, or the above MIS sampling distribution function can be modified to follow:
 ⁇ 1 , ⁇ 2 and ⁇ 3 are coefficients used to control the mixture and new sampling function centers ⁇ s1 , ⁇ s2 are used to improve the concentration of samples around two regions of interest. If more than two regions of interest are present, the above sampling function can be expanded to include other mean shifting values and their associated sampling function kernels in the above sampling function.
 FIG. 3B another technique adapted for treating circuits having multiple dominant failure regions is depicted, e.g., circuits for which multiple failure mechanisms have fairly equivalent statistical significance.
 the technique may also be used for single failure region analysis, as well.
 a vector of nominal memory cell parameter values 16 is used as a starting point for random generation of a sufficient initial number of vector directions 18 along which cell failure analysis proceeds until failure points are detected.
 a sufficient number of vectors is generated so that failure regions will not be missed by the analysis.
 Gaussian latin hypercube sampling can be used to ensure uniform placement of the vectors in all directions.
 the analysis then proceeds away from nominal vector 16 as illustrated.
 the generally monotonic behavior of the circuits as the parameters vary in one direction away from the nominal ensures that failing points will only be encountered at and beyond the boundaries of the failure regions 20 A, 20 B.
 the new sampling function center ⁇ s 14 for subsequent MIS analysis is determined either by the mean vector 14 B corresponding to the group of boundary points 22 , or an estimated vector 14 A is extrapolated within failure region of interest 20 B from the location of the boundary points.
 ⁇ s 14 is chosen as described above.
 regions of interest that are more distant from the nominal vector can be discarded as relatively unimportant failure mechanisms.
 the technique illustrated in FIG. 3B also provides better information about multiple failure mechanisms by locating the boundaries of the regions of interest. If the boundaries are not well defined after the above analysis has been attempted, then the entire process can be repeated with a larger set of initial random vectors.
 FIG. 4 is a flowchart illustrating operation of a centroidlocating technique in accordance with an illustrative embodiment.
 the flowchart of FIG. 4 corresponds to the centroidlocating technique described above with reference to FIG. 3A .
 a statistical analysis across ranges of memory circuit parameters is performed for multiple performance variables (block 30 ) and once a threshold number of failing samples is accumulated (possibly qualified as being in a single failure region if required) (block 32 ) the centroid of the parameters corresponding to the group of failures is determined (block 34 ).
 a new distribution of input parameter vectors is selected in conformity with the determined centroid and the nominal vector (block 36 ) and an MIS analysis is performed (block 38 ) using the new mixture distribution to gain more accurate results in the region of the failures and a faster convergence of the overall yield computation, and operation ends.
 FIG. 5 is a flowchart illustrating operation of a random vector technique in accordance with an illustrative embodiment.
 the flowchart of FIG. 5 corresponds to the random vector technique described above with reference to FIG. 3B .
 random vector directions are generated around the nominal value of the memory circuit parameters (block 50 ).
 the memory cell is simulated along the vectors until a failure is detected, corresponding to a failure region boundary (block 52 ).
 a mean point is computed from multiple failure region boundary points or a point is estimated within the failure region from the boundary points (block 54 ).
 An MIS distribution function is then selected (block 56 ) as a mixture of a distribution around the nominal parameter values and the mean point computed in block 54 (along with the uniform distribution), and an MIS analysis is performed (block 58 ) using the new mixture distribution to gain more accurate results in the region of the failures and a faster convergence of the overall yield computation, and operation ends.
 Variability is a key problem in circuit design. Statistical analysis and simulations are needed to analyze design yield. For this, importance sampling was developed as a fast statistical analysis tool versus regular MonteCarlo analysis. Often, circuit designers face situations where they revisit a circuit design with multiple design considerations. For example, design centering, optimization, and manufacturing variability require a lot of whatif statistical analysis studies.
 a mechanism is provided to minimize function evaluations (simulations) and to reuse importance samples. For different global variation corners, the mechanism may infer yield information from samples obtained around the old origin.
 FIG. 6 is a graph depicting global variability space in accordance with an illustrative embodiment.
 the disk represents the global variability space defined by the following:
 the mechanism of the illustrative embodiments may find importance samples for origin 602 and may recomputed new importance sample ratios for new origins 604 , which are “corners” on the boundary of the global variability space.
 FIGS. 7A and 7B are graphs illustrating global and local variation in two dimensions in accordance with an illustrative embodiment. More particularly, FIG. 7A illustrates failure direction with respect to the origin by regular sampling. FIG. 7B illustrates the operation of using the old set of samples with respect to a new origin. As seen in FIG. 7B , simply reusing the old set of samples may result in underestimating fails.
 FIG. 8 illustrates how reusing the old set of samples for a new origin may underestimate fails in accordance with an illustrative embodiment.
 the distance of the new origin to the failing samples e.g., the center of gravity (COG)
 COG center of gravity
 FIGS. 9A and 9B illustrate alternative approaches to determining fails for a new origin in accordance with illustrative embodiments.
 one approach is to project the new origin onto the line from the origin to the COG. This approach maintains failing samples close to the projected new origin.
 another approach is to move the population of samples, along the orthogonal direction to the line from the origin to the COG. This approach approximates the dominant fail direction in the proximity of the old origin via the COG of fails.
 the approach of FIG. 9B provides a fixed pattern of fails without enforcing or modeling using a fixed boundary. This approach is particularly reasonable when the new origin is not too far from the origin.
 FIG. 10 illustrates an example application to importance sampling in accordance with an example embodiment.
 area 1002 shows the real importance samples with respect to the origin.
 Area 1004 shows the shifted importance samples with respect to the new origin.
 FIG. 11 illustrates an example application for importance samples for multiple metrics in accordance with an example embodiment. In the example shown in FIG. 11 , each metric is identified by a dominant center of gravity of fails.
 the mechanism reevaluates importance sampling with respect to the new projected origin.
 the importance sampling weight function of x with respect to the origin is defined as follows:
 x is process variation variable of the device
 x COG is the center of gravity of the one or more failing samples
 ⁇ is the standard deviation of x.
 x is process variation variable of the device
 x np is a new point of the projected origin for the process variation variable x
 x COG is the center of gravity of the one or more failing samples
 ⁇ is the standard deviation of x
 the equations assume that the process variation variables are Gaussian. In case of nongaussian variables, transformation are used to normalize the process variations via cumulative distribution functions mapping tables, or more complex weight functions can be adopted. Most importantly if the probability density function is f(x), then the shifted weights are proportional to f(x ⁇ x np )/f(x ⁇ x cog ).
 the equations above also assume that the standard deviation, ⁇ , of the process variation variables remain the same. In case there is a change in ⁇ associated with origin of process variation change, then the weights are modified accordingly.
 x is process variation variable of the device
 x np is a new point of the projected origin for the process variation variable x
 x COG is the center of gravity of the one or more failing samples
 ⁇ is the standard deviation of x
 ⁇ np is the standard deviation associated with the new point of origin.
 FIG. 12 is a graph illustrating importance sampling reuse for a set of process variations in accordance with an illustrative embodiment.
 the mechanism of the illustrative embodiments may perform MIS analysis at an origin and predict yield at different corners 1202 with no additional simulations.
 the mechanism of the illustrative embodiments may be applied reuse importance sampling to determine yield given manufacturing variability.
 the mechanism may estimate yield at various corners.
 Designers currently study multiple corner combinations using conventional methods. For example, designers may maintain a table of a hundred or more v dd /v cc points for which yield is being computed.
 the mechanism of the illustrative embodiments allow designers to more easily and accurately estimate yield gradients and sensitivity to manufacturing variability space and to even estimate weighted equivalent yield within the manufacturing variability space at each of these points with minimum computation/simulation effort.
 FIG. 13 illustrates an example application of importance sampling reuse for manufacturing variability in accordance with an example embodiment.
 the mechanism may perform importance sampling reuse for various corners 1302 within the manufacturing variability space.
 the standard deviation within the manufacturing variability space ( ⁇ mv ) may be much less than the standard deviation for random dopant fluctuation ( ⁇ RDF ).
 the small standard deviation helps in terms of better accuracy.
 the corners 1302 may be defined by v t changes in twodimensional or threedimensional space. Importance sampling may be performed in sixdimensional space.
 FIG. 14 is a graph illustrating the manufacturing variability space in accordance with an example embodiment.
 the mechanism of the illustrative embodiment may estimate yield for each corner with no additional simulations.
 the mechanism may reuse samples from “nominal” corner analysis rather than one origin.
 the example shown in FIG. 14 assumes threedimensional importance sampling and twodimensional global variability space.
 the mechanism of the illustrative embodiments may be applied to design centering.
 the mechanism may determine yield as v t centers of design are moved around. This may enable identifying optimal design centers.
 the mechanism of the illustrative embodiments may be part of an adaptive search scheme (or hybrid), which is good to guide gradient, to provide initial solution, etc. True sampling could be performed to certify the yield determined using the importance sampling reuse.
 the mechanism of the illustrative embodiments may be used to determine yield for negative biased temperature instability (NBTI) or positive biased temperature instability (PBTI).
 NBTI negative biased temperature instability
 PBTI positive biased temperature instability
 FIG. 15 is a graph illustrating results for an example static random access memory in accordance with an illustrative embodiment. As can be seen, the writability and stability for importance sampling reuse are a good approximation for the true estimate. The estimated bounds are large enough for manufacturing variability.
 aspects of the present invention may be embodied as a system, method, or computer program product. Accordingly, aspects of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, microcode, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system.” Furthermore, aspects of the present invention may take the form of a computer program product embodied in any one or more computer readable medium(s) having computer usable program code embodied thereon.
 the computer readable medium may be a computer readable signal medium or a computer readable storage medium.
 a computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, device, or any suitable combination of the foregoing.
 a computer readable storage medium may be any tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device.
 a computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in a baseband or as part of a carrier wave. Such a propagated signal may take any of a variety of forms, including, but not limited to, electromagnetic, optical, or any suitable combination thereof.
 a computer readable signal medium may be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
 Computer code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, radio frequency (RF), etc., or any suitable combination thereof.
 any appropriate medium including but not limited to wireless, wireline, optical fiber cable, radio frequency (RF), etc., or any suitable combination thereof.
 Computer program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as JavaTM, SmalltalkTM, C++, or the like, and conventional procedural programming languages, such as the “C” programming language or similar programming languages.
 the program code may execute entirely on the user's computer, partly on the user's computer, as a standalone software package, partly on the user's computer and partly on a remote computer, or entirely on the remote computer or server.
 the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider).
 LAN local area network
 WAN wide area network
 Internet Service Provider for example, AT&T, MCI, Sprint, EarthLinkTM, MSN, GTE, etc.
 These computer program instructions may also be stored in a computer readable medium that can direct a computer, other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the computer readable medium produce an article of manufacture including instructions that implement the function/act specified in the flowchart and/or block diagram block or blocks.
 the computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.
 FIG. 16 is a flowchart illustrating operation of a mechanism for statistical design with importance sampling reuse in accordance with an illustrative embodiment. Operation begins, and the mechanism performs uniform sampling (block 1602 ). The mechanism finds a center of gravity (COG) for each metric (block 1604 ). Then, the mechanism finds importance samples (block 1606 ). For each new origin, the mechanism finds a suitable projection (bock 1608 ) and recomputes new importance sampling ratios (block 1610 ). Thereafter, operation ends.
 COG center of gravity
 the mechanism may project a new center of gravity with respect to the new origin.
 the mechanism may perform a second stage of importance sampling given the same uniform sampling from block 1602 .
 each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s).
 the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved.
 FIG. 17 is provided hereafter as an example environment in which aspects of the illustrative embodiments may be implemented. While the description of FIG. 17 will focus primarily on a single data processing device implementation, this is only an example and is not intended to state or imply any limitation with regard to the features of the present invention. To the contrary, the illustrative embodiments are intended to include distributed data processing environments and embodiments.
 FIG. 17 is a block diagram of an example data processing system in which aspects of the illustrative embodiments may be implemented.
 Data processing system 1700 is an example of a computer in which computer usable code or instructions implementing the processes for illustrative embodiments of the present invention may be located.
 data processing system 1700 employs a hub architecture including north bridge and memory controller hub (NB/MCH) 1702 and south bridge and input/output (I/O) controller hub (SB/ICH) 1704 .
 NB/MCH north bridge and memory controller hub
 I/O input/output controller hub
 Processing unit 1706 , main memory 1708 , and graphics processor 1710 are connected to NB/MCH 1702 .
 Graphics processor 1710 may be connected to NB/MCH 1702 through an accelerated graphics port (AGP).
 AGP accelerated graphics port
 local area network (LAN) adapter 1712 connects to SB/ICH 1704 .
 Audio adapter 1716 , keyboard and mouse adapter 1720 , modem 1722 , read only memory (ROM) 1724 , hard disk drive (HDD) 1726 , CDROM drive 1730 , universal serial bus (USB) ports and other communication ports 1732 , and PCI/PCIe devices 1734 connect to SB/ICH 1704 through bus 1738 and bus 1740 .
 PCI/PCIe devices may include, for example, Ethernet adapters, addin cards, and PC cards for notebook computers. PCI uses a card bus controller, while PCIe does not.
 ROM 1724 may be, for example, a flash basic input/output system (BIOS).
 BIOS basic input/output system
 HDD 1726 and CDROM drive 1730 connect to SB/ICH 1704 through bus 1740 .
 HDD 1726 and CDROM drive 1730 may use, for example, an integrated drive electronics (IDE) or serial advanced technology attachment (SATA) interface.
 IDE integrated drive electronics
 SATA serial advanced technology attachment
 Super I/O (SIO) device 1736 may be connected to SB/ICH 1704 .
 An operating system runs on processing unit 1706 .
 the operating system coordinates and provides control of various components within the data processing system 1700 in FIG. 17 .
 the operating system may be a commercially available operating system such as Microsoft® Windows® XP (Microsoft and Windows are trademarks of Microsoft Corporation in the United States, other countries, or both).
 An objectoriented programming system such as the JavaTM programming system, may run in conjunction with the operating system and provides calls to the operating system from JavaTM programs or applications executing on data processing system 1700 (Java is a trademark of Sun Microsystems, Inc. in the United States, other countries, or both).
 data processing system 1700 may be, for example, an IBM® eServerTM System p® computer system, running the Advanced Interactive Executive (AIX®) operating system or the LINUX® operating system (eServer, System p, and AIX are trademarks of International Business Machines Corporation in the United States, other countries, or both while LINUX is a trademark of Linus Torvalds in the United States, other countries, or both).
 Data processing system 1700 may be a symmetric multiprocessor (SMP) system including a plurality of processors in processing unit 1706 . Alternatively, a single processor system may be employed.
 SMP symmetric multiprocessor
 Instructions for the operating system, the objectoriented programming system, and applications or programs are located on storage devices, such as HDD 1726 , and may be loaded into main memory 1708 for execution by processing unit 1706 .
 the processes for illustrative embodiments of the present invention may be performed by processing unit 1706 using computer usable program code, which may be located in a memory such as, for example, main memory 1708 , ROM 1724 , or in one or more peripheral devices 1726 and 1730 , for example.
 a bus system such as bus 1738 or bus 1740 as shown in FIG. 17 , may be comprised of one or more buses.
 the bus system may be implemented using any type of communication fabric or architecture that provides for a transfer of data between different components or devices attached to the fabric or architecture.
 a communication unit such as modem 1722 or network adapter 1712 of FIG. 17 , may include one or more devices used to transmit and receive data.
 a memory may be, for example, main memory 1708 , ROM 1724 , or a cache such as found in NB/MCH 1702 in FIG. 17 .
 FIG. 17 may vary depending on the implementation.
 Other internal hardware or peripheral devices such as flash memory, equivalent nonvolatile memory, or optical disk drives and the like, may be used in addition to or in place of the hardware depicted in FIG. 17 .
 the processes of the illustrative embodiments may be applied to a multiprocessor data processing system, other than the SMP system mentioned previously, without departing from the spirit and scope of the present invention.
 data processing system 1700 may take the form of any of a number of different data processing systems including client computing devices, server computing devices, a tablet computer, laptop computer, telephone or other communication device, a personal digital assistant (PDA), or the like.
 data processing system 1700 may be a portable computing device which is configured with flash memory to provide nonvolatile memory for storing operating system files and/or usergenerated data, for example.
 data processing system 1700 may be any known or later developed data processing system without architectural limitation.
 the illustrative embodiments provide a mechanism for reusing importance sampling for efficient cell failure rate estimation of process variations and other design considerations.
 the mechanism performs a search across circuit parameters to determine failures with respect to a set of performance variables.
 the initial search may be a uniform sampling of the parameter space.
 Mixture importance sampling (MIS) efficiently may estimate the single failure region.
 the mechanism finds a center of gravity for each metric and finds importance samples.
 the mechanism finds a suitable projection and recomputes new importance sampling (IS) ratios.
 the illustrative embodiments may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment containing both hardware and software elements.
 the mechanisms of the illustrative embodiments are implemented in software or program code, which includes but is not limited to firmware, resident software, microcode, etc.
 a data processing system suitable for storing and/or executing program code will include at least one processor coupled directly or indirectly to memory elements through a system bus.
 the memory elements can include local memory employed during actual execution of the program code, bulk storage, and cache memories which provide temporary storage of at least some program code in order to reduce the number of times code must be retrieved from bulk storage during execution.
 I/O devices can be coupled to the system either directly or through intervening I/O controllers.
 Network adapters may also be coupled to the system to enable the data processing system to become coupled to other data processing systems or remote printers or storage devices through intervening private or public networks. Modems, cable modems and Ethernet cards are just a few of the currently available types of network adapters.
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Abstract
A mechanism is provided for reusing importance sampling for efficient cell failure rate estimation of process variations and other design considerations. First, the mechanism performs a search across circuit parameters to determine failures with respect to a set of performance variables. For a single failure region, the initial search may be a uniform sampling of the parameter space. Mixture importance sampling (MIS) efficiently may estimate the single failure region. The mechanism then finds a center of gravity for each metric and finds importance samples. Then, for each new origin corresponding to a process variation or other design consideration, the mechanism finds a suitable projection and recomputes new importance sampling (IS) ratios.
Description
 The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for simulation based characterization of circuits using statistical design with importance sampling reuse.
 As memory array architectures are pushed to their practical limits by increasing requirements for density and speed, accurately estimating the cell failure rate of a design becomes increasingly critical. Since a finite number of redundant rows and/or columns is available to replace those containing defective cells, a number of failed cells above this level of redundancy will yield a defective device. The number of defective devices, or device yield is then directly related to the cell failure rate. The larger arrays being fabricated today have increasingly stringent failure rate control requirements. For example, in order to achieve a yield of 90% in a onemillion cell array without redundancy, a failure rate below five standard deviations (5σ) must be held.
 Traditional techniques such as MonteCarlo analysis produce accurate results at a cost of a large number of iterations, due to the random sampling of the entire probability space of the independent variables that are treated in the analysis. As the cell failure rate decreases, the number of samples and iterations required for accurate analysis becomes increasingly large, because of the relatively sparse distribution of samples in the distribution tail(s) that correspond to failed cells. The effect of circuit changes on cell readability and writability, as well as minimum read and write cycle times and margins, are difficult to estimate at very low failure rate levels. Such low failure rates cause further complications for adjusting designs to achieve the best result.
 Techniques other than MonteCarlo analysis have been implemented for estimating cell failure rates, each with related drawbacks. Sensitivity analysis is a wellknown technique in which the gradients of the various independent variables are used to determine the bounds of the nonfailure confidence region. However, accurate estimates of the failure rate are not typically produced by sensitivity analysis, as sensitivity analysis by its very nature cannot determine the exact overlapping impact of all independent variables on the cell failure rate at once. Another technique that can accurately estimate the failure rate is the grid analysis approach, in which the grid size can be made arbitrarily small. However, the number of simulations increases exponentially with the number of independent variables and typically a large amount of custom coded program control (scripting) must be employed to direct the analysis.
 In one illustrative embodiment, a method, in a data processing system, is provided for determining failure rate of a device using importance sampling reuse. The method comprises performing, by the data processing system, a uniform sampling over a random sample space for a metric for the device with respect to an origin to form a set of samples. The set of samples comprises one or more failing samples. The method further comprises determining, by the data processing system, a center of gravity of the one or more failing samples with respect to the origin and determining, by the data processing system, importance samples based on the center of gravity of the one or more failing samples. The method further comprises selecting a new origin, recomputing, by the data processing system, new importance sampling weight ratios for the new origin, and determining, by the data processing system, a failure rate for the device based on the new importance sampling weight ratios for the new origin.
 In other illustrative embodiments, a computer program product comprising a computer usable or readable medium having a computer readable program is provided. The computer readable program, when executed on a computing device, causes the computing device to perform various ones, and combinations of, the operations outlined above with regard to the method illustrative embodiment.
 In yet another illustrative embodiment, a system/apparatus is provided. The system/apparatus may comprise one or more processors and a memory coupled to the one or more processors. The memory may comprise instructions which, when executed by the one or more processors, cause the one or more processors to perform various ones, and combinations of, the operations outlined above with regard to the method illustrative embodiment.
 These and other features and advantages of the present invention will be described in, or will become apparent to those of ordinary skill in the art in view of, the following detailed description of the example embodiments of the present invention.
 The invention, as well as a preferred mode of use and further objectives and advantages thereof, will best be understood by reference to the following detailed description of illustrative embodiments when read in conjunction with the accompanying drawings, wherein:

FIG. 1 is a schematic diagram of a memory cell within an array of memory cells that can be modeled in accordance with an illustrative embodiment; 
FIGS. 2A2B and 3A3B are graphs illustrating techniques employed in illustrative embodiments; 
FIG. 4 is a flowchart illustrating operation of a centroidlocating technique in accordance with an illustrative embodiment; 
FIG. 5 is a flowchart illustrating operation of a random direction vector technique in accordance with an illustrative embodiment; 
FIG. 6 is a graph depicting global variability space in accordance with an illustrative embodiment; 
FIGS. 7A and 7B are graphs illustrating global and local variation in two dimensions in accordance with an illustrative embodiment; 
FIG. 8 illustrates how reusing the old set of samples for a new origin may underestimate fails in accordance with an illustrative embodiment; 
FIGS. 9A and 9B illustrate alternative approaches to determining fails for a new origin in accordance with illustrative embodiments; 
FIG. 10 illustrates an example application to importance sampling in accordance with an example embodiment; 
FIG. 11 illustrates an example application for importance samples for multiple metrics in accordance with an example embodiment; 
FIG. 12 is a graph illustrating importance sampling reuse for a set of process variations in accordance with an illustrative embodiment; 
FIG. 13 illustrates an example application of importance sampling reuse for manufacturing variability in accordance with an example embodiment; 
FIG. 14 is a graph illustrating the manufacturing variability space in accordance with an example embodiment; 
FIG. 15 is a graph illustrating results for an example static random access memory in accordance with an illustrative embodiment; 
FIG. 16 is a flowchart illustrating operation of a mechanism for statistical design with importance sampling reuse in accordance with an illustrative embodiment; and 
FIG. 17 is a block diagram of an example data processing system in which aspects of the illustrative embodiments may be implemented.  The illustrative embodiments provide a mechanism for reusing importance sampling for efficient cell failure rate estimation of process variations and other design considerations. First, the mechanism performs a search across circuit parameters to determine failures with respect to a set of performance variables. For a single failure region, the initial search may be a uniform sampling of the parameter space. Mixture importance sampling (MIS) efficiently may estimate the single failure region. The mechanism then finds a center of gravity for each metric/region and finds importance samples. Then, for each new origin corresponding to a process variation or other design consideration, the mechanism finds a suitable projection and recomputes new importance sampling (IS) ratios.
 Importance sampling is a general technique for estimating properties of a particular distribution, while only having samples generated from a different distribution rather than the distribution of interest. Depending on the application, the term may refer to the process of sampling from this alternative distribution, the process of inference, or both. The idea behind importance sampling is that certain values of the input random variables in a simulation have more impact on the metric being estimated than others. If these “important” values are emphasized by sampling more frequently, then the estimator variance can be reduced. Hence, the basic methodology in importance sampling is to choose a distribution which encourages the important values. This use of biased distributions will result in a biased estimator if it is applied directly in the simulation. However, the simulation outputs are weighted to correct for the use of the biased distribution, and this ensures that the new importance sampling estimator is unbiased.
 The fundamental issue in implementing importance sampling simulation is the choice of the biased distribution which encourages the important regions of the input variables. Choosing or designing a good biased distribution is the art of importance sampling. The rewards for a good distribution can be huge runtime savings; the penalty for a bad distribution can be longer run times than for a general MonteCarlo simulation without importance sampling.
 More particularly, the mechanism of the illustrative embodiments may first perform uniform sampling until a predetermined number of failing samples are encountered. Then, the mechanism may perform importance sampling simulation to determine a biased (distorted) distribution for performing a second sampling. The mechanism may then weight the results to determine failure rate or yield information. Finally, in accordance with an illustrative embodiment, the mechanism may reuse the samples from the biased distribution with respect to a new origin to determine the yield for the new origin. In an alternative embodiment, the mechanism may reuse the samples from the uniform sampling to determine a new biased distribution for the new origin and then weight the results to determine the yield for the new origin.
 Thus, the illustrative embodiments concern techniques for overcoming the limitations of traditional MonteCarlo analysis for circuits where the failure rate of the circuit being analyzed is very low. For instance, with respect to circuits having large arrays of identical cells, the cells are generally the determining factor in the failure rate, but only as a totality of the cells. Because millions of cells may be incorporated in a memory array, even very low failure rates contribute significantly to the failure rate of the individual memory devices or other devices that incorporate memory such arrays.
 It is necessary to analyze the cell design and process variations at the extreme end of the distribution of actual cell parameters in order to gain meaningful information that can accurately predict device yields and permit improvement of the cells in order to improve device yields. The techniques used in the prior art either require exhaustive computation and storage, or do not perform well once there are more than a small number of variable design and process parameters, such as device areas or lengths and widths, doping densities, threshold voltages and other measures of design and process parameters. The illustrative embodiments provide a mechanism for using mixture importance sampling (MIS), which is a known technique, in a manner that effectively models memory cells.
 MIS uses a mixture of two or more distributions for generating sample values, with at least one of the distributions biased to generate samples in a region of interest. In the illustrative embodiments the sample values are input vectors of design and processdependent electrical circuit parameters that determine the performance of the memory cell. The performance is measured in terms of operational performance values such as read and write delay time, writability (i.e., can the cell value be changed during a write) and read stability (i.e., will the cell hold its value during reads), as well as the margins associated with the read and write times, under the operational and circuit parametric conditions simulated. Because a priori knowledge about what regions in Nspace might be of interest is not generally easily obtained (where N is the number of variable parameters), the illustrative embodiments provide a frontend mechanism to the MIS analysis that identifies and quantifies a particular region or regions of interest for further study via the MIS technique. The result is that the computational overhead and storage associated with the analysis is greatly reduced, while yielding the desired accuracy with respect to the failure mechanism(s) being studied.
 In order to locate a region of interest that provides information about a particular failure mechanism, a priori information about the failure mechanisms to expect is useful. If it is known that a single dominant failure mode is present, such as in many static random access memory (SRAM) cell designs, then the identification of the region of interest is simplified. If it is known that multiple regions of interest having statistically significant impact will be present, then the analysis can proceed until all regions of interest are identified. If it is not known how many failure mechanisms will be of interest and/or significant within the probability space to be explored, then techniques must be employed that can handle either the singleregion or multiple region cases.
 In the multiple region case, there are also two alternatives for applying the MIS technique. Either the regions of interest can be studied independently, or the sampling function for the MIS technique can include multiple sampling centers concentrated on the approximate centers of the multiple regions. The latter technique can be used to avoid error in failure rate prediction due to overlap of the regions of interest in one or more dimensions.
 With reference now to the figures, and in particular with reference to
FIG. 1 , an example memory cell that can be modeled by a method in accordance with an illustrative embodiment is shown in an array that includesother cells 5. Transistors P10, N10, P11, and N11 form a crosscoupled static latch that provides the storage of a value in the cell. Transistors N12 and N13 provide for access to the value in response to a wordline select signal WL. Bitlines BLT (true bitline) and BLC (complement bitline) couple all cells in a column, so that when a row is selected by signal WL, only one row cell from each column is exposed to the memory logic. For a write operation, bitlines BLC and BLT are charged to voltages corresponding to the desired state of the memory cell and WL is activated (pulsed), setting the state of the latch formed by transistors P10, N10, P11 and N11. For a read operation, the bitlines BLC and BLT are previously charged to opposite state predetermined voltages (generally V_{dd }and ground), and to commence the read, WL is pulsed and a sense amplifier coupled to bitlines BLC and BLT determines the stored state by differential comparison of bitlines BLC and BLT. Depending on the relative strengths of the transistors P1011 and N1013, the cell will exhibit varying ability to perform to predetermined read/write cycle times and may be unstable in that the cell value does not remain constant after a write or when being read. As operating frequencies are increased and device sizes correspondingly decreased, the variations take on a statistically significantly greater range causing failure of an increasing number of devices in a lot. The illustrative embodiments are directed toward an efficient method for statistically analyzing the design of memory cells so that the yield of memory cells can be predicted accurately and further so that yields may be improved by selecting optimized nominal values for the device parameters and other environmental parameters such as operating voltages.  While the illustrated cell is an example of a cell of
order 4 that may be analyzed and improved by a method according to an embodiment of the invention, it should be understood that the techniques illustrated herein may be applied to memory cells of any order and design and to circuits other than memory circuits, as well. (Order as used herein refers to the number of devices that implement the storage element of the cell exclusive of the bitline access transistors.)  Referring now to
FIG. 2A , a graph illustrating the purpose and techniques of the illustrative embodiments is shown. Adistribution 10 of operational performance values, such as the abovementioned delay times and writability/read stability measures, generally following a Gaussian shape extends past 5 standard deviations (5σ) on either side of a mean value. The input parameter values are generated by a similar Gaussian distribution of samples as generated around a nominal vector of cell parameter values by a MonteCarlo algorithm. 
Failure zone 12A in the graph is located past the 5σ point and is shown as a shaded area. The yield of the cell modeled bydistribution 10 can be predicted from the graph, and thus the yield of the overall device. However, the accuracy nearfailure zone 12A is limited due to the relatively sparse distribution of samples in the tails ofdistribution 10. The illustrative embodiments use MIS to concentrate sampling within one or more failure zones, so that more accurate estimates of yield are produced.  Referring now to
FIG. 2B , a graph showing the operation of the illustrative embodiments is shown. Once a region of interest is identified in the device and processdependent parameter space, amixture 10C ofdistributions zone 12A, while ensuring that gaps are not left in the distribution that might otherwise miss other failures. The mixturesampling function distribution 10C can be expressed by: 
g _{λ}(x)=λ_{1} p(x)+λ_{2} U(x)+(1−λ_{1}−λ_{2})p(x−μ_{s}),  where λ_{1 }and λ_{2 }are coefficients used to control the mixture, which can be determined by the position of a new sampling function center μ_{s } 14 that is used to improve the concentration of samples around μ_{s}. Note that μ_{s }is not the center of mixture
sampling function distribution 10C, but rather the center ofgaussian distribution 10A forming part ofsampling function distribution 10C. Uniform distribution U(x) 10B is also included in the mixture, which helps in ensuring that some samples are present for all values within the interval over whichuniform distribution 10B extends. The choice of coefficients, in combination with the inclusion of the uniform distribution is made so that the number of samples in the region of interest is increased, but no “dead spots” are present in the analysis.  The result of the mixture sampling function is to generate a relatively larger number of samples over
zone 12A (as compared to the distribution ofFIG. 2A ), yielding a much more precise estimate of the impact ofzone 12A on. Results show a more than 10× improvement (or greater, in proportion to the distance ofzone 12A from the nominal mean μ) in convergence time for estimates of the edges offailure zone 12A, which results in a corresponding improvement in convergence of the calculation of overall device yield.  While generally the statistical analysis detailed above will be conducted independently over the operational performance variables being studied, it is possible to conduct a combined pass/fail analysis over the parameter space in which no information about the particular operational performance variables associated with each failed point is retained, but the overall desirability of a particular design can be directly observed with respect to process variations. MIS analysis can then be conducted with one or more meanshifting distributions included to precisely predict the yield.
 Referring now to
FIG. 3A , a first technique for locating sampling function center μ_{s } 14, is depicted. Since memory cell operational performance variable failure regions generally will extend to the bounds of the analysis range (with respect to the parameter deviation) from the point at which the failures occur, failure regions can be ascribed to failure region boundaries beyond which the probability of failure only increases. The illustration is twodimensional but in actual practice, a larger number of dimensions are actually being evaluated simultaneously. A number of sample points are generated by uniformly sampling the variable memory cell parameter space, corresponding to the dots shown in the depicted example. Quasirandom sampling techniques can be used to improve the spread of the samples across the parameter space. In the depicted example, hollow dots depict nonfailing points and solid dots depict failing points. After a threshold number of failures is accumulated, which may be qualified by observing their proximity in the parameter space if multiple failure regions might be present (in order to group the failures), a particular failure region ofinterest 20B is identified and thevector centroid 14 of that region computed and used as new sampling function center μ_{s } 14 for subsequent MIS analysis. The vector centroid is computed from the vector distances of the points as the vector of average distance in each parameter space. There may be multiple failure regions for some applications of the techniques of the illustrative embodiments including other failure regions such as 20A, and those regions can be ignored if not of interest, or may be further evaluated with independent MIS analysis around their centers.  The abovedescribed technique is especially applicable to the study of memory cell designs that have a single dominant failure region of interest. However, if it is not known in advance that there will be a single dominant region, the positions of the failure samples in parameter vector space can be observed and the samples grouped into one or more groups as mentioned above. If a group is much more distant from the nominal parameter vector, then that group may be discarded as being due to a relatively unimportant failure mechanism. The technique of the illustrative embodiments can be used to obtain better information about multiple failure mechanisms by the above grouping technique or discarding of groups.
 A threshold number of samples can then be collected for each group to be studied and either an independent set of MIS analyses can be conducted for each group, or the above MIS sampling distribution function can be modified to follow:

g _{λ}(x)=λ_{1} p(x)+λ_{2} U(x)+λ_{3} p(x−μ _{s1})+(1−λ_{1}−λ_{2}−λ_{3})p(x−μ_{s2}),  where λ_{1}, λ_{2 }and λ_{3 }are coefficients used to control the mixture and new sampling function centers μ_{s1}, μ_{s2 }are used to improve the concentration of samples around two regions of interest. If more than two regions of interest are present, the above sampling function can be expanded to include other mean shifting values and their associated sampling function kernels in the above sampling function.
 Referring now to
FIG. 3B , another technique adapted for treating circuits having multiple dominant failure regions is depicted, e.g., circuits for which multiple failure mechanisms have fairly equivalent statistical significance. The technique may also be used for single failure region analysis, as well. A vector of nominal memory cell parameter values 16 is used as a starting point for random generation of a sufficient initial number ofvector directions 18 along which cell failure analysis proceeds until failure points are detected. A sufficient number of vectors is generated so that failure regions will not be missed by the analysis. Gaussian latin hypercube sampling can be used to ensure uniform placement of the vectors in all directions.  The analysis then proceeds away from
nominal vector 16 as illustrated. The generally monotonic behavior of the circuits as the parameters vary in one direction away from the nominal ensures that failing points will only be encountered at and beyond the boundaries of thefailure regions mean vector 14B corresponding to the group of boundary points 22, or an estimatedvector 14A is extrapolated within failure region ofinterest 20B from the location of the boundary points. After a first iteration, if the boundaries offailure regions boundaries μ_{ } _{s } 14 is chosen as described above. As in the center of gravity technique, regions of interest that are more distant from the nominal vector can be discarded as relatively unimportant failure mechanisms. The technique illustrated inFIG. 3B also provides better information about multiple failure mechanisms by locating the boundaries of the regions of interest. If the boundaries are not well defined after the above analysis has been attempted, then the entire process can be repeated with a larger set of initial random vectors. 
FIG. 4 is a flowchart illustrating operation of a centroidlocating technique in accordance with an illustrative embodiment. The flowchart ofFIG. 4 corresponds to the centroidlocating technique described above with reference toFIG. 3A . First, a statistical analysis across ranges of memory circuit parameters is performed for multiple performance variables (block 30) and once a threshold number of failing samples is accumulated (possibly qualified as being in a single failure region if required) (block 32) the centroid of the parameters corresponding to the group of failures is determined (block 34). Finally, a new distribution of input parameter vectors is selected in conformity with the determined centroid and the nominal vector (block 36) and an MIS analysis is performed (block 38) using the new mixture distribution to gain more accurate results in the region of the failures and a faster convergence of the overall yield computation, and operation ends. 
FIG. 5 is a flowchart illustrating operation of a random vector technique in accordance with an illustrative embodiment. The flowchart ofFIG. 5 corresponds to the random vector technique described above with reference toFIG. 3B . First, random vector directions are generated around the nominal value of the memory circuit parameters (block 50). The memory cell is simulated along the vectors until a failure is detected, corresponding to a failure region boundary (block 52). Then, a mean point is computed from multiple failure region boundary points or a point is estimated within the failure region from the boundary points (block 54). An MIS distribution function is then selected (block 56) as a mixture of a distribution around the nominal parameter values and the mean point computed in block 54 (along with the uniform distribution), and an MIS analysis is performed (block 58) using the new mixture distribution to gain more accurate results in the region of the failures and a faster convergence of the overall yield computation, and operation ends.  Variability is a key problem in circuit design. Statistical analysis and simulations are needed to analyze design yield. For this, importance sampling was developed as a fast statistical analysis tool versus regular MonteCarlo analysis. Often, circuit designers face situations where they revisit a circuit design with multiple design considerations. For example, design centering, optimization, and manufacturing variability require a lot of whatif statistical analysis studies.
 For the design centering and manufacturing variability space, often global variation space is a subset of the random sample space. In accordance with an illustrative embodiment, a mechanism is provided to minimize function evaluations (simulations) and to reuse importance samples. For different global variation corners, the mechanism may infer yield information from samples obtained around the old origin.

FIG. 6 is a graph depicting global variability space in accordance with an illustrative embodiment. The disk represents the global variability space defined by the following: 
x=−z,  where x, y, and z are random variables. The mechanism of the illustrative embodiments may find importance samples for
origin 602 and may recomputed new importance sample ratios fornew origins 604, which are “corners” on the boundary of the global variability space. 
FIGS. 7A and 7B are graphs illustrating global and local variation in two dimensions in accordance with an illustrative embodiment. More particularly,FIG. 7A illustrates failure direction with respect to the origin by regular sampling.FIG. 7B illustrates the operation of using the old set of samples with respect to a new origin. As seen inFIG. 7B , simply reusing the old set of samples may result in underestimating fails. 
FIG. 8 illustrates how reusing the old set of samples for a new origin may underestimate fails in accordance with an illustrative embodiment. The distance of the new origin to the failing samples (e.g., the center of gravity (COG)) can underestimate the fails, because the distance along theCOG direction 802 is greater than thedistance 804 of the new origin to the failing samples along the same direction of the origin to the COG. 
FIGS. 9A and 9B illustrate alternative approaches to determining fails for a new origin in accordance with illustrative embodiments. As shown inFIG. 9A , one approach is to project the new origin onto the line from the origin to the COG. This approach maintains failing samples close to the projected new origin. As shown inFIG. 9B , another approach is to move the population of samples, along the orthogonal direction to the line from the origin to the COG. This approach approximates the dominant fail direction in the proximity of the old origin via the COG of fails. The approach ofFIG. 9B provides a fixed pattern of fails without enforcing or modeling using a fixed boundary. This approach is particularly reasonable when the new origin is not too far from the origin. 
FIG. 10 illustrates an example application to importance sampling in accordance with an example embodiment. In the depicted example,area 1002 shows the real importance samples with respect to the origin.Area 1004 shows the shifted importance samples with respect to the new origin.FIG. 11 illustrates an example application for importance samples for multiple metrics in accordance with an example embodiment. In the example shown inFIG. 11 , each metric is identified by a dominant center of gravity of fails.  In accordance with the illustrative embodiments, the mechanism reevaluates importance sampling with respect to the new projected origin. The importance sampling weight function of x with respect to the origin is defined as follows:

$w\ue8a0\left(x\right)=\mathrm{\Pi exp}\ue8a0\left(0.5*{\left(\frac{x0}{\sigma}\right)}^{2}\right)/\mathrm{exp}\ue8a0\left(0.5*{\left(\frac{x{x}_{\mathrm{COG}}}{\sigma}\right)}^{2}\right)$  where x is process variation variable of the device, x_{COG }is the center of gravity of the one or more failing samples, and σ is the standard deviation of x. The importance sampling weight function of x with respect to the new projected origin (np) is defined as follows:

$w\ue8a0\left(x\right)=\mathrm{\Pi exp}\ue8a0\left(0.5*{\left(\frac{x{x}_{\mathrm{np}}}{\sigma}\right)}^{2}\right)/\mathrm{exp}\ue8a0\left(0.5*{\left(\frac{x{x}_{\mathrm{COG}}}{\sigma}\right)}^{2}\right)$  where x is process variation variable of the device, x_{np }is a new point of the projected origin for the process variation variable x, x_{COG }is the center of gravity of the one or more failing samples, and σ is the standard deviation of x; the equations assume that the process variation variables are Gaussian. In case of nongaussian variables, transformation are used to normalize the process variations via cumulative distribution functions mapping tables, or more complex weight functions can be adopted. Most importantly if the probability density function is f(x), then the shifted weights are proportional to f(x−x_{np})/f(x−x_{cog}). The equations above also assume that the standard deviation, σ, of the process variation variables remain the same. In case there is a change in σ associated with origin of process variation change, then the weights are modified accordingly.

$w\ue8a0\left(x\right)=\Pi \ue89e\frac{\sigma}{{\sigma}_{\mathrm{np}}}\ue89e\mathrm{exp}\ue8a0\left(0.5\ue89e{\left(\frac{x{x}_{\mathrm{np}}}{{\sigma}_{\mathrm{np}}}\right)}^{2}\right)/\mathrm{exp}\ue8a0\left(0.5\ue89e{\left(\frac{x{x}_{\mathrm{COG}}}{\sigma}\right)}^{2}\right)$  where x is process variation variable of the device, x_{np }is a new point of the projected origin for the process variation variable x, x_{COG }is the center of gravity of the one or more failing samples, σ is the standard deviation of x, and σ_{np }is the standard deviation associated with the new point of origin.

FIG. 12 is a graph illustrating importance sampling reuse for a set of process variations in accordance with an illustrative embodiment. In the example shown inFIG. 12 , there are three variables, in this instance for a pass gate (pg), a pullup transistor (pu), and a pulldown transistor (pd). The mechanism of the illustrative embodiments may perform MIS analysis at an origin and predict yield atdifferent corners 1202 with no additional simulations.  Thus, the mechanism of the illustrative embodiments may be applied reuse importance sampling to determine yield given manufacturing variability. The mechanism may estimate yield at various corners. Designers currently study multiple corner combinations using conventional methods. For example, designers may maintain a table of a hundred or more v_{dd}/v_{cc }points for which yield is being computed. The mechanism of the illustrative embodiments allow designers to more easily and accurately estimate yield gradients and sensitivity to manufacturing variability space and to even estimate weighted equivalent yield within the manufacturing variability space at each of these points with minimum computation/simulation effort.

FIG. 13 illustrates an example application of importance sampling reuse for manufacturing variability in accordance with an example embodiment. The mechanism may perform importance sampling reuse forvarious corners 1302 within the manufacturing variability space. The standard deviation within the manufacturing variability space (σ_{mv}) may be much less than the standard deviation for random dopant fluctuation (σ_{RDF}). The small standard deviation helps in terms of better accuracy. Thecorners 1302 may be defined by v_{t }changes in twodimensional or threedimensional space. Importance sampling may be performed in sixdimensional space. 
FIG. 14 is a graph illustrating the manufacturing variability space in accordance with an example embodiment. The mechanism of the illustrative embodiment may estimate yield for each corner with no additional simulations. The mechanism may reuse samples from “nominal” corner analysis rather than one origin. The example shown inFIG. 14 assumes threedimensional importance sampling and twodimensional global variability space.  The mechanism of the illustrative embodiments may be applied to design centering. The mechanism may determine yield as v_{t }centers of design are moved around. This may enable identifying optimal design centers. For instance, the mechanism of the illustrative embodiments may be part of an adaptive search scheme (or hybrid), which is good to guide gradient, to provide initial solution, etc. True sampling could be performed to certify the yield determined using the importance sampling reuse. In another example embodiment, the mechanism of the illustrative embodiments may be used to determine yield for negative biased temperature instability (NBTI) or positive biased temperature instability (PBTI).

FIG. 15 is a graph illustrating results for an example static random access memory in accordance with an illustrative embodiment. As can be seen, the writability and stability for importance sampling reuse are a good approximation for the true estimate. The estimated bounds are large enough for manufacturing variability.  As will be appreciated by one skilled in the art, the present invention may be embodied as a system, method, or computer program product. Accordingly, aspects of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, microcode, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system.” Furthermore, aspects of the present invention may take the form of a computer program product embodied in any one or more computer readable medium(s) having computer usable program code embodied thereon.
 Any combination of one or more computer readable medium(s) may be utilized. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, device, or any suitable combination of the foregoing. More specific examples (a nonexhaustive list) of the computer readable medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a readonly memory (ROM), an erasable programmable readonly memory (EPROM or Flash memory), an optical fiber, a portable compact disc readonly memory (CDROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device.
 A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in a baseband or as part of a carrier wave. Such a propagated signal may take any of a variety of forms, including, but not limited to, electromagnetic, optical, or any suitable combination thereof. A computer readable signal medium may be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
 Computer code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, radio frequency (RF), etc., or any suitable combination thereof.
 Computer program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java™, Smalltalk™, C++, or the like, and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a standalone software package, partly on the user's computer and partly on a remote computer, or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider).
 Aspects of the present invention are described below with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to the illustrative embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.
 These computer program instructions may also be stored in a computer readable medium that can direct a computer, other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the computer readable medium produce an article of manufacture including instructions that implement the function/act specified in the flowchart and/or block diagram block or blocks.
 The computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

FIG. 16 is a flowchart illustrating operation of a mechanism for statistical design with importance sampling reuse in accordance with an illustrative embodiment. Operation begins, and the mechanism performs uniform sampling (block 1602). The mechanism finds a center of gravity (COG) for each metric (block 1604). Then, the mechanism finds importance samples (block 1606). For each new origin, the mechanism finds a suitable projection (bock 1608) and recomputes new importance sampling ratios (block 1610). Thereafter, operation ends.  In an alternative embodiment, in
block 1610, the mechanism may project a new center of gravity with respect to the new origin. In another embodiment, the mechanism may perform a second stage of importance sampling given the same uniform sampling fromblock 1602.  The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardwarebased systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
 The illustrative embodiments may be utilized in many different types of data processing environments including a distributed data processing environment, a single data processing device, or the like. In order to provide a context for the description of the specific elements and functionality of the illustrative embodiments,
FIG. 17 is provided hereafter as an example environment in which aspects of the illustrative embodiments may be implemented. While the description ofFIG. 17 will focus primarily on a single data processing device implementation, this is only an example and is not intended to state or imply any limitation with regard to the features of the present invention. To the contrary, the illustrative embodiments are intended to include distributed data processing environments and embodiments. 
FIG. 17 is a block diagram of an example data processing system in which aspects of the illustrative embodiments may be implemented.Data processing system 1700 is an example of a computer in which computer usable code or instructions implementing the processes for illustrative embodiments of the present invention may be located.  In the depicted example,
data processing system 1700 employs a hub architecture including north bridge and memory controller hub (NB/MCH) 1702 and south bridge and input/output (I/O) controller hub (SB/ICH) 1704.Processing unit 1706,main memory 1708, andgraphics processor 1710 are connected to NB/MCH 1702.Graphics processor 1710 may be connected to NB/MCH 1702 through an accelerated graphics port (AGP).  In the depicted example, local area network (LAN)
adapter 1712 connects to SB/ICH 1704.Audio adapter 1716, keyboard andmouse adapter 1720,modem 1722, read only memory (ROM) 1724, hard disk drive (HDD) 1726, CDROM drive 1730, universal serial bus (USB) ports andother communication ports 1732, and PCI/PCIe devices 1734 connect to SB/ICH 1704 throughbus 1738 andbus 1740. PCI/PCIe devices may include, for example, Ethernet adapters, addin cards, and PC cards for notebook computers. PCI uses a card bus controller, while PCIe does not.ROM 1724 may be, for example, a flash basic input/output system (BIOS). 
HDD 1726 and CDROM drive 1730 connect to SB/ICH 1704 throughbus 1740.HDD 1726 and CDROM drive 1730 may use, for example, an integrated drive electronics (IDE) or serial advanced technology attachment (SATA) interface. Super I/O (SIO)device 1736 may be connected to SB/ICH 1704.  An operating system runs on
processing unit 1706. The operating system coordinates and provides control of various components within thedata processing system 1700 inFIG. 17 . As a client, the operating system may be a commercially available operating system such as Microsoft® Windows® XP (Microsoft and Windows are trademarks of Microsoft Corporation in the United States, other countries, or both). An objectoriented programming system, such as the Java™ programming system, may run in conjunction with the operating system and provides calls to the operating system from Java™ programs or applications executing on data processing system 1700 (Java is a trademark of Sun Microsystems, Inc. in the United States, other countries, or both).  As a server,
data processing system 1700 may be, for example, an IBM® eServer™ System p® computer system, running the Advanced Interactive Executive (AIX®) operating system or the LINUX® operating system (eServer, System p, and AIX are trademarks of International Business Machines Corporation in the United States, other countries, or both while LINUX is a trademark of Linus Torvalds in the United States, other countries, or both).Data processing system 1700 may be a symmetric multiprocessor (SMP) system including a plurality of processors inprocessing unit 1706. Alternatively, a single processor system may be employed.  Instructions for the operating system, the objectoriented programming system, and applications or programs are located on storage devices, such as
HDD 1726, and may be loaded intomain memory 1708 for execution byprocessing unit 1706. The processes for illustrative embodiments of the present invention may be performed byprocessing unit 1706 using computer usable program code, which may be located in a memory such as, for example,main memory 1708,ROM 1724, or in one or moreperipheral devices  A bus system, such as
bus 1738 orbus 1740 as shown inFIG. 17 , may be comprised of one or more buses. Of course, the bus system may be implemented using any type of communication fabric or architecture that provides for a transfer of data between different components or devices attached to the fabric or architecture. A communication unit, such asmodem 1722 ornetwork adapter 1712 ofFIG. 17 , may include one or more devices used to transmit and receive data. A memory may be, for example,main memory 1708,ROM 1724, or a cache such as found in NB/MCH 1702 inFIG. 17 .  Those of ordinary skill in the art will appreciate that the hardware in
FIG. 17 may vary depending on the implementation. Other internal hardware or peripheral devices, such as flash memory, equivalent nonvolatile memory, or optical disk drives and the like, may be used in addition to or in place of the hardware depicted inFIG. 17 . Also, the processes of the illustrative embodiments may be applied to a multiprocessor data processing system, other than the SMP system mentioned previously, without departing from the spirit and scope of the present invention.  Moreover, the
data processing system 1700 may take the form of any of a number of different data processing systems including client computing devices, server computing devices, a tablet computer, laptop computer, telephone or other communication device, a personal digital assistant (PDA), or the like. In some illustrative examples,data processing system 1700 may be a portable computing device which is configured with flash memory to provide nonvolatile memory for storing operating system files and/or usergenerated data, for example. Essentially,data processing system 1700 may be any known or later developed data processing system without architectural limitation.  Thus, the illustrative embodiments provide a mechanism for reusing importance sampling for efficient cell failure rate estimation of process variations and other design considerations. First, the mechanism performs a search across circuit parameters to determine failures with respect to a set of performance variables. For a single failure region, the initial search may be a uniform sampling of the parameter space. Mixture importance sampling (MIS) efficiently may estimate the single failure region. The mechanism then finds a center of gravity for each metric and finds importance samples. Then, for each new origin corresponding to a process variation or other design consideration, the mechanism finds a suitable projection and recomputes new importance sampling (IS) ratios.
 As noted above, it should be appreciated that the illustrative embodiments may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment containing both hardware and software elements. In one example embodiment, the mechanisms of the illustrative embodiments are implemented in software or program code, which includes but is not limited to firmware, resident software, microcode, etc.
 A data processing system suitable for storing and/or executing program code will include at least one processor coupled directly or indirectly to memory elements through a system bus. The memory elements can include local memory employed during actual execution of the program code, bulk storage, and cache memories which provide temporary storage of at least some program code in order to reduce the number of times code must be retrieved from bulk storage during execution.
 Input/output or I/O devices (including but not limited to keyboards, displays, pointing devices, etc.) can be coupled to the system either directly or through intervening I/O controllers. Network adapters may also be coupled to the system to enable the data processing system to become coupled to other data processing systems or remote printers or storage devices through intervening private or public networks. Modems, cable modems and Ethernet cards are just a few of the currently available types of network adapters.
 The description of the present invention has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiment was chosen and described in order to best explain the principles of the invention, the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.
Claims (25)
1. A method, in a data processing system, for determining failure rate of a device using importance sampling reuse, the method comprising:
performing, by the data processing system, a uniform sampling over a random sample space for a metric for the device with respect to an origin to form a set of samples, wherein the set of samples comprises one or more failing samples;
determining, by the data processing system, a center of gravity of the one or more failing samples with respect to the origin;
determining, by the data processing system, importance samples based on the center of gravity of the one or more failing samples;
selecting a new origin; recomputing, by the data processing system, new importance sampling weight ratios for the new origin; and
determining, by the data processing system, a failure rate for the device based on the new importance sampling weight ratios for the new origin.
2. The method of claim 1 , wherein recomputing new importance sampling weight ratios for the new origin comprises:
finding a projected origin; and
recomputing new importance sampling weight ratios with respect to the projected origin.
3. The method of claim 2 , wherein finding the projected origin comprises:
determining a line passing through the origin and the center of gravity of the one or more failing samples; and
projecting the new origin onto the line passing through the origin and the center of gravity of the one or more failing samples.
4. The method of claim 1 , wherein recomputing new importance sampling weight ratios for the new origin comprises:
finding a set of projected samples with respect to the new origin; and
recomputing new importance sampling ratios based on the projected samples.
5. The method of claim 4 , wherein finding the set of projected samples comprises:
determining a line passing through the origin and the center of gravity of the one or more failing samples; and
move the set of samples in a direction orthogonal to the line passing through the origin and the center of gravity of the one or more failing samples.
6. The method of claim 1 , wherein recomputing new importance sampling weight ratios for the new origin comprises computing a weight function, wherein the weight function is as follows:
where x is process variation variable of the device, x_{np }is a new point of a projected origin for the process variation variable x, x_{COG }is the center of gravity of the one or more failing samples, σ is the standard deviation of x, and σ_{np }is the standard deviation associated with the new point of projected origin.
7. The method of claim 1 , further comprising:
repeating selecting a new origin, recomputing new importance sampling weight ratios for the new origin, and determining a failure rate for the device based on the new importance sampling weight ratios for the new origin for a set of process variations.
8. The method of claim 1 , wherein recomputing new importance sampling weight ratios for the new origin comprises:
determining importance samples based on the center of gravity of the one or more failing samples and the new origin.
9. A computer program product comprising a computer readable storage medium having a computer readable program stored therein, wherein the computer readable program, when executed on a computing device, causes the computing device to:
perform a uniform sampling over a random sample space for a metric for the device with respect to an origin to form a set of samples, wherein the set of samples comprises one or more failing samples;
determine a center of gravity of the one or more failing samples with respect to the origin;
determine importance samples based on the center of gravity of the one or more failing samples;
recompute new importance sampling weight ratios for a selected new origin; and
determine a failure rate for the device based on the new importance sampling weight ratios for the new origin.
10. The computer program product of claim 9 , wherein recomputing new importance sampling weight ratios for the new origin comprises:
finding a projected origin; and
recomputing new importance sampling weight ratios with respect to the projected origin.
11. The computer program product of claim 10 , wherein finding the projected origin comprises:
determining a line passing through the origin and the center of gravity of the one or more failing samples; and
projecting the new origin onto the line passing though the origin and the center of gravity of the one or more failing samples.
12. The computer program product of claim 9 , wherein recomputing new importance sampling weight ratios for the new origin comprises:
finding a set of projected samples with respect to the new origin; and
recomputing new importance sampling ratios based on the projected samples.
13. The computer program product of claim 12 , wherein finding the set of projected samples comprises:
determining a line passing through the origin and the center of gravity of the one or more failing samples; and
move the set of samples in a direction orthogonal to the line passing through the origin and the center of gravity of the one or more failing samples.
14. The computer program product of claim 9 , wherein recomputing new importance sampling weight ratios for the new origin comprises computing a weight function, wherein the weight function is as follows:
where x is process variation variable of the device, x_{np }is a new point of a projected origin for the process variation variable x, x_{COG }is the center of gravity of the one or more failing samples, σ is the standard deviation of x, and σ_{np }is the standard deviation associated with the new point of projected origin.
15. The computer program product of claim 9 , wherein the computer readable program further causes the computing device to:
repeat selecting a new origin, recomputing new importance sampling weight ratios for the new origin, and determining a failure rate for the device based on the new importance sampling weight ratios for the new origin for a set of process variations.
16. The computer program product of claim 9 , wherein recomputing new importance sampling weight ratios for the new origin comprises:
determining importance samples based on the center of gravity of the one or more failing samples and the new origin.
17. The computer program product of claim 9 , wherein the computer readable program is stored in a computer readable storage medium in a data processing system and wherein the computer readable program was downloaded over a network from a remote data processing system.
18. The computer program product of claim 9 , wherein the computer readable program is stored in a computer readable storage medium in a server data processing system and wherein the computer readable program is downloaded over a network to a remote data processing system for use in a computer readable storage medium with the remote system.
19. An apparatus, comprising:
a processor; and
a memory coupled to the processor, wherein the memory comprises instructions which, when executed by the processor, cause the processor to:
perform a uniform sampling over a random sample space for a metric for the device with respect to an origin to form a set of samples, wherein the set of samples comprises one or more failing samples;
determine a center of gravity of the one or more failing samples with respect to the origin;
determine importance samples based on the center of gravity of the one or more failing samples;
recompute new importance sampling weight ratios for a selected new origin; and
determine a failure rate for the device based on the new importance sampling weight ratios for the new origin.
20. The apparatus of claim 19 , wherein recomputing new importance sampling weight ratios for the new origin comprises:
finding a projected origin; and
recomputing new importance sampling weight ratios with respect to the projected origin.
21. The apparatus of claim 20 , wherein finding the projected origin comprises:
determining a line passing through the origin and the center of gravity of the one or more failing samples; and
projecting the new origin onto the line passing through the origin and the center of gravity of the one or more failing samples.
22. The apparatus of claim 19 , wherein recomputing new importance sampling weight ratios for the new origin comprises:
finding a set of projected samples with respect to the new origin; and
recomputing new importance sampling ratios based on the projected samples.
23. The apparatus of claim 22 , wherein finding the set of projected samples comprises:
determining a line passing through the origin and the center of gravity of the one or more failing samples; and
move the set of samples in a direction orthogonal to the line passing through the origin and the center of gravity of the one or more failing samples.
24. The apparatus of claim 19 , wherein recomputing new importance sampling weight ratios for the new origin comprises computing a weight function, wherein the weight function is as follows:
where x is process variation variable of the device, x_{np }is a new point of a projected origin for the process variation variable x, x_{COG }is the center of gravity of the one or more failing samples, σ is the standard deviation of x, and σ_{np }is the standard deviation associated with the new point of projected origin.
25. The apparatus of claim 19 , wherein the instructions further cause the processor to:
repeat selecting a new origin, recomputing new importance sampling weight ratios for the new origin, and determining a failure rate for the device based on the new importance sampling weight ratios for the new origin for a set of process variations.
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US20120116850A1 (en) *  20101110  20120510  International Business Machines Corporation  Causal modeling of multidimensional hierachical metric cubes 
US20140215274A1 (en) *  20100820  20140731  International Business Machines Corporation  Statistical Design with Importance Sampling Reuse 
US8806418B1 (en)  20130619  20140812  Freescale Semiconductor, Inc.  Scaled sigma sampling 
US20140278309A1 (en) *  20130315  20140918  International Business Machines Corporation  Selective importance sampling 
KR20140139343A (en) *  20130527  20141205  삼성전자주식회사  Simulation system and method thereof, computing system comprising the simulation system 
WO2014204577A1 (en) *  20130621  20141224  California Institute Of Technology  Determination of electronic circuit robustness 
US20160063156A1 (en) *  20140826  20160303  International Business Machines Corporation  Multidimension variable predictive modeling for yield analysis acceleration 
CN105701293A (en) *  20160113  20160622  北京航空航天大学  Method for generating multistage task system fault physical simulation sections of avionic devices 
CN108427798A (en) *  20170812  20180821  中民筑友科技投资有限公司  A kind of entrucking sequence based on BIM building elements determines method and device 
CN108694273A (en) *  20170412  20181023  三星电子株式会社  Circuit yield analysis method and system for assessing rare failure event 
CN109347691A (en) *  20180801  20190215  温州大学苍南研究院  A kind of data sampling method, device and equipment for Web service 
US10325056B1 (en) *  20160610  20190618  Cadence Design Systems, Inc.  Failure boundary classification and corner creation for scaledsigma sampling 
US10452793B2 (en)  20140826  20191022  International Business Machines Corporation  Multidimension variable predictive modeling for analysis acceleration 
US10776996B2 (en)  20140806  20200915  Samsung Electronics Co., Ltd.  Method and apparatus for processing image 
US10853550B1 (en) *  20180703  20201201  Cadence Design Systems, Inc.  Sampling selection for enhanced high yield estimation in circuit designs 
US10891415B1 (en)  20190605  20210112  Cadence Design Systems, Inc.  Method, system, and product for generating radial bump patterns 
US11327825B2 (en) *  20170111  20220510  International Business Machines Corporation  Predictive analytics for failure detection 
Families Citing this family (5)
Publication number  Priority date  Publication date  Assignee  Title 

US20160116527A1 (en) *  20141027  20160428  Qualcomm Incorporated  Stochastic and topologically aware electromigration analysis methodology 
US20210124853A1 (en) *  20160405  20210429  Hewlett Packard Enterprise Development Lp  Simulation based on precomputed results of the simulation 
CN109918284A (en) *  20181213  20190621  江苏大学  A kind of method and system constructing software failure region mode 
EP3938942A1 (en)  20190314  20220119  Xenergic AB  Highdimensional multidistributed importance sampling for circuit yield analysis 
US11774498B2 (en)  20210607  20231003  International Business Machines Corporation  Multirate sampling for hierarchical system analysis 
Citations (38)
Publication number  Priority date  Publication date  Assignee  Title 

US20020035462A1 (en) *  20000724  20020321  Makoto Kidera  Method of and device for simulation 
US20030004679A1 (en) *  20010108  20030102  Tryon Robert G.  Method and apparatus for predicting failure in a system 
US20030061152A1 (en) *  20010926  20030327  De Rabi S.  System and method for determining ValueatRisk using FORM/SORM 
US20040199444A1 (en) *  20030123  20041007  Joel Woodcock  Method of characterizing financial benefits based upon input operational parameters having uncertainties 
US20050273308A1 (en) *  20040607  20051208  Houston Theodore W  Statistical evaluation of circuit robustness separating local and global variation 
US7016825B1 (en) *  20001026  20060321  Vextec Corporation  Method and apparatus for predicting the failure of a component 
US20060142988A1 (en) *  20041228  20060629  Satoru Akiyama  Design methodology and manufacturing method for semiconductor memory 
US20060150129A1 (en) *  20041210  20060706  Anova Solutions, Inc.  Stochastic analysis process optimization for integrated circuit design and manufacture 
US7096140B2 (en) *  20031030  20060822  Kabushiki Kaisha Toshiba  Test system, test method and test program for an integrated circuit by IDDQ testing 
US20060229856A1 (en) *  20050411  20061012  Nicolas Burrus  Systems, devices, and methods for diffusion tractography 
US20070097763A1 (en) *  20031110  20070503  Renesas Technology Corp.  Manufacturing method of semiconductor integrated circuit device 
US7272808B1 (en) *  20050608  20070918  Advanced Micro Devices, Inc.  Onchip variability impact simulation and analysis for circuit performance 
US20070220455A1 (en) *  20060314  20070920  Joshi Rajiv V  Method and computer program for efficient cell failure rate estimation in cell arrays 
US20080015827A1 (en) *  20060124  20080117  Tryon Robert G Iii  Materialsbased failure analysis in design of electronic devices, and prediction of operating life 
US20080059143A1 (en) *  20051212  20080306  HsienYen Chiu  Hierarchical stochastic analysis process optimization for integrated circuit design and manufacture 
US20080140363A1 (en) *  20061212  20080612  ChungKai Lin  Unified Model for process variations in integrated circuits 
US20080141190A1 (en) *  20061206  20080612  Qualcomm Incorporated  Process Variation Tolerant Memory Design 
US20090070716A1 (en) *  20070912  20090312  Joshi Rajiv V  System and method for optimization and predication of variability and yield in integrated ciruits 
US7508697B1 (en) *  20070509  20090324  Purdue Research Foundation  Selfrepairing technique in nanoscale SRAM to reduce parametric failures 
US20090182536A1 (en) *  20030714  20090716  Morris Joel M  System and method for estimating probabilities of events 
US20090248387A1 (en) *  20080328  20091001  Carnegie Mellon University  Method and apparatus for sampling and predicting rare events in complex electronic devices, circuits and systems 
US20100010744A1 (en) *  20080711  20100114  Schlumberger Technology Corporation  Monte carlo method for laplace inversion of nmr data 
US20100153086A1 (en) *  20081211  20100617  Jedat Inc.  System for creating parameter information, system for estimating yields, program and recording medium 
US7827018B2 (en) *  20071116  20101102  International Business Machines Corporation  Method and computer program for selecting circuit repairs using redundant elements with consideration of aging effects 
US20110054856A1 (en) *  20090901  20110303  International Business Machines Corporation  Equivalent Device Statistical Modeling for Bitline Leakage Modeling 
US7920995B2 (en) *  20050629  20110405  Siemens Aktiengesellschaft  Probabilistic design tool for optimizing a technical system 
US20110153271A1 (en) *  20091223  20110623  Cadence Design Systems, Inc.  Methods and systems for high sigma yield estimation 
US20110153272A1 (en) *  20091223  20110623  Cadence Design Systems, Inc.  Methods and systems for high sigma yield estimation using reduced dimensionality 
US8010325B2 (en) *  20080425  20110830  Microsoft Corporation  Failure simulation and availability report on same 
US20110307438A1 (en) *  20100614  20111215  Fern E Acu A Ee Ndez Mart E Acu I Ee Nez Juan Luis  Highdimensional data analysis 
US20110313747A1 (en) *  20100622  20111222  International Business Machines Corporation  Technology ComputerAided Design (TCAD)Based Virtual Fabrication 
US20120150500A1 (en) *  20101208  20120614  Fujitsu Limited  Optimization processing method and apparatus 
US8214190B2 (en) *  20090413  20120703  International Business Machines Corporation  Methodology for correlated memory fail estimations 
US8275596B2 (en) *  20061208  20120925  Globalfoundries Inc.  Method for robust statistical semiconductor device modeling 
US8285522B1 (en) *  20060124  20121009  Vextec Corporation  Materialsbased failure analysis in design of electronic devices 
US20120317656A1 (en) *  20110405  20121213  International Business Machines Corporation  Twoparty private estimation of dataset similarity 
US20130159947A1 (en) *  20111216  20130620  International Business Machines Corporation  Guiding design actions for complex failure modes 
US20130226544A1 (en) *  20101027  20130829  Solido Design Automation Inc.  Method and system for identifying rareevent failure rates 
Family Cites Families (26)
Publication number  Priority date  Publication date  Assignee  Title 

US5943661A (en) *  19910711  19990824  Texas Instruments Incorporated  Hybrid neural network classifier, systems and methods 
US5235506A (en) *  19910830  19930810  The United States Of America As Represented By The Secretary Of The Navy  Process which aids to the laying out of locations of a limited number of 100, personnel and equipments in functional organization 
US7050936B2 (en) *  20010906  20060523  Comverse, Ltd.  Failure prediction apparatus and method 
US7747624B2 (en) *  20020510  20100629  Oracle International Corporation  Data summarization 
US6999599B2 (en) *  20020607  20060214  Microsoft Corporation  System and method for modebased multihypothesis tracking using parametric contours 
US7474999B2 (en) *  20021223  20090106  Cadence Design Systems, Inc.  Method for accounting for process variation in the design of integrated circuits 
US20070166847A1 (en) *  20060117  20070719  Honeywell International Inc.  Boxes for Soft Error Rate Calculation 
US8050901B2 (en) *  20060914  20111101  Taiwan Semiconductor Manufacturing Company, Ltd.  Prediction and control of NBTI of integrated circuits 
US7571420B2 (en) *  20070216  20090804  Intel Corporation  Dynamic sampling with efficient model for overlay 
WO2009076600A2 (en)  20071212  20090618  New York University  System, method and computeraccessible medium for normalizing databases through mixing 
CA2652710A1 (en) *  20080205  20090805  Solido Design Automation Inc.  Pruningbased variationaware design 
US20090248368A1 (en) *  20080326  20091001  Livermore Software Technology Corporation  Systems and methods of constructing Radial Basis Function (RBF) based metamodels used in engineering design optimization 
US8443329B2 (en) *  20080516  20130514  Solido Design Automation Inc.  Trustworthy structural synthesis and expert knowledge extraction with application to analog circuit design 
US7996719B2 (en) *  20081024  20110809  Microsoft Corporation  Expressing fault correlation constraints 
EP2234026A1 (en) *  20090325  20100929  Imec  Method and system for analyzing performance metrics of array type circuits under process variability 
US8365118B2 (en) *  20090603  20130129  International Business Machines Corporation  Brokenspheres methodology for improved failure probability analysis in multifail regions 
US20120046929A1 (en) *  20100820  20120223  International Business Machines Corporation  Statistical Design with Importance Sampling Reuse 
US20120313747A1 (en)  20110609  20121213  Pawlik Thomas D  Method for authenticating security markers 
WO2013069138A1 (en) *  20111110  20130516  株式会社日立製作所  Operation information prediction computer, operation information prediction method and program 
US8832497B2 (en) *  20120207  20140909  A.L.D. Advanced Logistics Development Ltd  Methods, apparatus and systems for performing dynamic fault tree analysis 
KR102061763B1 (en) *  20130527  20200103  삼성전자 주식회사  Simulation system and method thereof, computing system comprising the simulation system 
US8806418B1 (en) *  20130619  20140812  Freescale Semiconductor, Inc.  Scaled sigma sampling 
US10387596B2 (en) *  20140826  20190820  International Business Machines Corporation  Multidimension variable predictive modeling for yield analysis acceleration 
US10139446B2 (en) *  20150828  20181127  International Business Machines Corporation  Massive multidimensionality failure analytics with smart converged bounds 
US10853550B1 (en) *  20180703  20201201  Cadence Design Systems, Inc.  Sampling selection for enhanced high yield estimation in circuit designs 
US10762166B1 (en) *  20190607  20200901  International Business Machines Corporation  Adaptive accelerated yield analysis 

2010
 20100820 US US12/859,871 patent/US20120046929A1/en not_active Abandoned

2014
 20140401 US US14/242,418 patent/US9348680B2/en not_active Expired  Fee Related

2016
 20160523 US US15/161,462 patent/US10387235B2/en active Active

2019
 20190819 US US16/543,776 patent/US11372701B2/en active Active
Patent Citations (50)
Publication number  Priority date  Publication date  Assignee  Title 

US20020035462A1 (en) *  20000724  20020321  Makoto Kidera  Method of and device for simulation 
US7480601B2 (en) *  20001026  20090120  Vextec Corporation  Methods and apparatus for predicting the failure of a component, and for determining a grain orientation factor for a material 
US7016825B1 (en) *  20001026  20060321  Vextec Corporation  Method and apparatus for predicting the failure of a component 
US20030004679A1 (en) *  20010108  20030102  Tryon Robert G.  Method and apparatus for predicting failure in a system 
US20060009951A1 (en) *  20010108  20060112  Vextec Corporation  Method and apparatus for predicting failure in a system 
US7006947B2 (en) *  20010108  20060228  Vextec Corporation  Method and apparatus for predicting failure in a system 
US20030061152A1 (en) *  20010926  20030327  De Rabi S.  System and method for determining ValueatRisk using FORM/SORM 
US20040199444A1 (en) *  20030123  20041007  Joel Woodcock  Method of characterizing financial benefits based upon input operational parameters having uncertainties 
US20090182536A1 (en) *  20030714  20090716  Morris Joel M  System and method for estimating probabilities of events 
US7096140B2 (en) *  20031030  20060822  Kabushiki Kaisha Toshiba  Test system, test method and test program for an integrated circuit by IDDQ testing 
US20070097763A1 (en) *  20031110  20070503  Renesas Technology Corp.  Manufacturing method of semiconductor integrated circuit device 
US20050273308A1 (en) *  20040607  20051208  Houston Theodore W  Statistical evaluation of circuit robustness separating local and global variation 
US20060150129A1 (en) *  20041210  20060706  Anova Solutions, Inc.  Stochastic analysis process optimization for integrated circuit design and manufacture 
US20060142988A1 (en) *  20041228  20060629  Satoru Akiyama  Design methodology and manufacturing method for semiconductor memory 
US20060229856A1 (en) *  20050411  20061012  Nicolas Burrus  Systems, devices, and methods for diffusion tractography 
US7272808B1 (en) *  20050608  20070918  Advanced Micro Devices, Inc.  Onchip variability impact simulation and analysis for circuit performance 
US7920995B2 (en) *  20050629  20110405  Siemens Aktiengesellschaft  Probabilistic design tool for optimizing a technical system 
US20080059143A1 (en) *  20051212  20080306  HsienYen Chiu  Hierarchical stochastic analysis process optimization for integrated circuit design and manufacture 
US8285522B1 (en) *  20060124  20121009  Vextec Corporation  Materialsbased failure analysis in design of electronic devices 
US8290753B2 (en) *  20060124  20121016  Vextec Corporation  Materialsbased failure analysis in design of electronic devices, and prediction of operating life 
US20080015827A1 (en) *  20060124  20080117  Tryon Robert G Iii  Materialsbased failure analysis in design of electronic devices, and prediction of operating life 
US20080195325A1 (en) *  20060314  20080814  Joshi Rajiv V  System and computer program for efficient cell failure rate estimation in cell arrays 
US7380225B2 (en) *  20060314  20080527  International Business Machines Corporation  Method and computer program for efficient cell failure rate estimation in cell arrays 
US20070220455A1 (en) *  20060314  20070920  Joshi Rajiv V  Method and computer program for efficient cell failure rate estimation in cell arrays 
US20080141190A1 (en) *  20061206  20080612  Qualcomm Incorporated  Process Variation Tolerant Memory Design 
US7979832B2 (en) *  20061206  20110712  Qualcomm Incorporated  Process variation tolerant memory design 
US8275596B2 (en) *  20061208  20120925  Globalfoundries Inc.  Method for robust statistical semiconductor device modeling 
US20080140363A1 (en) *  20061212  20080612  ChungKai Lin  Unified Model for process variations in integrated circuits 
US7508697B1 (en) *  20070509  20090324  Purdue Research Foundation  Selfrepairing technique in nanoscale SRAM to reduce parametric failures 
US20090070716A1 (en) *  20070912  20090312  Joshi Rajiv V  System and method for optimization and predication of variability and yield in integrated ciruits 
US7827018B2 (en) *  20071116  20101102  International Business Machines Corporation  Method and computer program for selecting circuit repairs using redundant elements with consideration of aging effects 
US8155938B2 (en) *  20080328  20120410  Carnegie Mellon University  Method and apparatus for sampling and predicting rare events in complex electronic devices, circuits and systems 
US20090248387A1 (en) *  20080328  20091001  Carnegie Mellon University  Method and apparatus for sampling and predicting rare events in complex electronic devices, circuits and systems 
US8010325B2 (en) *  20080425  20110830  Microsoft Corporation  Failure simulation and availability report on same 
US20100010744A1 (en) *  20080711  20100114  Schlumberger Technology Corporation  Monte carlo method for laplace inversion of nmr data 
US8374839B2 (en) *  20081211  20130212  Jedat Inc.  System for creating parameter information, system for estimating yields, program and recording medium 
US20100153086A1 (en) *  20081211  20100617  Jedat Inc.  System for creating parameter information, system for estimating yields, program and recording medium 
US8214190B2 (en) *  20090413  20120703  International Business Machines Corporation  Methodology for correlated memory fail estimations 
US20110054856A1 (en) *  20090901  20110303  International Business Machines Corporation  Equivalent Device Statistical Modeling for Bitline Leakage Modeling 
US8346528B2 (en) *  20090901  20130101  International Business Machines Corporation  Equivalent device statistical modeling for bitline leakage modeling 
US8219355B2 (en) *  20091223  20120710  Cadence Design Systems, Inc.  Methods and systems for high sigma yield estimation 
US20110153272A1 (en) *  20091223  20110623  Cadence Design Systems, Inc.  Methods and systems for high sigma yield estimation using reduced dimensionality 
US20110153271A1 (en) *  20091223  20110623  Cadence Design Systems, Inc.  Methods and systems for high sigma yield estimation 
US20110307438A1 (en) *  20100614  20111215  Fern E Acu A Ee Ndez Mart E Acu I Ee Nez Juan Luis  Highdimensional data analysis 
US20110313747A1 (en) *  20100622  20111222  International Business Machines Corporation  Technology ComputerAided Design (TCAD)Based Virtual Fabrication 
US8515724B2 (en) *  20100622  20130820  International Business Machines Corporation  Technology computeraided design (TCAD)based virtual fabrication 
US20130226544A1 (en) *  20101027  20130829  Solido Design Automation Inc.  Method and system for identifying rareevent failure rates 
US20120150500A1 (en) *  20101208  20120614  Fujitsu Limited  Optimization processing method and apparatus 
US20120317656A1 (en) *  20110405  20121213  International Business Machines Corporation  Twoparty private estimation of dataset similarity 
US20130159947A1 (en) *  20111216  20130620  International Business Machines Corporation  Guiding design actions for complex failure modes 
NonPatent Citations (4)
Title 

Efficient Rare Event Simulation: A Tutorial on Importance Sampling; Michele Pagano et al; July 2005; Pgs. 1244 * 
IEEE paper "Robust Importance Sampling for Efficient SRAM Yield AnalysisTakanori Date et al, (IEEE March 2010, Pgs: 1521) * 
Importance Sampling for the Simulation of Highly Reliable Markovian SystemsAuthor(s): Perwez ShahabuddinSource: Management Science, Vol. 40, No. 3 (Mar., 1994), pp. 333352 * 
Sequential Importance Sampling for LowProbability and HighDimensional SRAM Yield Analysis; Kentaro Katayama et al; 711 Nov.2010 IEEE; Page(s): 703  708 * 
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JP2014229311A (en) *  20130527  20141208  三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ．  Simulation system and method and computer system including simulation system 
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US8806418B1 (en)  20130619  20140812  Freescale Semiconductor, Inc.  Scaled sigma sampling 
WO2014204577A1 (en) *  20130621  20141224  California Institute Of Technology  Determination of electronic circuit robustness 
US10776996B2 (en)  20140806  20200915  Samsung Electronics Co., Ltd.  Method and apparatus for processing image 
US20160063156A1 (en) *  20140826  20160303  International Business Machines Corporation  Multidimension variable predictive modeling for yield analysis acceleration 
US10387596B2 (en) *  20140826  20190820  International Business Machines Corporation  Multidimension variable predictive modeling for yield analysis acceleration 
US10452793B2 (en)  20140826  20191022  International Business Machines Corporation  Multidimension variable predictive modeling for analysis acceleration 
CN105701293A (en) *  20160113  20160622  北京航空航天大学  Method for generating multistage task system fault physical simulation sections of avionic devices 
US10325056B1 (en) *  20160610  20190618  Cadence Design Systems, Inc.  Failure boundary classification and corner creation for scaledsigma sampling 
US11327825B2 (en) *  20170111  20220510  International Business Machines Corporation  Predictive analytics for failure detection 
US11340977B2 (en) *  20170111  20220524  International Business Machines Corporation  Predictive analytics for failure detection 
CN108694273A (en) *  20170412  20181023  三星电子株式会社  Circuit yield analysis method and system for assessing rare failure event 
CN108427798A (en) *  20170812  20180821  中民筑友科技投资有限公司  A kind of entrucking sequence based on BIM building elements determines method and device 
US10909293B1 (en)  20180703  20210202  Cadence Design Systems, Inc.  Sampling selection for enhanced high yield estimation in circuit designs 
US10853550B1 (en) *  20180703  20201201  Cadence Design Systems, Inc.  Sampling selection for enhanced high yield estimation in circuit designs 
CN109347691A (en) *  20180801  20190215  温州大学苍南研究院  A kind of data sampling method, device and equipment for Web service 
US10891415B1 (en)  20190605  20210112  Cadence Design Systems, Inc.  Method, system, and product for generating radial bump patterns 
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US20140215274A1 (en)  20140731 
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