US20110226520A1 - Integrated circuit carrier assembly - Google Patents

Integrated circuit carrier assembly Download PDF

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Publication number
US20110226520A1
US20110226520A1 US13/118,456 US201113118456A US2011226520A1 US 20110226520 A1 US20110226520 A1 US 20110226520A1 US 201113118456 A US201113118456 A US 201113118456A US 2011226520 A1 US2011226520 A1 US 2011226520A1
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US
United States
Prior art keywords
integrated circuit
island
carrier
receiving zone
carrier assembly
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US13/118,456
Inventor
Kia Silverbrook
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Precision Mechatronics Pty Ltd
Original Assignee
Silverbrook Research Pty Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US09/693,707 priority Critical patent/US7221043B1/en
Priority to US11/736,540 priority patent/US7402896B2/en
Priority to US12/140,268 priority patent/US7974102B2/en
Application filed by Silverbrook Research Pty Ltd filed Critical Silverbrook Research Pty Ltd
Priority to US13/118,456 priority patent/US20110226520A1/en
Assigned to SILVERBROOK RESEARCH PTY LTD reassignment SILVERBROOK RESEARCH PTY LTD ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SILVERBROOK, KIA
Publication of US20110226520A1 publication Critical patent/US20110226520A1/en
Assigned to PRECISION MECHATRONICS PTY LTD reassignment PRECISION MECHATRONICS PTY LTD ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SILVERBROOK RESEARCH PTY LTD
Application status is Abandoned legal-status Critical

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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0271Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/13Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/562Protection against mechanical damage
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09009Substrate related
    • H05K2201/09063Holes or slots in insulating substrate not used for electrical connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10734Ball grid array [BGA]; Bump grid array

Abstract

A carrier assembly for an integrated circuit is disclosed. The assembly has a printed circuit board, a receiving zone for operatively locating the integrated circuit, and a matrix of island contacts surrounding the receiving zone. The matrix of island contacts is separated from the receiving zone by a passage and is in electrical contact with the PCB. The receiving zone electrically connects the integrated circuit to the island contacts.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This application is a continuation of U.S. application Ser. No. 12/140,268 filed Jun. 17, 2008, which is a continuation application of U.S. application Ser. No. 11/736,540 filed on Apr. 17, 2007 now issued U.S. Pat. No. 7,402,896, which is a continuation application of U.S. application Ser. No. 09/693,707 filed on Oct. 20, 2000, now issued U.S. Pat. No. 7,221,043, all of which are herein incorporated by reference.
  • FIELD OF THE INVENTION
  • This invention relates to integrated circuit packages. More particularly, the invention relates to an integrated circuit carrier with recesses for an integrated circuit package.
  • BACKGROUND TO THE INVENTION
  • Due to the ever-increasing number of connections (pincount) of integrated circuits, the use of ball grid array packages to connect integrated circuits to printed circuit boards is increasing. This facilitates the redistribution of a very fine pitch of flip-chip bump array of the integrated circuit to a much larger pitch ball grid array for attachment to the printed circuit board (PCB).
  • The carrier is often referred to as an interposer and can be fabricated from different materials such as ceramic, or a plastics material such as bismaleimide triazine (BT).
  • The carrier also functions as a heat sink by removing thermal energy from the integrated circuit by thermal conduction. Accordingly, the carrier is subjected to thermal strains.
  • In addition, an electronic package assembly comprising the integrated circuit, the carrier and the PCB has a number of different materials with different mechanical properties. Complex thermal stresses can occur inside the package during operation due to non-uniform temperature distributions, geometry, material construction and thermal expansion mismatches.
  • Typically, these days the integrated circuit is electrically connected to the carrier by a ball grid array of gold or solder bumps. Similarly, the carrier is electrically connected to the PCB by a further, larger ball grid array of solder balls. The thermo-mechanical stresses are typically severest at the solder ball interfaces between the PCB and the carrier. This can result in shearing of the solder ball connection. The problem is amplified by an increase in edge length of the carrier because of an increase in the thermal strain differences between the PCB and the carrier. An increase in edge length of the carrier is typically associated with an increase in the number of integrated circuit connections and solder balls.
  • Current ball grid array design is, presently, at the limit of reliability for typical integrated circuit pin counts.
  • Typically, a solder ball has a peak elastic shear strain value of around 0.08%. Computational experiments done by the applicant using a 500 micron thick solid Silicon carrier, 500 micron diameter solder balls at 1 millimeter pitch, a 700 micron thick PCB and a 16 millimeter side silicon chip indicated a peak shear strain value of 1.476% in the outermost ball of the package which is far above the plastic yield value of the solder ball.
  • This result is to be expected as the balls at the outermost edge of the package experience the greatest amount of translational shear.
  • As indicated in the publication of the Assembly and Packaging Section of the International Technology Road Map for Semiconductors,—1999 Edition, the most recent edition available at the time of filing the present application, in Table 59a at page 217, a pin count of a high performance integrated circuit has of the order of 1800 pins. The technology requirements in the near term, i.e. until the year 2005 indicate that, for high performance integrated circuits, a pin count exceeding 3,000 will be required for which, as the table indicates, there is, to date, no known solution. Similarly, in Table 59b of that publication, at page 219, in the longer term, until approximately the year 2014, a pin count for high performance integrated circuit packages of the order of 9,000 will be required. Again, as indicated in the table, there is no known solution for this type of package.
  • These aspects are the focus of the present invention.
  • SUMMARY OF THE INVENTION
  • According to an aspect of the present invention there is provided an A carrier assembly for an integrated circuit, said assembly comprising:
      • a printed circuit board (PCB);
      • a receiving zone for operatively locating the integrated circuit; and
      • a matrix of island contacts surrounding the receiving zone, the matrix of island contacts being separated from the receiving zone by a passage, the island contacts being in electrical contact with the PCB,
        wherein said receiving zone electrically connects the integrated circuit to the island contacts.
    BRIEF DESCRIPTION OF THE DRAWINGS
  • The invention is now described by way of example with reference to the accompanying diagrammatic drawings in which:
  • FIG. 1 shows a schematic, plan view of part of a conceptual integrated circuit carrier;
  • FIG. 2 shows a plan view of a part of an integrated circuit carrier, in accordance with the invention;
  • FIG. 3 shows a perspective, sectional view of part of one embodiment of the integrated circuit carrier;
  • FIG. 4 shows a perspective, sectional view of part of a second embodiment of the integrated circuit carrier;
  • FIG. 5 shows a perspective, sectional view of part of a third embodiment of the integrated circuit carrier;
  • FIG. 6 shows a perspective, sectional view of part of a fourth embodiment of the integrated circuit carrier;
  • FIG. 7 shows a sectional, side view of one embodiment of the integrated circuit carrier, in use;
  • FIG. 8 shows a sectional, side view of another embodiment of the integrated circuit carrier, in use;
  • FIG. 9 shows, on an enlarged scale, the circled part ‘A’, of FIG. 8;
  • FIG. 10 shows, on an even greater enlarged scale, a sectional side view of part of the integrated circuit carrier;
  • FIG. 11 shows a side view of yet a further embodiment of the integrated circuit carrier;
  • FIG. 12 shows a sectional side view of still a further embodiment of the integrated circuit carrier;
  • FIG. 13 shows a multi-chip module based on the integrated circuit carrier; and
  • FIG. 14 shows a sectional side view of the multi-chip module based on the integrated circuit carrier.
  • DETAILED DESCRIPTION OF THE DRAWINGS
  • Referring to the drawings, an integrated circuit carrier, in accordance with the invention, is designated generally by the reference numeral 10. An integrated circuit carrier is shown in greater detail in FIG. 2 of the drawings.
  • The integrated circuit carrier 10 has a receiving zone 12 for receiving an integrated circuit or chip 14 (FIG. 7).
  • A plurality of island defining portions or islands 16 surround the receiving zone 12. Each island 16 has an electrical terminal 18 thereon to which a solder ball 20 is attach or reflowed.
  • Each island 16 is connected to its neighboring island or islands 16 via a rigidity reducing arrangement in the form of a serpentine member 22. This is shown in greater detail conceptually in FIG. 1 of the drawings. As illustrated in FIG. 1, each serpentine member 22 serves a spring-like function so that each island 16 has a degree of freedom of movement relative to its neighboring islands 16. Accordingly, the difference in expansion between a printed circuit board 24 (FIGS. 7 to 9) and the carrier 10 is compensated for by extension or retraction of the relevant serpentine members 22. As a result, the shear strain imparted to the solder balls 20 on the island 16 is considerably reduced and fatigue failure of the solder balls 20 is, correspondingly, reduced.
  • Various embodiments of the carrier 10 are now described with reference to FIGS. 3 to 6 of the drawings. In FIG. 3 of the drawings, the carrier 10 has each island 16 connected to its neighboring island 16 by a serpentine member 22 which has a single, curved arm 26.
  • In the embodiment of the invention shown in FIG. 4 of the drawings, each serpentine member 22 connects one island 16 to its neighboring island 16 by a pair of parallel arms 28 interconnected by an orthogonal bridging portion 30.
  • Each serpentine member 22 of the embodiment illustrated in FIG. 5 of the drawings connects one island 16 to its neighboring island 16 via an arrangement having three arms 34 extending parallel to each other. Adjacent arms 34 are connected together by an orthogonal bridging portion 32.
  • In the embodiment illustrated in FIG. 6 of the drawings, each serpentine member 22 which connects one island 16 to its neighboring island 16 has five parallel arms 36 with adjacent arms 36 being connected by an orthogonal bridging portion 38.
  • For ease of explanation, the embodiments illustrated in FIGS. 3 to 6 of the drawings shall be referred to below as the one arm 26 serpentine member 22, the two arm 28 serpentine member 22, the three arm 34 serpentine member 22, and the five arm 36 serpentine member 22, respectively.
  • As illustrated more clearly in FIGS. 7 to 9 of the drawings, those islands 16 surrounding the receiving zone 12 are connected to the receiving zone by a second rigidity reducing arrangement in the form of a zigzag element 40 which further aids in reducing the strain imparted to the solder balls 20.
  • Also, as illustrated in FIGS. 7 to 9 of the drawings, the integrated circuit 14 is electrically connected to electrical contacts 42 (FIG. 2) in the receiving zone 12 via solder bumps 44.
  • The carrier 10 is formed from the same material as the integrated circuit 14. Accordingly, the carrier 10 is formed of silicon having an insulating layer of silicon dioxide. The insulating layer also serves as a hard mask for etching the serpentine members 22, as will be discussed in greater detail below.
  • In the manufacture of the integrated circuit carrier 10, a wafer 46 of silicon is provided. The wafer 46 can be single crystal silicon or polycrystalline silicon.
  • It is to be noted that the version of the carrier 10 shown in FIG. 10 of the drawings is where the receiving zone 12 is on the same side of the carrier 10 as the pads 18 as shown in FIG. 7 of the drawings. Where the receiving zone 12 is on an opposite surface of the carrier 10, as shown in FIG. 8 of the drawings, the circuitry layer is applied to both sides of the wafer 46. This is shown on a smaller scale in FIG. 9 of the drawings. In this embodiment, each track 52 is electrically connected to its associated pad 18 via a plated through hole 58 extending through the wafer 46.
  • Referring now to FIGS. 11 and 12 of the drawings, two further embodiments of the carrier 10 are illustrated. With reference to the previous drawings, like reference numerals refer to like parts, unless otherwise specified.
  • In the examples illustrated, the receiving zone 12 is, instead of being demarcated on a surface of the carrier 10, a passage 60 defined through the carrier 10. The integrated circuit 14 is attached to a mounting means or retaining means in the form of a metallic lid 62 which is bonded to one surface of the carrier 10. An opposed surface of the integrated circuit 14 has bond pads for electrically connecting the integrated circuit to the carrier 10. It will be appreciated that, in this embodiment, the electrical contacts are arranged on that part of the carrier 10 surrounding the passage 60. In the embodiment illustrated in FIG. 11 of the drawings, the interconnects are wire bonds 64. Either ball or wedge bonds can be used. In the embodiment illustrated in FIG. 12 of the drawings, the interconnects are tape automated bond (TAB) films 66 or other planar connections such as beam leads.
  • Referring now to FIG. 13 of the drawings, a development of the integrated circuit carrier is illustrated and is designated generally by the reference numeral 70. With reference to the previous drawings, like reference numerals refer to like parts, unless otherwise specified.
  • In this embodiment of the invention, the carrier 70 is a multi-chip module substrate 70 carrying a plurality of integrated circuits or chips such as those illustrated at 72, 74 and 76 in FIG. 13. The chips 72, 74 and 76 are either carried on the surface of the carrier 70 or, as described above with reference to FIGS. 10 and 11, the chips are recessed in the carrier 70 as illustrated in FIG. 14 of the drawings.
  • As indicated above, the serpentine members 22 may have different configurations such as the one arm 26 configuration, the two arm 28 configuration, the three arm 34 configuration or the five arm 36 configuration. Other configurations such as 4 arm or 6 or more arm configurations are also possible using finite element analyses, a results matrix for different carrier implementations, having different forms of serpentine members 22 and different ball arrays was generated. The matrix, which is set out below, contains results for ball grid arrays having rows of one to twenty-four balls, carriers of solid silicon, solid Al2O3, solid BT, a one arm 26 serpentine member 22, a two arm 28 serpentine member 22, a three arm 34 serpentine member 22 and a five arm 36 serpentine member.
  • No. of Balls in Row
    1 4 8 16 24 100
    Solid Si 1.08% 1.48% 1.61% 1.01%
    Interposer
    Solid Al2O3 0.667% 0.953% 1.077% 0.72%
    Interposer
    Solid BT 0.126% 0.149% 0.150% 0.097%
    Interposer
    One arm 0.103% 0.0903% 0.085%
    serpentine
    member
    Two arm 0.47% 0.15% 0.147% 0.136% 0.128% 0.088%
    serpentine
    member
    Three arm 0.22% 0.082% 0.079% 0.058% 0.056%
    serpentine
    member
    Five arm 0.025% 0.025% 0.013%
    serpentine
    member
  • As indicated above, the elastic strain limit for solder is around 0.08%. A row of solder balls is defined as from an edge of the receiving zone 12 to the edge of the carrier 10.
  • The results show that the peak solder ball strain value for solid carriers increases with an increasing number of solder balls 20 up to a certain point, due to the cumulative effect of thermo-mechanical strain between the PCB 24 and carrier 10. The solder ball strain actually goes down for the hundred ball implementation, probably due to a change in deflection shape of the solid silicon carrier. Peak strain still occurs in the outermost ball however although it is decreased because differential expansion between the carrier and the PCB is minimised. Also, the peak strain value of the solid carriers, apart from the BT carrier, is still, far in excess of the elastic strain limit for solder.
  • The serpentine member 22 implementations show a decrease in peak solder ball strain with increasing number of solder balls. This is due to the fact that the thermal strain mismatch is distributed over a greater number of solder balls 20 resulting in a deflected shape with less severe gradients. Smaller ball grid arrays, i.e. having fewer balls in a row, exhibit more severe deflection gradients that induce a concentrated load on either the innermost or the outermost solder ball 20.
  • Accordingly, it is a particular advantage of the invention that, due to the reduction of the peak strain with an increasing number of solder balls 20 there is no thermo-mechanical limit to the amount of integrated circuit pin connections. A line of 100 balls on all sides of the receiving zone 12 equates to a ball grid array of more than 40,000 balls, well in excess of expected requirements of 9,000 balls by 2014. Finite element calculations indicate that the peak solder ball strain is less than the elastic limit of solder for carriers with three or more arm serpentine members, with 8 or more rows of balls. As the receiving zone is silicon, and therefore has the same coefficient of thermal expansion as a silicon integrated circuit, the strain on the bump connections from the integrated circuit 14 to the carrier 10 is minimised. This indicates that a silicon BGA with etched compliant regions as described herein can provide a definite solution to problems of failure from thermal cycling that currently limit the number of connections that can be made between a chip and a PCB using ball grid arrays. Also, as described above, with the provision of the serpentine members 22, a greater surface area is provided which is further enhanced by the re-entrant etch 50 such that the heat sink capability of the carrier 10 is enhanced. This also aids in the increase in the number of solder balls 20 which can constitute the array.
  • It will be appreciated by persons skilled in the art that numerous variations and/or modifications may be made to the invention as shown in the specific embodiments without departing from the spirit or scope of the invention as broadly described. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive.

Claims (6)

1. A carrier assembly for an integrated circuit, said assembly comprising:
a printed circuit board (PCB);
a receiving zone for operatively locating the integrated circuit; and
a matrix of island contacts surrounding the receiving zone, the matrix of island contacts being separated from the receiving zone by a passage, the island contacts being in electrical contact with the PCB,
wherein said receiving zone electrically connects the integrated circuit to the island contacts.
2. The carrier assembly of claim 1, wherein the island contacts are soldered to the PCB and a surface of the integrated circuit has bond pads for electrically connecting the integrated circuit to the island contacts.
3. The carrier assembly of claim 2, wherein the integrated circuit is operatively located between the receiving zone and the PCB.
4. The carrier assembly of claim 1, wherein each island contact includes a solder ball at a lower surface thereof.
5. The carrier assembly of claim 1, wherein each island contact has an electrical via passing therethrough.
6. The carrier assembly of claim 1, wherein the island contacts are interconnected by respective serpentine members to allow resilient deflection of said island contacts relative to each other.
US13/118,456 2000-10-20 2011-05-30 Integrated circuit carrier assembly Abandoned US20110226520A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US09/693,707 US7221043B1 (en) 2000-10-20 2000-10-20 Integrated circuit carrier with recesses
US11/736,540 US7402896B2 (en) 2000-10-20 2007-04-17 Integrated circuit (IC) carrier assembly incorporating serpentine suspension
US12/140,268 US7974102B2 (en) 2000-10-20 2008-06-17 Integrated circuit carrier assembly
US13/118,456 US20110226520A1 (en) 2000-10-20 2011-05-30 Integrated circuit carrier assembly

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/118,456 US20110226520A1 (en) 2000-10-20 2011-05-30 Integrated circuit carrier assembly

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US12/140,268 Continuation US7974102B2 (en) 2000-10-20 2008-06-17 Integrated circuit carrier assembly

Publications (1)

Publication Number Publication Date
US20110226520A1 true US20110226520A1 (en) 2011-09-22

Family

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US09/693,707 Expired - Fee Related US7221043B1 (en) 2000-10-20 2000-10-20 Integrated circuit carrier with recesses
US11/736,540 Expired - Fee Related US7402896B2 (en) 2000-10-20 2007-04-17 Integrated circuit (IC) carrier assembly incorporating serpentine suspension
US12/140,268 Expired - Fee Related US7974102B2 (en) 2000-10-20 2008-06-17 Integrated circuit carrier assembly
US13/118,456 Abandoned US20110226520A1 (en) 2000-10-20 2011-05-30 Integrated circuit carrier assembly

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Application Number Title Priority Date Filing Date
US09/693,707 Expired - Fee Related US7221043B1 (en) 2000-10-20 2000-10-20 Integrated circuit carrier with recesses
US11/736,540 Expired - Fee Related US7402896B2 (en) 2000-10-20 2007-04-17 Integrated circuit (IC) carrier assembly incorporating serpentine suspension
US12/140,268 Expired - Fee Related US7974102B2 (en) 2000-10-20 2008-06-17 Integrated circuit carrier assembly

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US (4) US7221043B1 (en)
EP (1) EP1410700B1 (en)
JP (1) JP3761520B2 (en)
KR (1) KR100526330B1 (en)
CN (1) CN1235453C (en)
AT (1) AT381249T (en)
AU (2) AU1025202A (en)
DE (1) DE60131906D1 (en)
IL (2) IL155466D0 (en)
SG (1) SG126771A1 (en)
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US7221043B1 (en) * 2000-10-20 2007-05-22 Silverbrook Research Pty Ltd Integrated circuit carrier with recesses
KR101016493B1 (en) * 2003-05-16 2011-02-24 소니 주식회사 Motion correction device and method
TW201241941A (en) * 2010-10-21 2012-10-16 Sumitomo Bakelite Co A method for manufacturing an electronic equipment, and the electronic equipment obtained by using the method, as well as a method for manufacturing electronics and electronic parts, and the electronics and the electronic parts obtained using the method
US9513666B2 (en) * 2014-07-25 2016-12-06 VivaLnk, Inc. Highly compliant wearable wireless patch having stress-relief capability
CN105338727B (en) * 2015-10-22 2018-05-25 北大方正集团有限公司 Preparation stepped groove step and a step board of the circuit board
CN105392306A (en) * 2015-11-27 2016-03-09 北大方正集团有限公司 High-frequency blind slot circuit board and processing method thereof
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CN1471804A (en) 2004-01-28
AT381249T (en) 2007-12-15
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US7221043B1 (en) 2007-05-22
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US7974102B2 (en) 2011-07-05
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US20070284725A1 (en) 2007-12-13
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EP1410700A4 (en) 2006-05-03
JP3761520B2 (en) 2006-03-29

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