US20110121390A1 - Semiconductor substrates and manufacturing methods of the same - Google Patents
Semiconductor substrates and manufacturing methods of the same Download PDFInfo
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- US20110121390A1 US20110121390A1 US12/929,455 US92945511A US2011121390A1 US 20110121390 A1 US20110121390 A1 US 20110121390A1 US 92945511 A US92945511 A US 92945511A US 2011121390 A1 US2011121390 A1 US 2011121390A1
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- 239000000758 substrate Substances 0.000 title claims abstract description 174
- 239000004065 semiconductor Substances 0.000 title claims abstract description 87
- 238000004519 manufacturing process Methods 0.000 title abstract description 28
- 210000000746 body region Anatomy 0.000 claims abstract description 83
- 238000009413 insulation Methods 0.000 claims abstract description 51
- 239000000463 material Substances 0.000 claims abstract description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 238000005530 etching Methods 0.000 abstract description 35
- 238000000034 method Methods 0.000 abstract description 24
- 239000011810 insulating material Substances 0.000 abstract description 11
- 238000002161 passivation Methods 0.000 description 12
- 230000008569 process Effects 0.000 description 10
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 238000000059 patterning Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 230000000670 limiting effect Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000012774 insulation material Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000002829 reductive effect Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7841—Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
Definitions
- Example embodiments provide semiconductor substrates and methods of manufacturing a semiconductor substrate. Other example embodiments relate to semiconductor substrates including a floating body and methods of manufacturing a semiconductor substrate.
- a 1-T dynamic random access memory which does not include a capacitor and uses one transistor, may be used.
- a 1-T DRAM may be manufactured using a fairly simple manufacturing process.
- a 1-T DRAM may have an increased sensing margin.
- 1-T DRAM is realized on a silicon-on-insulator (SOI) wafer, the manufacturing cost increases due to the SOI wafer.
- 1-T DRAMs are generally manufactured in an embedded form.
- Example embodiments provide semiconductor substrates and methods of manufacturing a semiconductor substrate. Other example embodiments relate to semiconductor substrates including a floating body and methods of manufacturing a semiconductor substrate.
- Example embodiments provide a method of manufacturing a semiconductor device in which a floating body region formed of a same material as a substrate region is realized using a selective etching technique.
- a semiconductor substrate including a substrate region, an insulation region formed on the substrate region, and a floating body region separated from the substrate region by the insulation region and disposed on the insulation region, wherein the substrate region and the floating body region are formed of materials having identical characteristics.
- the substrate region may be formed from a bulk semiconductor substrate.
- a method of manufacturing a semiconductor substrate including forming at least one floating body pattern by etching a bulk substrate, separating (or defining) the bulk substrate into a substrate region and a floating body region by etching a lower middle portion of the floating body pattern, and filling an insulating material between the floating body region and the substrate region.
- the lower middle portion of the floating body pattern may be etched using a selective wet or dry etching method.
- Forming the at least one floating body pattern by etching the bulk substrate may include etching the bulk substrate in a first direction, which is a major axis direction, to form a floating body line pattern extending in the first direction, filling sides of the floating body line pattern with an insulating layer, and etching the floating body line pattern and the insulating layer in a second direction perpendicular to the first direction, in which the floating body line pattern is extended, to form at least one floating body pattern that is extended in the second direction.
- Separating the bulk substrate into the substrate region and the floating body region by etching a lower middle portion of the floating body pattern may include forming a passivation layer on sidewalls of the floating body pattern, and etching the lower middle portion of the floating body pattern through a bottom surface disposed on sides of the floating body pattern where the passivation layer is not formed.
- Forming the at least one floating body pattern by etching the bulk substrate may include etching the bulk substrate in a first direction to form a plurality of floating body line patterns extending parallel to each other in the first direction, filling an insulating layer between the floating body line patterns, and etching the bulk substrate in a second direction perpendicular to the first direction, in which the floating body line patterns are extended, to form a plurality of floating body patterns extending parallel to each other in the second direction.
- Separating the bulk substrate into the substrate region and the floating body region by etching the lower middle portion of the floating body pattern may include forming a passivation layer on sidewalls of the floating body patterns, and etching the lower middle portion of the floating body patterns through a bottom surface where the passivation layer that is disposed between the floating body patterns is not formed.
- FIGS. 1-12F represent non-limiting, example embodiments as described herein.
- FIG. 1 is a perspective view of a semiconductor substrate according to example embodiments
- FIG. 2 illustrates a substrate region and a body region in the semiconductor substrate of FIG. 1 ;
- FIG. 3 illustrates an oxide region filled between the substrate region and the body region of FIG. 2 ;
- FIG. 4 illustrates a semiconductor substrate according to example embodiments.
- FIG. 5 illustrates a semiconductor substrate according to example embodiments
- FIGS. 6A through 6G are perspective views illustrating a method of manufacturing the semiconductor substrate according to example embodiments.
- FIG. 7 illustrates a word line pattern formed in a semiconductor substrate 400 according to example embodiments
- FIGS. 8A through 8G are perspective views illustrating a method of manufacturing a semiconductor substrate according to example embodiments.
- FIG. 9 is a perspective view of a semiconductor substrate according to example embodiments.
- FIG. 10 illustrates a substrate region and a body region in the semiconductor substrate of FIG. 9 ;
- FIG. 11 illustrates an insulation region filled between the substrate region and the body region in FIG. 10 ;
- FIGS. 12A through 12F are perspective views illustrating a method of manufacturing the semiconductor substrate in FIG. 9 .
- first, second, third etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the scope of example embodiments.
- spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or a relationship between a feature and another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the Figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, for example, the term “below” can encompass both an orientation which is above as well as below. The device may be otherwise oriented (rotated 90 degrees or viewed or referenced at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.
- Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, may be expected. Thus, example embodiments should not be construed as limited to the particular shapes of regions illustrated herein but may include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle may have rounded or curved features and/or a gradient (e.g., of implant concentration) at its edges rather than an abrupt change from an implanted region to a non-implanted region.
- a gradient e.g., of implant concentration
- a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation may take place.
- the regions illustrated in the figures are schematic in nature and their shapes do not necessarily illustrate the actual shape of a region of a device and do not limit the scope.
- Example embodiments provide semiconductor substrates and methods of manufacturing a semiconductor substrate. Other example embodiments relate to semiconductor substrates including a floating body and methods of manufacturing a semiconductor substrate.
- FIG. 1 is a perspective view of a semiconductor substrate 100 according to example embodiments.
- the semiconductor substrate 100 includes a substrate region 110 , a body region 150 and/or an insulation region 130 .
- the insulation region 130 may be disposed on the substrate region 110 .
- the body region 150 may be separated from the substrate region 110 .
- the body region 150 may be disposed on the insulation region 130 .
- the body region 150 may be a floating body region.
- the substrate region 110 and the body region 150 may be formed of materials having identical characteristics.
- the insulation region 130 may be formed of a silicon oxide or another insulation material.
- the insulation region 130 may be formed of two or more insulation materials.
- the semiconductor substrate 100 may include a plurality of body regions 150 _ 1 , 150 _ 2 , 150 _ 3 (collectively referred to as the body region 150 ) that are arranged parallel to each other.
- a plurality of insulating layers may be formed between the body regions 150 _ 1 , 150 _ 2 , 150 _ 3 .
- the insulating layers separate the body regions 150 _ 1 , 150 _ 2 , 150 _ 3 .
- the insulating layers disposed between the body regions 150 _ 1 , 150 _ 2 , 150 _ 3 may be connected to the insulation region 130 .
- a bulk substrate may be separated into an upper end portion and a lower end portion by selectively etching a center portion of the bulk substrate.
- the separated upper and lower end portions may be the body region 150 and the substrate region 110 , respectively.
- At least one of the body regions 150 _ 1 , 150 _ 2 , 150 _ 3 may be formed by forming at least one body pattern (not shown) extending in a desired direction on the bulk substrate and etching a lower middle portion of the body pattern.
- FIG. 2 illustrates the substrate region 110 and the body region 150 of the semiconductor substrate 100 .
- FIG. 3 illustrates the insulation region 130 between the substrate region 110 and the body region 150 of semiconductor substrate 100 .
- the substrate region 110 and the body region 150 may be separated from each other. Because the substrate region 110 and the body region 150 are formed from an identical substrate, the substrate region 110 and the body region 150 include identical materials. A more detailed description of the process of etching the center portion of the substrate may be obtained by referring to the article entitled “Sphere-Shaped-Recess-Channel-Array Transistor (S-RCAT) Technology for 70 nm DRAM Feature Size and Beyond,” 2005 Symposium on VLSI Technology Digest of Technical Papers, the entire contents of which are incorporated in this application.
- S-RCAT Sphere-Shaped-Recess-Channel-Array Transistor
- the body region 150 is manufactured through an epitaxial growing process on the substrate region 110 , materials included in the body region 150 have different characteristics than materials included in the substrate region 110 .
- the semiconductor substrate according to example embodiments may be formed from a bulk semiconductor substrate.
- the body region 150 may be formed from a bulk semiconductor substrate by selectively etching a center portion of the bulk semiconductor substrate. Compared to a semiconductor substrate in which the insulation region is formed on the substrate region and the body region is formed on the insulation region through an epitaxial growing process, the semiconductor substrate according to example embodiments may be manufactured at lower costs.
- FIG. 4 illustrates a semiconductor substrate 200 according to example embodiments. A description of like elements in FIG. 4 as described above with reference to FIGS. 1-3 will be omitted for the sake of brevity.
- a body region 250 may be formed with a decreased thickness.
- the thickness of the body region 250 is smaller than the thickness of the body region 150 of the semiconductor substrate 100 shown in FIG. 1 .
- the thickness of the body region of the semiconductor substrate may vary.
- the thickness of the body region may be adjusted by adjusting the selective etching position.
- the thickness of the body region 150 may be increased by selectively etching a region near a lower end portion of the bulk substrate.
- the thickness of the body region 250 may be reduced by selectively etching a region near an upper end portion of the bulk substrate.
- the thickness of the body region may not exceed a desired thickness.
- FIG. 5 illustrates a semiconductor substrate 300 according to example embodiments.
- a plurality of body regions 350 may be formed in the semiconductor substrate 300 .
- the body regions 350 may be separated from a substrate region 310 .
- An insulating material may be filled between the body regions 350 and the substrate region 310 to form insulation regions 330 .
- the body regions 350 may be formed by forming a plurality of body patterns extending in a desired direction on the bulk substrate and etching regions of the bulk substrate below the body patterns.
- the plurality of body regions 350 may be formed in one direction and uniform in size. However, example embodiments are not limited thereto.
- the plurality of body regions 350 may be arranged in different directions and/or have different sizes as illustrated in FIGS. 1 through 3 .
- the plurality of body regions 150 may be arranged in an array on one substrate region 110 .
- FIGS. 6A through 6G are perspective views illustrating a method of manufacturing a semiconductor substrate 100 according to example embodiments.
- the semiconductor substrate 100 may be patterned from upper end portions of the semiconductor substrate to a desired width and length.
- the semiconductor substrate 100 may be a bulk semiconductor substrate generated (or formed) from a bulk wafer.
- Patterning the semiconductor substrate 100 forms a body line pattern 150 a disposed between the patterned portions and a substrate region 110 below the body line pattern 150 a.
- the patterning width may vary according to the desired width of the body line pattern 150 a.
- the patterning length may vary according to the desired thickness of the body line pattern 150 a.
- the body region may be referred to as a body line pattern 150 a (or body pattern 150 b ) before being separated from the substrate region 110 , and a body region 150 after being separated from the substrate region 110 .
- an insulating material may be filled in the patterned portions to form insulation regions 130 .
- Insulation regions 130 may be disposed at sides of the body line pattern 150 a. If the body line pattern 150 a is separated from the substrate region 110 using a selective etching technology to form the body region 150 , the insulation regions 130 may support the body region 150 .
- the body line pattern 150 a and the insulation regions 130 may be patterned in a Z direction.
- the body line pattern 150 a and the insulation regions 130 may be separated into a plurality of body patterns 150 b and a plurality of insulation regions 130 .
- the body line pattern 150 a and the insulation regions 130 may be patterned from a top of the body line pattern 150 a and the insulation regions 130 to a desired length.
- the region 150 a illustrated in FIGS. 6A and 6B may be referred to as a body line pattern, and the region 150 b illustrated in FIG. 6C may be referred to as body patterns.
- a bulk substrate is patterned in a first direction (Y direction), which is a major axis direction, to form a body line pattern 150 a extending in the first direction (Y direction).
- sides of the body line pattern 150 a in FIG. 6A may be filled with insulating regions (or layers) 130 .
- the body line pattern 150 a and the insulating regions 130 may be etched in a second direction (Z direction) that is perpendicular to the first direction (Y direction) in which the body line pattern 150 a is extended to form at least one body pattern 150 b extending in the second direction (Z direction).
- the height of the body patterns 150 b may be lower than that of the body line pattern 150 a.
- a patterning process may be performed only on portions not covered by the mask 180 . As such, portions that are not covered by the mask 180 may be patterned.
- patterned inner surfaces of the body patterns 150 b and the insulation regions 130 may be covered by a first mask (a passivation layer) 184 .
- Bottom surfaces of the body patterns 150 b and the insulation regions 130 may be covered by a second mask 186 .
- the second mask 186 on the bottom surfaces may be removed.
- a lower middle portion of the body patterns 150 b may be selectively etched, exposing a bottom surface 188 of the body patterns 150 b and an upper surface 189 of the substrate region 110 .
- the lower middle portion of the body patterns 150 b may be selectively etched through the bottom surfaces 188 , from which the second mask 186 has been removed.
- the lower middle portion of the body pattern 150 b may be etched through the bottom surfaces 188 (as shown in FIG. 6E ), which are disposed on sides of the body patterns 150 b and on which the first mask (the passivation layer) 184 is not formed.
- the bulk substrate may be separated into a substrate region 110 and a body region 150 .
- the substrate region 110 may be disposed under the selectively etched region and the body region 150 may be disposed on the selectively etched region.
- the selective etching process may be a selective wet etching method or a selective dry etching method, which is used to etch the lower middle portion of the body patterns 150 b.
- the selectively etched region of the body patterns 150 b and the substrate region 100 may be filled with an insulating material.
- the selectively etched region may be filled with an insulating material. Spaces between the body patterns 150 b may be filled with the insulating material.
- FIGS. 6A through 6G may be used to manufacture the semiconductor substrate 300 of FIG. 5 in which a plurality of body regions are formed.
- several portions of the bulk substrate illustrated in FIG. 5 may be etched parallel to each other in the first direction to form a plurality of body line patterns extending parallel to each other in the first direction.
- insulating layers may be filled between the body line patterns.
- the bulk substrate may be etched in the second direction, which is perpendicular to the first direction, to form a plurality of body patterns extending parallel to each other in the second direction. (In FIG.
- a passivation layer may be formed on sidewalls of the body patterns.
- the lower middle portion of the body patterns may be etched through a bottom surface wherein the passivation layer disposed between the body patterns is not formed.
- the etched regions and spaces between the body patterns may be filled with an insulating material.
- FIG. 7 illustrates a word line pattern formed on a semiconductor substrate 400 according to example embodiments.
- a substrate region 410 , a body region 450 and an insulation region 430 are formed using a similar method as described with reference to semiconductor substrate 100 .
- a description of like elements will not be repeated for the sake of brevity.
- a word line pattern 472 may be formed on (or over) the body region 450 .
- a plurality of impurity doping regions may be formed on the body region 450 .
- Semiconductor devices according to example embodiments may be used as a bipolar junction transistor (BJT). If the semiconductor substrate 400 is used a BJT, a portion of the word line pattern 472 may function as a base of a transistor. For example, the portion of the word line pattern 472 passing (or over) an upper end of the body region 450 may function as the base of the transistor.
- the impurity doping regions may respectively function as an emitter and collector.
- example embodiments are not limited thereto.
- the semiconductor devices according to example embodiments may be realized as various circuit devices other than the BJT.
- the semiconductor devices may be realized as another type of transistor, a memory device, a sensor or a switching unit structure.
- a pattern other than the word line pattern 472 may be formed on (or over) the body region 450 .
- FIGS. 8A through 8G are perspective views illustrating a method of manufacturing a semiconductor substrate 800 according to example embodiments.
- a bulk substrate may be etched in a first direction (Y direction), which is a major axis direction, to form a body line pattern 850 a extended in the first direction (Y direction).
- sides of the body line pattern 850 a may be filled with insulating layers 830 .
- FIGS. 8A and 8B are identical to the processes of FIGS. 6A and 6B , description of like elements thereof will be omitted for the sake of brevity.
- the body line pattern 850 a illustrated in FIG. 8B is patterned in a Z direction.
- At least one body pattern 850 b may be formed by etching the body line pattern 850 a (excluding the insulating layers 830 ) in the first direction (Y direction) in which the body line pattern 850 a is extended and in the second direction (Z direction) that is perpendicular to the first direction.
- the insulation layer 830 is not patterned in FIG. 8C .
- the body pattern 850 b may be patterned to a desired length from a top surface of the body pattern 850 b.
- portions that are not covered by the mask 880 may be patterned.
- patterned inner surfaces 884 and bottom surfaces (not shown) of the body pattern 850 b and the insulation region 830 may be masked.
- the mask on the bottom surfaces (not shown) may be removed.
- a lower middle portion of the body pattern 850 b may be selectively etched through the bottom surface, from which the masking is removed.
- the lower middle portion of the body pattern 850 b may be selectively etched, exposing a bottom surface 888 of the body pattern 850 b and an upper surface 889 of the substrate region 810 .
- the selectively etched region of the body pattern 850 b and the substrate region 810 may be filled with an insulating material.
- the semiconductor 800 of FIG. 8G and the semiconductor substrate 100 of FIG. 6G may have the same form (or structure).
- FIG. 9 is a perspective view of a semiconductor substrate 900 according to example embodiments.
- FIG. 10 illustrates a substrate region and a body region of the semiconductor substrate 900 .
- FIG. 11 illustrates an insulation region between the substrate region and the body region of the semiconductor substrate 900 .
- the direction of the selective etching process is different from the manufacturing process of the semiconductor substrate 100 illustrated in FIGS. 1 through 3 .
- the direction of the selective etching is along the Z-axis direction.
- the direction of the selective etching is along the Y-axis direction.
- a body region 950 may be separated from a substrate region 910 .
- the body region 950 may be disposed on an insulation region 930 .
- Materials included in the body region 950 have identical characteristics as materials included in the substrate region 910 .
- the thickness of the body region 950 may be adjusted by adjusting the selective etching position.
- FIGS. 12A through 12F are perspective views illustrating a method of manufacturing the semiconductor substrate 900 In FIG. 9 .
- insulation regions 930 may formed on the semiconductor substrate 900 .
- the insulation regions 930 may be formed in a substrate region 910 .
- a bulk substrate may be etched in along the minor axis direction (z-axis direction) to form a plurality of body line patterns 950 a that extend in the minor axis direction (z-axis direction).
- the insulation regions 930 may be filled between the body line patterns 950 a.
- the bulk substrate may be divided into the body line patterns 950 a, which are formed from a top surface of the bulk substrate to the bottom surface of the insulation regions 930 , and the substrate region 910 , which is the remaining lower portion of the bulk substrate.
- the body line patterns 950 a and the insulation regions 930 may have the same length.
- the bulk substrate is patterned from upper end portions (or sidewalls) of the bulk substrate to a desired width and length.
- the body line patterns 950 a and the insulation regions 930 may be patterned simultaneously to form a plurality of body patterns 950 _ 1 , 950 _ 2 and 950 _ 3 , collectively denoted as body pattern 950 b, on the substrate region 910 .
- Sides of the body line patterns 950 a and the insulation regions 930 may be etched in a Y direction that is perpendicular to the Z direction in which the body line patterns 950 a extend. As such, the plurality of body patterns 950 b extending in the Z direction are formed.
- portions that are not covered with the first mask 980 may be patterned.
- the mask 980 may be formed on sidewalls of the body patterns 950 b.
- a second mask 984 may be formed over sides of the body patterns 950 b.
- a third mask 986 may be formed over exposed tops of the substrate region 910 and the insulation regions 930 .
- the third mask 986 covering the exposed tops of the substrate region 910 and the insulation regions 930 may be removed.
- a plurality of body regions 950 may be formed by selectively etching a lower middle portion of the body patterns 950 b through the portions from which the mask 986 has been removed. Because a selective etching technique is used, the insulation regions 930 are not etched.
- the lower middle portion of the body patterns 950 b may be etched through top surfaces of the substrate region 910 , which are disposed on sides of the body patterns 950 b and have no mask (passivation layer) formed thereon.
- the mask 980 may be removed.
- the selective etching region may be filled with an insulating material to form the semiconductor substrate 900 illustrated in FIG. 9 .
- the masks 980 and 984 the passivation layer formed on top surfaces and sidewalls of the body regions 950 may be removed.
- the selectively etched region below the body regions 950 and spaces between the body regions 950 may be filled with the insulating material.
Abstract
Semiconductor substrates and methods of manufacturing the same are provided. The semiconductor substrates include a substrate region, an insulation region and a floating body region. The insulation region is disposed on the substrate region. The floating body region is separated from the substrate region by the insulation region and is disposed on the insulation region. The substrate region and the floating body region are formed of materials having identical characteristics. The method of manufacturing the semiconductor substrate including forming at least one floating body pattern by etching a bulk substrate, separating the bulk substrate into a substrate region and a floating body region by etching a lower middle portion of the floating body pattern, and filling an insulating material between the floating body region and the substrate region.
Description
- This application is a divisional application of U.S. application Ser. No. 12/219,360, filed on Jul. 21, 2008, which claims the benefit of priority under 35 U.S.C. §119 from Korean Patent Application No. 10-2008-0017419, filed on Feb. 26, 2008 in the Korean Intellectual Property Office, the disclosure of each of which is incorporated herein by reference in their entirety.
- 1. Field
- Example embodiments provide semiconductor substrates and methods of manufacturing a semiconductor substrate. Other example embodiments relate to semiconductor substrates including a floating body and methods of manufacturing a semiconductor substrate.
- 2. Description of the Related Art
- Generally, a 1-T dynamic random access memory (DRAM), which does not include a capacitor and uses one transistor, may be used. A 1-T DRAM may be manufactured using a fairly simple manufacturing process. A 1-T DRAM may have an increased sensing margin.
- If a 1-T DRAM is realized on a silicon-on-insulator (SOI) wafer, the manufacturing cost increases due to the SOI wafer. 1-T DRAMs are generally manufactured in an embedded form.
- Example embodiments provide semiconductor substrates and methods of manufacturing a semiconductor substrate. Other example embodiments relate to semiconductor substrates including a floating body and methods of manufacturing a semiconductor substrate.
- Example embodiments provide a method of manufacturing a semiconductor device in which a floating body region formed of a same material as a substrate region is realized using a selective etching technique.
- According to example embodiments, there is provided a semiconductor substrate including a substrate region, an insulation region formed on the substrate region, and a floating body region separated from the substrate region by the insulation region and disposed on the insulation region, wherein the substrate region and the floating body region are formed of materials having identical characteristics. The substrate region may be formed from a bulk semiconductor substrate.
- According to example embodiments, there is provided a method of manufacturing a semiconductor substrate including forming at least one floating body pattern by etching a bulk substrate, separating (or defining) the bulk substrate into a substrate region and a floating body region by etching a lower middle portion of the floating body pattern, and filling an insulating material between the floating body region and the substrate region.
- In separating the bulk substrate into the substrate region and the floating body region by etching the lower middle portion of the floating body pattern, the lower middle portion of the floating body pattern may be etched using a selective wet or dry etching method.
- Forming the at least one floating body pattern by etching the bulk substrate may include etching the bulk substrate in a first direction, which is a major axis direction, to form a floating body line pattern extending in the first direction, filling sides of the floating body line pattern with an insulating layer, and etching the floating body line pattern and the insulating layer in a second direction perpendicular to the first direction, in which the floating body line pattern is extended, to form at least one floating body pattern that is extended in the second direction.
- Separating the bulk substrate into the substrate region and the floating body region by etching a lower middle portion of the floating body pattern may include forming a passivation layer on sidewalls of the floating body pattern, and etching the lower middle portion of the floating body pattern through a bottom surface disposed on sides of the floating body pattern where the passivation layer is not formed.
- Forming the at least one floating body pattern by etching the bulk substrate may include etching the bulk substrate in a first direction to form a plurality of floating body line patterns extending parallel to each other in the first direction, filling an insulating layer between the floating body line patterns, and etching the bulk substrate in a second direction perpendicular to the first direction, in which the floating body line patterns are extended, to form a plurality of floating body patterns extending parallel to each other in the second direction.
- Separating the bulk substrate into the substrate region and the floating body region by etching the lower middle portion of the floating body pattern, may include forming a passivation layer on sidewalls of the floating body patterns, and etching the lower middle portion of the floating body patterns through a bottom surface where the passivation layer that is disposed between the floating body patterns is not formed.
- Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.
FIGS. 1-12F represent non-limiting, example embodiments as described herein. -
FIG. 1 is a perspective view of a semiconductor substrate according to example embodiments; -
FIG. 2 illustrates a substrate region and a body region in the semiconductor substrate ofFIG. 1 ; -
FIG. 3 illustrates an oxide region filled between the substrate region and the body region ofFIG. 2 ; -
FIG. 4 illustrates a semiconductor substrate according to example embodiments. -
FIG. 5 illustrates a semiconductor substrate according to example embodiments; -
FIGS. 6A through 6G are perspective views illustrating a method of manufacturing the semiconductor substrate according to example embodiments; -
FIG. 7 illustrates a word line pattern formed in asemiconductor substrate 400 according to example embodiments; -
FIGS. 8A through 8G are perspective views illustrating a method of manufacturing a semiconductor substrate according to example embodiments. -
FIG. 9 is a perspective view of a semiconductor substrate according to example embodiments; -
FIG. 10 illustrates a substrate region and a body region in the semiconductor substrate ofFIG. 9 ; -
FIG. 11 illustrates an insulation region filled between the substrate region and the body region inFIG. 10 ; and -
FIGS. 12A through 12F are perspective views illustrating a method of manufacturing the semiconductor substrate inFIG. 9 . - Various example embodiments will now be described more fully with reference to the accompanying drawings in which some example embodiments are shown. In the drawings, the thicknesses of layers and regions may be exaggerated for clarity.
- Detailed illustrative embodiments are disclosed herein. However, specific structural and functional details disclosed herein are merely representative for purposes of describing example embodiments. This invention may, however, may be embodied in many alternate forms and should not be construed as limited to only example embodiments set forth herein.
- Accordingly, while example embodiments are capable of various modifications and alternative forms, embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that there is no intent to limit example embodiments to the particular forms disclosed, but on the contrary, example embodiments are to cover all modifications, equivalents, and alternatives falling within the scope of the invention. Like numbers refer to like elements throughout the description of the figures.
- It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” etc.).
- The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.
- It will be understood that, although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the scope of example embodiments.
- Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or a relationship between a feature and another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the Figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, for example, the term “below” can encompass both an orientation which is above as well as below. The device may be otherwise oriented (rotated 90 degrees or viewed or referenced at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.
- Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, may be expected. Thus, example embodiments should not be construed as limited to the particular shapes of regions illustrated herein but may include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle may have rounded or curved features and/or a gradient (e.g., of implant concentration) at its edges rather than an abrupt change from an implanted region to a non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation may take place. Thus, the regions illustrated in the figures are schematic in nature and their shapes do not necessarily illustrate the actual shape of a region of a device and do not limit the scope.
- It should also be noted that in some alternative implementations, the functions/acts noted may occur out of the order noted in the figures. For example, two figures shown in succession may in fact be executed substantially concurrently or may sometimes be executed in the reverse order, depending upon the functionality/acts involved.
- Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
- In order to more specifically describe example embodiments, various aspects will be described in detail with reference to the attached drawings. However, the present invention is not limited to example embodiments described.
- Example embodiments provide semiconductor substrates and methods of manufacturing a semiconductor substrate. Other example embodiments relate to semiconductor substrates including a floating body and methods of manufacturing a semiconductor substrate.
-
FIG. 1 is a perspective view of asemiconductor substrate 100 according to example embodiments. - Referring to
FIG. 1 , thesemiconductor substrate 100 includes asubstrate region 110, abody region 150 and/or aninsulation region 130. - The
insulation region 130 may be disposed on thesubstrate region 110. Thebody region 150 may be separated from thesubstrate region 110. Thebody region 150 may be disposed on theinsulation region 130. Thebody region 150 may be a floating body region. Thesubstrate region 110 and thebody region 150 may be formed of materials having identical characteristics. - The
insulation region 130 may be formed of a silicon oxide or another insulation material. Theinsulation region 130 may be formed of two or more insulation materials. - The
semiconductor substrate 100 may include a plurality of body regions 150_1, 150_2, 150_3 (collectively referred to as the body region 150) that are arranged parallel to each other. A plurality of insulating layers (not shown) may be formed between the body regions 150_1, 150_2, 150_3. The insulating layers separate the body regions 150_1, 150_2, 150_3. The insulating layers disposed between the body regions 150_1, 150_2, 150_3 may be connected to theinsulation region 130. - To manufacture the
semiconductor substrate 100, a bulk substrate may be separated into an upper end portion and a lower end portion by selectively etching a center portion of the bulk substrate. The separated upper and lower end portions may be thebody region 150 and thesubstrate region 110, respectively. - At least one of the body regions 150_1, 150_2, 150_3 may be formed by forming at least one body pattern (not shown) extending in a desired direction on the bulk substrate and etching a lower middle portion of the body pattern.
-
FIG. 2 illustrates thesubstrate region 110 and thebody region 150 of thesemiconductor substrate 100.FIG. 3 illustrates theinsulation region 130 between thesubstrate region 110 and thebody region 150 ofsemiconductor substrate 100. - Referring to
FIGS. 2 and 3 , thesubstrate region 110 and thebody region 150 may be separated from each other. Because thesubstrate region 110 and thebody region 150 are formed from an identical substrate, thesubstrate region 110 and thebody region 150 include identical materials. A more detailed description of the process of etching the center portion of the substrate may be obtained by referring to the article entitled “Sphere-Shaped-Recess-Channel-Array Transistor (S-RCAT) Technology for 70 nm DRAM Feature Size and Beyond,” 2005 Symposium on VLSI Technology Digest of Technical Papers, the entire contents of which are incorporated in this application. - If it is assumed that the
body region 150 is manufactured through an epitaxial growing process on thesubstrate region 110, materials included in thebody region 150 have different characteristics than materials included in thesubstrate region 110. - The semiconductor substrate according to example embodiments may be formed from a bulk semiconductor substrate. The
body region 150 may be formed from a bulk semiconductor substrate by selectively etching a center portion of the bulk semiconductor substrate. Compared to a semiconductor substrate in which the insulation region is formed on the substrate region and the body region is formed on the insulation region through an epitaxial growing process, the semiconductor substrate according to example embodiments may be manufactured at lower costs. -
FIG. 4 illustrates asemiconductor substrate 200 according to example embodiments. A description of like elements inFIG. 4 as described above with reference toFIGS. 1-3 will be omitted for the sake of brevity. - Referring to
FIG. 4 , a body region 250 may be formed with a decreased thickness. The thickness of the body region 250 is smaller than the thickness of thebody region 150 of thesemiconductor substrate 100 shown inFIG. 1 . According to example embodiments, the thickness of the body region of the semiconductor substrate may vary. - During manufacturing of the semiconductor substrate according to example embodiments, the thickness of the body region may be adjusted by adjusting the selective etching position. For example, the thickness of the
body region 150 may be increased by selectively etching a region near a lower end portion of the bulk substrate. The thickness of the body region 250 may be reduced by selectively etching a region near an upper end portion of the bulk substrate. - If the body region is manufactured through an epitaxial growing process, the thickness of the body region may not exceed a desired thickness.
-
FIG. 5 illustrates asemiconductor substrate 300 according to example embodiments. - Referring to
FIG. 5 , a plurality ofbody regions 350 may be formed in thesemiconductor substrate 300. By selectively etching a center portion of thesemiconductor substrate 300, thebody regions 350 may be separated from asubstrate region 310. An insulating material may be filled between thebody regions 350 and thesubstrate region 310 to forminsulation regions 330. - The
body regions 350 may be formed by forming a plurality of body patterns extending in a desired direction on the bulk substrate and etching regions of the bulk substrate below the body patterns. - In
FIG. 5 , the plurality ofbody regions 350 may be formed in one direction and uniform in size. However, example embodiments are not limited thereto. For example, the plurality ofbody regions 350 may be arranged in different directions and/or have different sizes as illustrated inFIGS. 1 through 3 . For example, the plurality ofbody regions 150 may be arranged in an array on onesubstrate region 110. -
FIGS. 6A through 6G are perspective views illustrating a method of manufacturing asemiconductor substrate 100 according to example embodiments. - Referring to
FIG. 6A , thesemiconductor substrate 100 may be patterned from upper end portions of the semiconductor substrate to a desired width and length. Thesemiconductor substrate 100 may be a bulk semiconductor substrate generated (or formed) from a bulk wafer. - Patterning the
semiconductor substrate 100 forms abody line pattern 150 a disposed between the patterned portions and asubstrate region 110 below thebody line pattern 150 a. The patterning width may vary according to the desired width of thebody line pattern 150 a. The patterning length may vary according to the desired thickness of thebody line pattern 150 a. - Herein, the body region may be referred to as a
body line pattern 150 a (orbody pattern 150 b) before being separated from thesubstrate region 110, and abody region 150 after being separated from thesubstrate region 110. - Referring to
FIG. 6B , an insulating material may be filled in the patterned portions to forminsulation regions 130.Insulation regions 130 may be disposed at sides of thebody line pattern 150 a. If thebody line pattern 150 a is separated from thesubstrate region 110 using a selective etching technology to form thebody region 150, theinsulation regions 130 may support thebody region 150. - Referring to
FIG. 6C , thebody line pattern 150 a and theinsulation regions 130 may be patterned in a Z direction. Thebody line pattern 150 a and theinsulation regions 130 may be separated into a plurality ofbody patterns 150 b and a plurality ofinsulation regions 130. InFIG. 6C , thebody line pattern 150 a and theinsulation regions 130 may be patterned from a top of thebody line pattern 150 a and theinsulation regions 130 to a desired length. - The
region 150 a illustrated inFIGS. 6A and 6B may be referred to as a body line pattern, and theregion 150 b illustrated inFIG. 6C may be referred to as body patterns. - Referring to
FIG. 6A , a bulk substrate is patterned in a first direction (Y direction), which is a major axis direction, to form abody line pattern 150 a extending in the first direction (Y direction). - Referring to
FIG. 6B , sides of thebody line pattern 150 a inFIG. 6A may be filled with insulating regions (or layers) 130. Referring toFIG. 6C , thebody line pattern 150 a and the insulatingregions 130 may be etched in a second direction (Z direction) that is perpendicular to the first direction (Y direction) in which thebody line pattern 150 a is extended to form at least onebody pattern 150 b extending in the second direction (Z direction). - The height of the
body patterns 150 b may be lower than that of thebody line pattern 150 a. - After forming a
mask 180 on portions of thebody patterns 150 b and the insulation regions 130 (excluding portions to be patterned), a patterning process may be performed only on portions not covered by themask 180. As such, portions that are not covered by themask 180 may be patterned. - Referring to
FIGS. 6D and 6E , patterned inner surfaces of thebody patterns 150 b and theinsulation regions 130 may be covered by a first mask (a passivation layer) 184. Bottom surfaces of thebody patterns 150 b and theinsulation regions 130 may be covered by asecond mask 186. Thesecond mask 186 on the bottom surfaces may be removed. - Referring to
FIG. 6F , a lower middle portion of thebody patterns 150 b may be selectively etched, exposing abottom surface 188 of thebody patterns 150 b and anupper surface 189 of thesubstrate region 110. The lower middle portion of thebody patterns 150 b may be selectively etched through the bottom surfaces 188, from which thesecond mask 186 has been removed. - After forming the first mask (the passivation layer) 184 on sidewalls of the
body patterns 150 b, the lower middle portion of thebody pattern 150 b may be etched through the bottom surfaces 188 (as shown inFIG. 6E ), which are disposed on sides of thebody patterns 150 b and on which the first mask (the passivation layer) 184 is not formed. As such, the bulk substrate may be separated into asubstrate region 110 and abody region 150. Thesubstrate region 110 may be disposed under the selectively etched region and thebody region 150 may be disposed on the selectively etched region. - The selective etching process may be a selective wet etching method or a selective dry etching method, which is used to etch the lower middle portion of the
body patterns 150 b. - Referring to
FIG. 6G , the selectively etched region of thebody patterns 150 b and thesubstrate region 100 may be filled with an insulating material. After removing the first mask (the passivation layer) 184 on top surfaces and sidewalls of thebody patterns 150 b, the selectively etched region may be filled with an insulating material. Spaces between thebody patterns 150 b may be filled with the insulating material. - The process illustrated in
FIGS. 6A through 6G may be used to manufacture thesemiconductor substrate 300 ofFIG. 5 in which a plurality of body regions are formed. For example, similar toFIG. 6A , several portions of the bulk substrate illustrated inFIG. 5 may be etched parallel to each other in the first direction to form a plurality of body line patterns extending parallel to each other in the first direction. As shown inFIG. 6B , insulating layers may be filled between the body line patterns. As shown inFIG. 6C , the bulk substrate may be etched in the second direction, which is perpendicular to the first direction, to form a plurality of body patterns extending parallel to each other in the second direction. (InFIG. 5 , one body pattern from among the plurality of body patterns formed from a body line pattern is illustrated.) As shown inFIG. 6D , a passivation layer may be formed on sidewalls of the body patterns. As shown inFIG. 6F , the lower middle portion of the body patterns may be etched through a bottom surface wherein the passivation layer disposed between the body patterns is not formed. As shown inFIG. 6G , the etched regions and spaces between the body patterns may be filled with an insulating material. -
FIG. 7 illustrates a word line pattern formed on asemiconductor substrate 400 according to example embodiments. - In
FIG. 7 , asubstrate region 410, abody region 450 and aninsulation region 430 are formed using a similar method as described with reference tosemiconductor substrate 100. Thus, a description of like elements will not be repeated for the sake of brevity. - Referring to
FIG. 7 , in thesemiconductor substrate 400, aword line pattern 472 may be formed on (or over) thebody region 450. A plurality of impurity doping regions (not shown) may be formed on thebody region 450. Semiconductor devices according to example embodiments may be used as a bipolar junction transistor (BJT). If thesemiconductor substrate 400 is used a BJT, a portion of theword line pattern 472 may function as a base of a transistor. For example, the portion of theword line pattern 472 passing (or over) an upper end of thebody region 450 may function as the base of the transistor. The impurity doping regions (not shown) may respectively function as an emitter and collector. - However, example embodiments are not limited thereto. The semiconductor devices according to example embodiments may be realized as various circuit devices other than the BJT. For example, the semiconductor devices may be realized as another type of transistor, a memory device, a sensor or a switching unit structure. As such, a pattern other than the
word line pattern 472 may be formed on (or over) thebody region 450. -
FIGS. 8A through 8G are perspective views illustrating a method of manufacturing asemiconductor substrate 800 according to example embodiments. - Referring to
FIG. 8A , a bulk substrate may be etched in a first direction (Y direction), which is a major axis direction, to form abody line pattern 850 a extended in the first direction (Y direction). - Referring to
FIG. 8B , sides of thebody line pattern 850 a may be filled with insulatinglayers 830. As the processes ofFIGS. 8A and 8B are identical to the processes ofFIGS. 6A and 6B , description of like elements thereof will be omitted for the sake of brevity. - Referring to
FIG. 8C , thebody line pattern 850 a illustrated inFIG. 8B is patterned in a Z direction. At least onebody pattern 850 b may be formed by etching thebody line pattern 850 a (excluding the insulating layers 830) in the first direction (Y direction) in which thebody line pattern 850 a is extended and in the second direction (Z direction) that is perpendicular to the first direction. Theinsulation layer 830 is not patterned inFIG. 8C . InFIG. 8C , thebody pattern 850 b may be patterned to a desired length from a top surface of thebody pattern 850 b. - After forming a
mask 880 on portions of thebody pattern 850 b (excluding portions to be patterned) and on theinsulation region 830, portions that are not covered by themask 880 may be patterned. - Referring to
FIGS. 8D and 8E , patternedinner surfaces 884 and bottom surfaces (not shown) of thebody pattern 850 b and theinsulation region 830 may be masked. The mask on the bottom surfaces (not shown) may be removed. A lower middle portion of thebody pattern 850 b may be selectively etched through the bottom surface, from which the masking is removed. - Referring to
FIG. 8F , the lower middle portion of thebody pattern 850 b may be selectively etched, exposing abottom surface 888 of thebody pattern 850 b and anupper surface 889 of thesubstrate region 810. - Referring to
FIG. 8G , the selectively etched region of thebody pattern 850 b and thesubstrate region 810 may be filled with an insulating material. As such, thesemiconductor 800 ofFIG. 8G and thesemiconductor substrate 100 ofFIG. 6G may have the same form (or structure). -
FIG. 9 is a perspective view of asemiconductor substrate 900 according to example embodiments. -
FIG. 10 illustrates a substrate region and a body region of thesemiconductor substrate 900. -
FIG. 11 illustrates an insulation region between the substrate region and the body region of thesemiconductor substrate 900. - In the manufacturing process of the
semiconductor substrate 900 illustrated inFIGS. 9 through 11 , the direction of the selective etching process is different from the manufacturing process of thesemiconductor substrate 100 illustrated inFIGS. 1 through 3 . In the manufacturing process of thesemiconductor substrate 100 illustrated inFIGS. 1 through 3 , the direction of the selective etching is along the Z-axis direction. In the manufacturing process of thesemiconductor substrate 900 illustrated inFIGS. 9 through 11 , the direction of the selective etching is along the Y-axis direction. - In the
semiconductor substrate 900 illustrated inFIGS. 9 through 11 , abody region 950 may be separated from asubstrate region 910. Thebody region 950 may be disposed on aninsulation region 930. Materials included in thebody region 950 have identical characteristics as materials included in thesubstrate region 910. - The thickness of the
body region 950 may be adjusted by adjusting the selective etching position. -
FIGS. 12A through 12F are perspective views illustrating a method of manufacturing thesemiconductor substrate 900 InFIG. 9 . - Referring to
FIG. 12A ,insulation regions 930 may formed on thesemiconductor substrate 900. Theinsulation regions 930 may be formed in asubstrate region 910. A bulk substrate may be etched in along the minor axis direction (z-axis direction) to form a plurality ofbody line patterns 950 a that extend in the minor axis direction (z-axis direction). Theinsulation regions 930 may be filled between thebody line patterns 950 a. The bulk substrate may be divided into thebody line patterns 950 a, which are formed from a top surface of the bulk substrate to the bottom surface of theinsulation regions 930, and thesubstrate region 910, which is the remaining lower portion of the bulk substrate. Thebody line patterns 950 a and theinsulation regions 930 may have the same length. - Referring to
FIG. 12B , the bulk substrate is patterned from upper end portions (or sidewalls) of the bulk substrate to a desired width and length. Thebody line patterns 950 a and theinsulation regions 930 may be patterned simultaneously to form a plurality of body patterns 950_1, 950_2 and 950_3, collectively denoted asbody pattern 950 b, on thesubstrate region 910. Sides of thebody line patterns 950 a and theinsulation regions 930 may be etched in a Y direction that is perpendicular to the Z direction in which thebody line patterns 950 a extend. As such, the plurality ofbody patterns 950 b extending in the Z direction are formed. - After forming a
first mask 980 over portions of thebody patterns 950 b and the insulation regions 930 (excluding portions to be patterned), portions that are not covered with thefirst mask 980 may be patterned. For example, themask 980 may be formed on sidewalls of thebody patterns 950 b. - Referring to
FIG. 12C , asecond mask 984 may be formed over sides of thebody patterns 950 b. Athird mask 986 may be formed over exposed tops of thesubstrate region 910 and theinsulation regions 930. - Referring to
FIG. 12D , thethird mask 986 covering the exposed tops of thesubstrate region 910 and theinsulation regions 930 may be removed. - Referring to
FIG. 12E , a plurality ofbody regions 950 may be formed by selectively etching a lower middle portion of thebody patterns 950 b through the portions from which themask 986 has been removed. Because a selective etching technique is used, theinsulation regions 930 are not etched. The lower middle portion of thebody patterns 950 b may be etched through top surfaces of thesubstrate region 910, which are disposed on sides of thebody patterns 950 b and have no mask (passivation layer) formed thereon. - Referring to
FIG. 12F , themask 980 may be removed. The selective etching region may be filled with an insulating material to form thesemiconductor substrate 900 illustrated inFIG. 9 . Namely, themasks 980 and 984 (the passivation layer) formed on top surfaces and sidewalls of thebody regions 950 may be removed. The selectively etched region below thebody regions 950 and spaces between thebody regions 950 may be filled with the insulating material. - The foregoing is illustrative of example embodiments and is not to be construed as limiting thereof. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in example embodiments without materially departing from the novel teachings and advantages. Accordingly, all such modifications are intended to be included within the scope of this invention as defined in the claims. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function, and not only structural equivalents but also equivalent structures. Therefore, it is to be understood that the foregoing is illustrative of various example embodiments and is not to be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims.
Claims (9)
1. A semiconductor substrate, comprising:
an insulation region on a substrate region; and
a floating body region separated from the substrate region by the insulation region and disposed on the insulation region,
the substrate region and the floating body region being formed of materials having identical characteristics.
2. The semiconductor substrate of claim 1 , wherein the substrate region is formed from a bulk semiconductor substrate.
3. The semiconductor substrate of claim 1 , wherein the insulation region is formed of a silicon oxide.
4. The semiconductor substrate of claim 1 , wherein the floating body region includes a plurality of floating body patterns disposed parallel to the floating body region.
5. The semiconductor substrate of claim 4 , further comprising a plurality of insulating layers between the plurality of floating body patterns, the plurality of insulating layers separating the plurality of floating body patterns from one another.
6. The semiconductor substrate of claim 5 , wherein the plurality of insulating layers are connected to the insulation region.
7. The semiconductor substrate of claim 1 , wherein a thickness of the floating body region varies.
8. The semiconductor device of claim 1 , further comprising a device structure on the floating body region.
9. The semiconductor device of claim 8 , wherein the device structure is one selected from the group consisting of a transistor, a memory device, a sensor and a switching unit.
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US12/929,455 US20110121390A1 (en) | 2008-02-26 | 2011-01-26 | Semiconductor substrates and manufacturing methods of the same |
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KR1020080017419A KR20090092103A (en) | 2008-02-26 | 2008-02-26 | Semiconductor substrate and manufacturing method of semiconductor substrate |
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US12/219,360 US7902007B2 (en) | 2008-02-26 | 2008-07-21 | Semiconductor substrates and manufacturing methods of the same |
US12/929,455 US20110121390A1 (en) | 2008-02-26 | 2011-01-26 | Semiconductor substrates and manufacturing methods of the same |
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US12/219,360 Division US7902007B2 (en) | 2008-02-26 | 2008-07-21 | Semiconductor substrates and manufacturing methods of the same |
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US12/929,455 Abandoned US20110121390A1 (en) | 2008-02-26 | 2011-01-26 | Semiconductor substrates and manufacturing methods of the same |
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JP2007234926A (en) * | 2006-03-02 | 2007-09-13 | Seiko Epson Corp | Semiconductor device and manufacturing method therefor |
US7537994B2 (en) * | 2006-08-28 | 2009-05-26 | Micron Technology, Inc. | Methods of forming semiconductor devices, assemblies and constructions |
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2008
- 2008-02-26 KR KR1020080017419A patent/KR20090092103A/en not_active Application Discontinuation
- 2008-07-21 US US12/219,360 patent/US7902007B2/en not_active Expired - Fee Related
-
2009
- 2009-02-19 CN CN2009100080359A patent/CN101521211B/en not_active Expired - Fee Related
- 2009-02-25 JP JP2009042823A patent/JP2009206515A/en active Pending
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2011
- 2011-01-26 US US12/929,455 patent/US20110121390A1/en not_active Abandoned
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US5372952A (en) * | 1992-04-03 | 1994-12-13 | National Semiconductor Corporation | Method for forming isolated semiconductor structures |
US6277703B1 (en) * | 1998-05-15 | 2001-08-21 | Stmicroelectronics S.R.L. | Method for manufacturing an SOI wafer |
US6214653B1 (en) * | 1999-06-04 | 2001-04-10 | International Business Machines Corporation | Method for fabricating complementary metal oxide semiconductor (CMOS) devices on a mixed bulk and silicon-on-insulator (SOI) substrate |
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US7902007B2 (en) | 2011-03-08 |
JP2009206515A (en) | 2009-09-10 |
CN101521211B (en) | 2012-12-19 |
US20090212364A1 (en) | 2009-08-27 |
KR20090092103A (en) | 2009-08-31 |
CN101521211A (en) | 2009-09-02 |
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