US20110104891A1 - Methods and apparatus of creating airgap in dielectric layers for the reduction of rc delay - Google Patents

Methods and apparatus of creating airgap in dielectric layers for the reduction of rc delay Download PDF

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US20110104891A1
US20110104891A1 US12986809 US98680911A US2011104891A1 US 20110104891 A1 US20110104891 A1 US 20110104891A1 US 12986809 US12986809 US 12986809 US 98680911 A US98680911 A US 98680911A US 2011104891 A1 US2011104891 A1 US 2011104891A1
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dielectric
material
layer
dielectric layer
air gaps
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Amir Al-Bayati
Alexandros T. Demos
Kang Sub Yim
Mehul Naik
Zhenjiang David Cui
Mihaela Balseanu
Meiyee Maggie Le Shek
Li-Qun Xia
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Applied Materials Inc
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Applied Materials Inc
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    • HELECTRICITY
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    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • HELECTRICITY
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/3105After-treatment
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    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • HELECTRICITY
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31144Etching the insulating layers by chemical or physical means using masks
    • HELECTRICITY
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
    • HELECTRICITY
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    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • HELECTRICITY
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • HELECTRICITY
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885By forming conductive members before deposition of protective insulating material, e.g. pillars, studs

Abstract

A method and apparatus for generating air gaps in a dielectric material of an interconnect structure. One embodiment provides a method for forming a semiconductor structure comprising depositing a first dielectric layer on a substrate, forming trenches in the first dielectric layer, filling the trenches with a conductive material, planarizing the conductive material to expose the first dielectric layer, depositing a dielectric barrier film on the conductive material and exposed first dielectric layer, depositing a hard mask layer over the dielectric barrier film, forming a pattern in the dielectric barrier film and the hard mask layer to expose selected regions of the substrate, oxidizing at least a portion of the first dielectric layer in the selected region of the substrate, removing oxidized portion of the first dielectric layer to form reversed trenches around the conductive material, and forming air gaps in the reversed trenches while depositing a second dielectric material in the reversed trenches.

Description

    CROSS REFERENCE TO RELATED PATENT APPLICATIONS
  • This application is a Divisional Application of a pending U.S. Provisional patent application Ser. No. 11/869,396 (Attorney Docket No. 12174L), filed Oct. 9, 2007, which is herein incorporated by reference.
  • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • Embodiments of the present invention generally relate to the fabrication of integrated circuits. More particularly, embodiments of the present invention relate to methods for forming multilevel interconnect structures that include dielectric materials having low dielectric constants.
  • 2. Description of the Related Art
  • Integrated circuit geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore's Law), which means that the number of devices on a chip doubles every two years. Today's fabrication facilities are routinely producing devices having 0.1 μm feature sizes, and tomorrow's facilities soon will be producing devices having even smaller feature sizes.
  • The continued reduction in device geometries has generated a demand for films having low dielectric constant (k) values because the capacitive coupling between adjacent metal lines must be reduced to further reduce the size of devices on integrated circuits. For example, the scaling of CMOS (complementary field-effect transistor) device requires a continuous reduction to the RC (resistive capacitive) delay in the BEOL (Back-End-Of-the-Line) interconnects. To meet this requirement the dielectric constant (k) of the insulating layers used in the BEOL must be further reduced.
  • Over the last 10-15 years, the semiconductor industry went through many cycles in reducing the dielectric constant of the insulating layers, from using pure silicon dioxide (SiO2) with k=4.2 to the present day of porous carbon doped silicon oxide film, which comprises silicon, carbon, oxygen and hydrogen (commonly referred as SiCOH), with k=2.4. Conventional techniques generally use two methods to reduce k: (1) adding carbon to the SiO2 matrix and (2) adding porosity. However, these methods of reducing result in lower mechanical properties compared to that of SiO2. These low mechanical properties, such as low modulus, and low hardness, made it difficult to integrate such films with metal lines, for example copper lines, in the dual damascene flow, which is generally used in forming BEOL interconnects. Additionally, future technologies (32 nm node and beyond) will require higher porosity in the SiCOH films. However, the loss of mechanical properties with higher porosity would indicate a lower limit of k˜2.0 for this type of films.
  • Therefore, in view of the continuing decrease in integrated circuit feature sizes and existing problems in the conventional methods, there remains a need for a method of forming dielectric layers having dielectric constants lower than 2.0
  • SUMMARY OF THE INVENTION
  • The present invention generally provides methods for forming air gaps in a dielectric around conductive lines in the interconnect materials.
  • One embodiment provides a method for forming a semiconductor structure comprising depositing a first dielectric layer on a substrate, forming trenches in the first dielectric layer, filling the trenches with a conductive material, planarizing the conductive material to expose the first dielectric layer, depositing a dielectric barrier film on the conductive material and exposed first dielectric layer, depositing a hard mask layer over the dielectric barrier film, forming a pattern in the dielectric barrier film and the hard mask layer to expose selected regions of the substrate, oxidizing at least a portion of the first dielectric layer in the selected region of the substrate, removing oxidized portion of the first dielectric layer to form reversed trenches around the conductive material, and forming air gaps in the reversed trenches while depositing a second dielectric material in the reversed trenches.
  • In another embodiment, a porous dielectric material is used to form the trenches and an electron beam treatment is used to oxidize the porous dielectric material.
  • Yet another embodiment provides a method for forming a dielectric structure having air gaps comprising depositing a first dielectric layer on a substrate, depositing a second dielectric layer on the first dielectric layer, forming trench-via structures in the first and second dielectric layer, wherein vias are formed in the first dielectric layer and trenches are formed in the second dielectric layer, filling the trench-via structures with a conductive material, planarizing the conductive material to expose the second dielectric layer, depositing a dielectric barrier film on the conductive material and exposed second dielectric layer, forming a pattern in the dielectric barrier film and the hard mask layer to expose selected regions of the substrate, removing the second dielectric layer in the selected regions of the substrate to form reversed trenches around the conductive material filled in the trenches, and forming air gaps in the reversed trenches while depositing a dielectric material in the reversed trenches.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
  • FIG. 1 is a flow chart showing a method for forming air gaps in interconnect in accordance with one embodiment of the present invention.
  • FIG. 2A is a flow chart showing a process sequence for forming trench-via structures in accordance with one embodiment of the present invention.
  • FIG. 2B a flow chart showing a process sequence for forming trench-via structures in accordance with another embodiment of the present invention.
  • FIG. 3A is a flow chart showing a process sequence for removing portions of dielectric material in accordance with one embodiment of the present invention.
  • FIG. 3B is a flow chart showing a process sequence for removing portions of dielectric material in accordance with another embodiment of the present invention.
  • FIG. 4A is a flow chart showing a process sequence for forming a dielectric layer having air gaps in accordance with one embodiment of the present invention.
  • FIG. 4B is a flow chart showing a process sequence for forming a dielectric layer having air gaps in accordance with another embodiment of the present invention.
  • FIGS. 5A-5G schematically illustrate formation of a substrate stack having air gaps in accordance with one embodiment of the present invention.
  • FIGS. 6A-6C schematically illustrate formation of a substrate stack having air gaps in accordance with another embodiment of the present invention.
  • FIG. 7 schematically illustrates a substrate stack having trench via structures formed using the process sequence of FIG. 2B.
  • FIGS. 8A-8B schematically illustrate formation of a substrate stack having air gaps in accordance with one embodiment of the present invention.
  • FIGS. 9A-9B schematically illustrate formation of a substrate stack having air gaps in accordance with one embodiment of the present invention.
  • FIG. 10 schematically illustrates relationships of air gap fraction with effective dielectric constant and ratio of capacitance reduction for a barrier dielectric with k=5.1.
  • FIG. 11 schematically illustrates relationships of air gap fraction with effective dielectric constant and ratio of capacitance reduction for a barrier dielectric with k=2.5.
  • To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation.
  • DETAILED DESCRIPTION
  • Embodiments of the present invention provide method for forming air gaps between conductive lines to reduce the dielectric constant k and to reduce RC delay in BEOL interconnects.
  • Embodiments of the present invention provide methods for forming air gaps in a trench level during fabrication of interconnects. The methods comprise forming conductive lines in a porous low k dielectric material, then removing portions of the porous low k dielectric material to create trenches around the conductive lines, and forming air gaps in the trenches around the conductive lines while depositing a non-uniform dielectric material therein. Depending on the fraction of air gaps in the dielectric material, the dielectric constant of the dielectric material may be reduced by about 25% to about 50%. The methods of the present invention may extend utility of porous low k dielectric material to fabricating devices with critical dimension of 22 nm and beyond. The methods may be applied to any trench level and are economical to perform because steps of forming air gaps are easily incorporated in to the flow of damascene process.
  • FIG. 1 is a flow chart showing a method 100 for forming air gaps in interconnect in accordance with one embodiment of the present invention. BEOL interconnect generally includes multiple levels of interconnect structures, typically including alternate trench layers and via layers of conductive materials and dielectrics. A trench layer generally refers to a dielectric film having conductive lines formed therein. A via layer is a layer of dielectrics having small metal vias that provide electrical pathways from one trench layer to another trench layer. The method 100 may be applied in any level of the interconnects.
  • In step 110 of the method 100, a trench layer having metal structures in a low k porous dielectric material is formed. The trench layer may be formed by itself, for example above a contact layer of devices formed in a semiconductor substrate. In other cases, the trench layer may be formed along with a via layer using any suitable process sequences, for example commonly used damascene process. The trench layer is generally formed from a low k dielectric base which is removable for subsequent air gap formation. In one embodiment, the via layer is also formed in the low k dielectric layer, as illustrated in a process sequence 110 a shown in FIG. 2A. In another embodiment, the via layer is formed in a different dielectric material, as illustrated in a process sequence 110 b shown in FIG. 2B.
  • After the formation of the trench layer, selected portions of the low k porous dielectric may be removed so that reversed trenches are formed around the metal structures in the trench layer, as shown in step 130. In one embodiment, the porous low k dielectric material may be removed by oxidizing controlled thickness of the porous low k dielectric followed by a wet etching step, as shown in a process sequence 130 a of FIG. 3A. In another embodiment, when the trench layer and the via layer underneath are formed in different dielectric materials, selected regions of the low k porous material in the dielectric layer may be removed by a masked etching process, as illustrated in a process sequence 130 b shown in FIG. 3B.
  • After removing the selected portion of the porous low k dielectric material in the trench layer, air gaps may be formed in the reversed trenches by deposition a non-conformal layer of a dielectric material, as shown in step 150 of FIG. 1. In one embodiment, the air gaps may be formed by depositing a non-conformal layer of dielectric barrier, as shown in a process sequence 150 a of FIG. 4A. In another embodiment, the air gaps may be formed while filling the reversed trenches with an interlayer dielectric material, as shown in a process sequence 150 b of FIG. 4B.
  • Upon the formation of the air gaps, fabrication of the trench layer is completed, a new layer of low k porous dielectric material may be deposited and cured directly or indirectly on the trench layer, as shown in step 170 of FIG. 1.
  • In step 180, a new trench-via layer having metal structures may be formed in the new layer of low k porous dielectric material. Air gaps may be formed in the new low k porous dielectric material using steps 130 and 150 if so desired.
  • Air gaps may be formed in dielectric layers using the method 100. Different embodiments are available using combinations of different process sequences for steps 110, 130, 150. Four exemplary embodiments are described below.
  • Embodiment 1
  • FIGS. 5A-5G schematically illustrate formation of a substrate stack 200 a having air gaps in accordance with one embodiment of the present invention. The substrate stack 200 a are formed using the process sequence 110 a of FIG. 2A, followed by the process sequence 130 a of FIG. 3A, followed by the process sequence 150 a of FIG. 4A.
  • Referring to FIG. 5A, a via layer 202 and a trench layer 203 are formed on a preexisting layer 201, which includes a conductive line 210. FIG. 2A illustrates a step 110 that may be used to form the via layer 202 and the trench layer 203 as shown.
  • In step 111 of the process sequence 110 a, a dielectric barrier film 211 is deposited all over the preexisting layer 201. The dielectric barrier film 211 is configured to prevent diffusion of conductive materials, for example metals for the conductive line 210, into a subsequent dielectric layer. The dielectric barrier film 211 generally comprises a barrier dielectric material, such as silicon nitride, silicon oxycarbide, amorphous hydrogenated silicon carbide, or nitrogen doped silicon carbide (BLOk™).
  • In step 112, a porous low k dielectric material 212 is formed over the dielectric barrier film 211. The porous low k dielectric material 212 has a thickness sufficient to form both the via layer 202 and the trench layer 203. Forming the porous low k dielectric material 212 generally comprises depositing a silicon/oxygen containing material that further contains labile organic group, and curing the silicon/oxygen containing material to form microscopic gas pockets that uniformly dispersed in the layer. Curing the porous low k material 212 t may include electron beam (e-beam) treatments, ultraviolet (UV) treatments, thermal annealing treatments (in the absence of an electron beam and/or UV treatment), and combinations thereof.
  • The porous low k dielectric material 212 generally has a dielectric constant lower than 2.5. Detailed description of exemplary methods for forming the porous low k dielectric material 212 may be found in the United States Patent Application Publication No. 2005/0233591, entitled “Techniques Promoting Adhesion of Porous Low K Film to Underlying Barrier Layer”, which is incorporated herein by reference.
  • In step 113, trench-via structures are formed in the porous low k dielectric material 212. The trench-via structures comprises trenches 205 formed above vias 204 and may be formed using damascene methods. Exemplary methods for forming the trench-via structures in one dielectric layer may be found in the U.S. Pat. No. 6,753,258, entitled “Integration Scheme for Dual Damascene Structure”, which is incorporated herein by reference.
  • In step 114, a metallic diffusion barrier 213 is lined on the surface of the trench-via structure. The metallic diffusion barrier 213 is configured to prevent diffusion between metal lines subsequently deposited in the trenches and the dielectric structures nearby. The metallic diffusion barrier 213 may comprise tantalum (Ta) and/or tantalum nitride (TaN).
  • In step 115, the trench-via structures is filled with conductive lines 214 comprising one or more metals. In one embodiment, a sputtering step may be performed to remove the metallic diffusion barrier 213 from entire or portions of bottom walls of the trench-via structures, so that the conductive lines 214 may be in direct contact with the conductive lines 210 of the preexisting layer 201. Depositing the conductive lines 214 may comprise forming a conductive seed layer and depositing a metal on the conductive seed layer. The conductive lines 214 may comprise copper (Cu), aluminum (Al), or any suitable material with desirable electrical conductivity.
  • In step 116, a chemical mechanical polishing (CMP) process is performed on the conductive lines 214, and the metallic diffusion barrier 213 so that the porous low k dielectric 212 is exposed on a top surface 215 of the substrate stack 200 a, as shown in FIG. 5A.
  • Upon the formation the via layer 202 and the trench layer 203, portions of the porous low k dielectric 212 in the trench layer 203 may be removed so that air gaps may be formed between the conductive lines 214.
  • The process sequence 130 a shown in FIG. 3A may be used to remove the porous low k dielectric 212.
  • In step 131, a dense dielectric barrier film 216 is deposited over the top surface 215, as shown in FIG. 5B. The dense dielectric barrier film 216 is configured to prevent diffusion of metals, such as copper, in the conductive lines 214, and migration of wet etching chemistry to the conductive lines 214 in the subsequent process. The dense dielectric barrier 216 may comprises a thin low k dielectric barrier film, such as silicon carbide (SiC), silicon carbide nitride (SiCN), boron nitride (BN), silicon boron nitride (SiBN), silicon boron carbide nitride (SiBCN), or combinations thereof.
  • In step 133, a hard mask layer 217 is deposited over the dense dielectric barrier film 216, as shown in FIG. 5B. The hard mask layer 217 is configured to provide patterning to the substrate stack in a thermal process. The hard mask layer 217 may comprises silicon oxide.
  • In step 135, a pattern 219 is formed in the hard mask layer 217 and the dense dielectric barrier 216 using a photoresist 218, as shown in FIG. 5B. The pattern 219 exposes only portions of the substrate where air gaps are desired. It is desirable to form air gaps in areas densely packed with conductive lines. In one embodiment, air gaps may be formed in areas where the distance between neighboring conductive lines 214 is between about 100 nm to about 200 nm.
  • In step 137, an oxidizing process is performed to the porous low k dielectric material 212 exposed by the hard mask layer 217, as shown in FIG. 5C. In one embodiment, the oxidizing process may be performed by dispensing energy to the porous low k dielectric material 212 using an electron beam (E-beam) in an ambient of inert gas and/or oxygen. E-beam treated porous dielectric 220 has increased wet etching rate and may be selectively removed. Experiments have shown that E-beam treatment in accordance with embodiments of the present invention may increase the wet etching rate (WER) of the low k porous dielectric material 212 by about 100 times. For example, the etching rate of a porous low k dielectric material after UV curing (which forms nanosized air bubbles in the dielectric) is about 0.219 Å/min in a 100:1 dilute hydrogen fluoride (DHF) solution. While the same material after an E-beam treatment may have a wet etch rate of about 30 Å/min in a 100:1 DHF solution. Thus, the porous low k dielectric material 212 may be selectively removed using wet etching process after exposing selected portion to the E-beam treatment.
  • An E-beam treatment apparatus generally includes a vacuum chamber, a large-area cathode, a target or substrate to be treated located in field-free region, and an anode placed between the target and the cathode at a distance from the cathode that is less than the mean free path length of electrons emitted therefrom. An E-beam apparatus further comprises a high voltage power supply connected to the cathode and a low voltage power supply connected to the anode.
  • During processing, gas in a space between the cathode and the target may become ionized to initiate electron emission. This occurs as a result of naturally occurring gamma rays, or emission can instead be initiated artificially inside the chamber by a high voltage spark gap. Once this initial ionization takes place, positive ions are attracted to the anode by a slightly negative voltage being applied to the anode. These positive ions pass into an accelerating field region between the cathode and the anode, and are accelerated towards the cathode surface as a result of the high voltage applied to the cathode. Upon striking the surface of the cathode, these high energy ions produce secondary electrons that are accelerated back toward the anode. Some of these electrons (which are now traveling mostly perpendicular to the cathode surface) strike the anode, but many pass through the anode and continue on to the target, thus, performing an E-beam treatment to the substrate. Detailed description on apparatus and method for an E-beam treatment may be found in U.S. Pat. No. 6,936,551, entitled “Method and Apparatus for E-beam Treatment Used to Fabricate Integrated Circuit Devices”, which is incorporated herein by reference. The E-beam treatment may be performed in an EBk™ electron beam chamber available from Applied Materials, Inc. of Santa Clara, Calif.
  • The E-beam treatment may be performed in an inert ambient, such as argon. In another embodiment, the E-beam treatment may also be performed in an oxygen environment, for example in an ambient of pure oxygen or mixture of inert gas and oxygen.
  • One embodiment of the present invention comprises controlling the depth of the E-beam treated porous dielectric 220. The depth of the E-beam treated porous dielectric 220 is determined by the depth to which impinging electrons penetrate the dielectric layer before being absorbed. The depth generally depends on many factors (including the particular material which is being treated). One of the most critical of which is the energy of the electron beam as determined by the accelerating voltage. In one embodiment of the present invention, the depth of the E-beam treatment may be controlled using the following equation:
  • Depth = 0.046 ( V acc ) a ρ ( 1 )
  • wherein Depth is treatment depth in Angstroms, Vacc is voltage applied to the cathode in keV, a is a constant, and p is density of the film being processed in gm/cm3. In one embodiment, for the porous low k dielectric material 212 having a dielectric constant k=2.35 and a density of p=1.08 gm/cm3, the depth of treatment may be calculated using a=1.80.
  • Alternatively, the oxidizing process may be performed by exposing the selected areas to ultra violet (UV) energy in an ambient with inert gas and/or oxygen gas.
  • In an optional step 139, a self-aligned capping layer 221 is formed on the conductive lines 214, as shown in FIG. 5D. The self-aligned capping layer 221 may be formed using electroless deposition and formed only on the exposed surface of the conductive lines 214. The self-aligned capping layer 221 is configured to be a barrier to protect the conductive lines 214 from wet etching chemistry used in air gap formation and to prevent diffusion of species across an upper surface of the conductive lines 210. The self-aligned capping layer 221 may prevent diffusion of both copper and oxygen. For the conductive lines 214 comprise copper, the self-aligned capping layer 221 may comprise a variety of compositions containing cobalt (Co), tungsten (W) or molybdenum (Mo), phosphorus (P), boron (B), rhenium (Re), and combinations thereof. Detailed descriptions for forming the self-aligned capping layer 221 may be found in the United States Patent Publication No. 2007/0099417, entitled “Adhesion and Minimizing Oxidation on Electroless Co Alloy Films for Integration with Low k Inter-Metal Dielectric and Etch Stop”, which are incorporated herein by reference.
  • In step 141, the E-beam treated porous dielectric 220 and the hard mask layer 217 are removed using a wet etching chemistry, as shown in FIG. 5E. The wet etching chemistry may be a DHF solution. Other wet etching chemicals, such as buffered hydrogen fluoride (BHF, NH4F+HF+H2O), may also be used. Exemplary etching methods may be found in U.S. Pat. No. 6,936,183, entitled “Etch Process for Etching Microstructures”, which is herein incorporated by reference. After the removal of the E-beam treated porous dielectric 220, reversed trenches 222 are formed between the conductive lines 214.
  • Example for Curing and Etching
  • Copper conductive lines are formed in a nitrogen doped silicon dioxide layer. The copper conductive lines are deposited in trenches with depth of about 257 nm. Distances between neighboring conductive lines are about 88 nm. After CMP and masking, the nitrogen doped silicon dioxide layer is cured by electron beam of 150 Dose. During electron beam curing, argon is flown to the processing chamber at a flow rate of about 50 sccm. The cured structure is the subjected to etching solution of diluted HF with a water/HF ratio of 100:1. The etch depth is about 150 nm after 1 minute wet etching, about 180 nm after 2 minute wet etching, and about 190 nm about 3 minute wet etching.
  • After formation of the reversed trenches 222, one or more dielectric material having air gaps may be filled in the reversed trenches 222. The process sequence 150 a shown in FIG. 4A may be used to fill the reversed trenches 222 and to form air gaps.
  • In step 151, the reversed trenches 222 are filled with a dielectric barrier 223. Air gaps 224 are uniformly formed and sealed in the reversed trenches 222 during the deposition of the dielectric barrier 223. The air gaps 224 are formed in the reversed trenches 222 due to the non-conformality of the deposition process, wherein a deposition rate on the side walls is relatively slow compared to the deposition rate near the entrance of the reversed trenches 222 “pinching off” the entrance before the reversed trenches 222 are filled and forming air gaps 224 therein.
  • In one embodiment, the dielectric barrier 223 is the same or similar to the dielectric barrier 216. The dielectric barrier 223 generally covers the sidewalls of the reversed trenches 222 prior to pinch off providing barrier against the diffusion of the conductive lines 214.
  • The dielectric barrier 223 may be deposited using PECVD. The deposition process of the dielectric barrier 223 is controlled so that bottoms and sidewalls of the reversed trenches 222 are covered prior to the pinch off and the air gaps are uniformly height wise so that the subsequent CMP process does not break the air gaps 224. In one embodiment, the process may be controlled by adjusting chamber pressure, and/or bias power in plasma generation. In another embodiment, the process may be adjusted by adjusting the shape and/or aspect ratio of the reversed trenches to control the location of the air gaps 224.
  • The dielectric barrier 223 may comprise a dense low k, k=5.1, barrier dielectric. The presence of the air gaps 224 in the dielectric barrier 223 reduces the effective dielectric constant of the dielectric material between the conductive lines 214, thus reducing the capacitance between the conductive lines 214. FIG. 10 schematically illustrates relationships of air gap fraction with effective dielectric constant and ratio of capacitance reduction for a barrier dielectric with k=5.1. It is shown, the effective dielectric constant may be reduced to 2 and the capacitance reduced by about 58% by introducing about 38% of air gaps in the dielectric barrier 223 between the conductive lines 214.
  • In step 153, a CMP process is performed on the dielectric barrier 223 to remove excessive material and to achieve a planar top surface 225 for subsequent trench and via layers, as shown in FIG. 5F. In one embodiment, the dielectric barrier 223 may be planarized to have a desired thickness above the top surface 215 of the trench layer 203 so that the dielectric barrier 223 provides barrier for subsequent interlayer dielectric against the conductive lines 214 in the trench layer 203. In one embodiment, the planarization may be terminated prior to breaking into the air gaps 224. To avoid increasing thickness of the substrate stack, it is desired to control the height of the air gaps 224.
  • Referring to FIG. 5G, a new interlayer dielectric 226, for example a new porous low k dielectric layer, is deposited on the top surface 225 of the dielectric barrier 223, as described in step 170 of FIG. 1. Via layer 227 and trench layer 228 may be subsequently formed in the new interlayer dielectric 226. Trench 230 and via 229 is then filled with conductive material. A new cycle of air gap formation may be performed on the trench layer 228 if desired.
  • It should be noted that air gaps generated using methods of the present invention do not have problems with unlanded vias, as shown in FIG. 5G. The via 229 does not completely land on the conductive lines 214 of the trench layer 203. Portions of the via 229 is in contact with the porous low k dielectric material 212. However, contacts between the unlanded portion of the via 229 and the air gaps 224 is avoidable because the air gaps only forms in a selected region.
  • Embodiment 2
  • FIGS. 6A-6C schematically illustrate formation of a substrate stack 200 b having air gaps in accordance with one embodiment of the present invention. The substrate stack 200 b are formed using the process sequence 110 a of FIG. 2A, followed by the process sequence 130 a of FIG. 3A, followed by the process sequence 150 b of FIG. 4B. The process sequence of the substrate stack 200 b is similar to that of the substrate stack 200 a prior to formation of air gaps and is illustrated in FIGS. 5A-5D.
  • After formation of the reversed trenches 222, one or more dielectric material having air gaps may be filled in the reversed trenches 222. The process sequence 150 b shown in FIG. 4B may be used to fill the reversed trenches 222 and to form air gaps.
  • In step 155, the reversed trenches 222 are lined with a thin layer of dielectric barrier material 240, as shown in FIG. 6A. In one embodiment, the dielectric barrier material 240 is the same or similar to the dielectric barrier 216. The dielectric barrier material 240 generally covers the sidewalls of the reversed trenches 222 providing barrier against the diffusion of the conductive lines 214 for subsequent dielectric materials.
  • In step 157, the reversed trenches 222 are filled with an interlayer dielectric material 241, as shown in FIG. 6B. Air gaps 242 are uniformly formed and sealed in the reversed trenches 222 during the deposition of the interlayer dielectric material 241. The air gaps 242 are formed in the reversed trenches 222 due to the non-conformality of the deposition process, wherein a deposition rate on the side walls is relatively slow compared to the deposition rate near the entrance of the reversed trenches 222 “pinching off” the entrance before the reversed trenches 222 are filled and forming air gaps 242 therein.
  • The interlayer dielectric 241 may be deposited using PECVD. The deposition process of the interlayer dielectric 241 is controlled so that the air gaps 242 are formed from pinching off effect near the entrance of the reversed trenches 222. In one embodiment, the air gaps 242 are uniform height wise so that the subsequent CMP process does not break the air gaps 242. In one embodiment, the process may be controlled by adjusting chamber pressure, and/or bias power in plasma generation. In another embodiment, the process may be adjusted by adjusting the shape and/or aspect ratio of the reversed trenches to control the location of the air gaps 242. A detailed description of formation of the interlayer dielectric 242 may be found in the U.S. Pat. No. 6,054,379, entitled “Method of Depositing a Low K Dielectric with Organo Silane”, which is incorporated herein by reference.
  • The interlayer dielectric material 241 may comprise a low k, k=2.5, dielectric material. The presence of the air gaps 242 in the interlayer dielectric 241 reduces the effective dielectric constant of the dielectric material between the conductive lines 214, thus reducing the capacitance between the conductive lines 214. FIG. 11 schematically illustrates relationships of air gap fraction with effective dielectric constant and ratio of capacitance reduction for an interlayer dielectric with k=2.5. It is shown, the effective dielectric constant may be reduced to k=2 and the capacitance reduced by about 20% by introducing about 17% of air gaps in the interlayer dielectric 241 between the conductive lines 214.
  • In step 159, a CMP process is performed on the interlayer dielectric 241 to remove excessive material and to achieve a planar top surface 243 for subsequent, as shown in FIG. 6B. In one embodiment, the interlayer dielectric 241 may be planarized to have a desired thickness above the top surface 215 of the trench layer 203 so that a subsequent via layer may be formed in the interlayer dielectric 241. In one embodiment, the planarization may be terminated prior to breaking into the air gaps 242. To avoid increasing thickness of the substrate stack, it is desired to control the height of the air gaps 242. In this embodiment, the top of the air gaps 242 may be at a higher position than the top surface 215 of the trench layer 203, because the interlayer dielectric 214 has a thickness allowance of a via layer.
  • Referring to FIG. 6C, a new porous low k dielectric layer 246 is deposited on the top surface 243 of the interlayer dielectric 241. A via layer 244 is formed in the interlayer dielectric 241 and a trench layer 245 is formed in the new porous dielectric layer 246. Trench-via structures may then be filled with conductive material. A new cycle of air gap formation may be performed on the trench layer 245 if desired.
  • Embodiment 3
  • FIG. 7 and FIGS. 8A-8B schematically illustrate formation of a substrate stack 200 c having air gaps in accordance with one embodiment of the present invention. The substrate stack 200 c are formed using the process sequence 110 b of FIG. 2B, followed by the process sequence 130 a of FIG. 3A, followed by the process sequence 150 b of FIG. 4B.
  • Referring to FIG. 7, a via layer 250 and a trench layer 251 are formed above a preexisting layer 201, which includes a conductive line 210. FIG. 2B illustrates one process sequence 110 b that may be used to form the via layer 250 and the trench layer 251 as shown.
  • In step 120 of the process sequence 110 b, a dielectric barrier film 252 is deposited all over the preexisting layer 201. The dielectric barrier film 252 is configured to prevent diffusion of conductive materials, for example metals for the conductive line 210, into a subsequent dielectric layer. The dielectric barrier film 252 generally comprises a barrier dielectric material, such as silicon nitride, silicon oxycarbide, or amorphous hydrogenated silicon carbide (BLOk™).
  • In step 121, an interlayer dielectric material 253 is deposited above the dielectric barrier film 252. The interlayer dielectric material 253 has a thickness enough to form the via layer 250 therein. The interlayer dielectric material 253 may comprises carbon doped silicon dioxide or nitrogen doped silicon dioxide. A detailed description of formation of the interlayer dielectric 253 may be found in the U.S. Pat. No. 6,054,379, entitled “Method of Depositing a Low K Dielectric with Organo Silane”, which is incorporated herein by reference.
  • In step 122, a porous low k dielectric material 254 is formed over the interlayer dielectric 253. The porous low k dielectric material 254 has a thickness enough to form the trench layer 251 therein.
  • In step 123, trench-via structures are formed in the interlayer dielectric material 253 and the porous low k dielectric material 254.
  • In step 124, a metallic diffusion barrier 255 is lined on the surface of the trench-via structure. The metallic diffusion barrier 255 is configured to prevent diffusion between metal lines subsequently deposited in the trenches and the dielectric structures nearby. The metallic diffusion barrier 255 may comprise tantalum (Ta) and/or tantalum nitride (TaN).
  • In step 125, the trench-via structures is filled with conductive lines 256 comprising one or more metals.
  • In step 126, a CMP process is performed on the conductive lines 256, the metallic diffusion barrier 255 so that the porous low k dielectric 254 is exposed on a top surface 257, as shown in FIG. 7.
  • Upon the formation the via layer 250 and the trench layer 251, portions of the porous low k dielectric 254 in the trench layer 251 may be removed so that air gaps may be formed between the conductive lines 256 using E-beam treatment via a pattern formed in a dielectric barrier 258 and a hard mask 259. The process sequence 130 a shown in FIG. 3A may be used to remove the porous low k dielectric 254 forming reversed trenches 260 as shown in FIG. 8A.
  • After formation of the reversed trenches 260, air gaps 263 may be formed using the process sequence 150 a shown in FIG. 4A or the process sequence 150 b shown in FIG. 4B. FIG. 8B illustrates air gaps 263 formed using the process sequence 150 b shown in FIG. 4B. A thin layer of dielectric barrier 261 is lined in the reversed trenches 260. The air gaps 263 are formed in the reversed trenches 260 due to the non-conformality of the deposition process of an interlayer dielectric 262, wherein a deposition rate on the side walls is relatively slow compared to the deposition rate near the entrance of the reversed trenches 260 “pinching off” the entrance before the reversed trenches 260 are filled.
  • Embodiment 4
  • FIG. 7 and FIGS. 9A-9B schematically illustrate formation of a substrate stack 200 d having air gaps in accordance with one embodiment of the present invention.
  • As shown in FIG. 7, the via layer 250 and the trench layer 251 are formed using the process sequence 110 b of FIG. 2B. The via layer 250 based on the interlayer dielectric 253. The trench layer 251 is based on the porous low k dielectric layer 254.
  • Due to the property difference of the interlayer dielectric 253 and the porous low k dielectric layer 254, the interlayer dielectric 253 may be used as an etch stop while removing the porous low k dielectric layer 254 to form reversed trenches 270, as show in FIG. 9A, and described in step 143 of process sequence 130 b. The reversed trenches 270 may be formed using a masked dry etching process to remove any porous low k dielectric 254 in selected regions.
  • After formation of the reversed trenches 270, air gaps 272 may be formed using the process sequence 150 a shown in FIG. 4A or the process sequence 150 b shown in FIG. 4B. FIG. 9B illustrates air gaps 272 are formed in the reversed trenches 270 due to the non-conformality of the deposition process of an interlayer dielectric 271, wherein a deposition rate on the side walls is relatively slow compared to the deposition rate near the entrance of the reversed trenches 270 “pinching off” the entrance before the reversed trenches 270 are filled.
  • In another embodiment, air gaps may be formed in trenches with sloped sidewalls to facilitate formation of air gaps. For example, air gaps may be formed while filling dielectric materials in trenches that have entrances narrower than bottoms. Detailed description regarding forming air gaps in trenches with sloped sidewalls may be found in U.S. patent application Ser. No. 11/869,409 (Attorney Docket No. 12054), filed Oct. 9, 2007, entitled “Method for Forming an Air Gap in Multilevel Interconnect Structures”, which is incorporated herein by reference.
  • While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims (20)

  1. 1. A method for forming a dielectric structure having air gaps, comprising:
    depositing a first dielectric layer on a substrate;
    depositing a second dielectric layer on the first dielectric layer;
    forming trench-via structures in the first and second dielectric layer, wherein vias are formed in the first dielectric layer and trenches are formed in the second dielectric layer;
    filling the trench-via structures with a conductive material;
    planarizing the conductive material to expose the second dielectric layer;
    depositing a dielectric barrier film on the conductive material and exposed second dielectric layer;
    forming a pattern in the dielectric barrier film and the hard mask layer to expose selected regions of the substrate;
    removing the second dielectric layer in the selected regions of the substrate to form reversed trenches around the conductive material filled in the trenches; and
    forming air gaps in the reversed trenches while depositing a third dielectric material in the reversed trenches.
  2. 2. The method of claim 1, wherein depositing the second dielectric layer comprises:
    depositing a silicon/oxygen containing material having labile organic group; and
    curing the silicon/oxygen containing material to form microscopic gas pockets that uniformly dispersed in the first dielectric layer.
  3. 3. The method of claim 1, wherein removing the second dielectric layer comprising etching the second dielectric layer exposed by the pattern.
  4. 4. The method of claim 3, wherein the first dielectric layer and second dielectric layer are different in property such that the first dielectric layer serves as an etch stop during etching the second dielectric layer.
  5. 5. The method of claim 3, wherein etching the second dielectric layer is performed using a masked dry etch process.
  6. 6. The method of claim 1, further comprising lining the reversed trenches with a dielectric barrier prior to forming air gaps.
  7. 7. The method of claim 6, wherein the third dielectric material comprises a dielectric barrier material deposited non-conformally in the reversed trenches so that the air gaps are formed and sealed within the dielectric barrier material.
  8. 8. The method of claim 6, wherein the third dielectric material comprises an interlayer dielectric material deposited non-conformally in the reversed trenches so that the air gaps are formed and sealed within the interlayer dielectric material.
  9. 9. The method of claim 1, wherein the third dielectric material comprises a dielectric barrier material deposited non-conformally in the reversed trenches so that the air gaps are formed and sealed within the dielectric barrier material.
  10. 10. The method of claim 9, further comprising polishing the third dielectric material without breaking the air gaps.
  11. 11. The method of claim 1, wherein the third dielectric material comprises an interlayer dielectric material deposited non-conformally in the reversed trenches so that the air gaps are formed and sealed within the interlayer dielectric material.
  12. 12. The method of claim 11, further comprising polishing the third dielectric material without breaking the air gaps.
  13. 13. A method for forming a dielectric structure having air gaps, comprising:
    depositing an interlayer dielectric material layer on a substrate;
    depositing a porous dielectric layer on the interlayer dielectric material layer;
    forming trench-via structures in the interlayer dielectric material layer and the porous dielectric layer;
    depositing a metallic diffusion barrier over the trench-via structure;
    filling the trench-via structures with a conductive material;
    planarizing the conductive material to expose the porous dielectric layer;
    removing the porous dielectric layer in selected regions of the substrate to form reversed trenches around the conductive material filled in the trenches; and
    forming air gaps in the reversed trenches while depositing a non-conformal dielectric material in the reversed trenches.
  14. 14. The method of claim 13, wherein depositing the porous dielectric layer comprises:
    depositing a silicon/oxygen containing material having labile organic group; and
    curing the silicon/oxygen containing material to form microscopic gas pockets that uniformly dispersed in the porous dielectric layer.
  15. 15. The method of claim 14, wherein removing the porous dielectric layer comprising etching the porous dielectric layer to expose the interlayer dielectric material layer.
  16. 16. The method of claim 15, wherein the interlayer dielectric material layer and porous dielectric layer are different in property such that the interlayer dielectric material layer serves as an etch stop during etching of the porous dielectric layer.
  17. 17. The method of claim 15, wherein the non-conformal dielectric material comprises a dielectric barrier material deposited non-conformally in the reversed trenches so that the air gaps are formed and sealed within the dielectric barrier material.
  18. 18. The method of claim 15, wherein the non-conformal dielectric material comprises a dielectric barrier material deposited non-conformally in the reversed trenches so that the air gaps are formed and sealed within the dielectric barrier material.
  19. 19. The method of claim 17, further comprising lining the reversed trenches with a dielectric barrier prior to forming air gaps.
  20. 20. The method of claim 15, comprising polishing the non-conformal dielectric material without breaking the air gaps.
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