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US20110103391A1 - System and method for high-performance, low-power data center interconnect fabric - Google Patents

System and method for high-performance, low-power data center interconnect fabric Download PDF

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Publication number
US20110103391A1
US20110103391A1 US12794996 US79499610A US2011103391A1 US 20110103391 A1 US20110103391 A1 US 20110103391A1 US 12794996 US12794996 US 12794996 US 79499610 A US79499610 A US 79499610A US 2011103391 A1 US2011103391 A1 US 2011103391A1
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Prior art keywords
node
mac
routing
switch
packet
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Abandoned
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US12794996
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Mark Bradley Davis
David James Borland
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Silicon Valley Bank
III Holdings 2 LLC
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SMOOTH STONE Inc C/O BARRY EVANS
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract

A system and method are provided that support a routing using a tree-like or graph topology that supports multiple links per node, where each link is designated as an Up, Down, or Lateral link, or both, within the topology. The system may use a segmented MAC architecture which may have a method of re-purposing MAC IP addresses for inside MACs and outside MACs, and leveraging what would normally be the physical signaling for the MAC to feed into the switch.

Description

    PRIORITY CLAIMS/RELATED APPLICATIONS
  • [0001]
    This patent application claims the benefit under 35 USC 119(e) to U.S. Provisional Patent Application Ser. No. 61/256,723 filed on Oct. 30, 2009 and entitled “System and Method for Enhanced Communications in a Multi-Processor System of a Chip (SOC), which is incorporated herein by reference.
  • FIELD
  • [0002]
    The disclosure relates generally to a switching fabric for a computer-based system.
  • BACKGROUND
  • [0003]
    With the continued growth of the internet, web-based companies and systems and the proliferation of computers, there are numerous data centers that house multiple server computers in a location that is temperature controlled and can be externally managed as is well known.
  • [0004]
    FIGS. 1A and 1B show a classic data center network aggregation as is currently well known. FIG. 1A shows a diagrammatical view of a typical network data center architecture 100 wherein top level switches 101 a-n are at the tops of racks 102 a-n filled with blade servers 107 a-n interspersed with local routers 103 a-f. Additional storage routers and core switches. 105 a-b and additional rack units 108 a-n contain additional servers 104 e-k and routers 106 a-g FIG. 1 b shows an exemplary physical view 110 of a system with peripheral servers 111 a-bn arranged around edge router systems 112 a-h, which are placed around centrally located core switching systems 113. Typically such an aggregation 110 has 1-Gb Ethernet from the rack servers to their top of rack switches, and often 10 Gb Ethernet ports to the edge and core routers.
  • [0005]
    However, what is needed is a system and method for packet switching functionality focused on network aggregation that reduces size and power requirements of typical systems while reducing cost all at the same time and it is to this end that the disclosure is directed.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0006]
    FIGS. 1A and 1B illustrate a typical data center system;
  • [0007]
    FIG. 2 is an overview of a network aggregation system;
  • [0008]
    FIG. 3 illustrates an overview of an exemplary data center in a rack system;
  • [0009]
    FIG. 4 illustrates a high-level topology of a network aggregating system;
  • [0010]
    FIG. 5A illustrates a block diagram of an exemplary switch of the network aggregation system;
  • [0011]
    FIG. 5B illustrates the MAC address encoding;
  • [0012]
    FIG. 6 illustrates a first embodiment of a broadcast mechanism of the network aggregation system;
  • [0013]
    FIG. 7 illustrates an example of unicast routing of the network aggregation system;
  • [0014]
    FIG. 8 illustrates an example of fault-resistant unicast routing of the network aggregation system; and
  • [0015]
    FIG. 9 illustrates a second embodiment of a broadcast mechanism of the network aggregation system.
  • DETAILED DESCRIPTION OF ONE OR MORE EMBODIMENTS
  • [0016]
    The disclosure is particularly applicable to a network aggregation system and method as illustrated and described below and it is in this context that the disclosure will be described. It will be appreciated, however, that the system and method has greater utility since the system and method can be implemented using other elements and architectures that are within the scope of the disclosure and the disclosure is not limited to the illustrative embodiments described below.
  • [0017]
    The system and method also supports a routing using a tree-like or graph topology that supports multiple links per node, where each link is designated as an Up, Down, or Lateral link, or both, within the topology. In addition, each node in the system maybe be a combination computational/switch node, or just a switch node, and input/output (I/O) can reside on any node as described below in more detail. The system may also provide a system with a segmented Ethernet Media Access Control (MAC) architecture which may have a method of re-purposing MAC IP addresses for inside MACs and outside MACs, and leveraging what would normally be the physical signaling for the MAC to feed into the switch. The system may also provide a method of non-spoofing communication, as well as a method of fault-resilient broadcasting, which may have a method of unicast misrouting for fault resilience. In the context of network security, a spoofing attack is a situation in which one person or program successfully masquerades as another by falsifying data and thereby gaining an illegitimate advantage.
  • [0018]
    The system may also provide a rigorous security between the management processors, such that management processors can “trust” one another. In the example system shown in FIG. 5A (which is described below in more detail), there is a management processor within each SoC (the M3 microcontroller, block 906, FIG. 5A). The software running on the management processor is trusted because a) the vendor (in this case Smooth-Stone) has developed and verified the code, b) non-vendor code is not allowed to run on the processor.
  • [0019]
    Maintaining a Trust relationship between the management processors allow them to communicate commands (e.g. reboot another node) or request sensitive information from another node without worrying that a user could spoof the request and gain access to information or control of the system.
  • [0020]
    The system may also provide a network proxy that has an integrated microcontroller in an always-on power domain within a system on a chip (SOC) that can take over network proxying for the larger onboard processor, and which may apply to a subtree. The system also provide a multi-domaining technique that can dramatically expand the size of a routable fat tree like structure with only trivial changes to the routing header and the routing table.
  • [0021]
    FIG. 2 illustrates a network aggregation system 300. The network aggregation supports one or more high speed links 301 (thick lines), such as a 10-Gb/sec Ethernet communication, that connect an aggregation router 302 and one or more racks 303, such as three racks 303 a-c as shown in FIG. 3. In a first rack 303 a, the network aggregation system provides multiple high-speed 10 Gb paths, represented by thick lines, between one or more Smooth-Stone computing unit 306 a-d, such as server computers, on shelves within a rack. Further details of each Smooth-Stone computing unit are described in more detail in U.S. Provisional Patent Application Ser. No. 61/256,723 filed on Oct. 30, 2009 and entitled “System and Method for Enhanced Communications in a Multi-Processor System of a Chip (SOC)” which is incorporated herein in its entirety by reference. An embedded switch 306 a-d in the Smooth-Stone computing units can replace a top-of-rack switch, thus saving a dramatic amount of power and cost, while still providing a 10 Gb Ethernet port to the aggregation router 302. The network aggregation system switching fabric can integrate traditional Ethernet (1 Gb or 10 Gb) into the XAUI fabric, and the Smooth-Stone computing units can act as a top of rack switch for third-party Ethernet connected servers.
  • [0022]
    A middle rack 303 b illustrates another configuration of a rack in the network aggregation system in which one or more Smooth-Stone computing units 306 e, f can integrate into existing data center racks that already contain a top-of-rack switch 308 a. In this case, the IT group can continue to have their other computing units connected via 1 Gb Ethernet up to the existing top-of-rack switch and the internal Smooth-Stone computing units can be connected via 10 Gb XAUI fabric and they can integrate up to the existing top-of-rack switch with either a 1 Gb or 10 Gb Ethernet interconnects as shown in FIG. 2. A third rack 303 c illustrates a current way that data center racks are traditionally deployed. The thin red lines in the third rack 303 c represent 1 Gb Ethernet. Thus, the current deployments of data center racks is traditionally 1 Gb Ethernet up to the top-of-rack switch 308 b, and then 10 Gb (thick red line 301) out from the top of rack switch to the aggregation router. Note that all servers are present in an unknown quantity, while they are pictured here in finite quantities for purposes of clarity and simplicity. Also, using the enhanced SS servers, no additional routers are needed, as they operate their own XAUI switching fabric, discussed below.
  • [0023]
    FIG. 3 shows an overview of an exemplary “data center in a rack” 400 according to one embodiment of the system. The “data center in a rack” 400 may have 10-Gb Ethernet PHY 401 a-n and 1-Gb private Ethernet PHY 402. Large computers (power servers) 403 a-n support search; data mining; indexing; Apache Hadoop, a Java software framework; MapReduce, a software framework introduced by Google to support distributed computing on large data sets on clusters of computers; cloud applications; etc. Computers (servers) 404 a-n with local flash and/or solid-state disk (SSD) support search, MySQL, CDN, software-as-a-service (SaaS), cloud applications, etc. A single, large, slow-speed fan 405 augments the convection cooling of the vertically mounted servers above it. Data center 400 has an array 406 of hard disks, e.g., in a Just a Bunch of Disks (JBOD) configuration, and, optionally, Smooth-Stone computing units in a disk form factor (for example, the green boxes in arrays 406 and 407), optionally acting as disk controllers. Hard disk servers or SS disk servers may be used for web servers, user applications, and cloud applications, etc. Also shown are an array 407 of storage servers and historic servers 408 a, b (any size, any vendor) with standard Ethernet interfaces for legacy applications.
  • [0024]
    The data center in a rack 400 uses a proprietary system interconnect approach that dramatically reduces power and wires and enables heterogeneous systems, integrating existing Ethernet-based servers and enabling legacy applications. In one aspect, a complete server or storage server is put in a disk or SSD form factor, with 8-16 SATA interfaces with 4 ServerNodes™ and 8 PCIe x4 interfaces with 4 ServerNodes™. It supports disk and/or SSD+ServerNode™, using a proprietary board paired with a disk(s) and supporting Web server, user applications, cloud applications, disk caching, etc.
  • [0025]
    The Smooth-Stone XAUI system interconnect reduces power, wires and the size of the rack. There is no need for high powered, expensive Ethernet switches and high-power Ethernet Phys on the individual servers. It dramatically reduces cables (cable complexity, costs, significant source of failures). It also enables a heterogeneous server mixture inside the rack, supporting any equipment that uses Ethernet or SATA or PCIe. It can be integrated into the system interconnect.
  • [0026]
    The herein presented aspects of a server-on-a-chip (SOC) with packet switch functionality are focused on network aggregation. The SOC is not a fully functionally equivalent to an industry-standard network switch, such as, for example, a Cisco switch or router. But for certain applications discussed throughout this document, it offers a better price/performance ratio as well as a power/performance ratio. It contains a layer 2 packet switch, with routing based on source/destination MAC addresses. It further supports virtual local area network (VLAN), with configurable VLAN filtering on domain incoming packets to minimize unnecessary traffic in a domain. The embedded MACs within the SOC do have complete VLAN support providing VLAN capability to the overall SOC without the embedded switch explicitly having VLAN support. It can also wake up the system by management processor notifying the management processor on link state transitions to reprogram routing configurations to route around faults. Such functionality does not require layer3 (or above) processing (i.e., it is not a router). It also does not offer complete VLAN support, support for QoS/CoS, address learning, filtering, spanning tree protocol (STP), etc.
  • [0027]
    FIG. 4 shows a high-level topology 800 of the network system that illustrates XAUI connected SoC nodes connected by the switching fabric. The 10 Gb Ethernet ports Eth0 801 a and Eth1 801 b come from the top of the tree. Ovals 802 a-n are Smooth-Stone nodes that comprise both computational processors as well as the embedded switch. The nodes have five XAUI links connected to the internal switch. The switching layers use all five XAUI links for switching. Level 0 leaf nodes 802 d, e (i.e., N0 n nodes, or Nxy, where x=level and y=item number) only use one XAUI link to attach to the interconnect, leaving four high-speed ports that can be used as XAUI, 10 Gb Ethernet, PCIe, SATA, etc., for attachment to I/O. The vast majority of trees and fat trees have active nodes only as leaf nodes, and the other nodes are pure switching nodes. This approach makes routing much more straightforward. Topology 800 has the flexibility to permit every node to be a combination computational and switch node, or just a switch node. Most tree-type implementations have I/O on the leaf nodes, but topology 800 let the I/O be on any node. In general, placing the Ethernet at the top of the tree minimizes the average number of hops to the Ethernet.
  • [0028]
    In more detail, the ovals shown in the tree-oriented topology in FIG. 6 represent independent nodes within a computing cluster. FIG. 5A illustrates one example implementation of an individual node of the cluster. When looking at a conventional implementation of a topology e.g. in FIG. 6, usually computing nodes are found in the lower level leaf nodes (e.g. N00-N08), and the upper level nodes don't have computing elements but are just network switching elements (N10-N21). With the node architecture shown in FIG. 6A, the A9 Cores (905) may be optionally enabled, or could be just left powered-off. So the upper level switching nodes (N10-N21) in FIG. 6 can be used as pure switching elements (like traditional implementations), or we can power on the A9 Cores module and use them as complete nodes within the computing cluster.
  • [0029]
    The switch architecture calls for a routing frame to be prepended to the Ethernet frame. The switch operates only against fields within the routing frame, and does not inspect the Ethernet frame directly. FIG. 5 a shows a block diagram of an exemplary switch 900 according to one aspect of the system and method disclosed herein. It has four areas of interest 910 a-d. Area 910 a corresponds to Ethernet packets between the CPUs and the inside MACs. Area 910 b corresponds to Ethernet frames at the Ethernet physical interface at the inside MACs, that contains the preamble, start of frame, and inter-frame gap fields. Area 910 c corresponds to Ethernet frames at the Ethernet physical interface at the outside MAC, that contains the preamble, start of frame, and inter-frame gap fields. Area 910 d corresponds to Ethernet packets between the processor of routing header 901 and outside MAC 904. This segmented MAC architecture is asymmetric. The inside MACs have the Ethernet physical signaling interface into the routing header processor, and the outside MAC has an Ethernet packet interface into the routing header processor. Thus the MAC IP is re-purposed for inside MACs and outside MACs, and what would normally be the physical signaling for the MAC to feed into the switch is leveraged. MAC configuration is such that the operating system device drivers of A9 cores 905 manage and control inside Eth0 MAC 902 and inside ETH1 MAC 903. The device driver of management processor 906 manages and controls Inside Eth2 MAC 907. Outside Eth MAC 904 is not controlled by a device driver. MAC 904 is configured in Promiscuous mode to pass all frames without any filtering for network monitoring. Initialization of this MAC is coordinated between the hardware instantiation of the MAC and any other necessary management processor initialization. Outside Eth MAC 904 registers are visible to both A9 905 and management processor 906 address maps. Interrupts for Outside Eth MAC 904 are routable to either the A9 or management processor. The XGMAC supports several interruptible events that the CPUs may want to monitor, including any change in XGMII link fault status, hot-plugging or removal of PHY, alive status or link status change, and any RMON counter reaching a value equal to the threshold register.
  • [0030]
    In some cases, there may be Preamble, Start of Frame, and Inter-Frame gap fields across XAUI, depending on the specific micro-architecture. The routing frame header processor may standardize these fields. The XAUI interface may need some or all of these fields. In this case, the routing header processor at area 910 d needs to add these going into the switch, and to remove them leaving the switch. To reduce the number of bytes that need to be sent over XAUI, these three fields may be removed (if the XAUI interface allows it). In this case, the routing header processor at area 910 b will need to strip these going into the switch, and add them back leaving the switch.
  • [0031]
    The routing frame header processor receives an Ethernet frame from a MAC, sending a routing frame to the switch. It also standardizes the preamble, start of frame, and inter-frame gap fields, prepends a routing header, and receives a routing frame from the switch, sending the Ethernet frame into a MAC. This processor then strips the routing header and standardizes the preamble, start of frame, and inter-frame gap fields. Note that all frames that are flowing within the fabric are routing frames, not Ethernet frames. The Ethernet frame/routing frame conversion is done only as the packet is entering or leaving the fabric via a MAC. Note also that the routing logic within the switch may change fields within the routing frame. The Ethernet frame is never modified (except the adding/removing of the preamble, start of frame, and inter-frame gap fields).
  • [0032]
    The routing frame is composed of the routing frame header plus the core part of the Ethernet frame, and is structured as shown in Table 1, below:
  • [0000]
    TABLE 1
    Routing
    Frame Header Ethernet Frame Packet
    RF MAC MAC Ethertype/ (data and CRC32
    Header destination Source Length padding)
  • [0033]
    Note that the implementation assumptions for bit sizing are 4096 nodes→12 bit node IDs. These fields may be resized during implementation as needed.
  • [0034]
    The routing frame header consists of the fields shown in Table 2, below:
  • [0000]
    TABLE 2
    Width
    Field (Bits) Notes
    Domain ID 5 Domain ID associated with this packet. 0 indicates
    that no domain has been specified.
    Mgmt Domain 1 Specifies that the packet is allowed on the private
    management domain.
    Source Node 12 Source node ID
    Source Port 2 0 = MAC0, 1 = MAC1, 2 = MAC_management
    processor, 3 = MAC_OUT
    Dest Node 12 Destination node ID
    Dest Port 2 0 = MAC0, 1 = MAC1, 2 = MAC_management
    processor, 3 = MAC_OUT
    RF Type 2 Routing Frame Type (0 = Unicast, 1 = Multicast,
    2 = Neighbor Multicast, 3 = Link Directed)
    TTL 6 Time to Live - # of hops that this frame has existed.
    Switch will drop packet if the TTL threshold is exceeded
    (and notify management processor of exception).
    Broadcast ID 5 Broadcast ID for this source node for this broadcast
    packet.
    Checksum Checksum of the frame header fields.
    Total 46 +checksum
  • [0035]
    If a switch receives a packet that fails the checksum, the packet is dropped, a statistic counter is incremented, and the management processor is notified.
  • [0036]
    The routing frame processor differentiates between several destination MAC address encodings. As a reminder, MAC addresses are formatted as shown in FIG. 5 b. The following table describes the usage of the 3 byte OUI and 3 byte NIC specific field within the MAC address. One of the novel aspects of the system and method disclosed herein is the use of additional address bits to encode an internal to external MAC mapping, as shown also in the Table 3, below, in the second entry under “Fabric Internal Node local address Hits MAC Lookup CAM”.
  • [0000]
    TABLE 3
    MAC Address
    Type 3 bytes OUI 3 bytes NIC Specific Operation
    External Multicast bit Arbitrary Packet unicast
    Misses MAC not set routed to
    Lookup CAM gateway node #.
    Fabric Internal Arbitrary Node local address (meaning Packet unicast
    Node local low 2 bits - port unit routed to
    address ID) are not present. MAC fabric node #
    Hits MAC Lookup CAM for entry obtained from
    Lookup CAM marked as Node Local. MAC Lookup CAM
    Fabric Internal Arbitrary Arbitrary Packet unicast
    Arbitrary MAC routed to
    address fabric node #
    Hits MAC obtained from
    Lookup CAM MAC Lookup CAM
    Node Encoded Unicast 10 bits: Packet
    Unicast Locally SS_MAC_NODE_ENCODED_MAGIC unicast
    administered 12 bits: Node ID routed to
    OUI == Switch 2 bits: Port ID Node ID.
    OUI
    Link Encoded Unicast 12 bits: Packet sent
    Unicast Locally SS_MAC_LINK_ENCODED_MAGIC down specific
    administered 7 bits: Reserved Link #.
    OUI == Switch 3 bits: Link # (0-4)
    OUI 2 bits: Port
    Multicast/ Multicast bit Arbitrary Packet
    Broadcast set broadcast
    routed through
    fabric and
    gateways.
    Neighbor Multicast bit 12 bits: Packet sent
    Multicast set SS_NEIGHBOR_MCAST_MAGIC through all
    Locally 12 bits: Reserved XAUI links to
    administered neighboring
    OUI = Switch nodes and not
    OUI rebroadcast
    to other nodes
  • [0037]
    Further, other novel aspects can be found in Table 3 under “Node Encoded Unicast” as well as “Link Encoded Unicast,” allowing one internal node or link to address all external MAC sections, and the “Neighbor Multicast” entry, allowing a multicast to neighboring nodes.
  • [0038]
    Note that the values SS_MAC_NODE_ENCODED_MAGIC and SS_MAC_LINK_ENCODED_MAGIC are constant identifiers used for uniquely identifying these MAC address types. The term “magic number” is a standard industry term for a constant numerical or text value used to identify a file format or protocol. These magic numbers are configured in two registers (magicNodeEncodedMAC and magicLinkEncodedMAC that default to standard values during hardware initialization, but allow the management processor software to change them if necessary.
  • [0039]
    The header processor contains a MAC Lookup CAM (Content Addressable Memory), macAddrLookup, that maps from 6 byte MAC addresses to 12-bit Node IDs, as shown in Table 4, below.
  • [0000]
    TABLE 4
    MAC Lookup CAM Input MAC Lookup CAM Output
    Node Local MAC Address Node ID Port ID
    1 bit 6 bytes 12 bits 2 bits
  • [0040]
    The number of rows in this CAM is implementation dependent, but would be expected to be on the order of 256-1024 rows. The management processor initializes the CAM with Node ID mappings for all the nodes within the SS fabric. There are two types of rows, depending upon the setting of the Node Local bit for the row. The Node Local field allows a 4:1 compression of MAC addresses in the CAM for default MAC addresses, mapping all four MACs into a single row in the CAM table, which is Table 5, below.
  • [0000]
    TABLE 5
    MAC
    Address Node
    Type Local MAC Address Port ID
    Node 1 A Node Encoded Address refers to a Smooth Stone Taken from
    Local assigned MAC address for a node. It encodes the port # low 2 bits of
    (MAC0, MAC1, management processor, Rsvd) into a 2- MAC Address
    bit Port ID in the lowest two bits of the NIC address Input
    field. Ignores low 2 bits during match.
    Arbitrary 0 Matches against all 6 bytes Taken from
    CAM Output
    field
  • [0041]
    The arbitrary rows in the CAM allow mapping of the MAC address aliases to the nodes. Linux (and the MACs) allow the MAC addresses to be reassigned on a network interface (e.g., with ifconfig eth0 hw ether 00:80:48:BA:d1:30). This is sometime used by virtualization/cloud computing to avoid needing to re-ARP after starting a session.
  • [0042]
    The switch architecture provides for a secondary MAC Lookup CAM that only stores the 3 bytes of the NIC Specific part of the MAC address for those addresses that match the Switch OUI. The availability of this local OUI CAM is determined by the implementation. See Table 6, below.
  • [0000]
    TABLE 6
    MAC Lookup CAM Input MAC Lookup CAM Output
    MAC Address NIC Specific Node ID Port ID
    3 bytes 12 bits 2 bits
  • [0043]
    The maximum number of nodes limitation for three types of MAC address encodings may be evaluated as follows:
  • [0044]
    1. Default MAC Addressees—management processor sets Node Local mappings for each of the nodes in the fabric. There is one entry in the CAM for each node. Max # of nodes is controlled by maximum # of rows in the MAC Address Lookup CAM.
  • [0045]
    2. Node Encoded Addresses—All the MACs are reprogrammed to use Node Encoded Addresses. In this way the Node IDs are directly encoded into the MAC addresses. No entries in the MAC Lookup CAM are used. Max # of nodes is controlled by maximum # of rows in the Unicast lookup table (easier to make big compared to the Lookup CAM). Note that this also gives us some risk mitigation in case the MAC Lookup CAM logic is busted. Provides use case for the node encoded addresses idea.
  • [0046]
    3. Arbitrary MAC Address Aliases—Takes a row in the CAM. As an example, a 512-row CAM could hold 256 nodes (Node local addresses)+1 MAC address alias per node.
  • [0047]
    Since the Lookup CAM is only accessed during Routing Header creation, the management processor actually only needs to populate a row if the MAC address within the fabric is being used as a source or destination MAC address within a packet. In other words, if two nodes never will talk to each other, a mapping row does not need to be created. But usually the management processor won't have that knowledge, so it's expected that mappings for all nodes are created in all nodes. Also note that even if an entry is not created in the Lookup CAM, the routing will actually still succeed by routing the packet out the Ethernet gateway, through an external router, back into the Fabric, to the destination node.
  • [0048]
    Table 7 defines how to set fields within the Routing Header for all the fields except for destination node and port.
  • [0000]
    TABLE 7
    Field Set To
    Domain ID Set to the macDomainID field for the MAC that
    the packet came from.
    Mgmt Set to the macMgmtDomain field for the MAC that
    Domain the packet came from.
    Source Node Switch Node ID
    Source Port Source MAC Port ID
    RF Type Multicast (if dstMAC multicast and not Neighbor
    Multicast format)
    Neighbor Multicast (if dstMAC multicast and is
    Neighbor Multicast format)
    Link Directed (is Link Encoded format)
    Unicast (if not one of the above)
    TTL 0
    Broadcast If dstMAC is unicast - Set to 0
    ID If dstMAC is multicast - Set to incremented local
    broadcast ID (bcastIDNext++ & 0xf)
  • [0049]
    Table 8 defines how to set destination node and port for addresses within the fabric:
  • [0000]
    TABLE 8
    Field: Field:
    Destination Destination
    Case Node Port
    Node Encoded Dest Address Dest Node Dest Port
    Link Encoded Dest Address Encoded Link Dest Port
    Hits Lookup CAM (node local) CAM Dest Node Dest MAC
    (low 2 bits)
    Hits Lookup CAM (not node local) CAM Dest Node CAM Dest Port
  • [0050]
    Table 9 defines how to set destination node and port for addresses outside the fabric:
  • [0000]
    TABLE 9
    Field: Field:
    Destination Destination
    Case Node Port
    Came in an OUT Ethernet, but no Drop packet, update statistics counter
    secondary gateway defined
    Came in an OUT Ethernet, and secondaryEthGatewayNode[OUT] OUT
    secondary gateway defined
    From an Inside MAC, but no Drop packet, update statistics
    primary gateway defined counter, and notify management
    processor
    From an Inside MAC, and primaryEthGatewayNode[fromPort] OUT
    primary gateway defined
  • [0051]
    Additionally, the management processor software architecture of the system and method disclosed here currently depends on the ability of management processor nodes to “trust” each other. This more rigorous security on management processor to management processor communication is desirable, as well a better security on private management LANs across the fabric. This fabric issue may be mitigated by simply defining, for environments that require multiple “hard” security domains, that customers simply don't mix security domains within a fabric. In such cases, it may be possible to connect 14-node boards to the top of rack switch, allowing customers to have VLAN granularity control of each 14-node board.
  • [0052]
    The multi-domain fabric architecture that has been described addresses the lack of VLAN support by creating secure “tunnels” and domains across the fabric, and it can interoperate with VLAN protected router ports on a 1:1 basis.
  • [0053]
    The approach to domain management in the system and method disclosed here is as follows: Support multiple domain IDs within the fabric. Allow each of the MACs within a node (management processor, MAC0, MAC1, Gateway) to be assigned to a domain ID individually (and tagged with domain 0 if not set). Allow each of the MACs within a node to have a bit indicating access to the management domain. The domain IDs associated with a MAC could only be assigned by the management processor, and could not be altered by the A9. For frames generated by MACs (both inside and outside), the routing frame processor would tag the routing frame with the domain ID and management domain state associated with that MAC. Domains would provide the effect of tunnels or VLANs, in that they keep packets (both unicast and multicast) within that domain, allowing MACs outside that domain to be able to neither sniff or spoof those packets. Additionally, this approach would employ a five-bit domain ID. It would add options to control domain processing, such as, for example, a switch with a boolean per MAC that defines whether packets are delivered with non-defined (i.e., zero) domain ID, or a switch that has a boolean per MAC that defines whether packets are delivered with defined (non-zero) but non-matching domain IDs. A further option in the switch could turn off node encoded MAC addresses per MAC (eliminating another style of potential attack vector).
  • [0054]
    To keep management processor to management processor communication secure, the management domain bit on all management processor MACs could be marked. Generally, the management processor should route on domain 1 (by convention). Such a technique allows all the management processor's to tunnel packets on the management domain so that they cannot be inspected or spoofed by any other devices (inside or outside the fabric), on other VLANs or domains. Further, to provide a secure management LAN, a gateway MAC that has the management domain bit set could be assigned, keeping management packets private to the management processor domain. Additionally, the switch fabric could support “multi-tenant” within itself, by associating each gateway MAC with a separate domain. For example, each gateway MAC could connect to an individual port on an outside router, allowing that port to be optionally associated with a VLAN. As the packets come into the gateway, they are tagged with the domain ID, keeping that traffic private to the MACs associated with that domain across the fabric.
  • [0055]
    The switch supports a number of registers (aka CSRs, aka MMRs) to allow software or firmware to control the switch. The actual layout of these registers will be defined by the implementation. The fields listed in Table 10 are software read/write. All these registers need to have a mechanism to secure them from writing from the A9 (could be secure mode or on a management processor private bus).
  • [0000]
    TABLE 10
    Field Size Notes
    Adaptive 1 bit Adaptive unicast routing enabled.
    broadcastLateral 1 bit Enable to have broadcasts go through lateral
    links, rather than just Up and Down links.
    Turning this off will work for most topologies
    and will reduce # duplicate broadcast packets.
    intPortBroadcastVec 4 bits Vector of ports to send internally generated
    broadcast packet into.
    extPortBroadcastVec 4 bits Vector of ports to send externally generated
    broadcast packet into.
    linkDir[LINKS] Array [LINKS] x Specifies link direction for each link
    2 bits (0 = DOWN, 1 = LATERAL, 2 = UP, 3 = Rsvd)
    linkState 5 bits Link state vector for each of the 5 links. Bit
    set indicates that link is active (trained and
    linked).
    linkType[LINKS] Array [LINKS] x Specifies type of each link
    2 bits (0 = No Link, 1 = XAUI, 2 = Ethernet}
    localBroadcastM3Snoop 1 bit When set, then we'll always send a copy of
    the locally initiated broadcast into the
    management processor. The use case here is
    where the management processor wants to see
    the gratuitous ARPs that are locally initiated
    so that it can communicate across the
    management processor fabric and add
    corresponding entries into the local unicast
    routing tables.
    macAddrLookup Lookup CAM which is MAC address lookup CAM to convert MAC
    described elsewhere in addresses to Node IDs.
    the document
    macAcceptOtherDomain[MAC] 1 bit[MAC] Defines that the MAC accepts packets that are
    tagged with a non-zero, non-matching domain
    ID.
    macAcceptZeroDomain[MAC] 1 bit[MAC] Defines that the MAC accepts packets that are
    not tagged with a domain (i.e. 0 domain)
    macDomainID[MAC] 5 bits[MAC] Defines the Domain ID for each of the 4
    MACs. A value of 0 indicates that the domain
    ID for that MAC is not set.
    macMgmtDomain[MAC] 1 bit[MAC] Defines that the MAC may access the
    management domain. Setting this tags the
    management domain in the routing frame, as
    well as allows the switch to route
    management frame packets into this MAC.
    magicNodeEncodedMAC 10 bits Magic number for Node Encoded MAC
    addresses
    magicLinkEncodedMAC 12 bits Magic number for Link Encoded MAC
    addresses
    maxTTL 6 bits Maximum TTL count allowed in a routing
    header. Exceeding this number of hops causes
    the switch to drop the packet, update a
    statistic counter, and inform the management
    processor.
    myNodeID 12 bits Need not be contiguous. Subtree's should
    ideally be numbered within a range to
    facilitate subtree network proxying.
    myOUI 3 bytes 3 upper bytes of MAC addresses in fabric.
    Should be the same for all nodes in the fabric.
    nodeRangeEnable 1 bit Enables the expanded Node ID matching of
    [nodeRangeLo, nodeRangeHi]. Used for
    Network Proxying through a subtree. When
    enabled, a packet will be routed into the node
    (rather than through the node) if either
    DstNode == myNodeID OR (nodeRangeLo <=
    DstNode <= nodeRangeHi).
    nodeRangeHi 12 bits Enabled with nodeRangeEnable. Specifies
    high node ID of node range match.
    nodeRangeLo 12 bits Enabled with nodeRangeEnable. Specifies
    low node ID of node range match.
    noFlowControl 1 bit When enabled, there will be no flow control.
    portRemap[INT_PORTS]; Array [INT_PORTS] x Allows remapping of incoming destination
    2 bits port IDs to the internal port where it'll be
    delivered. This register defaults to an
    equivalence remapping. An example of where
    this will get remapped is during Network
    Proxy where the management processor will
    remap MAC0 packets to be sent to the
    management processor.
    INT_PORTS = 4. Array elements are the Ports
    enumeration (management processor, MAC0,
    MAC1, OUT).
    2 bits contents is the Ports enumeration.
    primaryEthGatewayNode[INT_PORTS] Array [INT_PORTS] Specifies Node ID of primary Ethernet
    of 12-bit gateway for this node. Packets destined to
    node IDs that aren't within the fabric will get
    routed here.
    promiscuousPortVec 4 bits Can be configured for Promiscuous Mode
    allowing traffic on one or more links to be
    snooped by the management processor or A9s
    in order to collect trace data or to implement
    an Intruder Detection System (IDS). This
    causes all traffic passing through the switch to
    be copied to the internal ports defined by this
    port vector.
    routeForeignMACsOut 1 bit When enabled, a MAC address that does not
    contain a myOUI address, will not check the
    MAC lookup CAM, and will get treated as a
    MAC lookup CAM miss, thus getting routed
    to the gateway port. This saves latency in the
    common case of not populating the CAM
    with foreign MAC aliases.
    secondaryEthGatewayNode[INT_PORTS] Array [INT_PORTS] Specifies Node ID of secondary Ethernet
    of 12-bit gateway. Incoming (from OUT) packets
    routing through the fabric will be sent here.
    unicastPortsFromOtherExt 1 bit An incoming unicast from an external
    Gateways gateway will get the gateway node put into
    the source node field of the routing header.
    Upon reaching the destination node, this bit
    will be checked. When the bit is clear, the
    external gateway node must match the
    destination gateway node for it to be delivered
    to internal ports. This is to handle the case
    where the fabric is connected to an external
    learning switch that hasn't yet learned the
    mac/port relationship, and floods the unicast
    packet down multiple ports. This will prevent
    a fabric node from getting the unicast packet
    multiple times.
    unicastRoute[NODES] Array [NODES] of Link vector of unicast next route. 10 bits is 2-
    10 bits bit weight for each of 5 links.
  • [0056]
    The registers shown in Table 11 are contained within the Switch implementation, but need not be software accessible.
  • [0000]
    TABLE 11
    Field Size Notes
    bcastIDNext 5 bits Next broadcast sequence ID to issue
    next. Hardware will increment this
    for each broadcast packet initiated
    by this node.
    bcastIDSeen[BCAST_ID_LEN] Array [BCAST_ID_LEN] FIFO list of broadcast tags seen by
    of 5 bits. this node.
    bcastIDSeenNext # bits to index into Next array position into
    BCAST_ID_LEN bcastIDSeen[ ] to insert a broadcast
    tag.
  • [0057]
    Note that software should be able to update the routing tables (unicastRoute) and the macAddrLookup CAM atomically with respect to active packet routing. One implementation will be to hold off routing access to these tables during an update operation.
  • Broadcast/Multicast Routing
  • [0058]
    FIG. 6 shows an exemplary broadcast mechanism 1000 according to one aspect of the system and method disclosed herein. The link between nodes N101001 and N21 1002 is down, as indicated by the dashed line 1003. During routing header generation of multicast packets, the source node puts an incremented broadcast ID for that source node in the routing frame (rframe.bcastID). When a node receives a multicast routing frame (i.e. rframe.rfType==Multicast∥rframe.rfType==NeighborMulticast), it checks to see whether it has already seen this broadcast packet. The check is done by accessing the bcastIDSeen CAM with a tag formed with the broadcast source node and the broadcast ID. If it has already been seen (i.e. CAM hit), no action is be performed. If the broadcast frame has not been seen before, it broadcasts it to appropriate internal ports and external gateways (intPortBroadcastVec register) and rebroadcasts it through all outward XAUI links except for the link it came in on. Note that it only broadcasts through laterals if the broadcastLateral register is set. It is unnecessary to broadcast laterals on most topologies, and doing so may reduce the number of duplicated broadcast packets by disabling it. It then adds this broadcast tag to the bcastIDSeen CAM in FIFO order. In FIG. 7, N04 1004 initiates a broadcast to all neighbors, i.e., N11 1105. N11 has not seen the packet, so it broadcasts to all non-incoming neighbors, which, in this example, are N21 1002, N20 1006, N03 1007, and N05 1008, and accepts the packet internally. Nodes N03 and N05 haven't seen the packet, so they accept the broadcast internally and are done. N21 hasn't seen the packet, so it broadcasts the packet to all active, non-incoming links (e.g., N10, N12 1009), and accepts the packet internally. N20 broadcasts the packet to all active, non-incoming links (i.e., N12), and accepts the packet internally. N10 broadcasts down to N00 1010, N01 1011, and N02 1012. N12 rebroadcasts to N06 1013, N07 1014, N08 1015 and to one of N21 and N20 (the one it didn't get the broadcast packet from). Note that one of N20 and N21, and N12, see the packet twice. They take action only on their first instance, the secondary times it hits the broadcast CAM as a duplicate, and the packet is ignored.
  • Unicast Routing
  • [0059]
    Unicast to Other Node
  • [0060]
    Unicast routing (as shown in FIG. 7) is responsible for routing non-multicast (i.e. unicast) packets to the next node. This is done by utilizing a software computed unicastRoute[ ] next node routing table that provides a vector of available links to get to the destination node.
  • [0061]
    Condition
  • [0062]
    rframe.rfType=Unicast
  • [0063]
    Routing
  • [0064]
    There are substantial complexities related to routing around faults. Fault free routing and routing around faults will be discussed separately.
  • [0065]
    Traditionally in tree routing, the packet will be routed upward until a common parent of (source, destination) is reached. This upward routing can be deterministic, oblivious, or adaptive. The packet is then routed downward to the destination using deterministic routing.
  • [0066]
    As an example, FIG. 7 illustrates a packet routing from node N00 1010 to N08 1015. The packet is routed in the upward phase to the common ancestor (N21) through node N10 1001, and then a descent phase to the destination.
  • [0067]
    Note that during the upward phase at node N10, there are two candidate links (N10,N21) and (N10,N20). The first candidate link could be chosen deterministically, or an adaptive algorithm could dynamically select either of the links. But, once the node reaches the common ancestor and turns downward, there are no redundant paths (in general) for the node to reach the destination.
  • Unicast Routing in the Presence of No Faults
  • [0068]
    Each link is annotated within this unicastRoute table with a 2-bit linkWeight where software can express the relative cost/distance to the destination node via this link. By convention, link weights should represent:
      • 0=No route
      • 3=Direct next-hop connection
      • 1 and 2=Software computed relative costs. As an example if there are routes across 3 links with costs of 2 hops, 3 hops, and 6 hops, the first two links could be assigned weight=2 and the 6 hops path could be assigned weight=1.
        Algorithm for fault-free unicast routing:
      • Get link weight vector from the unicast routing table
        • linkWeightVector=unicastRoute[rframe.dstNode]
      • Remove link that it came in on to remove possibility of sending it back
      • Remove any links that are not up
      • At this point, have a candidate list of links with associated link weights.
      • Iterate through link weights, starting with highest priority (3) down through 1. Gather candidate list of links at this priority, stopping once the candidate list has at least one link. The result is a candidate list of links at the highest priority. As an example, if there are 2 links at weight=2, and 2 links at weight=1, the prioritized candidate list will contain the two links at weight=2.
      • The adaptive register is checked to determine whether to do adaptive or deterministic routing.
        • adaptive==0 indicates that deterministic routing is to be used, so the first link is chosen from the prioritized candidate list.
        • adaptive==1 indicates that adaptive routing is to be used. The switch implementation will choose an algorithm for adaptively choosing the target link from the prioritized candidate list. This adaptive algorithm could be as simple as round-robin around the list. Alternatively, may choose to factor in other attributes e.g. FIFO free depth, link speed, . . .
          • An implementation option could be to add a register option to allow the router to adaptively choose from all non-zero weights, or to only adaptively choose from the highest priority candidate lists.
      • The packet is sent out the selected link.
    Fault-Resilient Unicast Routing
  • [0083]
    A couple of issues contribute to the complexity of fault-resilient unicast routing:
      • The desire to do fault routing with only localized knowledge. A node implicitly knows that a link is down to a neighbor node. We choose a design to avoid having to communicate that a link (or node) goes down elsewhere in the fabric due to the complexities of maintaining a global, unified state in the presence of failures.
      • The nature of routing in a tree. During the ascent phase of packet routing, links can be adaptively chosen from redundant links so it can be straightforward to avoid a link with the normal adaptive link selection.
      • But, once the packet starts descending, traditionally there is not redundant paths for the descent path (that follow the routing rules), so fault routing can become challenging.
      • FIG. 8 illustrates a link failure (N10,N21) and unicast routing selected the (N10, N20) link using the normal adaptive routing algorithm previously described. But note, if the packet is routed up to N20 and link (N20,N12) is down, it has no easy path to get to the destination.
  • [0088]
    We have two approaches to handling routing around fails:
      • Software can compose alternative but non-desirable routes with weight=1. We'll call these escape routes. These are low priority routes that may violate the strict routing rules used during routing around faults. As an example, if the link (N20, N12) was down, the unicastRoute[N08] entry for N20 could contain link to N12 with weight=2 and a link to N11 with weight=1. In this way, the normal adaptive routing algorithms will automatically do the N20->N11->N21->N12->N08 path.
      • The fabric architecture includes a technique that we refer to as “misrouting”. Misrouting provides for iterative backtracking
      • Both of these techniques will provide substantial unicast fault-resilience.
    Unicast Misrouting
  • [0092]
    As an example, consider the following topology, with 3 links 1101, 1102 and 1103 that have failed (shown in Red in FIG. 9). Consider a unicast route from N0 to N3. We'll consider the following routing to understand the misrouting technique, understanding that this is only one of several routes that could have been chosen adaptively.
      • Packet routed N0 to N6.
      • Packet routed N6 to N10
      • N10 sees that it has no paths to get to N3, other than the link it came in on. N10 sets the misrouting bit in the routing header, and sends it back to N6.
      • N6 sees that the packet is being misrouted, sets the bit for the N10 link in the misrouteVector in the routing header, chooses an alternative link that has not been misrouted, and sends the packet to N11.
      • N11 sees that it has no path to N3, other than the link it came in on. misrouting bit is already on, and sends it back to N6.
      • N6 sees that the packet is being misrouted, adds N11 link to the misrouteVector (now contains N10 and N11 link IDs), chooses an alternative link that has not been misrouted, and sends it N7.
      • N7 sees that the misrouting bit is set, but does have a valid link to N3 (to N12), and thus clears the misrouting bit in the header, and forwards the packet to N12.
      • N12 sends to N9.
      • N9 unicastRoute now likely contains link to N3 (weight=3) and link to N8 (weight=2). Normal adaptive routing will not choose the direct link to N3 since it's down, and will route the packet to N8, then finally to N3.
      • If N6 had exhausted its list of candidate links (meaning the misrouteVector masked them all), the implementation then has two choices:
        • drop the packet and inform the M3 of the failure to route.
        • clear the misrouteVector leaving misrouting set, and forward the packet through one of the downward facing links (if one exists). This will retry misrouting at one layer lower. The implementation may want to have a register bit (enableRecursiveMisrouting) to enable this retry at lower layer option.
  • [0105]
    There is a register enableMisrouting that allows software to control whether the switch will initiate the misrouting algorithm.
  • Multi-Domaining
  • [0106]
    Also known to the inventors is Multi-Domaining, whose goal is to increase the addressability of nodes to a large number of nodes (e.g., 64K nodes), without having to increase the size of the unicast routing table to 64K nodes.
  • [0107]
    As currently described, the unicast routing table is a single-dimension array indexed by node number (i.e. 0 to MAX_NODES−1), where a typical implementation will be between 256 and 4K nodes.
  • [0108]
    This section will now describe how the current architecture is altered to support multiple domains, with 64K max nodes.
      • The node namespace is changed from a node ID from 0 to MAX_NODES−1, to a 2-tuple of (domain ID, node ID), where both domain ID and node ID range from 0 to 255. So, there can effectively be 256 domains where each domain can contain up to 256 nodes.
      • The unicast routing table is changed from a single dimension table of size MAX_NODES, to a two-dimension table of size 256. The unicast routing table is now changed from a structure of unicastRoute[NODES] to unicastRoute[2][256].
        • Local domain routing: When routing to a node within this domain, the unicast routing table is accessed as unicastRoute[0] [node ID], and provides a weighted link vector to route to the specified node ID from the current node.
        • Remote domain routing: When routing to a node within a remote domain, the unicast routing table is accessed as unicastRoute[1][domain ID], and provides a weighted link vector to route to the specified domain ID from the current node.
      • Routing frame: One bit is added to the routing frame, dstRemote, which is set true when routing to a remote domain.
        • Locally administered MAC addresses: The section below describes the Node Encoded Unicast MAC address encoding as follows:
  • [0000]
    Node Unicast 10 bits:
    Encoded Locally SS_MAC_NODE_ENCODED_MAGIC
    Unicast administered 12 bits: Node ID
    OUI == Switch 2 bits: Port ID
    OUI
  • [0115]
    This gets altered for multi-domaining as follows:
  • [0000]
    Node Unicast 6 bits:
    Encoded Locally SS_MAC_NODE_ENCODED_MAGIC
    Unicast administered 8 bits: Domain ID
    OUI == Switch 8 bits: Node ID
    OUI 2 bits: Port ID
      • Creating the routing frame header: Table 2 describes the algorithms for creating the routing frame header. This is augmented in the multi-domaining case by:
  • [0000]
    if ( dstDomain == myDomainID ) { // Route to local domain
    rframe.dstRemote = false;
    rframe.dstNode = dstNode;
    }
    else { // Route to remote domain
    rframe.dstRemote = true;
    rframe.dstNode = dstDomain;
  • Network Proxy
  • [0117]
    The concept of network proxy is the ability of the main processors (FIG. 5A, 905) to maintain network presence while in a low-power sleep/hibernation state, and intelligently wake when further processing is required. There are several architectural features related to Network Proxy:
      • There is a CSR (portRemap) to allow the remapping of Port IDs. In effect, when the switch is to deliver a packet to an internal MAC0 port (e.g. FIG. 5A, 902), this Port Remapping CSR allows software to remap MAC0 to the management processor MAC (e.g. FIG. 5A, 907) and have the packet delivered to the management processor for Network Proxy processing. This remapping CSR could also be used to remap MAC1 traffic to MAC0, or MAC1 traffic to the management processor.
      • Normally, the switch looks at the destination node ID of the routing frame to decide whether the packet is delivered to an internal port within the node, or gets routed to other XAUI connected nodes. This is done by matching Destination Node ID to “My Node ID”. The Node ID Match register (nodeRangeLo, nodeRangeHi) causes the packet to be delivered to an internal port within the node if nodeRangeLo<=Destination_Node<=nodeRangeHi∥myNodeID==Destination_Node. This allows a node to proxy for a subtree of nodes.
        A typical use sequence would be of the form:
      • Management processor maintains the IP to MAC address mappings for MAC0 and MAC1 on the node. This can be done via either explicit communication of these mappings from the main processor OS to the management processor, or can be done implicitly by having the management processor snoop local gratuitous ARP broadcasts.
      • The main processor coordinates with the management processor to go to a low power dormant state. During this transition, the management processor sets up the Port ID remapping CSR to route MAC0 and MAC1 traffic to the management processor.
      • The management processor processes any incoming MAC0/MAC1 packets. There are 3 categories of processing:
        • Respond to some classes of transactions that require simple responses (e.g. ARP responses and ICMP ping).
        • Dump and ignore some classes of packets, typically unicast or broadcast packets that are targeting other computers.
        • Decide that the main processor must be woken to process some classes of packets. The management processor will wake the main processor, undo the Port ID remapping register, and re-send the packets back through the switch where they will get rerouted back to MAC0/1.
    Wake-on-LAN Magic Packet
  • [0126]
    In a traditional desktop computer, the computer to be woken is shut down (sleeping, hibernating, or soft off; i.e., ACPI state G1 or G2), with power reserved for the network card, but not disconnected from its power source. The network card listens for a specific packet containing its MAC address, called the magic packet, broadcast on the broadcast address for that particular subnet (or an entire LAN, though this requires special hardware or configuration). The magic packet is sent on the data link or layer 2 in the OSI model and broadcast to all NICs within the network of the broadcast address; the IP-address (layer 3 in the OSI model) is not used. When the listening computer receives this packet, the network card checks the packet for the correct information. If the magic packet is valid, the network card takes the computer out of hibernation or standby, or starts it up.
  • [0127]
    The magic packet is a broadcast frame containing anywhere within its payload: 6 bytes of ones (resulting in hexadecimal FF FF FF FF FF FF), followed by sixteen repetitions of the target computer's MAC address. Since the magic packet is only scanned for the string above, and not actually parsed by a full protocol stack, it may be sent as a broadcast packet of any network- and transport-layer protocol. It is typically sent as a UDP datagram to port 0, 7 or 9, or, in former times, as an IPX packet.
  • [0128]
    Using the Network Proxy architecture just described, the management processor can support these Wake-On-LAN packets. It will get these broadcast packets, will know the MAC addresses for the other MACs on the node, and be able to wake up the main processor as appropriate. No further functionality is needed in the switch to support these Wake-on-LAN packets.
  • [0129]
    While the foregoing has been with reference to a particular embodiment of the invention, it will be appreciated by those skilled in the art that changes in this embodiment may be made without departing from the principles and spirit of the disclosure, the scope of which is defined by the appended claims.

Claims (14)

  1. 1. A switch fabric system, comprising a plurality of nodes; a plurality of links associated with each node that connect the node to another node in the plurality of nodes to create one of a tree topology and a graph topology of the switch fabric for routing data through the plurality of nodes; and wherein each link is designated as one of an Up link, a Down link and a Lateral link within the topology.
  2. 2. The switch fabric system of claim 1, wherein each node may be one of a computational and switch node and a switch node.
  3. 3. The system of claim 2, wherein each node includes input/output.
  4. 4. A switch fabric system having a plurality of nodes wherein each node may be one of a computational and switch node and a switch node.
  5. 5. A switch for a switch fabric system having a plurality of nodes with a segmented media access control (MAC) architecture, the switch comprising:
    at least one processor unit that controls routing of data in the switch;
    a first portion of the switch connected to the at least one processor and having an interface to an Ethernet controller for data;
    a second portion of the switch that converts the data into a plurality of packets and sends the plurality of packets to a fabric switch; and
    the packet switch having a port that is connected to the second portion of the switch that perform Ethernet signaling.
  6. 6. The system of claim 1, wherein the switch fabric further comprises at least one processor unit that controls routing of data in the switch, a first portion of the switch connected to the at least one processor and having an interface to an Ethernet controller for data, a second portion of the switch that converts the data into a plurality of packets and sends the plurality of packets to a fabric switch, and the packet switch having a port that is connected to the second portion of the switch that perform Ethernet signaling.
  7. 7. The system of claim 4, wherein the switch fabric further comprises at least one processor unit that controls routing of data in the switch, a first portion of the switch connected to the at least one processor and having an interface to an Ethernet controller for data, a second portion of the switch that converts the data into a plurality of packets and sends the plurality of packets to a fabric switch, and the packet switch having a port that is connected to the second portion of the switch that perform Ethernet signaling.
  8. 8. A switch fabric system, comprising a plurality of nodes; each nodes having a management processor; and wherein a communications path between the management processors of the plurality of nodes is secure so that the management processors can trust each other.
  9. 9. A method of re-purposing an Ethernet MAC controller IP for inside MACs and outside MACs, and leveraging what would normally be the physical signaling for the MAC to feed into the switch.
  10. 10. A method of nonspoofing communication in a switch fabric system, the method comprising:
    providing a plurality of nodes wherein each node has a management processor and one or more pieces of software being executed by the management processor are verified software; and
    establishing a trusted relationship between the plurality of nodes, wherein establishing the trusted relationship further comprises inserting a domain ID into a routing header at a source node of a packet; and
    communicating securely between the management processors of the source node and a destination node, wherein the secure communication occurs when the routing header of the packet with the domain ID is verified by the destination node.
  11. 11. A method of fault-resilient unicast routing in a switch fabric having a plurality of nodes and a plurality of links associated with each node that connect the node to another node in the plurality of nodes to create a switch fabric with a plurality of routes, the method comprising:
    generating an escape route from a first node to a second node in the switch fabric wherein the escape route has a low priority weight; and
    misrouting data from the first node to the second node when a link is inactive wherein the escape route and misrouting provide fault tolerance to the switch fabric.
  12. 12. The method of claim 11, wherein the misrouting data from the first node to the second node further comprises iteratively backtracking to route data from the first node to the second node through one or more intervening nodes when a link between the first and second nodes is inactive.
  13. 13. The method of claim 12, wherein the iteratively backtracking further comprises:
    setting, when a node in the data path does not have a link path to the second node, a misrouting bit in a header of the data;
    sending the data back to an originating node that sent the data to the node that set the misrouting bit;
    choosing one or more alternate links, by the originating node, for the data; and
    clearing the misrouting bit in a header of the data if the data reaches the second node over one of the alternative links.
  14. 14-24. (canceled)
US12794996 2009-10-30 2010-06-07 System and method for high-performance, low-power data center interconnect fabric Abandoned US20110103391A1 (en)

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US12794996 US20110103391A1 (en) 2009-10-30 2010-06-07 System and method for high-performance, low-power data center interconnect fabric
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CN 201510827453 CN105357152A (en) 2009-10-30 2010-10-19 System and method for high-performance, low-power data center interconnect fabric
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CN 201080060153 CN102668473B (en) 2009-10-30 2010-10-19 For high-performance, low power systems and methods for data center interconnect structure
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EP20160163413 EP3070894A1 (en) 2009-10-30 2010-10-19 Multiprocessor system with hibernation state
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US13234054 US9876735B2 (en) 2009-10-30 2011-09-15 Performance and power optimized computer system architectures and methods leveraging power optimized tree fabric interconnect
US13453086 US8599863B2 (en) 2009-10-30 2012-04-23 System and method for using a multi-protocol fabric module across a distributed server interconnect fabric
US13475713 US9054990B2 (en) 2009-10-30 2012-05-18 System and method for data center security enhancements leveraging server SOCs or server fabrics
US13475722 US9077654B2 (en) 2009-10-30 2012-05-18 System and method for data center security enhancements leveraging managed server SOCs
US13624725 US9405584B2 (en) 2009-10-30 2012-09-21 System and method for high-performance, low-power data center interconnect fabric with addressing and unicast routing
US13624731 US9075655B2 (en) 2009-10-30 2012-09-21 System and method for high-performance, low-power data center interconnect fabric with broadcast or multicast addressing
US13662759 US9465771B2 (en) 2009-09-24 2012-10-29 Server on a chip and node cards comprising one or more of same
US13692741 US9311269B2 (en) 2009-10-30 2012-12-03 Network proxy for high-performance, low-power data center interconnect fabric
US13705428 US20130097351A1 (en) 2009-10-30 2012-12-05 System and Method for High-Performance, Low-Power Data Center Interconnect Fabric
US13705386 US8745302B2 (en) 2009-10-30 2012-12-05 System and method for high-performance, low-power data center interconnect fabric
US13705340 US9008079B2 (en) 2009-10-30 2012-12-05 System and method for high-performance, low-power data center interconnect fabric
US13705414 US8737410B2 (en) 2009-10-30 2012-12-05 System and method for high-performance, low-power data center interconnect fabric
US13728308 US9262225B2 (en) 2009-10-30 2012-12-27 Remote memory access functionality in a cluster of data processing nodes
US14052723 US9680770B2 (en) 2009-10-30 2013-10-12 System and method for using a multi-protocol fabric module across a distributed server interconnect fabric
US14334178 US9479463B2 (en) 2009-10-30 2014-07-17 System and method for data center security enhancements leveraging managed server SOCs
US14334931 US9454403B2 (en) 2009-10-30 2014-07-18 System and method for high-performance, low-power data center interconnect fabric
US14725543 US9509552B2 (en) 2009-10-30 2015-05-29 System and method for data center security enhancements leveraging server SOCs or server fabrics
US15042489 US20160239415A1 (en) 2009-10-30 2016-02-12 Remote memory access functionality in a cluster of data processing nodes
US15078115 US20160202752A1 (en) 2009-10-30 2016-03-23 Network Proxy for High-Performance, Low-Power Data Center Interconnect Fabric
US15254111 US9866477B2 (en) 2009-10-30 2016-09-01 System and method for high-performance, low-power data center interconnect fabric
US15270418 US9929976B2 (en) 2009-10-30 2016-09-20 System and method for data center security enhancements leveraging managed server SOCs
US15281462 US20170115712A1 (en) 2009-09-24 2016-09-30 Server on a Chip and Node Cards Comprising One or More of Same
US15357332 US20170068639A1 (en) 2009-10-30 2016-11-21 Memcached server functionality in a cluster of data processing nodes
US15360668 US9749326B2 (en) 2009-10-30 2016-11-23 System and method for data center security enhancements leveraging server SOCs or server fabrics
US15672418 US20170359347A1 (en) 2009-10-30 2017-08-09 SYSTEM AND METHOD FOR DATA CENTER SECURITY ENHANCEMENTS LEVERAGING SERVER SOCs OR SERVER FABRICS

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US13284855 Continuation-In-Part US20130107444A1 (en) 2011-10-28 2011-10-28 System and method for flexible storage and networking provisioning in large scalable processor installations
US13475713 Continuation-In-Part US9054990B2 (en) 2009-10-30 2012-05-18 System and method for data center security enhancements leveraging server SOCs or server fabrics
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US13453086 Continuation-In-Part US8599863B2 (en) 2009-10-30 2012-04-23 System and method for using a multi-protocol fabric module across a distributed server interconnect fabric
US13475713 Continuation-In-Part US9054990B2 (en) 2009-10-30 2012-05-18 System and method for data center security enhancements leveraging server SOCs or server fabrics
US13475722 Continuation-In-Part US9077654B2 (en) 2009-10-30 2012-05-18 System and method for data center security enhancements leveraging managed server SOCs
US13624731 Division US9075655B2 (en) 2009-10-30 2012-09-21 System and method for high-performance, low-power data center interconnect fabric with broadcast or multicast addressing
US13624725 Division US9405584B2 (en) 2009-10-30 2012-09-21 System and method for high-performance, low-power data center interconnect fabric with addressing and unicast routing
US13662759 Continuation-In-Part US9465771B2 (en) 2009-09-24 2012-10-29 Server on a chip and node cards comprising one or more of same
US13692741 Continuation-In-Part US9311269B2 (en) 2009-10-30 2012-12-03 Network proxy for high-performance, low-power data center interconnect fabric
US13705386 Continuation US8745302B2 (en) 2009-10-30 2012-12-05 System and method for high-performance, low-power data center interconnect fabric
US13705428 Continuation US20130097351A1 (en) 2009-10-30 2012-12-05 System and Method for High-Performance, Low-Power Data Center Interconnect Fabric
US13705340 Continuation US9008079B2 (en) 2009-10-30 2012-12-05 System and method for high-performance, low-power data center interconnect fabric
US13705414 Continuation US8737410B2 (en) 2009-10-30 2012-12-05 System and method for high-performance, low-power data center interconnect fabric
US13728308 Continuation US9262225B2 (en) 2009-10-30 2012-12-27 Remote memory access functionality in a cluster of data processing nodes
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Cited By (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110258641A1 (en) * 2010-04-20 2011-10-20 International Business Machines Corporation Remote Adapter Configuration
US20120254400A1 (en) * 2011-03-31 2012-10-04 International Business Machines Corporation System to improve operation of a data center with heterogeneous computing clouds
WO2012162313A2 (en) * 2011-05-24 2012-11-29 Calxeda, Inc. System and method for data center security enhancements leveraging server socs or server fabrics
WO2012162314A1 (en) * 2011-05-24 2012-11-29 Calxeda, Inc. System and method for data center security enhancements leveraging managed server socs
US20130089104A1 (en) * 2009-10-30 2013-04-11 Calxeda, Inc. System and Method for High-Performance, Low-Power Data Center Interconnect Fabric
US20130250802A1 (en) * 2012-03-26 2013-09-26 Praveen Yalagandula Reducing cabling costs in a datacenter network
US8594100B2 (en) 2010-03-31 2013-11-26 International Business Machines Corporation Data frame forwarding using a distributed virtual bridge
US8619796B2 (en) 2010-04-22 2013-12-31 International Business Machines Corporation Forwarding data frames with a distributed fiber channel forwarder
WO2014015664A1 (en) * 2012-07-26 2014-01-30 华为技术有限公司 Communication method and system
WO2014039922A2 (en) * 2012-09-06 2014-03-13 Pi-Coral, Inc. Large-scale data storage and delivery system
US20140181573A1 (en) * 2012-12-26 2014-06-26 Calxeda, Inc. Fabric discovery for a cluster of nodes
US8856419B2 (en) 2010-07-19 2014-10-07 International Business Machines Corporation Register access in distributed virtual bridge environment
US8861400B2 (en) 2012-01-18 2014-10-14 International Business Machines Corporation Requesting multicast membership information in a distributed switch in response to a miss event
US8891535B2 (en) 2012-01-18 2014-11-18 International Business Machines Corporation Managing a global forwarding table in a distributed switch
US20150181317A1 (en) * 2013-12-24 2015-06-25 Nec Laboratories America, Inc. Scalable hybrid packet/circuit switching network architecture
US9069929B2 (en) 2011-10-31 2015-06-30 Iii Holdings 2, Llc Arbitrating usage of serial port in node card of scalable and modular servers
US20150333926A1 (en) * 2014-05-14 2015-11-19 International Business Machines Corporation Autonomous multi-node network configuration and self-awareness through establishment of a switch port group
US9311269B2 (en) 2009-10-30 2016-04-12 Iii Holdings 2, Llc Network proxy for high-performance, low-power data center interconnect fabric
US9465771B2 (en) 2009-09-24 2016-10-11 Iii Holdings 2, Llc Server on a chip and node cards comprising one or more of same
US20160352775A1 (en) * 2014-04-09 2016-12-01 Hewlett Packard Enterprise Development Lp Identifying suspicious activity in a load test
US9585281B2 (en) 2011-10-28 2017-02-28 Iii Holdings 2, Llc System and method for flexible storage and networking provisioning in large scalable processor installations
US20170068639A1 (en) * 2009-10-30 2017-03-09 Iii Holdings 2, Llc Memcached server functionality in a cluster of data processing nodes
US9648102B1 (en) * 2012-12-27 2017-05-09 Iii Holdings 2, Llc Memcached server functionality in a cluster of data processing nodes
US9680770B2 (en) 2009-10-30 2017-06-13 Iii Holdings 2, Llc System and method for using a multi-protocol fabric module across a distributed server interconnect fabric
WO2017100292A1 (en) * 2015-12-08 2017-06-15 Ultrata, Llc. Object memory interfaces across shared links
US9876735B2 (en) 2009-10-30 2018-01-23 Iii Holdings 2, Llc Performance and power optimized computer system architectures and methods leveraging power optimized tree fabric interconnect
US9886210B2 (en) 2015-06-09 2018-02-06 Ultrata, Llc Infinite memory fabric hardware implementation with router

Families Citing this family (67)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011156746A3 (en) * 2010-06-11 2012-04-19 California Institute Of Technology Systems and methods for rapid processing and storage of data
US8924752B1 (en) 2011-04-20 2014-12-30 Apple Inc. Power management for a graphics processing unit or other circuit
US9066160B2 (en) * 2011-07-07 2015-06-23 Alcatel Lucent Apparatus and method for protection in a data center
US8612583B2 (en) * 2011-07-29 2013-12-17 Cisco Technology, Inc. Network management system scheduling for low power and lossy networks
WO2012083705A1 (en) * 2011-08-11 2012-06-28 华为技术有限公司 A node aggregation system for implementing a symmetric multi-processing system
US9128949B2 (en) * 2012-01-18 2015-09-08 Cloudera, Inc. Memory allocation buffer for reduction of heap fragmentation
US9390461B1 (en) * 2012-05-08 2016-07-12 Apple Inc. Graphics hardware mode controls
US20130346655A1 (en) * 2012-06-22 2013-12-26 Advanced Micro Devices, Inc. Bus agent capable of supporting extended atomic operations and method therefor
US9699263B1 (en) 2012-08-17 2017-07-04 Sandisk Technologies Llc. Automatic read and write acceleration of data accessed by virtual machines
US9507406B2 (en) 2012-09-21 2016-11-29 Atmel Corporation Configuring power domains of a microcontroller system
US9618991B1 (en) 2012-09-27 2017-04-11 Google Inc. Large-scale power back-up for data centers
US9537793B2 (en) * 2012-10-10 2017-01-03 Cisco Technology, Inc. Ensuring any-to-any reachability with opportunistic layer 3 forwarding in massive scale data center environments
US9372825B1 (en) * 2013-02-27 2016-06-21 Netapp, Inc. Global non-volatile solid-state cache in a network storage system
US9389940B2 (en) * 2013-02-28 2016-07-12 Silicon Graphics International Corp. System and method for error logging
KR20140112717A (en) * 2013-03-14 2014-09-24 삼성전자주식회사 Data Storage System based on a key-value and Operating Method thereof
US9870830B1 (en) 2013-03-14 2018-01-16 Sandisk Technologies Llc Optimal multilevel sensing for reading data from a storage medium
US20140344431A1 (en) * 2013-05-16 2014-11-20 Aspeed Technology Inc. Baseboard management system architecture
CN103297560A (en) * 2013-05-21 2013-09-11 江苏物联网研究发展中心 Data flow classification method and data flow classification server
US9330055B2 (en) * 2013-06-04 2016-05-03 International Business Machines Corporation Modular architecture for extreme-scale distributed processing applications
US9304577B2 (en) 2013-06-05 2016-04-05 Avago Technologies General Ip (Singapore) Pte. Ltd. Reducing power consumption and wakeup latency in SSD controllers by not resetting flash devices
US9477276B2 (en) * 2013-06-13 2016-10-25 Dell Products L.P. System and method for switch management
US9619389B1 (en) * 2013-07-11 2017-04-11 Unigen Corporation System for a backward and forward application environment compatible distributed shared coherent storage
US9146814B1 (en) * 2013-08-26 2015-09-29 Amazon Technologies, Inc. Mitigating an impact of a datacenter thermal event
US9639463B1 (en) 2013-08-26 2017-05-02 Sandisk Technologies Llc Heuristic aware garbage collection scheme in storage systems
KR20150058600A (en) 2013-11-18 2015-05-29 삼성전자주식회사 Flexible server system
US9703816B2 (en) 2013-11-19 2017-07-11 Sandisk Technologies Llc Method and system for forward reference logging in a persistent datastore
US9582058B2 (en) 2013-11-29 2017-02-28 Sandisk Technologies Llc Power inrush management of storage devices
KR200476881Y1 (en) * 2013-12-09 2015-04-10 네이버비즈니스플랫폼 주식회사 Booth apparatus for supplying cooling air
US9497283B2 (en) * 2013-12-13 2016-11-15 Oracle International Corporation System and method for providing data interoperability in a distributed data grid
US9438435B2 (en) 2014-01-31 2016-09-06 Intenational Business Machines Corporation Secure, multi-tenancy aware and bandwidth-efficient data center multicast
US9734063B2 (en) 2014-02-27 2017-08-15 École Polytechnique Fédérale De Lausanne (Epfl) Scale-out non-uniform memory access
US9703636B2 (en) * 2014-03-01 2017-07-11 Sandisk Technologies Llc Firmware reversion trigger and control
US9547553B1 (en) 2014-03-10 2017-01-17 Parallel Machines Ltd. Data resiliency in a shared memory pool
US9690713B1 (en) 2014-04-22 2017-06-27 Parallel Machines Ltd. Systems and methods for effectively interacting with a flash memory
EP2924934A1 (en) * 2014-03-28 2015-09-30 Airbus Operations GmbH Ethernet switch and method for establishing forwarding patterns in an Ethernet switch
US9626400B2 (en) 2014-03-31 2017-04-18 Sandisk Technologies Llc Compaction of information in tiered data structure
US9626399B2 (en) 2014-03-31 2017-04-18 Sandisk Technologies Llc Conditional updates for reducing frequency of data modification operations
US9697267B2 (en) 2014-04-03 2017-07-04 Sandisk Technologies Llc Methods and systems for performing efficient snapshots in tiered data structures
US9781027B1 (en) 2014-04-06 2017-10-03 Parallel Machines Ltd. Systems and methods to communicate with external destinations via a memory network
US9846658B2 (en) * 2014-04-21 2017-12-19 Cisco Technology, Inc. Dynamic temporary use of packet memory as resource memory
US20150304233A1 (en) * 2014-04-22 2015-10-22 Cisco Technology, Inc. Efficient management and configuration of in-band resources
US20170048167A1 (en) * 2014-04-30 2017-02-16 Hewlett Packard Enterprise Development Lp Flood disable on network switch
US9703491B2 (en) 2014-05-30 2017-07-11 Sandisk Technologies Llc Using history of unaligned writes to cache data and avoid read-modify-writes in a non-volatile storage device
US9652381B2 (en) 2014-06-19 2017-05-16 Sandisk Technologies Llc Sub-block garbage collection
US9397939B2 (en) * 2014-06-24 2016-07-19 International Business Machines Corporation Hybrid approach for performance enhancing proxies
US9684367B2 (en) * 2014-06-26 2017-06-20 Atmel Corporation Power trace port for tracing states of power domains
US9852138B2 (en) 2014-06-30 2017-12-26 EMC IP Holding Company LLC Content fabric for a distributed file system
US20150381426A1 (en) * 2014-06-30 2015-12-31 Emc Corporation Dynamically composed compute nodes comprising disaggregated components
US9720868B2 (en) * 2014-07-07 2017-08-01 Xilinx, Inc. Bridging inter-bus communications
US20160098376A1 (en) * 2014-10-07 2016-04-07 Elliptic Technologies Inc. Side channel communication hardware driver
US9588863B2 (en) * 2014-10-21 2017-03-07 International Business Machines Corporation Generation and application of stressmarks in a computer system
CN104378237A (en) * 2014-11-24 2015-02-25 英业达科技有限公司 Method for judging service node state
US9781225B1 (en) 2014-12-09 2017-10-03 Parallel Machines Ltd. Systems and methods for cache streams
US9594688B1 (en) 2014-12-09 2017-03-14 Parallel Machines Ltd. Systems and methods for executing actions using cached data
US9753873B1 (en) 2014-12-09 2017-09-05 Parallel Machines Ltd. Systems and methods for key-value transactions
US9690705B1 (en) 2014-12-09 2017-06-27 Parallel Machines Ltd. Systems and methods for processing data sets according to an instructed order
US9639473B1 (en) 2014-12-09 2017-05-02 Parallel Machines Ltd. Utilizing a cache mechanism by copying a data set from a cache-disabled memory location to a cache-enabled memory location
US9594696B1 (en) 2014-12-09 2017-03-14 Parallel Machines Ltd. Systems and methods for automatic generation of parallel data processing code
US9684689B2 (en) * 2015-02-03 2017-06-20 Ca, Inc. Distributed parallel processing system having jobs processed by nodes based on authentication using unique identification of data
US20160275194A1 (en) * 2015-03-18 2016-09-22 Microsoft Technology Licensing, Llc Query formulation via task continuum
US9792248B2 (en) 2015-06-02 2017-10-17 Microsoft Technology Licensing, Llc Fast read/write between networked computers via RDMA-based RPC requests
US20160378344A1 (en) * 2015-06-24 2016-12-29 Intel Corporation Processor and platform assisted nvdimm solution using standard dram and consolidated storage
US9658671B2 (en) * 2015-09-28 2017-05-23 Qualcomm Incorporated Power-aware CPU power grid design
US9906370B2 (en) 2015-11-16 2018-02-27 International Business Machines Corporation Trust relationship management amongst racks in a data center
US20170180271A1 (en) * 2015-12-22 2017-06-22 Intel Corporation Techniques for embedding fabric address information into locally-administered ethernet media access control addresses (macs) and a multi-node fabric system implementing the same
CN105550157B (en) * 2015-12-24 2017-06-27 中国科学院计算技术研究所 Fractal tree communication structure, method, control device and the smart chip
US9921997B2 (en) * 2016-04-01 2018-03-20 Intel Corporation Mechanism for PCIE cable topology discovery in a rack scale architecture environment

Citations (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6252878B1 (en) * 1997-10-30 2001-06-26 Cisco Technology, Inc. Switched architecture access server
US20020097732A1 (en) * 2001-01-19 2002-07-25 Tom Worster Virtual private network protocol
US20030007493A1 (en) * 2001-06-28 2003-01-09 Hitoshi Oi Routing mechanism for static load balancing in a partitioned computer system with a fully connected network
US6574238B1 (en) * 1998-08-26 2003-06-03 Intel Corporation Inter-switch link header modification
US20030110262A1 (en) * 2001-07-06 2003-06-12 Taqi Hasan Integrated rule network management system
US20030202520A1 (en) * 2002-04-26 2003-10-30 Maxxan Systems, Inc. Scalable switch fabric system and apparatus for computer networks
US20030231624A1 (en) * 2002-06-12 2003-12-18 Alappat Kuriappan P. Backplane for switch fabric
US20040210693A1 (en) * 2003-04-15 2004-10-21 Newisys, Inc. Managing I/O accesses in multiprocessor systems
US6842430B1 (en) * 1996-10-16 2005-01-11 Koninklijke Philips Electronics N.V. Method for configuring and routing data within a wireless multihop network and a wireless network for implementing the same
US20050240688A1 (en) * 2004-04-27 2005-10-27 Filip Moerman Efficient data transfer from an ASIC to a host using DMA
US6990063B1 (en) * 2000-03-07 2006-01-24 Cisco Technology, Inc. Distributing fault indications and maintaining and using a data structure indicating faults to route traffic in a packet switching system
US20060029053A1 (en) * 2000-05-03 2006-02-09 At&T Laboratories-Cambridge Ltd. Data transfer, synchronising applications, and low latency networks
US20070226795A1 (en) * 2006-02-09 2007-09-27 Texas Instruments Incorporated Virtual cores and hardware-supported hypervisor integrated circuits, systems, methods and processes of manufacture
US20070280230A1 (en) * 2006-05-31 2007-12-06 Motorola, Inc Method and system for service discovery across a wide area network
US20080013453A1 (en) * 2006-07-13 2008-01-17 Sbc Knowledge Ventures, L.P. Method and apparatus for configuring a network topology with alternative communication paths
US20080075089A1 (en) * 2006-09-26 2008-03-27 Cisco Technology, Inc. Snooping of on-path ip reservation protocols for layer 2 nodes
US20080140771A1 (en) * 2006-12-08 2008-06-12 Sony Computer Entertainment Inc. Simulated environment computing framework
US20080183882A1 (en) * 2006-12-06 2008-07-31 David Flynn Apparatus, system, and method for a device shared between multiple independent hosts
US7447197B2 (en) * 2001-10-18 2008-11-04 Qlogic, Corporation System and method of providing network node services
US20080301794A1 (en) * 2007-05-31 2008-12-04 Jaushin Lee Method and system for providing remote access to resources in a secure data center over a network
US7466712B2 (en) * 2004-07-30 2008-12-16 Brocade Communications Systems, Inc. System and method for providing proxy and translation domains in a fibre channel router
US20080320161A1 (en) * 2007-06-25 2008-12-25 Stmicroelectronics Sa Method for transferring data from a source target to a destination target, and corresponding network interface
US20090080428A1 (en) * 2007-09-25 2009-03-26 Maxxan Systems, Inc. System and method for scalable switch fabric for computer network
US20090135835A1 (en) * 2004-05-05 2009-05-28 Gigamon Systems Llc Asymmetric packet switch and a method of use
US7586841B2 (en) * 2005-05-31 2009-09-08 Cisco Technology, Inc. System and method for protecting against failure of a TE-LSP tail-end node
US20090225751A1 (en) * 2007-05-22 2009-09-10 Koenck Steven E Mobile nodal based communication system, method and apparatus
US7599360B2 (en) * 2001-12-26 2009-10-06 Cisco Technology, Inc. Methods and apparatus for encapsulating a frame for transmission in a storage area network
US7606225B2 (en) * 2006-02-06 2009-10-20 Fortinet, Inc. Integrated security switch
US20090279518A1 (en) * 2006-08-24 2009-11-12 Rainer Falk Method and arrangement for providing a wireless mesh network
US7620057B1 (en) * 2004-10-19 2009-11-17 Broadcom Corporation Cache line replacement with zero latency
US7710936B2 (en) * 2004-06-02 2010-05-04 Jose Morales Barroso Universal ethernet telecommunications service
US7760720B2 (en) * 2004-11-09 2010-07-20 Cisco Technology, Inc. Translating native medium access control (MAC) addresses to hierarchical MAC addresses and their use
US7831839B2 (en) * 2005-02-07 2010-11-09 Sony Computer Entertainment Inc. Methods and apparatus for providing a secure booting sequence in a processor
US7840703B2 (en) * 2007-08-27 2010-11-23 International Business Machines Corporation System and method for dynamically supporting indirect routing within a multi-tiered full-graph interconnect architecture
US20100318812A1 (en) * 2009-06-12 2010-12-16 Microsoft Corporation Secure and private backup storage and processing for trusted computing and data services
US8019832B2 (en) * 2007-05-16 2011-09-13 Coreworks, S.A. Network core access architecture
US20120020207A1 (en) * 2008-05-12 2012-01-26 Telfonaktiebolaget L M Ericsson (Publ) Re-routing traffice in a communications network
US8199636B1 (en) * 2002-10-18 2012-06-12 Alcatel Lucent Bridged network system with traffic resiliency upon link failure

Family Cites Families (319)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5594908A (en) 1989-12-27 1997-01-14 Hyatt; Gilbert P. Computer system having a serial keyboard, a serial display, and a dynamic memory with memory refresh
US5396635A (en) 1990-06-01 1995-03-07 Vadem Corporation Power conservation apparatus having multiple power reduction levels dependent upon the activity of the computer system
US5451936A (en) 1991-06-20 1995-09-19 The Johns Hopkins University Non-blocking broadcast network
US5781187A (en) 1994-05-31 1998-07-14 Advanced Micro Devices, Inc. Interrupt transmission via specialized bus cycle within a symmetrical multiprocessing system
JPH08123763A (en) 1994-10-26 1996-05-17 Nec Corp Memory assigning system for distributed processing system
US6055618A (en) * 1995-10-31 2000-04-25 Cray Research, Inc. Virtual maintenance network in multiprocessing system having a non-flow controlled virtual maintenance channel
JP3541335B2 (en) * 1996-06-28 2004-07-07 富士通株式会社 Information processing apparatus and distributed processing control method
JP3662378B2 (en) * 1996-12-17 2005-06-22 川崎マイクロエレクトロニクス株式会社 Network repeaters
US5968176A (en) 1997-05-29 1999-10-19 3Com Corporation Multilayer firewall system
US5971804A (en) 1997-06-30 1999-10-26 Emc Corporation Backplane having strip transmission line ethernet bus
US6507586B1 (en) * 1997-09-18 2003-01-14 International Business Machines Corporation Multicast data transmission over a one-way broadband channel
KR100286375B1 (en) 1997-10-02 2001-01-12 윤종용 Radiator of electronic system and computer system having the same
US5908468A (en) 1997-10-24 1999-06-01 Advanced Micro Devices, Inc. Data transfer network on a chip utilizing a multiple traffic circle topology
US5901048A (en) 1997-12-11 1999-05-04 International Business Machines Corporation Printed circuit board with chip collar
KR100250437B1 (en) * 1997-12-26 2000-04-01 정선종 Path control device for round robin arbitration and adaptation
US6192414B1 (en) 1998-01-27 2001-02-20 Moore Products Co. Network communications system manager
US7801132B2 (en) 1999-11-09 2010-09-21 Synchrodyne Networks, Inc. Interface system and methodology having scheduled connection responsive to common time reference
US8108508B1 (en) 1998-06-22 2012-01-31 Hewlett-Packard Development Company, L.P. Web server chip for network manageability
US6373841B1 (en) 1998-06-22 2002-04-16 Agilent Technologies, Inc. Integrated LAN controller and web server chip
US6181699B1 (en) 1998-07-01 2001-01-30 National Semiconductor Corporation Apparatus and method of assigning VLAN tags
US6314501B1 (en) 1998-07-23 2001-11-06 Unisys Corporation Computer system and method for operating multiple operating systems in different partitions of the computer system and for allowing the different partitions to communicate with one another through shared memory
US6963926B1 (en) 1999-03-31 2005-11-08 British Telecommunications Public Limited Company Progressive routing in a communications network
US6711691B1 (en) 1999-05-13 2004-03-23 Apple Computer, Inc. Power management for computer systems
US6442137B1 (en) 1999-05-24 2002-08-27 Advanced Micro Devices, Inc. Apparatus and method in a network switch for swapping memory access slots between gigabit port and expansion port
US7020695B1 (en) 1999-05-28 2006-03-28 Oracle International Corporation Using a cluster-wide shared repository to provide the latest consistent definition of the cluster (avoiding the partition-in time problem)
US6446192B1 (en) 1999-06-04 2002-09-03 Embrace Networks, Inc. Remote monitoring and control of equipment over computer networks using a single web interfacing chip
US6697359B1 (en) 1999-07-02 2004-02-24 Ancor Communications, Inc. High performance switch fabric element and switch systems
US8171204B2 (en) 2000-01-06 2012-05-01 Super Talent Electronics, Inc. Intelligent solid-state non-volatile memory device (NVMD) system with multi-level caching of multiple channels
US6857026B1 (en) 1999-12-14 2005-02-15 Nortel Networks Limited Using alternate routes for fail-over in a communication network
US6608564B2 (en) 2000-01-25 2003-08-19 Hewlett-Packard Development Company, L.P. Removable memory cartridge system for use with a server or other processor-based device
US6556952B1 (en) 2000-05-04 2003-04-29 Advanced Micro Devices, Inc. Performance monitoring and optimizing of controller parameters
US7080078B1 (en) 2000-05-09 2006-07-18 Sun Microsystems, Inc. Mechanism and apparatus for URI-addressable repositories of service advertisements and other content in a distributed computing environment
US7143153B1 (en) 2000-11-09 2006-11-28 Ciena Corporation Internal network device dynamic health monitoring
JP2001333091A (en) * 2000-05-23 2001-11-30 Fujitsu Ltd Communication equipment
US6816750B1 (en) 2000-06-09 2004-11-09 Cirrus Logic, Inc. System-on-a-chip
US6668308B2 (en) 2000-06-10 2003-12-23 Hewlett-Packard Development Company, L.P. Scalable architecture based on single-chip multiprocessing
US6760861B2 (en) 2000-09-29 2004-07-06 Zeronines Technology, Inc. System, method and apparatus for data processing and storage to provide continuous operations independent of device failure or disaster
US7032119B2 (en) 2000-09-27 2006-04-18 Amphus, Inc. Dynamic power and workload management for multi-server system
US7274705B2 (en) 2000-10-03 2007-09-25 Broadcom Corporation Method and apparatus for reducing clock speed and power consumption
US20020040391A1 (en) 2000-10-04 2002-04-04 David Chaiken Server farm formed of systems on a chip
US7165120B1 (en) 2000-10-11 2007-01-16 Sun Microsystems, Inc. Server node with interated networking capabilities
US20020107903A1 (en) 2000-11-07 2002-08-08 Richter Roger K. Methods and systems for the order serialization of information in a network processing environment
US6452809B1 (en) 2000-11-10 2002-09-17 Galactic Computing Corporation Scalable internet engine
US6954463B1 (en) 2000-12-11 2005-10-11 Cisco Technology, Inc. Distributed packet processing architecture for network access servers
US7616646B1 (en) 2000-12-12 2009-11-10 Cisco Technology, Inc. Intraserver tag-switched distributed packet processing for network access servers
JP3532153B2 (en) 2000-12-22 2004-05-31 株式会社 沖マイクロデザイン Level shifter control circuit
CN1503946A (en) 2000-12-29 2004-06-09 明 裘 Server array hardware architecture and system
US6977939B2 (en) 2001-01-26 2005-12-20 Microsoft Corporation Method and apparatus for emulating ethernet functionality over a serial bus
US7339786B2 (en) 2001-03-05 2008-03-04 Intel Corporation Modular server architecture with Ethernet routed across a backplane utilizing an integrated Ethernet switch module
US7093280B2 (en) 2001-03-30 2006-08-15 Juniper Networks, Inc. Internet security system
US20020188754A1 (en) 2001-04-27 2002-12-12 Foster Michael S. Method and system for domain addressing in a communications network
US20020161917A1 (en) * 2001-04-30 2002-10-31 Shapiro Aaron M. Methods and systems for dynamic routing of data in a network
US7161901B2 (en) 2001-05-07 2007-01-09 Vitesse Semiconductor Corporation Automatic load balancing in switch fabrics
WO2002091672A3 (en) 2001-05-07 2003-09-12 Vitesse Semiconductor Corp A system and a method for processing data packets or frames
US6766389B2 (en) 2001-05-18 2004-07-20 Broadcom Corporation System on a chip for networking
DE10127198A1 (en) 2001-06-05 2002-12-19 Infineon Technologies Ag Physical address provision method for processor system with virtual addressing uses hierarchy mapping process for conversion of virtual address
US6950895B2 (en) 2001-06-13 2005-09-27 Intel Corporation Modular server architecture
US6501660B1 (en) 2001-06-22 2002-12-31 Sun Microsystems, Inc. Reliable card detection in a CPCI system
US6813676B1 (en) 2001-07-27 2004-11-02 Lsi Logic Corporation Host interface bypass on a fabric based array controller
US6944786B2 (en) * 2001-07-27 2005-09-13 International Business Machines Corporation Network node failover using multicast address or port
US7525904B1 (en) * 2002-06-20 2009-04-28 Cisco Technology, Inc. Redundant packet routing and switching device and method
US6968470B2 (en) 2001-08-07 2005-11-22 Hewlett-Packard Development Company, L.P. System and method for power management in a server system
US6724635B2 (en) 2001-08-07 2004-04-20 Hewlett-Packard Development Company, L.P. LCD panel for a server system
US7337333B2 (en) 2001-09-19 2008-02-26 Dell Products L.P. System and method for strategic power supply sequencing in a computer system with multiple processing resources and multiple power supplies
US7325050B2 (en) 2001-09-19 2008-01-29 Dell Products L.P. System and method for strategic power reduction in a computer system
US6779086B2 (en) 2001-10-16 2004-08-17 International Business Machines Corporation Symmetric multiprocessor systems with an independent super-coherent cache directory
US8325716B2 (en) 2001-10-22 2012-12-04 Broadcom Corporation Data path optimization algorithm
US6963948B1 (en) 2001-11-01 2005-11-08 Advanced Micro Devices, Inc. Microcomputer bridge architecture with an embedded microcontroller
US7310319B2 (en) 2001-11-02 2007-12-18 Intel Corporation Multiple-domain processing system using hierarchically orthogonal switching fabric
US7464016B2 (en) 2001-11-09 2008-12-09 Sun Microsystems, Inc. Hot plug and hot pull system simulation
US7209657B1 (en) 2001-12-03 2007-04-24 Cheetah Omni, Llc Optical routing using a star switching fabric
US20030140190A1 (en) 2002-01-23 2003-07-24 Sun Microsystems, Inc. Auto-SCSI termination enable in a CPCI hot swap system
US7284067B2 (en) 2002-02-20 2007-10-16 Hewlett-Packard Development Company, L.P. Method for integrated load balancing among peer servers
US20030172191A1 (en) 2002-02-22 2003-09-11 Williams Joel R. Coupling of CPU and disk drive to form a server and aggregating a plurality of servers into server farms
US7970929B1 (en) * 2002-03-19 2011-06-28 Dunti Llc Apparatus, system, and method for routing data to and from a host that is moved from one location on a communication system to another location on the communication system
US7096377B2 (en) 2002-03-27 2006-08-22 Intel Corporation Method and apparatus for setting timing parameters
US20030196126A1 (en) 2002-04-11 2003-10-16 Fung Henry T. System, method, and architecture for dynamic server power management and dynamic workload management for multi-server environment
US7095738B1 (en) * 2002-05-07 2006-08-22 Cisco Technology, Inc. System and method for deriving IPv6 scope identifiers and for mapping the identifiers into IPv6 addresses
US7353530B1 (en) 2002-05-10 2008-04-01 At&T Corp. Method and apparatus for assigning communication nodes to CMTS cards
US7161904B2 (en) 2002-06-04 2007-01-09 Fortinet, Inc. System and method for hierarchical metering in a virtual router based network switch
US7376125B1 (en) 2002-06-04 2008-05-20 Fortinet, Inc. Service processing switch
US7415723B2 (en) 2002-06-11 2008-08-19 Pandya Ashish A Distributed network security system and a hardware processor therefor
US7685254B2 (en) 2003-06-10 2010-03-23 Pandya Ashish A Runtime adaptable search processor
US7180866B1 (en) * 2002-07-11 2007-02-20 Nortel Networks Limited Rerouting in connection-oriented communication networks and communication systems
US7039018B2 (en) * 2002-07-17 2006-05-02 Intel Corporation Technique to improve network routing using best-match and exact-match techniques
US7286544B2 (en) 2002-07-25 2007-10-23 Brocade Communications Systems, Inc. Virtualized multiport switch
US7286527B2 (en) 2002-07-26 2007-10-23 Brocade Communications Systems, Inc. Method and apparatus for round trip delay measurement in a bi-directional, point-to-point, serial data channel
US8295288B2 (en) 2002-07-30 2012-10-23 Brocade Communications System, Inc. Registered state change notification for a fibre channel network
US7055044B2 (en) 2002-08-12 2006-05-30 Hewlett-Packard Development Company, L.P. System and method for voltage management of a processor to optimize performance and power dissipation
EP1394985A1 (en) 2002-08-28 2004-03-03 Siemens Aktiengesellschaft Test method for network path between network elements in communication networks
US20110090633A1 (en) 2002-09-23 2011-04-21 Josef Rabinovitz Modular sata data storage device assembly
US7934005B2 (en) 2003-09-08 2011-04-26 Koolspan, Inc. Subnet box
US7080283B1 (en) 2002-10-15 2006-07-18 Tensilica, Inc. Simultaneous real-time trace and debug for multiple processing core systems on a chip
US7792113B1 (en) * 2002-10-21 2010-09-07 Cisco Technology, Inc. Method and system for policy-based forwarding
US6661671B1 (en) 2002-11-27 2003-12-09 International Business Machines Corporation Apparatus, method and article of manufacture for determining power permission for a blade spanning power back planes
US7512788B2 (en) 2002-12-10 2009-03-31 International Business Machines Corporation Method and apparatus for anonymous group messaging in a distributed messaging system
US7917658B2 (en) 2003-01-21 2011-03-29 Emulex Design And Manufacturing Corporation Switching apparatus and method for link initialization in a shared I/O environment
US8024548B2 (en) 2003-02-18 2011-09-20 Christopher Joseph Daffron Integrated circuit microprocessor that constructs, at run time, integrated reconfigurable logic into persistent finite state machines from pre-compiled machine code instruction sequences
US7447147B2 (en) 2003-02-28 2008-11-04 Cisco Technology, Inc. Ethernet switch with configurable alarms
US7039771B1 (en) 2003-03-10 2006-05-02 Marvell International Ltd. Method and system for supporting multiple external serial port devices using a serial port controller in embedded disk controllers
US7216123B2 (en) 2003-03-28 2007-05-08 Board Of Trustees Of The Leland Stanford Junior University Methods for ranking nodes in large directed graphs
US7340777B1 (en) 2003-03-31 2008-03-04 Symantec Corporation In memory heuristic system and method for detecting viruses
US20040215650A1 (en) 2003-04-09 2004-10-28 Ullattil Shaji Interfaces and methods for group policy management
US20040215991A1 (en) 2003-04-23 2004-10-28 Dell Products L.P. Power-up of multiple processors when a voltage regulator module has failed
US7676600B2 (en) 2003-04-23 2010-03-09 Dot Hill Systems Corporation Network, storage appliance, and method for externalizing an internal I/O link between a server and a storage controller integrated within the storage appliance chassis
US20040215864A1 (en) 2003-04-28 2004-10-28 International Business Machines Corporation Non-disruptive, dynamic hot-add and hot-remove of non-symmetric data processing system resources
US7400996B2 (en) 2003-06-26 2008-07-15 Benjamin Thomas Percer Use of I2C-based potentiometers to enable voltage rail variation under BMC control
US7512067B2 (en) 2003-07-21 2009-03-31 Qlogic, Corporation Method and system for congestion control based on optimum bandwidth allocation in a fibre channel switch
US7646767B2 (en) 2003-07-21 2010-01-12 Qlogic, Corporation Method and system for programmable data dependant network routing
US7477655B2 (en) 2003-07-21 2009-01-13 Qlogic, Corporation Method and system for power control of fibre channel switches
US7894348B2 (en) 2003-07-21 2011-02-22 Qlogic, Corporation Method and system for congestion control in a fibre channel switch
JP2005041127A (en) 2003-07-23 2005-02-17 Brother Ind Ltd Status information notification system, network terminal device and communication processing device
US7412588B2 (en) 2003-07-25 2008-08-12 International Business Machines Corporation Network processor system on chip with bridge coupling protocol converting multiprocessor macro core local bus to peripheral interfaces coupled system bus
US7353362B2 (en) 2003-07-25 2008-04-01 International Business Machines Corporation Multiprocessor subsystem in SoC with bridge between processor clusters interconnetion and SoC system bus
US7170315B2 (en) 2003-07-31 2007-01-30 Actel Corporation Programmable system on a chip
US7028125B2 (en) 2003-08-04 2006-04-11 Inventec Corporation Hot-pluggable peripheral input device coupling system
US7620736B2 (en) * 2003-08-08 2009-11-17 Cray Canada Corporation Network topology having nodes interconnected by extended diagonal links
US7512808B2 (en) 2003-08-29 2009-03-31 Trend Micro, Inc. Anti-computer viral agent suitable for innoculation of computing devices
JP2007507990A (en) 2003-10-14 2007-03-29 ラプター・ネツトワークス・テクノロジー・インコーポレイテツド Switching system comprising a distributed switching structure
US7174470B2 (en) 2003-10-14 2007-02-06 Hewlett-Packard Development Company, L.P. Computer data bus interface control
US7415543B2 (en) 2003-11-12 2008-08-19 Lsi Corporation Serial port initialization in storage system controllers
CN1890990B (en) * 2003-12-12 2011-04-06 诺基亚西门子通信有限责任两合公司 Method for backup switching spatially separated switching systems
US7916638B2 (en) 2003-12-24 2011-03-29 Alcatel Lucent Time-independent deficit round robin method and system
US7109760B1 (en) 2004-01-05 2006-09-19 Integrated Device Technology, Inc. Delay-locked loop (DLL) integrated circuits that support efficient phase locking of clock signals having non-unity duty cycles
CN1906573B (en) * 2004-01-20 2011-01-05 美国博通公司 System and method for supporting multiple users
JP4248420B2 (en) 2004-02-06 2009-04-02 日本電信電話株式会社 Handover control method of a mobile communication network
US7664110B1 (en) 2004-02-07 2010-02-16 Habanero Holdings, Inc. Input/output controller for coupling the processor-memory complex to the fabric in fabric-backplane interprise servers
US7583661B2 (en) 2004-03-05 2009-09-01 Sid Chaudhuri Method and apparatus for improved IP networks and high-quality services
US7865582B2 (en) 2004-03-24 2011-01-04 Hewlett-Packard Development Company, L.P. System and method for assigning an application component to a computing resource
US7437540B2 (en) 2004-03-26 2008-10-14 Atmel Corporation Complex domain floating point VLIW DSP with data/program bus multiplexer and microprocessor interface
US7203063B2 (en) 2004-05-21 2007-04-10 Hewlett-Packard Development Company, L.P. Small form factor liquid loop cooling system
US7467358B2 (en) 2004-06-03 2008-12-16 Gwangju Institute Of Science And Technology Asynchronous switch based on butterfly fat-tree for network on chip application
WO2005125027A1 (en) 2004-06-15 2005-12-29 Fujitsu Component Limited Transceiver module
JP4334419B2 (en) 2004-06-30 2009-09-30 富士通株式会社 Transmission equipment
US7586904B2 (en) 2004-07-15 2009-09-08 Broadcom Corp. Method and system for a gigabit Ethernet IP telephone chip with no DSP core, which uses a RISC core with instruction extensions to support voice processing
US9264384B1 (en) 2004-07-22 2016-02-16 Oracle International Corporation Resource virtualization mechanism including virtual host bus adapters
JP4455206B2 (en) 2004-07-29 2010-04-21 キヤノン株式会社 Image forming apparatus and control method thereof
US7657756B2 (en) 2004-10-08 2010-02-02 International Business Machines Corporaiton Secure memory caching structures for data, integrity and version values
US7257655B1 (en) 2004-10-13 2007-08-14 Altera Corporation Embedded PCI-Express implementation
WO2006041218A3 (en) 2004-10-15 2007-04-26 Sony Computer Entertainment Inc Methods and apparatus for supporting multiple configurations in a multi-processor system
US20060090025A1 (en) 2004-10-25 2006-04-27 Tufford Robert C 9U payload module configurations
US7278582B1 (en) 2004-12-03 2007-10-09 Sun Microsystems, Inc. Hardware security module (HSM) chip card
US7394288B1 (en) 2004-12-13 2008-07-01 Massachusetts Institute Of Technology Transferring data in a parallel processing environment
US7657677B2 (en) 2004-12-27 2010-02-02 Quanta Computer Inc. Blade server system with a management bus and method for managing the same
US8533777B2 (en) 2004-12-29 2013-09-10 Intel Corporation Mechanism to determine trust of out-of-band management agents
US7676841B2 (en) 2005-02-01 2010-03-09 Fmr Llc Network intrusion mitigation
US8140770B2 (en) 2005-02-10 2012-03-20 International Business Machines Corporation Data processing system and method for predictively selecting a scope of broadcast of an operation
US7467306B2 (en) 2005-03-08 2008-12-16 Hewlett-Packard Development Company, L.P. Methods and systems for allocating power to an electronic device
US7881332B2 (en) 2005-04-01 2011-02-01 International Business Machines Corporation Configurable ports for a host ethernet adapter
JP4591185B2 (en) 2005-04-28 2010-12-01 株式会社日立製作所 The server device
US7363463B2 (en) 2005-05-13 2008-04-22 Microsoft Corporation Method and system for caching address translations from multiple address spaces in virtual machines
US7596144B2 (en) 2005-06-07 2009-09-29 Broadcom Corp. System-on-a-chip (SoC) device with integrated support for ethernet, TCP, iSCSI, RDMA, and network application acceleration
US8200739B2 (en) 2005-06-23 2012-06-12 Telefonaktiebolaget L M Ericsson (Publ) Arrangement and method relating to load distribution
JP2007012000A (en) 2005-07-04 2007-01-18 Hitachi Ltd Storage controller and storage system
US7461274B2 (en) 2005-08-23 2008-12-02 International Business Machines Corporation Method for maximizing server utilization in a resource constrained environment
US7307837B2 (en) 2005-08-23 2007-12-11 International Business Machines Corporation Method and apparatus for enforcing of power control in a blade center chassis
US7315456B2 (en) 2005-08-29 2008-01-01 Hewlett-Packard Development Company, L.P. Configurable IO subsystem
US8982778B2 (en) * 2005-09-19 2015-03-17 Qualcomm Incorporated Packet routing in a wireless communications environment
US7382154B2 (en) 2005-10-03 2008-06-03 Honeywell International Inc. Reconfigurable network on a chip
US8516165B2 (en) 2005-10-19 2013-08-20 Nvidia Corporation System and method for encoding packet header to enable higher bandwidth efficiency across bus links
US7574590B2 (en) 2005-10-26 2009-08-11 Sigmatel, Inc. Method for booting a system on a chip integrated circuit
CN100417118C (en) * 2005-10-28 2008-09-03 华为技术有限公司;西安电子科技大学 System and method for renewing network mobile node position in wireless net-like network
US8051189B2 (en) * 2005-11-18 2011-11-01 Genband Us Llc Methods, systems, and computer program products for session initiation protocol (SIP) fast switchover
CN2852260Y (en) 2005-12-01 2006-12-27 华为技术有限公司 Server
EP1808994A1 (en) 2006-01-12 2007-07-18 Alcatel Lucent Universal switch for transporting packet data frames
WO2007084403A3 (en) 2006-01-13 2008-04-24 Andreas V Bechtolsheim Compact rackmount storage server
WO2007084422A3 (en) 2006-01-13 2008-05-08 Sun Microsystems Inc Modular blade server
US20070174390A1 (en) * 2006-01-20 2007-07-26 Avise Partners Customer service management
US7991817B2 (en) 2006-01-23 2011-08-02 California Institute Of Technology Method and a circuit using an associative calculator for calculating a sequence of non-associative operations
US20070180310A1 (en) * 2006-02-02 2007-08-02 Texas Instruments, Inc. Multi-core architecture with hardware messaging
US9177176B2 (en) 2006-02-27 2015-11-03 Broadcom Corporation Method and system for secure system-on-a-chip architecture for multimedia data processing
US20090133129A1 (en) 2006-03-06 2009-05-21 Lg Electronics Inc. Data transferring method
FR2898753B1 (en) 2006-03-16 2008-04-18 Commissariat Energie Atomique SoC has semi-distributed control
CN101060442A (en) * 2006-04-22 2007-10-24 华为技术有限公司 A linkage status detection device and method
US7555666B2 (en) 2006-05-04 2009-06-30 Dell Products L.P. Power profiling application for managing power allocation in an information handling system
JP2007304687A (en) 2006-05-09 2007-11-22 Hitachi Ltd Cluster constitution and its control means
US7660922B2 (en) 2006-05-12 2010-02-09 Intel Corporation Mechanism to flexibly support multiple device numbers on point-to-point interconnect upstream ports
CN101083606B (en) * 2006-05-29 2011-03-02 中兴通讯股份有限公司 Disaster recovery backup method and apparatus for mobile switching centre simulation
US7522468B2 (en) 2006-06-08 2009-04-21 Unity Semiconductor Corporation Serial memory interface
CN101094125A (en) 2006-06-23 2007-12-26 华为技术有限公司 Exchange structure in ATCA / ATCA300 expanded exchange bandwidth
US20080040463A1 (en) 2006-08-08 2008-02-14 International Business Machines Corporation Communication System for Multiple Chassis Computer Systems
CN101127696B (en) * 2006-08-15 2012-06-27 华为技术有限公司 Data forwarding method for layer 2 network and network and node devices
US20080052437A1 (en) 2006-08-28 2008-02-28 Dell Products L.P. Hot Plug Power Policy for Modular Chassis
US7802082B2 (en) 2006-08-31 2010-09-21 Intel Corporation Methods and systems to dynamically configure computing apparatuses
US7853755B1 (en) 2006-09-29 2010-12-14 Tilera Corporation Caching in multicore and multiprocessor architectures
US8684802B1 (en) 2006-10-27 2014-04-01 Oracle America, Inc. Method and apparatus for balancing thermal variations across a set of computer systems
US8447872B2 (en) 2006-11-01 2013-05-21 Intel Corporation Load balancing in a storage system
US7992151B2 (en) 2006-11-30 2011-08-02 Intel Corporation Methods and apparatuses for core allocations
US20080140930A1 (en) 2006-12-08 2008-06-12 Emulex Design & Manufacturing Corporation Virtual drive mapping
CN101212345A (en) 2006-12-31 2008-07-02 联想(北京)有限公司 Blade server management system
US8504791B2 (en) 2007-01-26 2013-08-06 Hicamp Systems, Inc. Hierarchical immutable content-addressable memory coprocessor
JP5106020B2 (en) 2007-02-08 2012-12-26 パナソニック株式会社 The pattern forming method
US7865614B2 (en) 2007-02-12 2011-01-04 International Business Machines Corporation Method and apparatus for load balancing with server state change awareness
FI120088B (en) 2007-03-01 2009-06-30 Kone Corp The arrangement and method for monitoring a safety circuit
US7870907B2 (en) 2007-03-08 2011-01-18 Weatherford/Lamb, Inc. Debris protection for sliding sleeve
JP4370336B2 (en) 2007-03-09 2009-11-25 株式会社日立製作所 Low Power job management method and a computer system
US20080239649A1 (en) 2007-03-29 2008-10-02 Bradicich Thomas M Design structure for an interposer for expanded capability of a blade server chassis system
US7783910B2 (en) 2007-03-30 2010-08-24 International Business Machines Corporation Method and system for associating power consumption of a server with a network address assigned to the server
US20090097200A1 (en) 2007-04-11 2009-04-16 Viswa Sharma Modular blade for providing scalable mechanical, electrical and environmental functionality in the enterprise using advancedtca boards
JP4815385B2 (en) 2007-04-13 2011-11-16 株式会社日立製作所 Storage devices
US7515412B2 (en) 2007-04-26 2009-04-07 Enermax Technology Corporation Cooling structure for power supply
US7715400B1 (en) 2007-04-26 2010-05-11 3 Leaf Networks Node identification for distributed shared memory system
US7925795B2 (en) 2007-04-30 2011-04-12 Broadcom Corporation Method and system for configuring a plurality of network interfaces that share a physical interface
DE102007020296A1 (en) 2007-04-30 2008-11-13 Philip Behrens Apparatus and method for wireless making contact
US7552241B2 (en) 2007-05-18 2009-06-23 Tilera Corporation Method and system for managing a plurality of I/O interfaces with an array of multicore processor resources in a semiconductor chip
WO2008147926A1 (en) 2007-05-25 2008-12-04 Venkat Konda Fully connected generalized butterfly fat tree networks
US7783813B2 (en) 2007-06-14 2010-08-24 International Business Machines Corporation Multi-node configuration of processor cards connected via processor fabrics
US8060775B1 (en) 2007-06-14 2011-11-15 Symantec Corporation Method and apparatus for providing dynamic multi-pathing (DMP) for an asymmetric logical unit access (ALUA) based storage system
JP4962152B2 (en) 2007-06-15 2012-06-27 日立電線株式会社 Combined optical and electrical transmission assembly
US8140719B2 (en) 2007-06-21 2012-03-20 Sea Micro, Inc. Dis-aggregated and distributed data-center architecture using a direct interconnect fabric
US7761687B2 (en) 2007-06-26 2010-07-20 International Business Machines Corporation Ultrascalable petaflop parallel supercomputer
US8060760B2 (en) 2007-07-13 2011-11-15 Dell Products L.P. System and method for dynamic information handling system prioritization
US7688578B2 (en) 2007-07-19 2010-03-30 Hewlett-Packard Development Company, L.P. Modular high-density computer system
WO2009023563A1 (en) 2007-08-10 2009-02-19 Smith Robert B Path redundant hardware efficient communications interconnect system
CN101369958A (en) * 2007-08-15 2009-02-18 华为技术有限公司 Fast rerouting method and label exchange router
US7895463B2 (en) 2007-08-28 2011-02-22 Cisco Technology, Inc. Redundant application network appliances using a low latency lossless interconnect link
US7898941B2 (en) * 2007-09-11 2011-03-01 Polycom, Inc. Method and system for assigning a plurality of MACs to a plurality of processors
US20090251867A1 (en) 2007-10-09 2009-10-08 Sharma Viswa N Reconfigurable, modularized fpga-based amc module
US7739475B2 (en) 2007-10-24 2010-06-15 Inventec Corporation System and method for updating dirty data of designated raw device
US7822841B2 (en) 2007-10-30 2010-10-26 Modern Grids, Inc. Method and system for hosting multiple, customized computing clusters
EP2061191A1 (en) 2007-11-13 2009-05-20 STMicroelectronics (Grenoble) SAS Buffering architecture for packet injection and extraction in on-chip networks.
US8068433B2 (en) 2007-11-26 2011-11-29 Microsoft Corporation Low power operation of networked devices
US7877622B2 (en) 2007-12-13 2011-01-25 International Business Machines Corporation Selecting between high availability redundant power supply modes for powering a computer system
US7962771B2 (en) 2007-12-31 2011-06-14 Intel Corporation Method, system, and apparatus for rerouting interrupts in a multi-core processor
US20090166065A1 (en) 2008-01-02 2009-07-02 Clayton James E Thin multi-chip flex module
US7779148B2 (en) 2008-02-01 2010-08-17 International Business Machines Corporation Dynamic routing based on information of not responded active source requests quantity received in broadcast heartbeat signal and stored in local data structure for other processor chips
US20090204834A1 (en) 2008-02-11 2009-08-13 Nvidia Corporation System and method for using inputs as wake signals
US20090204837A1 (en) 2008-02-11 2009-08-13 Udaykumar Raval Power control system and method
US8082400B1 (en) 2008-02-26 2011-12-20 Hewlett-Packard Development Company, L.P. Partitioning a memory pool among plural computing nodes
US8156362B2 (en) 2008-03-11 2012-04-10 Globalfoundries Inc. Hardware monitoring and decision making for transitioning in and out of low-power state
US20090248943A1 (en) 2008-04-01 2009-10-01 Inventec Corporation Server
US8762759B2 (en) 2008-04-10 2014-06-24 Nvidia Corporation Responding to interrupts while in a reduced power state
US20090259864A1 (en) 2008-04-10 2009-10-15 Nvidia Corporation System and method for input/output control during power down mode
JP5350461B2 (en) 2008-04-16 2013-11-27 テレフオンアクチーボラゲット エル エム エリクソン(パブル) Expansion of the traffic instructions in Connectivity Fault Management
US7742844B2 (en) 2008-04-21 2010-06-22 Dell Products, Lp Information handling system including cooling devices and methods of use thereof
JP5075727B2 (en) 2008-04-25 2012-11-21 株式会社日立製作所 Stream distribution system and fault detection method
US7725603B1 (en) 2008-04-30 2010-05-25 Network Appliance, Inc. Automatic network cluster path management
US7861110B2 (en) 2008-04-30 2010-12-28 Egenera, Inc. System, method, and adapter for creating fault-tolerant communication busses from standard components
US20090282419A1 (en) 2008-05-09 2009-11-12 International Business Machines Corporation Ordered And Unordered Network-Addressed Message Control With Embedded DMA Commands For A Network On Chip
US7921315B2 (en) 2008-05-09 2011-04-05 International Business Machines Corporation Managing power consumption in a data center based on monitoring circuit breakers
US8180996B2 (en) 2008-05-15 2012-05-15 Calxeda, Inc. Distributed computing system with universal address system and method
US20100008038A1 (en) 2008-05-15 2010-01-14 Giovanni Coglitore Apparatus and Method for Reliable and Efficient Computing Based on Separating Computing Modules From Components With Moving Parts
US8775718B2 (en) 2008-05-23 2014-07-08 Netapp, Inc. Use of RDMA to access non-volatile solid-state memory in a network storage system
US7519843B1 (en) 2008-05-30 2009-04-14 International Business Machines Corporation Method and system for dynamic processor speed control to always maximize processor performance based on processing load and available power
US7904345B2 (en) 2008-06-10 2011-03-08 The Go Daddy Group, Inc. Providing website hosting overage protection by transference to an overflow server
US8244918B2 (en) 2008-06-11 2012-08-14 International Business Machines Corporation Resource sharing expansion card
US8767749B2 (en) 2008-06-12 2014-07-01 Tejas Israel Ltd Method and system for transparent LAN services in a packet network
US8886985B2 (en) 2008-07-07 2014-11-11 Raritan Americas, Inc. Automatic discovery of physical connectivity between power outlets and IT equipment
EP2313819A2 (en) 2008-07-14 2011-04-27 The Regents of the University of California Architecture to enable energy savings in networked computers
US20100026408A1 (en) 2008-07-30 2010-02-04 Jeng-Jye Shau Signal transfer for ultra-high capacity circuits
US8031703B2 (en) 2008-08-14 2011-10-04 Dell Products, Lp System and method for dynamic maintenance of fabric subsets in a network
US8132034B2 (en) 2008-08-28 2012-03-06 Dell Products L.P. System and method for managing information handling system power supply capacity utilization based on load sharing power loss
JP5428267B2 (en) 2008-09-26 2014-02-26 富士通株式会社 Power control system, and a power supply control method
US8484493B2 (en) 2008-10-29 2013-07-09 Dell Products, Lp Method for pre-chassis power multi-slot blade identification and inventory
US8068482B2 (en) 2008-11-13 2011-11-29 Qlogic, Corporation Method and system for network switch element
US20100125915A1 (en) 2008-11-17 2010-05-20 International Business Machines Corporation Secure Computer Architecture
JP5151924B2 (en) 2008-11-19 2013-02-27 富士通株式会社 Power management proxy system, the server device, server power control method using the proxy device, the proxy device power management program, the server device power management program
US20100161909A1 (en) 2008-12-18 2010-06-24 Lsi Corporation Systems and Methods for Quota Management in a Memory Appliance
US20100158005A1 (en) * 2008-12-23 2010-06-24 Suvhasis Mukhopadhyay System-On-a-Chip and Multi-Chip Systems Supporting Advanced Telecommunication Functions
US20100169479A1 (en) 2008-12-26 2010-07-01 Electronics And Telecommunications Research Institute Apparatus and method for extracting user information using client-based script
US8804710B2 (en) 2008-12-29 2014-08-12 Juniper Networks, Inc. System architecture for a scalable and distributed multi-stage switch fabric
US8122269B2 (en) 2009-01-07 2012-02-21 International Business Machines Corporation Regulating power consumption in a multi-core processor by dynamically distributing power and processing requests by a managing core to a configuration of processing cores
US8775544B2 (en) 2009-02-04 2014-07-08 Citrix Systems, Inc. Methods and systems for dynamically switching between communications protocols
US8510744B2 (en) 2009-02-24 2013-08-13 Siemens Product Lifecycle Management Software Inc. Using resource defining attributes to enhance thread scheduling in processors
GB0903229D0 (en) 2009-02-25 2009-04-08 Advanced Risc Mach Ltd Blade server
JP5816407B2 (en) 2009-02-27 2015-11-18 ルネサスエレクトロニクス株式会社 The semiconductor integrated circuit device
US8725946B2 (en) 2009-03-23 2014-05-13 Ocz Storage Solutions, Inc. Mass storage system and method of using hard disk, solid-state media, PCIe edge connector, and raid controller
US8140871B2 (en) 2009-03-27 2012-03-20 International Business Machines Corporation Wake on Lan for blade server
US7889490B2 (en) 2009-04-17 2011-02-15 Inventec Corporation Server with trays for electronic components
US8127128B2 (en) 2009-05-04 2012-02-28 International Business Machines Corporation Synchronization of swappable module in modular system
US8004922B2 (en) 2009-06-05 2011-08-23 Nxp B.V. Power island with independent power characteristics for memory and logic
US9001846B2 (en) 2009-06-09 2015-04-07 Broadcom Corporation Physical layer device with dual medium access controller path
CN102473157B (en) 2009-07-17 2015-12-16 惠普开发有限公司 Shared virtual hot i / o insertion environment
CN101989212B (en) 2009-07-31 2015-01-07 国际商业机器公司 Method and device for providing virtual machine management program for starting blade server
US8340120B2 (en) 2009-09-04 2012-12-25 Brocade Communications Systems, Inc. User selectable multiple protocol network interface device
US9465771B2 (en) 2009-09-24 2016-10-11 Iii Holdings 2, Llc Server on a chip and node cards comprising one or more of same
US20110075369A1 (en) 2009-09-29 2011-03-31 Inventec Corporation Electronic device
US20110087771A1 (en) 2009-10-05 2011-04-14 Vss Monitoring, Inc. Method, apparatus and system for a layer of stacked network captured traffic distribution devices
US8194659B2 (en) 2009-10-06 2012-06-05 Red Hat, Inc. Mechanism for processing messages using logical addresses
US8571031B2 (en) 2009-10-07 2013-10-29 Intel Corporation Configurable frame processing pipeline in a packet switch
CN103444133A (en) 2010-09-16 2013-12-11 卡尔克塞达公司 Performance and power optimized computer system architecture and leveraging power optimized tree fabric interconnecting
US8599863B2 (en) 2009-10-30 2013-12-03 Calxeda, Inc. System and method for using a multi-protocol fabric module across a distributed server interconnect fabric
US9876735B2 (en) 2009-10-30 2018-01-23 Iii Holdings 2, Llc Performance and power optimized computer system architectures and methods leveraging power optimized tree fabric interconnect
US9054990B2 (en) 2009-10-30 2015-06-09 Iii Holdings 2, Llc System and method for data center security enhancements leveraging server SOCs or server fabrics
US9311269B2 (en) 2009-10-30 2016-04-12 Iii Holdings 2, Llc Network proxy for high-performance, low-power data center interconnect fabric
US9680770B2 (en) 2009-10-30 2017-06-13 Iii Holdings 2, Llc System and method for using a multi-protocol fabric module across a distributed server interconnect fabric
US20110103391A1 (en) * 2009-10-30 2011-05-05 Smooth-Stone, Inc. C/O Barry Evans System and method for high-performance, low-power data center interconnect fabric
US9767070B2 (en) 2009-11-06 2017-09-19 Hewlett Packard Enterprise Development Lp Storage system with a memory blade that generates a computational result for a storage device
US20110119344A1 (en) 2009-11-17 2011-05-19 Susan Eustis Apparatus And Method For Using Distributed Servers As Mainframe Class Computers
US20110191514A1 (en) 2010-01-29 2011-08-04 Inventec Corporation Server system
JP5648926B2 (en) 2010-02-01 2015-01-07 日本電気株式会社 Network system, controller, network control method
US8291147B2 (en) 2010-02-08 2012-10-16 Hon Hai Precision Industry Co., Ltd. Computer motherboard with adjustable connection between central processing unit and peripheral interfaces
US20110210975A1 (en) 2010-02-26 2011-09-01 Xgi Technology, Inc. Multi-screen signal processing device and multi-screen system
US8397092B2 (en) 2010-03-24 2013-03-12 Emulex Design & Manufacturing Corporation Power management for input/output devices by creating a virtual port for redirecting traffic
KR101641108B1 (en) 2010-04-30 2016-07-20 삼성전자주식회사 Target device providing debugging functionality and test system comprising the same
US8045328B1 (en) 2010-05-04 2011-10-25 Chenbro Micom Co., Ltd. Server and cooler moduel arrangement
US8407428B2 (en) 2010-05-20 2013-03-26 Hicamp Systems, Inc. Structured memory coprocessor
US8750164B2 (en) 2010-07-06 2014-06-10 Nicira, Inc. Hierarchical managed switch architecture
US8812400B2 (en) 2010-07-09 2014-08-19 Hewlett-Packard Development Company, L.P. Managing a memory segment using a memory virtual appliance
US9083612B2 (en) 2010-08-20 2015-07-14 Nec Corporation Communication system, control apparatus, communication method, and program
CN102385417B (en) 2010-08-25 2013-02-20 英业达股份有限公司 Rack-mounted server
US8601288B2 (en) 2010-08-31 2013-12-03 Sonics, Inc. Intelligent power controller
JP2012053504A (en) 2010-08-31 2012-03-15 Hitachi Ltd Blade server device
US20120081850A1 (en) 2010-09-30 2012-04-05 Dell Products L.P. Rack Assembly for Housing and Providing Power to Information Handling Systems
US8699220B2 (en) 2010-10-22 2014-04-15 Xplore Technologies Corp. Computer with removable cartridge
US8738860B1 (en) 2010-10-25 2014-05-27 Tilera Corporation Computing in parallel processing environments
DE102011056141A1 (en) 2010-12-20 2012-06-21 Samsung Electronics Co., Ltd. Negative voltage generator, decoders, non-volatile memory device and memory system that uses a negative voltage
US20120198252A1 (en) 2011-02-01 2012-08-02 Kirschtein Phillip M System and Method for Managing and Detecting Server Power Connections
US8670450B2 (en) 2011-05-13 2014-03-11 International Business Machines Corporation Efficient software-based private VLAN solution for distributed virtual switches
US8547825B2 (en) 2011-07-07 2013-10-01 International Business Machines Corporation Switch fabric management
US8683125B2 (en) 2011-11-01 2014-03-25 Hewlett-Packard Development Company, L.P. Tier identification (TID) for tiered memory characteristics
US9565132B2 (en) 2011-12-27 2017-02-07 Intel Corporation Multi-protocol I/O interconnect including a switching fabric
US8782321B2 (en) 2012-02-08 2014-07-15 Intel Corporation PCI express tunneling over a multi-protocol I/O interconnect
US8854831B2 (en) 2012-04-10 2014-10-07 Arnouse Digital Devices Corporation Low power, high density server and portable device for use with same
US8954698B2 (en) * 2012-04-13 2015-02-10 International Business Machines Corporation Switching optically connected memory
US20130290643A1 (en) 2012-04-30 2013-10-31 Kevin T. Lim Using a cache in a disaggregated memory architecture
US20130290650A1 (en) 2012-04-30 2013-10-31 Jichuan Chang Distributed active data storage system
US9286472B2 (en) 2012-05-22 2016-03-15 Xockets, Inc. Efficient packet handling, redirection, and inspection using offload processors
US9304896B2 (en) 2013-08-05 2016-04-05 Iii Holdings 2, Llc Remote memory ring buffers in a cluster of data processing nodes

Patent Citations (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6842430B1 (en) * 1996-10-16 2005-01-11 Koninklijke Philips Electronics N.V. Method for configuring and routing data within a wireless multihop network and a wireless network for implementing the same
US6252878B1 (en) * 1997-10-30 2001-06-26 Cisco Technology, Inc. Switched architecture access server
US6574238B1 (en) * 1998-08-26 2003-06-03 Intel Corporation Inter-switch link header modification
US6990063B1 (en) * 2000-03-07 2006-01-24 Cisco Technology, Inc. Distributing fault indications and maintaining and using a data structure indicating faults to route traffic in a packet switching system
US20060029053A1 (en) * 2000-05-03 2006-02-09 At&T Laboratories-Cambridge Ltd. Data transfer, synchronising applications, and low latency networks
US20020097732A1 (en) * 2001-01-19 2002-07-25 Tom Worster Virtual private network protocol
US20030007493A1 (en) * 2001-06-28 2003-01-09 Hitoshi Oi Routing mechanism for static load balancing in a partitioned computer system with a fully connected network
US20030110262A1 (en) * 2001-07-06 2003-06-12 Taqi Hasan Integrated rule network management system
US7447197B2 (en) * 2001-10-18 2008-11-04 Qlogic, Corporation System and method of providing network node services
US7599360B2 (en) * 2001-12-26 2009-10-06 Cisco Technology, Inc. Methods and apparatus for encapsulating a frame for transmission in a storage area network
US20030202520A1 (en) * 2002-04-26 2003-10-30 Maxxan Systems, Inc. Scalable switch fabric system and apparatus for computer networks
US20030231624A1 (en) * 2002-06-12 2003-12-18 Alappat Kuriappan P. Backplane for switch fabric
US8199636B1 (en) * 2002-10-18 2012-06-12 Alcatel Lucent Bridged network system with traffic resiliency upon link failure
US20040210693A1 (en) * 2003-04-15 2004-10-21 Newisys, Inc. Managing I/O accesses in multiprocessor systems
US20050240688A1 (en) * 2004-04-27 2005-10-27 Filip Moerman Efficient data transfer from an ASIC to a host using DMA
US20090135835A1 (en) * 2004-05-05 2009-05-28 Gigamon Systems Llc Asymmetric packet switch and a method of use
US7710936B2 (en) * 2004-06-02 2010-05-04 Jose Morales Barroso Universal ethernet telecommunications service
US7466712B2 (en) * 2004-07-30 2008-12-16 Brocade Communications Systems, Inc. System and method for providing proxy and translation domains in a fibre channel router
US7620057B1 (en) * 2004-10-19 2009-11-17 Broadcom Corporation Cache line replacement with zero latency
US7760720B2 (en) * 2004-11-09 2010-07-20 Cisco Technology, Inc. Translating native medium access control (MAC) addresses to hierarchical MAC addresses and their use
US7831839B2 (en) * 2005-02-07 2010-11-09 Sony Computer Entertainment Inc. Methods and apparatus for providing a secure booting sequence in a processor
US7586841B2 (en) * 2005-05-31 2009-09-08 Cisco Technology, Inc. System and method for protecting against failure of a TE-LSP tail-end node
US7606225B2 (en) * 2006-02-06 2009-10-20 Fortinet, Inc. Integrated security switch
US20070226795A1 (en) * 2006-02-09 2007-09-27 Texas Instruments Incorporated Virtual cores and hardware-supported hypervisor integrated circuits, systems, methods and processes of manufacture
US20070280230A1 (en) * 2006-05-31 2007-12-06 Motorola, Inc Method and system for service discovery across a wide area network
US20080013453A1 (en) * 2006-07-13 2008-01-17 Sbc Knowledge Ventures, L.P. Method and apparatus for configuring a network topology with alternative communication paths
US20090279518A1 (en) * 2006-08-24 2009-11-12 Rainer Falk Method and arrangement for providing a wireless mesh network
US20080075089A1 (en) * 2006-09-26 2008-03-27 Cisco Technology, Inc. Snooping of on-path ip reservation protocols for layer 2 nodes
US20080183882A1 (en) * 2006-12-06 2008-07-31 David Flynn Apparatus, system, and method for a device shared between multiple independent hosts
US20080140771A1 (en) * 2006-12-08 2008-06-12 Sony Computer Entertainment Inc. Simulated environment computing framework
US8019832B2 (en) * 2007-05-16 2011-09-13 Coreworks, S.A. Network core access architecture
US20090225751A1 (en) * 2007-05-22 2009-09-10 Koenck Steven E Mobile nodal based communication system, method and apparatus
US20080301794A1 (en) * 2007-05-31 2008-12-04 Jaushin Lee Method and system for providing remote access to resources in a secure data center over a network
US20080320161A1 (en) * 2007-06-25 2008-12-25 Stmicroelectronics Sa Method for transferring data from a source target to a destination target, and corresponding network interface
US7840703B2 (en) * 2007-08-27 2010-11-23 International Business Machines Corporation System and method for dynamically supporting indirect routing within a multi-tiered full-graph interconnect architecture
US20090080428A1 (en) * 2007-09-25 2009-03-26 Maxxan Systems, Inc. System and method for scalable switch fabric for computer network
US20120020207A1 (en) * 2008-05-12 2012-01-26 Telfonaktiebolaget L M Ericsson (Publ) Re-routing traffice in a communications network
US20100318812A1 (en) * 2009-06-12 2010-12-16 Microsoft Corporation Secure and private backup storage and processing for trusted computing and data services

Cited By (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9465771B2 (en) 2009-09-24 2016-10-11 Iii Holdings 2, Llc Server on a chip and node cards comprising one or more of same
US9008079B2 (en) 2009-10-30 2015-04-14 Iii Holdings 2, Llc System and method for high-performance, low-power data center interconnect fabric
US9866477B2 (en) 2009-10-30 2018-01-09 Iii Holdings 2, Llc System and method for high-performance, low-power data center interconnect fabric
US9749326B2 (en) 2009-10-30 2017-08-29 Iii Holdings 2, Llc System and method for data center security enhancements leveraging server SOCs or server fabrics
US9680770B2 (en) 2009-10-30 2017-06-13 Iii Holdings 2, Llc System and method for using a multi-protocol fabric module across a distributed server interconnect fabric
US20130089104A1 (en) * 2009-10-30 2013-04-11 Calxeda, Inc. System and Method for High-Performance, Low-Power Data Center Interconnect Fabric
US20170068639A1 (en) * 2009-10-30 2017-03-09 Iii Holdings 2, Llc Memcached server functionality in a cluster of data processing nodes
US9509552B2 (en) 2009-10-30 2016-11-29 Iii Holdings 2, Llc System and method for data center security enhancements leveraging server SOCs or server fabrics
US9479463B2 (en) 2009-10-30 2016-10-25 Iii Holdings 2, Llc System and method for data center security enhancements leveraging managed server SOCs
US9876735B2 (en) 2009-10-30 2018-01-23 Iii Holdings 2, Llc Performance and power optimized computer system architectures and methods leveraging power optimized tree fabric interconnect
US9454403B2 (en) 2009-10-30 2016-09-27 Iii Holdings 2, Llc System and method for high-performance, low-power data center interconnect fabric
US9311269B2 (en) 2009-10-30 2016-04-12 Iii Holdings 2, Llc Network proxy for high-performance, low-power data center interconnect fabric
US9262225B2 (en) 2009-10-30 2016-02-16 Iii Holdings 2, Llc Remote memory access functionality in a cluster of data processing nodes
US8737410B2 (en) * 2009-10-30 2014-05-27 Calxeda, Inc. System and method for high-performance, low-power data center interconnect fabric
US8745302B2 (en) * 2009-10-30 2014-06-03 Calxeda, Inc. System and method for high-performance, low-power data center interconnect fabric
US9405584B2 (en) 2009-10-30 2016-08-02 Iii Holdings 2, Llc System and method for high-performance, low-power data center interconnect fabric with addressing and unicast routing
US9077654B2 (en) 2009-10-30 2015-07-07 Iii Holdings 2, Llc System and method for data center security enhancements leveraging managed server SOCs
US9075655B2 (en) 2009-10-30 2015-07-07 Iii Holdings 2, Llc System and method for high-performance, low-power data center interconnect fabric with broadcast or multicast addressing
US9054990B2 (en) 2009-10-30 2015-06-09 Iii Holdings 2, Llc System and method for data center security enhancements leveraging server SOCs or server fabrics
US9929976B2 (en) 2009-10-30 2018-03-27 Iii Holdings 2, Llc System and method for data center security enhancements leveraging managed server SOCs
US8594100B2 (en) 2010-03-31 2013-11-26 International Business Machines Corporation Data frame forwarding using a distributed virtual bridge
US20110258641A1 (en) * 2010-04-20 2011-10-20 International Business Machines Corporation Remote Adapter Configuration
US8358661B2 (en) * 2010-04-20 2013-01-22 International Business Machines Corporation Remote adapter configuration
US8619796B2 (en) 2010-04-22 2013-12-31 International Business Machines Corporation Forwarding data frames with a distributed fiber channel forwarder
US8856419B2 (en) 2010-07-19 2014-10-07 International Business Machines Corporation Register access in distributed virtual bridge environment
US8856321B2 (en) * 2011-03-31 2014-10-07 International Business Machines Corporation System to improve operation of a data center with heterogeneous computing clouds
US20120254400A1 (en) * 2011-03-31 2012-10-04 International Business Machines Corporation System to improve operation of a data center with heterogeneous computing clouds
WO2012162313A2 (en) * 2011-05-24 2012-11-29 Calxeda, Inc. System and method for data center security enhancements leveraging server socs or server fabrics
WO2012162313A3 (en) * 2011-05-24 2013-05-02 Calxeda, Inc. System and method for data center security enhancements leveraging server socs or server fabrics
WO2012162314A1 (en) * 2011-05-24 2012-11-29 Calxeda, Inc. System and method for data center security enhancements leveraging managed server socs
US9585281B2 (en) 2011-10-28 2017-02-28 Iii Holdings 2, Llc System and method for flexible storage and networking provisioning in large scalable processor installations
US9092594B2 (en) 2011-10-31 2015-07-28 Iii Holdings 2, Llc Node card management in a modular and large scalable server system
US9069929B2 (en) 2011-10-31 2015-06-30 Iii Holdings 2, Llc Arbitrating usage of serial port in node card of scalable and modular servers
US9792249B2 (en) 2011-10-31 2017-10-17 Iii Holdings 2, Llc Node card utilizing a same connector to communicate pluralities of signals
US8861400B2 (en) 2012-01-18 2014-10-14 International Business Machines Corporation Requesting multicast membership information in a distributed switch in response to a miss event
US8891535B2 (en) 2012-01-18 2014-11-18 International Business Machines Corporation Managing a global forwarding table in a distributed switch
US20130250802A1 (en) * 2012-03-26 2013-09-26 Praveen Yalagandula Reducing cabling costs in a datacenter network
WO2014015664A1 (en) * 2012-07-26 2014-01-30 华为技术有限公司 Communication method and system
WO2014039922A2 (en) * 2012-09-06 2014-03-13 Pi-Coral, Inc. Large-scale data storage and delivery system
WO2014039922A3 (en) * 2012-09-06 2014-05-15 Pi-Coral, Inc. Large-scale data storage and delivery system
CN104903874A (en) * 2012-09-06 2015-09-09 百科容(科技)公司 Large-scale data storage and delivery system
US9742662B2 (en) 2012-12-26 2017-08-22 Iii Holdings 2, Llc Fabric discovery for a cluster of nodes
US20140181573A1 (en) * 2012-12-26 2014-06-26 Calxeda, Inc. Fabric discovery for a cluster of nodes
US9170971B2 (en) * 2012-12-26 2015-10-27 Iii Holdings 2, Llc Fabric discovery for a cluster of nodes
US9648102B1 (en) * 2012-12-27 2017-05-09 Iii Holdings 2, Llc Memcached server functionality in a cluster of data processing nodes
US9654852B2 (en) * 2013-12-24 2017-05-16 Nec Corporation Scalable hybrid packet/circuit switching network architecture
US20150181317A1 (en) * 2013-12-24 2015-06-25 Nec Laboratories America, Inc. Scalable hybrid packet/circuit switching network architecture
US20160352775A1 (en) * 2014-04-09 2016-12-01 Hewlett Packard Enterprise Development Lp Identifying suspicious activity in a load test
US9866587B2 (en) * 2014-04-09 2018-01-09 Entit Software Llc Identifying suspicious activity in a load test
US9497140B2 (en) * 2014-05-14 2016-11-15 International Business Machines Corporation Autonomous multi-node network configuration and self-awareness through establishment of a switch port group
US20150333926A1 (en) * 2014-05-14 2015-11-19 International Business Machines Corporation Autonomous multi-node network configuration and self-awareness through establishment of a switch port group
US9886210B2 (en) 2015-06-09 2018-02-06 Ultrata, Llc Infinite memory fabric hardware implementation with router
WO2017100292A1 (en) * 2015-12-08 2017-06-15 Ultrata, Llc. Object memory interfaces across shared links

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