US20110079853A1 - Liquid crystal display and fabrication method thereof - Google Patents

Liquid crystal display and fabrication method thereof Download PDF

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US20110079853A1
US20110079853A1 US12/963,403 US96340310A US2011079853A1 US 20110079853 A1 US20110079853 A1 US 20110079853A1 US 96340310 A US96340310 A US 96340310A US 2011079853 A1 US2011079853 A1 US 2011079853A1
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pattern
insulating layer
gate
substrate
transparent conductive
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US8187927B2 (en
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Seung-hee Nam
Nam-Kook Kim
Soon-Sung Yoo
Youn-Gyoung Chang
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LG Display Co Ltd
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LG Display Co Ltd
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Priority to KR1020070024185A priority patent/KR101357042B1/en
Priority to US11/968,065 priority patent/US7867796B2/en
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Priority to US12/963,403 priority patent/US8187927B2/en
Publication of US20110079853A1 publication Critical patent/US20110079853A1/en
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/1288Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/127Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1285Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/1292Multistep manufacturing methods using liquid deposition, e.g. printing
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • H01L29/6675Amorphous silicon or polysilicon transistors
    • H01L29/66765Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate

Abstract

A method for fabricating an LCD includes: providing a substrate with a thin film transistor (TFT) part defined thereon; forming a metallic film for a gate electrode on the substrate; etching the metallic film through a first printing process to form a gate electrode; sequentially forming a gate insulating layer, a semiconductor layer, and a metallic film for source and drain electrodes on the substrate; selectively etching the metallic film for source and drain electrodes, the semiconductor layer and the gate insulating layer through a second printing process to form a gate insulating layer pattern, a preliminary active pattern and a metallic film pattern which are sequentially stacked such that the gate insulating layer pattern is over-etched from the side of the preliminary active pattern; forming an insulating layer on the substrate with the metallic film pattern; etching the insulating layer to expose the metallic film pattern; forming a transparent conductive film on the metallic film pattern and a remaining insulating film; and selectively etching the transparent conductive film, the metallic film pattern, the preliminary active pattern to form an active pattern, a source electrode, a drain electrode, and a pixel electrode connected with the drain electrode.

Description

  • The present patent document is a divisional of U.S. patent application Ser. No. 11/968,065, filed Dec. 31, 2007, which claims priority to Korean Patent Application No. 10-2007-0024185 filed in Korea on Mar. 12, 2007, which is hereby incorporated by reference.
  • BACKGROUND
  • 1. Field of the Invention
  • The present invention relates to a liquid crystal display and its fabrication method, and more particularly, to a liquid crystal display and its fabrication method capable of simplifying a process.
  • 2. Discussion of the Related Art
  • In general, a liquid crystal display (LCD) displays images by controlling light transmittance of liquid crystal by using electric fields. LCDs are divided into a vertical field application type LCD and a horizontal field (in-plane) field application type LCD according to the direction of electric fields driving the liquid crystals.
  • The vertical field application type LCD drives TN (Twisted Nematic) mode liquid crystals by a vertical electric field formed between pixel electrodes and common electrodes disposed to face each other on upper and lower substrates. Such vertical field application type LCD advantageously has a large aperture ratio but is disadvantageous in that its viewing angle is narrow as 90°.
  • On the other hand, the in-plane field application type LCD drives IPS (In-Plane Switch) mode liquid crystals by an in-plane field between pixel electrodes and common electrodes disposed to be parallel to each other on a lower substrate. Such in-plane field application type LCD advantageously has a wide viewing angle of about 160° but is disadvantageous in that its aperture ratio and transmittance are low.
  • Thus, in order to improve the shortcomings of the in-plane field application type LCD, a fringe field switching (FFS) mode LCD that operates using a fringe field has been proposed.
  • In the FFS mode LCD, a common electrode plate and pixel electrodes are formed with an insulation film interposed therebetween at a pixel area, and in this case, the space between the common electrode plate and the pixel electrodes is narrower than that between upper and lower substrates to form a fringe field. Liquid crystal molecules filled between the upper and lower substrates operate to thus improve an aperture ratio and transmittance.
  • FIG. 1 is a sectional view showing a schematic construction of the FFS mode LCD according to the related art. FIGS. 2 a to 2 e are sectional views showing the sequential processes of fabricating the FFS mode LCD. The related art FFS mode LCD and its fabrication method will now be described with reference to FIG. 1 and FIGS. 2 a to 2 e.
  • Referring to FIG. 1, the related art FFS mode TFT substrate includes a gate line (not shown) and a data line 4 formed to cross each other with a gate insulating layer 22 interposed therebetween on a substrate 20, a thin film transistor (TFT) formed at each crossing of the gate line and the data line, a common electrode plate 14 and pixel electrode slits 18 formed with the gate insulating layer 22 and a passivation film 28 interposed therebetween to form a fringe field at a pixel area formed with a crossing structure of the gate line and the data line, and a common line 16 connected with the common electrode plate 14.
  • The common electrode plate 14 receives a reference voltage through the common line 16 which is formed on the common electrode plate 14 and connected with the common electrode plate 14 at each pixel area. The common electrode plate 14 is formed of a transparent conductive layer, and the common line 16 is formed of a gate metallic layer together with the gate line.
  • In the TFT, a pixel signal of the data line 4 is charged in the pixel electrode slits 18 and maintained in response to a gate signal of the gate line.
  • For this purpose, the TFT includes a gate electrode 6 connected with the gate line, a source electrode 8 connected with the data line 4, a drain electrode 10 connected with the pixel electrode slits 18, an active layer 24 overlapping with the gate electrode 6 with the gate insulating layer 22 and forming a channel between the source electrode 8 and the drain electrode 10, and an ohmic-contact layer 26 for ohmic-contacting with the source electrode 8, the drain electrode 10, and the active layer 24.
  • The pixel electrode slits 18 are connected with the drain electrode 10 of the TFT via a contact hole 12 that penetrates the passivation layer 28 so as to overlap with the common electrode plate 14. Such pixel electrode slits 18 form a fringe field with the common electrode plate 14 to allow liquid crystal molecules arranged in a horizontal direction between the TFT substrate and a color filter substrate to be rotated by dielectric anisotropy. Transmittance of light that transmits through the pixel area varies according to the rotation degree of the liquid crystal molecules to thus represent gray scales.
  • A storage capacitor that stably maintains a video signal supplied to the pixel electrode slits 18 is formed at the overlap portion of the common electrode plate 14 and the pixel electrode slits 18.
  • The fabrication method of the FFS mode TFT substrate will now be described with reference to FIGS. 2 a to 2 e.
  • As shown in FIG. 2 a, the common electrode plate 14 is formed at each pixel area of the substrate 20. The common electrode plate 14 is formed at each pixel area by forming a transparent conductive film on the substrate 20 and then patterning the transparent conductive film according to a first photomasking process.
  • As shown in FIG. 2 b, the gate line including the gate electrode 6 and the common line 16 are formed on the substrate 20 with the common electrode plate 14 formed thereon through a second photomasking process. The gate line and the common line 16 are formed such that a metallic film for the gate line is formed on the substrate 20 with the common electrode plate 14 formed thereon and then patterned through the second photomasking process.
  • As shown in FIG. 2 c, the gate insulating layer 22 is formed on the substrate 20 with a gate metallic pattern formed thereon, and a semiconductor pattern including the active layer 24 and the ohmic-contact layer 26, and a source/drain metallic pattern including the data line 4, the source electrode 8 and the drain electrode 10 are formed.
  • In detail, the gate insulating layer 22, an amorphous silicon layer, an n+ amorphous silicon layer, and source/drain metallic layers are sequentially formed on the substrate 20 with the gate metallic pattern formed thereon. And then, a photoresist pattern having a step is formed on the source/drain metallic pattern through a photolithography process using a third mask, a slit (diffraction) exposure mask. The photoresist pattern having a step has a relatively lower height at a channel part of the TFT. Through the etching process using the photoresist pattern, there are formed source and drain patterns and a semiconductor pattern therebelow. Subsequently, the photoresist pattern is ashed and the exposed source and drain patterns are removed together with the lower ohmic-contact layer 26 to separate the source electrode 8 and the drain electrode 10.
  • As shown in FIG. 2 d, the passivation layer 28 with an opening 12 is formed on the source and drain electrodes 8 and 10 and the gate insulating layer 22 through a fourth photomasking process. Namely, the passivation layer 28 is formed on the source and drain electrodes 8 and 10 and the gate insulating layer 22 and then patterned through the fourth photomasking process to form the opening 12 exposing the drain electrode 10.
  • As shown in FIG. 2 e, the pixel electrode slits 18 are formed on the passivation layer 28 through a fifth photomasking process. The pixel electrode slits 18 are formed such that a transparent conductive layer is formed on the passivation layer 28 and then patterned through a photolithography process using a fifth photo mask and an etching process.
  • In the related art FFS mode TFT substrate fabrication method, a total of five masks are used, and in this case, the number of masks indicates the number of processes for fabricating an array substrate. In this case, the photolithography process accompanies several processes such as washing, and coating, exposing, developing and etching of a photosensitive film, causing a problem that much processing time is taken and a fabrication cost increases.
  • Thus, if only one time of photolithography process would be omitted, the fabrication time could be considerably shortened and the fabrication cost and the defect rate could be also reduced. Thus, a method for reducing the number of masks needs to be proposed.
  • BRIEF SUMMARY
  • Therefore, in order to address the above matters the various features described herein have been conceived. One aspect of the exemplary embodiments is to provide a liquid crystal display (LCD) and its fabrication method capable of simplifying a process by reducing the number of photomasks used.
  • This specification provides a method for fabricating an LCD including: providing a substrate with a thin film transistor (TFT) part defined thereon; forming a metallic film for a gate electrode on the substrate; etching the metallic film through a first printing process to form a gate electrode; sequentially forming a gate insulating layer, a semiconductor layer, and a metallic film for source and drain electrodes on the substrate; selectively etching the metallic film for source and drain electrodes, the semiconductor layer and the gate insulating layer through a second printing process to form a gate insulating layer pattern, a preliminary active pattern and a metallic film pattern which are sequentially stacked such that the gate insulating layer pattern is over-etched from the side of the preliminary active pattern; forming an insulating layer on the substrate with the metallic film pattern; etching the insulating layer to expose the metallic film pattern; forming a transparent conductive film on the metallic film pattern and a remaining insulating film; and selectively etching the transparent conductive film, the metallic film pattern, the preliminary active pattern to form an active pattern, a source electrode, a drain electrode, and a pixel electrode connected with the drain electrode.
  • This specification also provides a liquid crystal display (LCD) including: a substrate with a thin film transistor (TFT) part, a pixel part, and a gate pad part defined thereon; a gate electrode and a gate pad formed on the substrate; a gate insulating layer pattern, an active pattern, and source and drain electrodes sequentially formed on the substrate with the gate pad formed thereon; a first transparent conductive film pattern that covers a common electrode and the gate pad on the substrate with the source and drain electrodes and is formed of the same layer as the common electrode; an insulating layer covering the first transparent conductive film pattern and having an opening that exposes the source and drain electrodes and a portion corresponding to the gate pad; and a pixel electrode formed on the insulating layer and covering the drain electrode, and a second transparent conductive film pattern formed on the insulating layer, connected with the first transparent conductive film pattern via the opening and formed on the same layer on which the pixel electrode is formed.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a sectional view showing a schematic construction of a fringe field switching (FFS) mode liquid crystal display (LCD) according to the related art;
  • FIGS. 2 a to 2 e are sectional views showing sequential processes of fabricating the FFS mode LCD according to the related art; and
  • FIGS. 3 a to 3 i are sectional views showing the schematic construction of an FFS mode LCD according to the present disclosure.
  • DETAILED DESCRIPTION OF THE DRAWINGS AND THE PRESENTLY PREFERRED EMBODIMENTS
  • A liquid crystal display (LCD) and its fabrication method according to the present disclosure will now be described with reference to the accompanying drawings.
  • In the disclosed embodiments, in order to simplify the process by reducing the number of photomasks, a printing process, instead of a photolithography process, is applied. Namely, a gate line having a gate electrode and a gate pad is formed by using a first printing process, source and drain electrodes are formed by using a second printing process, and an opening exposing the gate pad is formed by using a third printing process. And the source electrode, the drain electrode and a pixel electrode are sequentially formed by using a photomasking process.
  • Thus, in the disclosed embodiments, the FFS mode LCD is fabricated by performing a total of three printing processes and a single photomasking process, thereby simplifying the photomasking process, and thus, reducing a material cost and a facility investment cost, and improving a production yield.
  • FIGS. 3 a to 3 i are sectional views showing the schematic construction of an FFS mode LCD according to the present disclosure. Here, a left portion of the drawing includes a TFT part and a pixel part, a middle portion includes a gate pad part, and a right portion includes a data pad part.
  • As shown in FIG. 3 a, a substrate 201, on which the TFT part, the pixel part, the gate pad part and the data pad part are defined, is provided. In this case, the substrate 201 refers to a TFT array substrate. Subsequently, a metallic film (not shown) for gate lines (a gate line metallic film) is formed over the entire surface of the substrate 201. A buffer film 205 may be interposed between the substrate 201 and the metallic film. The gate line metallic film may be metal such as Al, Cu, Ta, Ti, Mo, a molybdenum alloy, an aluminum alloy, etc.
  • Next, the gate line metallic film is patterned to form a gate line 270 having a gate electrode 203G and a gate pad 203P. In this case, the gate line 270 may be formed by patterning the gate line metallic film through a printing process. The printing process may be performed by using one of a roll printing method and an in-plane printing method (a first printing process).
  • Thereafter, as shown in FIG. 3 b, a gate insulating layer 207, a semiconductor layer 209, and a data line metallic film 213 are sequentially formed on the substrate with the gate line 203 formed thereon. In this case, the gate insulating layer 207 may be a silicon nitride. The semiconductor layer 209 may be a silicon film. The data line metallic film 213 may be a metal such as Al, Cu, Ta, Ti, Mo, a molybdenum alloy, an aluminum alloy, etc., the same as the gate line metallic film.
  • Subsequently, a first photosensitive film pattern 251 is formed on the substrate with the data line metallic film 213 formed thereon. In this case, the first photosensitive film pattern 251 is patterned to selectively cover portions of the TFT part and the data pad part. Here, the first photosensitive film pattern 251 may be formed through a printing process. The printing process may be performed by using any one of the roll printing method and the in-plane printing method (a second printing process).
  • Then, as shown in FIG. 3 c, the data line metallic film, the semiconductor layer, and the gate insulating layer are etched by using the first photosensitive film pattern 251 as a mask to form a gate insulating layer pattern 207P, a preliminary active pattern 209A, and a data line which are sequentially stacked. The data line includes a metallic film pattern 213P1 formed at the TFT part and a data pad 213P2 formed at the data pad part. The gate insulating layer pattern 207P is formed to have an undercut shape from the sides of the preliminary active pattern 209A by over-etching the gate insulating layer.
  • Next, as shown in FIG. 3 d, a first transparent conductive film 215 and an insulating layer 217 are sequentially formed to cover the first photosensitive film pattern 251 on the substrate with the metallic film pattern 213P1 formed thereon. In this case, the first transparent conductive film 215 corresponds to a common electrode film to form a common electrode and may be made of ITO. The insulating layer 217 may be formed by coating an organic insulating layer. The insulating layer 217 may planarize (smooth) the entire surface of the substrate with the first transparent conductive film 215.
  • Thereafter, as shown in FIG. 3 e, the insulating layer is first etched until the metallic film pattern 213P1 is exposed. In this case, the first etching process of the insulating layer may be performed by using an ashing process using plasma. O2 gas may be used in the plasma process.
  • Through the ashing process using plasma, the insulating layer 217P may be first etched to expose the side of the first transparent conductive film 215 on the first photosensitive film pattern 251 and the side of the first photosensitive film pattern 251 and cover the metallic film pattern 213P1. In FIG. 3 e, the part indicated by dotted lines shows an initial thickness of the insulating layer before being first etched.
  • Subsequently, as shown in FIG. 3 f, the first transparent conductive film pattern 251 and the first transparent conductive film 215 on the first photosensitive film pattern are removed. Here, the first photosensitive film pattern and the first transparent conductive film on the first photosensitive film pattern may be removed by performing a lift-off method. Of the first transparent conductive film 215 on the first photosensitive film pattern 251 is removed, and then, the first photosensitive film pattern is removed. In this case, while the first photosensitive film pattern 251 and the first transparent conductive film on the first photosensitive film pattern are removed, the insulating layer remaining after etching serves to support the metallic film pattern 213P1. Hereinafter, the first transparent conductive film arranged to be parallel to the gate line will be referred to as a common electrode 215P1, and the first transparent conductive films remaining at the gate pad part and the data pad part will be referred to as first transparent conductive film patterns 215P2 and 215P3.
  • The first transparent conductive film remaining at the pixel part corresponds to the common electrode 215P1.
  • The first transparent conductive films remaining at the gate pad part and the data pad part correspond to the first transparent conductive film patterns 215P2 and 215P3.
  • A second photosensitive film pattern 253 is formed on the substrate with the first-etched insulating layer 217P formed thereon. IN this case, the second photosensitive film pattern 253 is patterned to entirely cover the TFT part, the pixel part and the data pad part and expose a certain region of the gate pad part. In this case, the second photosensitive film pattern 253 may be formed through a printing process (a third printing process). The printing process may be performed by using any one of the roll printing method and the in-plane printing method.
  • Subsequently, the first-etched insulating layer is second etched by using the second photosensitive film pattern 253 as a mask to form an opening 217PO at the gate pad part (photomasking process).
  • Next, as shown in FIG. 3 g, the second photosensitive film pattern is removed, and then, a second transparent conductive film is formed over the entire surface of the substrate having the opening 217PO. In this case, the second transparent conductive film is to form a pixel electrode and can be made of ITO or IZO.
  • Then, a photosensitive film is coated on the second transparent conductive film, which is then exposed and developed to form a third photosensitive film pattern 255 in order to form a channel and a pixel electrode at the TFT part (a first photomasking process). In this case, the third photosensitive film pattern 255 may have different thicknesses. That is, the third photosensitive film pattern may be formed to be thinner at the channel formation region of the TFT than at other regions.
  • Next, the second transparent conductive film is etched by using the third photosensitive film pattern 255 as a mask to form a pixel electrode 219P1 and, at the same time, to form second transparent conductive film patterns 219P2 and 219P3 at the gate pad part and the data pad part. In this case, the second transparent conductive film pattern 219P2 is electrically connected with the first transparent conductive film pattern 215P2 on the gate pad 203P via the opening 217PO at the gate pad part.
  • Subsequently, the remaining insulating layer, the metallic film pattern and the preliminary active pattern are etched by using the third photosensitive film pattern 255 as a mask to form an active pattern 209A1 and a preliminary source/drain electrode pattern 213P1A which are sequentially stacked.
  • Then, as shown in FIG. 3 h, the third photosensitive film pattern is ashed to expose the second transparent conductive film corresponding to the channel formation region of the TFT part. Thereafter, the second transparent conductive film and the preliminary source/drain electrode pattern are etched by using the ashed third photosensitive film pattern 255P as a mask to form source and drain electrodes 213S and 213D.
  • Thereafter, as shown in FIG. 3 i, the ashed third photosensitive film pattern is removed, and a passivation film 221 is formed on the substrate with the source and drain electrodes 213S and 213D formed thereon.
  • As shown in FIG. 3 i, the LCD formed by using the above-described method according to the present disclosure includes the substrate 201 on which the TFT part, the pixel part, the gate pad part, and the data pad part are defined, the gate electrode 203G and the gate pad 203P formed on the substrate 201, the gate insulating layer pattern 207P, the active pattern 209PA1 and the source and drain electrodes 213S and 213D sequentially formed on the substrate with the gate pad 203 formed thereon, the first transparent conductive film pattern 215P2 covering the common electrode 215P1 and the gate pad 203P on the substrate with the source and drain electrodes 213S and 213D and formed of the same layer as the common electrode 215P1, the insulating layer 217P covering the substrate with the first transparent conductive film pattern 215P2 formed thereon and having the opening 217P0 exposing the source and drain electrodes 213S and 213D and a portion corresponding to the gate pad 203P, and the pixel electrode 219P1 formed on the insulating layer 210P to cover the drain electrode 213D and formed of the same layer as the pixel electrode 219P1.
  • The gate insulating layer pattern 207P is formed to have an undercut shape from the sides of the active pattern 209PA1.
  • As so far described, the FFS mode LCD according to the present invention is fabricated by using a total of three printing processes and the single photomasking process. In detail, the gate line having the gate electrode and the gate pad is formed by using the first printing process, the metallic film pattern for forming the source and drain electrodes is formed by using the second printing process, the opening exposing the gate pad is formed by using the third printing process, and the source, drain and pixel electrodes are formed by using the photomasking process in sequence. Thus, the photomasking process can be simplified.
  • The present invention provides the LCD fabricated through the total three printing processes and the single photomasking process and its fabrication method. Thus, the photomasking process can be simplified, and accordingly, the material cost and facility investment costs can be reduced and the production yield can be improved.
  • As the present invention may be embodied in several forms without departing from the characteristics thereof, it should also be understood that the above-described embodiments are not limited by any of the details of the foregoing description, unless otherwise specified, but rather should be construed broadly within its scope as defined in the appended claims, and therefore all changes and modifications that fall within the metes and bounds of the claims, or equivalents of such metes and bounds are therefore intended to be embraced by the appended claims.

Claims (11)

1. A method for fabricating a liquid crystal display, comprising:
providing a substrate on which a thin film transistor (TFT) part, a pixel part, and a gate pad part are formed;
forming a metallic film for a gate line on the substrate;
etching the gate line metallic film through a first printing process to form a gate line having a gate electrode and a gate pad at the TFT part and the pad part;
sequentially forming a gate insulating layer, a semiconductor layer and a metallic film for a data line on the substrate;
forming a resist pattern covering a portion of the TFT part on the substrate with the data line metallic film formed thereon through a second printing process;
etching the data line metallic film, the semiconductor layer and the gate insulating layer by using the resist pattern as a mask to form a gate insulating layer pattern, a preliminary active pattern and a metallic film pattern that are sequentially stacked, the gate insulating layer pattern being formed to be undercut at the sides of the preliminary active pattern;
sequentially forming a first transparent conductive film and an insulating layer to cover the resist pattern on the substrate with the metallic film pattern formed thereon;
etching the insulating layer until the metallic film pattern is exposed;
removing the resist pattern and the first transparent conductive film on the resist pattern to form a common electrode arranged to be parallel to the gate line;
selectively etching the remaining insulating layer through a third printing process to form an opening exposing a portion of the first transparent conductive film pattern;
forming a second transparent conductive film on the substrate having the opening; and
selectively etching the second transparent conductive film, the metallic film pattern and the preliminary active pattern to form an active pattern, a source electrode, a drain electrode and a pixel electrode connected with the drain electrode.
2. The method of claim 1, wherein the forming of the gate insulating layer pattern, the preliminary active pattern and the metallic film pattern comprises:
forming the resist pattern on the data line metallic film through the second printing process; and
etching the data line metallic film, the semiconductor layer and the gate insulating layer by using the resist pattern as a mask.
3. The method of claim 1, wherein the insulating layer is formed as an organic insulating layer.
4. The method of claim 2, wherein the insulating layer is etched by performing an ashing process.
5. The method of claim 2, wherein the plasma ashing process uses O2 gas.
6. The method of claim 1, wherein the resist pattern and the common electrode film on the resist pattern are removed through a lift-off method.
7. The method of claim 1, further comprising:
forming a photoresist pattern formed to be thinner at a channel formation region of the TFT part than at other regions on the second transparent conductive film, after the second transparent conductive film is formed.
19. The method of claim 7, wherein the forming of the source and drain electrodes and the pixel electrode comprising:
etching the second transparent conductive film, the metallic film pattern and the preliminary active pattern by using the photoresist pattern to form a preliminary pixel electrode pattern, a preliminary source and drain electrode pattern, and an active pattern;
ashing the photoresist pattern;
etching the preliminary pixel electrode pattern, the preliminary source and drain electrode pattern using the ashed photoresist pattern; and
removing the ashed photoresist pattern.
8. The method of claim 1, further comprising:
forming a passivation film on the substrate with the pixel electrode formed thereon, after forming the source and drain electrodes and the pixel electrode.
9. A liquid crystal display device comprising:
a substrate with a thin film transistor (TFT) part, a pixel part, and a gate pad part defined thereon;
a gate electrode and a gate pad disposed on the substrate;
a gate insulating layer pattern, an active pattern, and source and drain electrodes sequentially disposed on the substrate with the gate pad disposed thereon;
a first transparent conductive film pattern that covers a common electrode and the gate pad on the substrate with the source and drain electrodes and is disposed in the same layer as the common electrode;
an insulating layer covering the first transparent conductive film pattern and having an opening that exposes the source and drain electrodes and a portion corresponding to the gate pad; and
a pixel electrode disposed on the insulating layer and covering the drain electrode, and a second transparent conductive film pattern disposed on the insulating layer, connected with the first transparent conductive film pattern via the opening and formed on the same layer on which the pixel electrode is disposed.
10. The device of claim 9, wherein the gate insulating layer pattern has an undercut shape from the side of the active pattern.
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