US20110068365A1 - Isolated SCR ESD device - Google Patents

Isolated SCR ESD device Download PDF

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Publication number
US20110068365A1
US20110068365A1 US12586455 US58645509A US2011068365A1 US 20110068365 A1 US20110068365 A1 US 20110068365A1 US 12586455 US12586455 US 12586455 US 58645509 A US58645509 A US 58645509A US 2011068365 A1 US2011068365 A1 US 2011068365A1
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Prior art keywords
doped region
well
high density
conductivity type
density doped
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Abandoned
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US12586455
Inventor
Chih-Feng Huang
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Richtek Technology Corp
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Richtek Technology Corp
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H01L27/0262Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/74Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/7436Lateral thyristors

Abstract

The present invention discloses an isolated SCR ESD device, comprising: a substrate; a first well located in the substrate, which is floating and has a first conductivity type; a first high density doped region located in the first well and having a second conductivity type; a second well nearby the first well and having the second conductivity type; a second high density doped region located in the second well and having the second conductivity type; and a third high density doped region located in the second well and having the first conductivity type, wherein the first high density doped region is for electrical connection with a pad, and wherein the first well is not provided with a high density doped region having the first conductivity type for connection with the pad.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of Invention
  • The present invention relates to an isolated silicon controlled rectifier (SCR) electro-static discharge (ESD) device; particularly, it relates to an isolated SCR ESD device which prevents a negative voltage from adversely impacting a circuit.
  • 2. Description of Related Art
  • ESD devices are used in many integrated circuits to discharge high voltage received by external pins before the high voltage damages internal devices. One type of ESD devices uses an SCR. FIG. 1 shows such a conventional SCR ESD device, which includes: an N-type well 11 and a P-type well 21 located in a P-type substrate 100, a high density P+ doped region 13 and a high density N+ doped region 15 located in the N-type well 11, and a high density P+ doped region 23 and a high density N+ doped region 25 located in the P-type well 21. In this SCR ESD device, the P+ doped region 13, the N+ doped region 15, the N-type well 11, and the P-type well 21 constitute a PNP transistor; the N-type well 11, the P-type well 21, and the N+ doped region 25 constitute an NPN transistor. An external pad PAD is coupled to the P+ doped region 13 and the N+ doped region 15, and, an external grounding pad GND is coupled to the P+ doped region 23 and the N+ doped region 25. Therefore, when the external pad PAD receives a high voltage, the SCR ESD device is triggered to conduct a current to the grounding pad GND.
  • The abovementioned prior art has the following shortcoming. When the external pad PAD receives a negative voltage, a junction diode formed by the high density N+ doped region 15, the N-type well 11, and the P-type substrate 100 will be forward biased and turned on, resulting in a current loss from the substrate 100 to the external pad PAD. The current loss consumes power, and furthermore it may create a latch-up effect, causing malfunctions of internal circuit devices. In general ESD design, it is not expected that a negative voltage will be applied to the external pad PAD. However, when the circuit is used to drive power transistor switches, a transient negative voltage may be applied to the external pad PAD due to the switching ringing of the power transistor switches.
  • In view of the foregoing, the present invention provides an isolated SCR ESD device, which can avoid the adverse impact on a circuit caused by a negative voltage.
  • SUMMARY OF THE INVENTION
  • An objective of the present invention is to provide an SCR ESD device.
  • In order to achieve the foregoing objective, according to one perspective of the present invention, it provides an SCR ESD device, comprising: a substrate; a first well located in the substrate, which is floating and has a first conductivity type; a first high density doped region located in the first well and having a second conductivity type; a second well nearby the first well and having the second conductivity type; a second high density doped region located in the second well and having the second conductivity type; and a third high density doped region located in the second well and having the first conductivity type, wherein the first high density doped region is for electrical connection with a pad, and wherein the first well is not provided with a high density doped region having the first conductivity type for connection with the pad.
  • In the isolated SCR ESD device mentioned above, in one embodiment, a high density doped region is formed at the junction area between the first well and second well. The high density doped region can be the first conductivity type or the second conductivity type. In another embodiment, a high density doped region of the first conductivity type is formed in the first well with a predetermined distance apart from the junction area between the first well and second well. Or in another embodiment, a high density doped region of the second conductivity type is formed in the second well with a predetermined distance apart from the junction area between the first well and second well.
  • The objectives, technical details, features, and effects of the present invention will be better understood with regard to the detailed description of the embodiments below.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a cross-sectioned diagram of a prior art SCR ESD device.
  • FIG. 2 to FIG. 6 show schematic cross-sectional diagrams of several embodiments of the present invention.
  • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • The drawings as referred to throughout the description of the present invention are for illustration only, but not drawn according to actual scale.
  • Referring to FIG. 2, it shows the first embodiment of the present invention. In this embodiment, the N-type well 11 is floating; furthermore, only the high density P+ doped region 13 is formed in the N-type well 11 but not the high density N+ doped region (15 in FIG. 1). The external pad PAD is only connected to the P+ doped region 13. When the external pad PAD receives a high voltage, it can be discharged via a path 200 shown in the diagram. Importantly, the present invention is different from the prior art in that, when the external pad PAD receives a negative voltage, the negative voltage does not impact on the circuit due to the PN junction formed by the P+ doped region 13 and the N-type well 11. The problem in the prior art can be solved because the negative voltage can not induce any current loss from the substrate by any path.
  • FIG. 3 shows another embodiment of the present invention. In this embodiment, a high density N+ doped region 17 is formed at the junction area between the N-type well 11 and the P-type well 21. The purpose of the N+ doped region 17 is to adjust the trigger voltage of the ESD device. More specifically, the breakdown voltage of the junction diode formed by the N-type well 11 and the P-type well 21 is high, for example, about 40V or so. If the N+ doped region 17 is provided, by means of the junction formed by the N+ doped region 17 and the P-type well 21, the breakdown voltage can be effectively reduced to, e.g., about 12-15V or so; as a result, the SCR can be turned on at a lower voltage to trigger the ESD function.
  • FIG. 4 shows a similar embodiment to FIG. 3. A high density P+ doped region 27 is formed at the junction area between the N-type well 11 and the P-type well 21. The purpose of the P+ doped region 27 is also for adjusting the trigger voltage of the ESD device. The junction formed by the N-type well 11 and P+ doped region 27 can also reduce the breakdown voltage, so as to trigger the ESD function earlier.
  • FIG. 5 shows another embodiment of the present invention. In this embodiment, the N+ doped region 17 is not formed at the junction area between the N-type well 11 and P-type well 21, but rather at a predetermined distance d apart from the boundary of the P-type well 21. By adjusting the distance d, the trigger voltage of the ESD device can be adjusted to a range between the embodiments of FIG. 2 and FIG. 3.
  • FIG. 6 shows another embodiment of the present invention. In this embodiment, the P+ doped region 27 is not formed at the junction area between N-type well 11 and P-type well 21, but rather at a predetermined distance d′ apart from the boundary of the N-type well 11. By adjusting the distance d′, the trigger voltage of the ESD device can be adjusted to a range between the embodiments of FIG. 2 and FIG. 4.
  • The present invention has been described in considerable detail with reference to certain preferred embodiments thereof. It should be understood that the description is for illustrative purpose, not for limiting the scope of the present invention. Those skilled in this art can readily conceive variations and modifications within the spirit of the present invention. In view of the foregoing, the spirit of the present invention should cover all such and other modifications and variations, which should be interpreted to fall within the scope of the following claims and their equivalents.

Claims (10)

  1. 1. An isolated silicon controlled rectifier (SCR) electro-static discharge (ESD) device comprising:
    a substrate;
    a first well located in the substrate, which is floating and has a first conductivity type;
    a first high density doped region located in the first well and having a second conductivity type;
    a second well nearby the first well and having the second conductivity type;
    a second high density doped region located in the second well and having the second conductivity type; and
    a third high density doped region located in the second well and having the first conductivity type,
    wherein the first high density doped region is for electrical connection with a pad, and wherein the first well is not provided with a high density doped region having the first conductivity type for connection with the pad.
  2. 2. The isolated SCR ESD device of claim 1, wherein the first high density doped region, the first well, the second well, and the third high density doped region constitute an SCR.
  3. 3. The isolated SCR ESD device of claim 1, wherein the first conductivity type is N-type and the second conductivity type is P-type.
  4. 4. The isolated SCR ESD device of claim 1, further comprising a fourth high density doped region located at a junction area between the first and second wells.
  5. 5. The isolated SCR ESD device of claim 4, wherein the fourth high density doped region is the first or second conductivity type.
  6. 6. The isolated SCR ESD device of claim 1, further comprising a fourth high density doped region located in the first well and with a predetermined distance from a junction area between the first and second wells.
  7. 7. The isolated SCR ESD device of claim 6, wherein the fourth high density doped region is the first conductivity type.
  8. 8. The isolated SCR ESD device of claim 1, further comprising a fourth high density doped region located in the second well and with a predetermined distance from a junction area between the first and second wells.
  9. 9. The isolated SCR ESD device of claim 8, wherein the fourth high density doped region is the second conductivity type.
  10. 10. The isolated SCR ESD device of claim 1, wherein the second and third high density doped regions are coupled to a grounding pad.
US12586455 2009-09-22 2009-09-22 Isolated SCR ESD device Abandoned US20110068365A1 (en)

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US13345694 US8710544B2 (en) 2009-01-06 2012-01-07 Isolated SCR ESD device

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120074497A1 (en) * 2010-09-25 2012-03-29 Xiang Gao Esd protection structure
US20160148992A1 (en) * 2014-11-20 2016-05-26 Mediatek Inc. Semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050145947A1 (en) * 2000-11-06 2005-07-07 Russ Cornelius C. Silicon controlled rectifier electrostatic discharge protection device for power supply lines with powerdown mode of operation

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6573566B2 (en) * 2001-07-09 2003-06-03 United Microelectronics Corp. Low-voltage-triggered SOI-SCR device and associated ESD protection circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050145947A1 (en) * 2000-11-06 2005-07-07 Russ Cornelius C. Silicon controlled rectifier electrostatic discharge protection device for power supply lines with powerdown mode of operation

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120074497A1 (en) * 2010-09-25 2012-03-29 Xiang Gao Esd protection structure
US8981482B2 (en) * 2010-09-25 2015-03-17 Shanghai Huahong Grace Semiconductor Manufacturing Corporation ESD protection structure
US20160148992A1 (en) * 2014-11-20 2016-05-26 Mediatek Inc. Semiconductor device
US9543377B2 (en) * 2014-11-20 2017-01-10 Mediatek Inc. Semiconductor device
US9806146B2 (en) 2014-11-20 2017-10-31 Mediatek Inc. Semiconductor device

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US8710544B2 (en) 2014-04-29 grant
US20120104458A1 (en) 2012-05-03 application

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AS Assignment

Owner name: RICHTEK TECHNOLOGY CORPORATION, TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HUANG, CHIH-FENG;REEL/FRAME:023317/0368

Effective date: 20090916